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Bug #761

Mostrar el status del PLL en el LCD

Added by Cristian Castillo about 8 years ago. Updated about 8 years ago.

Status:
Closed
Priority:
Normal
Assignee:
Cristian Castillo
Target version:
Huancayo 1.0
Start date:
08/25/2016
Due date:
09/22/2016
% Done:

0%

Estimated time:
0.00 h

Description

Se necesita saber si el PLL del clock reference está enclavado, es decir, si el sistema realmente genera las frecuencias que dice generar.

History

#1 Updated by Cristian Castillo about 8 years ago

  • Target version set to Huancayo 1.0

#2 Updated by Redmine Admin about 8 years ago

  • Parent task deleted (#212)

#3 Updated by Redmine Admin about 8 years ago

  • Parent task set to #137

#4 Updated by Redmine Admin about 8 years ago

  • Due date set to 12/01/2016
  • Estimated time set to 0.00 h

#5 Updated by Redmine Admin about 8 years ago

  • Due date changed from 12/01/2016 to 11/21/2016
  • Start date changed from 09/26/2016 to 10/24/2016
  • Parent task deleted (#137)

#6 Updated by Redmine Admin about 8 years ago

  • Priority changed from Urgent to Normal

#7 Updated by Redmine Admin about 8 years ago

  • Target version deleted (Huancayo 1.0)

#8 Updated by Redmine Admin about 8 years ago

  • Target version set to Huancayo 1.0

#9 Updated by Redmine Admin about 8 years ago

  • Due date changed from 11/21/2016 to 09/22/2016
  • Start date changed from 10/24/2016 to 08/25/2016

#10 Updated by Cristian Castillo about 8 years ago

  • Status changed from New to Closed

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