Task #197
Milestone #128: PRUEBAS DE DISEÑO
Ejecutar tests y corregir posibles errores
Start date:
05/15/2017
Due date:
05/25/2017
% Done:
100%
Subtasks
History
#1
Updated by Joaquín Verástegui over 8 years ago
Updated by - Target version set to Versión 2.0
#2
Updated by John Rojas over 8 years ago
Updated by - Due date set to 04/03/2016
- Start date changed from 10/29/2015 to 01/04/2016
#3
Updated by John Rojas over 8 years ago
- Due date changed from 04/03/2016 to 06/30/2016
- Start date changed from 01/04/2016 to 04/25/2016
#4
Updated by John Rojas about 8 years ago
- Due date changed from 06/30/2016 to 05/31/2016
- Start date changed from 04/25/2016 to 05/16/2016
#5
Updated by John Rojas about 8 years ago
- Due date changed from 05/31/2016 to 06/30/2016
#6
Updated by John Rojas almost 8 years ago
- Start date changed from 05/16/2016 to 06/13/2016
#7
Updated by John Rojas almost 8 years ago
- Due date changed from 06/30/2016 to 07/21/2016
- % Done changed from 0 to 30
- Se adaptó la comunicación entre las tarjetas prototipo Bus y Control. Se está evaluando los bloques para sincronización con el controlador de radar.
#8
Updated by John Rojas almost 8 years ago
- Due date changed from 07/21/2016 to 07/27/2016
- % Done changed from 30 to 50
#9
Updated by John Rojas almost 8 years ago
- Due date changed from 07/27/2016 to 08/11/2016
#10
Updated by John Rojas over 7 years ago
- Due date changed from 08/11/2016 to 10/13/2016
- Status changed from New to In progress
- % Done changed from 50 to 70
-21/09/2016: Correcciones en las señales de sincronización del bloque de transferencia.
#11
Updated by John Rojas over 7 years ago
- Due date changed from 10/13/2016 to 11/10/2016
#12
Updated by John Rojas over 7 years ago
- % Done changed from 70 to 80
#13
Updated by John Rojas over 7 years ago
- Due date changed from 11/10/2016 to 12/15/2016
#14
Updated by John Rojas over 7 years ago
- Due date changed from 12/15/2016 to 01/31/2017
#15
Updated by John Rojas about 7 years ago
- Due date changed from 01/31/2017 to 02/28/2017
- % Done changed from 80 to 90
#16
Updated by John Rojas about 7 years ago
- Due date changed from 02/28/2017 to 03/09/2017
- Modificaciones adicionales:
- Enviar varios paquetes para un determinado perfil de datos
- Revisar diseño del sistema para corregir forma del componente Q.
#17
Updated by John Rojas about 7 years ago
- Due date changed from 03/09/2017 to 03/16/2017
#18
Updated by John Rojas about 7 years ago
- Due date changed from 03/16/2017 to 04/13/2017
Hardware:
- Debido a que el tiempo de envío de componentes I y Q estaban muy cercanas se agregó una compuerta inversora al reloj del AD6620 y circuito de activación data-ready para aumentar este tiempo, consiguiéndose adquirir correctamente.
- Debido a que regulador de 5.0V del ADC disipa una potencia (747mW) mayor a la máxima(612mW) para una entrada de 7.5V, ocasionando calentamiento del componente, se reemplazó por un circuito de habilitación con FET.
- Se agregó Bus driver en tarjeta Bus para habilitación de circuito de energía de tarjetas de adquisición.
Firmware/Software:
- Se encuentra pendiente modificación del firmware para adquisición de varios paquetes por perfil.
- Se evaluará adquisición para obtener máximo tiempo ventana de muestreo.
#19
Updated by John Rojas about 7 years ago
- Due date changed from 04/13/2017 to 05/04/2017
#20
Updated by John Rojas about 7 years ago
- Due date changed from 05/04/2017 to 05/18/2017
Siguientes pruebas:
- Determinar máxima cantidad de muestras para cada frecuencia de muestreo y número de canales.
- Test de adquisición con más de un IPP. (NTX>1)
#21
Updated by John Rojas over 6 years ago
- Status changed from In progress to Closed