Task #181
Milestone #127: TEST DE DESCRIPCIÓN Y VERIFICACIÓN DE HARDWARE (TESTBENCH)
Implementar testbench de protocolo LVDS (programación y control)
Start date:
01/27/2016
Due date:
01/28/2016
% Done:
100%
History
#1
Updated by Joaquín Verástegui over 8 years ago
Updated by - Target version set to Versión 2.0
#2
Updated by John Rojas over 8 years ago
Updated by - Due date set to 12/27/2015
- Start date changed from 10/28/2015 to 12/07/2015
#3
Updated by John Rojas over 8 years ago
- Due date changed from 12/27/2015 to 01/31/2016
- Start date changed from 12/07/2015 to 01/04/2016
#4
Updated by John Rojas over 8 years ago
- Due date changed from 01/31/2016 to 01/28/2016
- Start date changed from 01/04/2016 to 01/27/2016
#5
Updated by John Rojas over 8 years ago
- Status changed from New to Resolved
- % Done changed from 0 to 100
- 28/01/2016: Se simuló la comunicación del FPGA de Control y el FPGA de Programación para la recepción de comandos a través de LVDS, utilizando los sub-bloques cmd_mux y lvds_tx_prog en el FPGA de Control y lvds_rx_prog y cmd_demux en el FPGA de Programación.
#6
Updated by John Rojas almost 7 years ago
- Status changed from Resolved to Closed