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Task #1585

Milestone #1576: RC 2.1 IMAGING

Implementar lectura de tiempo en alta de línea WINDOW (FPGA)

Added by Joaquín Verástegui almost 6 years ago. Updated 11 months ago.

Status:
Closed
Priority:
High
Assignee:
Juan Llanos
Start date:
04/02/2019
Due date:
07/10/2019
% Done:

100%

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History

#1 Updated by Joaquín Verástegui almost 6 years ago

  • Priority changed from Normal to High

#2 Updated by Juan Llanos over 5 years ago

  • Due date set to 04/29/2019
  • Start date changed from 01/30/2019 to 04/02/2019

#3 Updated by Juan Llanos over 5 years ago

  • Status changed from New to In progress

#4 Updated by Juan Llanos over 5 years ago

  • Due date changed from 04/29/2019 to 05/30/2019
  • % Done changed from 0 to 80

#5 Updated by Juan Llanos over 5 years ago

  • Status changed from In progress to Resolved

#6 Updated by Juan Llanos over 5 years ago

  • Due date changed from 05/30/2019 to 07/10/2019
  • % Done changed from 80 to 100

#7 Updated by John Rojas 11 months ago

  • Status changed from Resolved to Closed
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