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'''
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Created on Feb 15, 2016
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@author: Miguel Urco
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'''
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import struct
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import string
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DDS_NBITS = 48
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FILE_STRUCTURE = """Phase Adjust Register 1
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-----------------------
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00000000
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00000000
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-----------------------
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Phase Adjust Register 2
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-----------------------
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00000000
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00000000
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-----------------------
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Frequency Tuning Word 1
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-----------------------
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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-----------------------
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Frequency Tuning Word 2
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-----------------------
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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-----------------------
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Delta Frequency Word
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-----------------------
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00000000
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00000000
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00000000
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00000000
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00000000
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00000000
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-----------------------
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Update Clock
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-----------------------
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00000000
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00000000
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00000000
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00000000
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-----------------------
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Ramp Rate Clock
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-----------------------
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00000000
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00000000
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00000000
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-----------------------
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Control Register
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-----------------------
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00000000
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00000000
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00000000
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00000000
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-----------------------
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Output Shaped Keying I
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Multiplier
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-----------------------
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00000000
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00000000
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-----------------------
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Output Shaped Keying Q
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Multiplier
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-----------------------
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00000000
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00000000
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-----------------------
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Output Shaped Keying
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Ramp Rate
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-----------------------
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00000000
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-----------------------
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QDAC
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-----------------------
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00000000
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00000000
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-----------------------
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CLOCK INPUT
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-----------------------
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10.00000000"""
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def freq_to_binary(freq, mclock):
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if not mclock:
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return None
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try:
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binary = int((float(freq)/mclock)*(2**DDS_NBITS))
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except:
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return 0
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return binary
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def binary_to_freq(binary, mclock):
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if not mclock:
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return None
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try:
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freq = (float(binary)/(2**DDS_NBITS))*mclock
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except:
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return 0
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return freq
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def phase_to_binary(phase):
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try:
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binary = int(float(phase)*8192/180.0)
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except:
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return 0
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return binary
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def binary_to_phase(binary):
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try:
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phase = float(binary)*180.0/8192
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except:
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return 0
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return phase
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def __fill_dds_dict(parms):
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my_dict = {'clock' : None,
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'multiplier' : 1,
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'frequencyA' : 0,
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'frequencyB' : 0,
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'frequencyA_Mhz' : 0,
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'frequencyB_Mhz' : 0,
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'phaseA_degress' : 0,
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'phaseB_degress' : 0,
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'modulation' : 0,
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'amplitudeI' : 0,
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'amplitudeQ' : 0,
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'amplitude_enabled' : 0,
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'delta_frequency' : 0,
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'update_clock' : 0,
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'ramp_rate_clock' : 0,
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'amplitude_ramp_rate' : 0,
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'qdac' : 0
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}
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my_dict.update(parms)
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my_dict['phaseA'] = phase_to_binary(my_dict['phaseA_degrees'])
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my_dict['phaseB'] = phase_to_binary(my_dict['phaseB_degrees'])
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pll_range = 0
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if my_dict['clock'] >= 200:
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pll_range = 1
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pll_bypass = 0
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if my_dict['multiplier'] < 4:
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pll_bypass = 1
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control_register = (1 << 28) + \
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(pll_range << 22) + (pll_bypass << 21) + \
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(my_dict['multiplier'] << 16) + \
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(my_dict['modulation'] << 9) + \
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(my_dict['amplitude_enabled'] << 5)
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my_dict['control_register'] = control_register
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return my_dict
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def dds_str_to_dict(registers, clock=None):
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"""
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Output:
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parms : Dictionary with keys
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multiplier :
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frequencyA :
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frequencyB :
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frequencyA_Mhz :
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frequencyB_Mhz :
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modulation :
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phaseA_degrees :
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phaseB_degrees :
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amplitudeI :
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amplitudeQ :
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"""
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if not registers:
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return {}
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if len(registers) != 0x28:
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return {}
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phaseA = struct.unpack('>H', registers[0x0:0x2])[0]
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phaseB = struct.unpack('>H', registers[0x2:0x4])[0]
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frequencyA = struct.unpack('>Q', '\x00\x00' + registers[0x04:0x0A])[0]
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frequencyB = struct.unpack('>Q', '\x00\x00' + registers[0x0A:0x10])[0]
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delta_frequency = struct.unpack('>Q', '\x00\x00' + registers[0x10:0x16])[0]
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update_clock = struct.unpack('>I', registers[0x16:0x1A])[0]
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ramp_rate_clock = struct.unpack('>I', '\x00' + registers[0x1A:0x1D])[0]
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control_register = struct.unpack('>I', registers[0x1D:0x21])[0]
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amplitudeI = struct.unpack('>H', registers[0x21:0x23])[0]
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amplitudeQ = struct.unpack('>H', registers[0x23:0x25])[0]
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amp_ramp_rate = ord(registers[0x25])
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qdac = struct.unpack('>H', registers[0x26:0x28])[0]
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multiplier = (control_register & 0x001F0000) >> 16
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modulation = (control_register & 0x00000E00) >> 9
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amplitude_enabled = (control_register & 0x00000020) >> 5
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frequencyA_Mhz = None
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frequencyB_Mhz = None
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if clock:
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mclock = clock*multiplier
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frequencyA_Mhz = binary_to_freq(frequencyA, mclock)
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frequencyB_Mhz = binary_to_freq(frequencyB, mclock)
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parms = {'clock' : clock,
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'multiplier' : multiplier,
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'frequencyA' : frequencyA,
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'frequencyB' : frequencyB,
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'frequencyA_Mhz' : frequencyA_Mhz,
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'frequencyB_Mhz' : frequencyB_Mhz,
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'phaseA' : phaseA,
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'phaseB' : phaseB,
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'phaseA_degrees' : binary_to_phase(phaseA),
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'phaseB_degrees' : binary_to_phase(phaseB),
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'modulation' : modulation,
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'amplitudeI' : amplitudeI,
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'amplitudeQ' : amplitudeQ,
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'amplitude_enabled' : amplitude_enabled,
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'delta_frequency' : delta_frequency,
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'update_clock' : update_clock,
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'ramp_rate_clock' : ramp_rate_clock,
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'amp_ramp_rate' : amp_ramp_rate,
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'qdac' : qdac
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}
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return parms
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def dict_to_dds_str(parms):
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"""
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Input:
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parms : Dictionary with keys
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multiplier : 4 to 20
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frequencyA : 0 to (2**48-1) equivalent to: 0 - "Master clock"
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frequencyB : 0 to (2**48-1) equivalent to: 0 - "Master clock"
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modulation : 0 to 3
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phaseA_degrees : 0 - 360 degrees
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phaseB_degrees : 0 - 360 degrees
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amplitudeI : 0 to (2**12-1) equivalent to: 0 - 100%
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amplitudeQ : 0 to (2**12-1) equivalent to: 0 - 100%
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"""
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my_dict = __fill_dds_dict(parms)
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registers = ""
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registers += struct.pack(">H", my_dict['phaseA'])
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registers += struct.pack(">H", my_dict['phaseB'])
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registers += struct.pack(">Q", my_dict['frequencyA'])[2:]
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registers += struct.pack(">Q", my_dict['frequencyB'])[2:]
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registers += struct.pack(">Q", my_dict['delta_frequency'])[2:]
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registers += struct.pack(">I", my_dict['update_clock'])
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registers += struct.pack(">I", my_dict['ramp_rate_clock'])[1:]
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registers += struct.pack(">I", my_dict['control_register'])
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registers += struct.pack(">H", my_dict['amplitudeI'])
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registers += struct.pack(">H", my_dict['amplitudeQ'])
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registers += chr(my_dict['amplitude_ramp_rate'])
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registers += struct.pack(">H", my_dict['qdac'])
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return registers
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def text_to_dict(lines):
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registers = ""
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registers_v2 = []
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for this_line in lines:
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this_line = str.strip(this_line)
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if str.isalpha(this_line):
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continue
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if not str.isdigit(this_line):
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try:
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value = float(this_line)
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except:
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continue
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registers_v2.append(value)
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continue
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if len(this_line) != 8:
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continue
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registers += chr(string.atoi(this_line,2))
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mclock = None
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if len(registers_v2) > 0:
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mclock = registers_v2[0]
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my_dict = dds_str_to_dict(registers, mclock)
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return my_dict
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def dict_to_text(parms):
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"""
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It creates formatted DDS text using dictionary values.
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"""
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my_dict = __fill_dds_dict(parms)
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lines = FILE_STRUCTURE.split('\n')
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cad = '{0:016b}'.format(my_dict['phaseA'])
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lines[2] = cad[0:8]
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lines[3] = cad[8:16]
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cad = '{0:016b}'.format(my_dict['phaseB'])
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lines[7] = cad[0:8]
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lines[8] = cad[8:16]
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cad = '{0:048b}'.format(my_dict['frequencyA'])
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lines[12] = cad[0:8]
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lines[13] = cad[8:16]
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lines[14] = cad[16:24]
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lines[15] = cad[24:32]
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lines[16] = cad[32:40]
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lines[17] = cad[40:48]
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cad = '{0:048b}'.format(my_dict['frequencyB'])
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lines[21] = cad[0:8]
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lines[22] = cad[8:16]
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lines[23] = cad[16:24]
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lines[24] = cad[24:32]
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lines[25] = cad[32:40]
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lines[26] = cad[40:48]
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cad = '{0:048b}'.format(my_dict['delta_frequency'])
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lines[30] = cad[0:8]
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lines[31] = cad[8:16]
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lines[32] = cad[16:24]
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lines[33] = cad[24:32]
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lines[34] = cad[32:40]
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lines[35] = cad[40:48]
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cad = '{0:032b}'.format(my_dict['update_clock'])
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lines[39] = cad[0:8]
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lines[40] = cad[8:16]
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lines[41] = cad[16:24]
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lines[42] = cad[24:32]
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cad = '{0:024b}'.format(my_dict['ramp_rate_clock'])
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lines[46] = cad[0:8]
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lines[47] = cad[8:16]
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lines[48] = cad[16:24]
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cad = '{0:032b}'.format(my_dict['control_register'])
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lines[52] = cad[0:8]
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lines[53] = cad[8:16]
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lines[54] = cad[16:24]
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lines[55] = cad[24:32]
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cad = '{0:016b}'.format(my_dict['amplitudeI'])
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lines[60] = cad[0:8]
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lines[61] = cad[8:16]
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cad = '{0:016b}'.format(my_dict['amplitudeQ'])
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lines[66] = cad[0:8]
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lines[67] = cad[8:16]
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cad = '{0:08b}'.format(my_dict['amplitude_ramp_rate'])
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lines[72] = cad[0:8]
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cad = '{0:016b}'.format(my_dict['qdac'])
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lines[76] = cad[0:8]
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lines[77] = cad[8:16]
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lines[81] = '%10.8f' %my_dict['clock']
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text = '\n'.join(lines)
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return text
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