diff --git a/apps/rc/models.py b/apps/rc/models.py
index f873cd8..fbdeb03 100644
--- a/apps/rc/models.py
+++ b/apps/rc/models.py
@@ -80,6 +80,7 @@ class RCConfiguration(Configuration):
     time_before = models.PositiveIntegerField(verbose_name='Time before [μS]', default=12)
     time_after = models.PositiveIntegerField(verbose_name='Time after [μS]', default=1)
     sync = models.PositiveIntegerField(verbose_name='Synchro delay', default=0)
+    ch_monitor = models.PositiveIntegerField(verbose_name='Channel Monitor', validators=[MinValueValidator(0), MaxValueValidator(15)], default=6)
     sampling_reference = models.CharField(verbose_name='Sampling Reference', choices=SAMPLING_REFS, default='none', max_length=40)
     control_tx = models.BooleanField(verbose_name='Control Switch TX', default=False)
     control_sw = models.BooleanField(verbose_name='Control Switch SW', default=False)
@@ -267,7 +268,6 @@ class RCConfiguration(Configuration):
             #print(dum)
             states.append(dum)
             last = dum
-        print("Finish loading")
         #########################################################################
 
         if binary: