Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.13 secs
 
--> Reading design: FrontEnd_Acq.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "FrontEnd_Acq.prj"
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "FrontEnd_Acq"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : FrontEnd_Acq
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" into library work
Parsing entity <joiner_samp>.
Parsing architecture <Behavioral> of entity <joiner_samp>.
Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" into library work
Parsing entity <DtoDPRAM>.
Parsing architecture <Behavioral> of entity <dtodpram>.
Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd" into library work
Parsing entity <DCM_fwd_int>.
Parsing architecture <Behavioral> of entity <dcm_fwd_int>.
Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd" into library work
Parsing entity <Data_Req_gen>.
Parsing architecture <Behavioral> of entity <data_req_gen>.
Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd" into library work
Parsing entity <FrontEnd_Acq>.
Parsing architecture <Behavioral> of entity <frontend_acq>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <FrontEnd_Acq> (architecture <Behavioral>) with generics from library <work>.

Elaborating entity <DCM_fwd_int> (architecture <Behavioral>) from library <work>.

Elaborating entity <Data_Req_gen> (architecture <Behavioral>) with generics from library <work>.

Elaborating entity <joiner_samp> (architecture <Behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 183. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 220. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 315. Case statement is complete. others clause is never selected

Elaborating entity <DtoDPRAM> (architecture <Behavioral>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 228. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 469. Case statement is complete. others clause is never selected

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <FrontEnd_Acq>.
    Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd".
        DBIT_SZ = 3
        ADDR_LENGTH = 12
        DATAOUT_LENGTH = 8
        CH_SZ = 5
        NBITS_PERIOD = 18
        NBITS_DUTY = 12
        NBITS_PULSES = 10
        RESUL_NP_SZ = 40
        ID_CH_SZ = 4
    Found 16-bit register for signal <cont_200MHz>.
    Found 1-bit register for signal <lock_rst_bar>.
    Found 16-bit adder for signal <cont_200MHz[15]_GND_5_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  17 D-type flip-flop(s).
Unit <FrontEnd_Acq> synthesized.

Synthesizing Unit <DCM_fwd_int>.
    Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd".
    Summary:
	no macro.
Unit <DCM_fwd_int> synthesized.

Synthesizing Unit <Data_Req_gen>.
    Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd".
        NBITS_PERIOD = 18
        NBITS_DUTY = 12
        NBITS_PULSES = 10
    Found 1-bit register for signal <pps_rising>.
    Found 1-bit register for signal <data_req_s>.
    Found 18-bit register for signal <count_clock>.
    Found 10-bit register for signal <count_pulses>.
    Found 2-bit register for signal <pps_r>.
    Found 10-bit adder for signal <count_pulses[9]_GND_11_o_add_5_OUT> created at line 1241.
    Found 18-bit adder for signal <count_clock[17]_GND_11_o_add_10_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
Unit <Data_Req_gen> synthesized.

Synthesizing Unit <joiner_samp>.
    Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd".
        DBIT_SZ = 3
        BITS_COUNT_SZ = 3
        RESUL_NP_SZ = 40
        SAMPLE_SZ = 24
        SAMPLE_COUNT_SZ = 12
        HEADER_NIB_SZ = 4
        DATA_HEADER_NIB_SZ = 4
        CH_COUNT_SZ = 4
    Found 2-bit register for signal <chn_bits_acq_bit1>.
    Found 2-bit register for signal <chn_bits_acq_bit2>.
    Found 3-bit register for signal <clk_acq_r>.
    Found 1-bit register for signal <clk_acq_rise>.
    Found 1-bit register for signal <pack_cur_state>.
    Found 3-bit register for signal <dbits_counter>.
    Found 24-bit register for signal <resul_mem_internal>.
    Found 1-bit register for signal <resul_mem_internal_aux<35>>.
    Found 1-bit register for signal <resul_mem_internal_aux<34>>.
    Found 1-bit register for signal <resul_mem_internal_aux<33>>.
    Found 1-bit register for signal <resul_mem_internal_aux<32>>.
    Found 1-bit register for signal <resul_mem_internal_aux<31>>.
    Found 1-bit register for signal <resul_mem_internal_aux<30>>.
    Found 1-bit register for signal <resul_mem_internal_aux<29>>.
    Found 1-bit register for signal <resul_mem_internal_aux<28>>.
    Found 1-bit register for signal <resul_mem_internal_aux<27>>.
    Found 1-bit register for signal <resul_mem_internal_aux<26>>.
    Found 1-bit register for signal <resul_mem_internal_aux<25>>.
    Found 1-bit register for signal <resul_mem_internal_aux<24>>.
    Found 1-bit register for signal <resul_mem_internal_aux<23>>.
    Found 1-bit register for signal <resul_mem_internal_aux<22>>.
    Found 1-bit register for signal <resul_mem_internal_aux<21>>.
    Found 1-bit register for signal <resul_mem_internal_aux<20>>.
    Found 1-bit register for signal <resul_mem_internal_aux<19>>.
    Found 1-bit register for signal <resul_mem_internal_aux<18>>.
    Found 1-bit register for signal <resul_mem_internal_aux<17>>.
    Found 1-bit register for signal <resul_mem_internal_aux<16>>.
    Found 1-bit register for signal <resul_mem_internal_aux<15>>.
    Found 1-bit register for signal <resul_mem_internal_aux<14>>.
    Found 1-bit register for signal <resul_mem_internal_aux<13>>.
    Found 1-bit register for signal <resul_mem_internal_aux<12>>.
    Found 1-bit register for signal <resul_mem_internal_aux<11>>.
    Found 1-bit register for signal <resul_mem_internal_aux<10>>.
    Found 1-bit register for signal <resul_mem_internal_aux<9>>.
    Found 1-bit register for signal <resul_mem_internal_aux<8>>.
    Found 1-bit register for signal <resul_mem_internal_aux<7>>.
    Found 1-bit register for signal <resul_mem_internal_aux<6>>.
    Found 1-bit register for signal <resul_mem_internal_aux<5>>.
    Found 1-bit register for signal <resul_mem_internal_aux<4>>.
    Found 1-bit register for signal <resul_mem_internal_aux<3>>.
    Found 1-bit register for signal <resul_mem_internal_aux<2>>.
    Found 1-bit register for signal <resul_mem_internal_aux<1>>.
    Found 1-bit register for signal <resul_mem_internal_aux<0>>.
    Found 12-bit register for signal <samp_count>.
    Found 1-bit register for signal <rdy_mem_aux>.
    Found 2-bit register for signal <data_cur_state>.
    Found 2-bit register for signal <chn_bits_acq_bit0>.
    Found finite state machine <FSM_0> for signal <data_cur_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 4                                              |
    | Clock              | clk_main (rising_edge)                         |
    | Reset              | rst_bar_INV_14_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <dbits_counter[2]_GND_12_o_add_13_OUT> created at line 1241.
    Found 12-bit adder for signal <samp_count[11]_GND_12_o_add_29_OUT> created at line 1241.
    Found 24-bit 8-to-1 multiplexer for signal <dbits_counter[2]_resul_mem_internal[23]_wide_mux_14_OUT> created at line 202.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  87 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <joiner_samp> synthesized.

Synthesizing Unit <DtoDPRAM>.
    Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd".
        ADDR_LENGTH = 12
        DATAOUT_LENGTH = 8
        DATAIN_LENGTH = 40
        CHAN_NUM = 5
        COUNT_BYTE_SZ = 3
        COUNT_PACK_SZ = 6
    Found 4-bit register for signal <ram_contr_cur_state>.
    Found 6-bit register for signal <count_pack>.
    Found 1-bit register for signal <sel_buf>.
    Found 1-bit register for signal <rpi_req>.
    Found 3-bit register for signal <count_ch_byte>.
    Found 8-bit register for signal <datach1_aux>.
    Found 8-bit register for signal <datach2_aux>.
    Found 8-bit register for signal <datach3_aux>.
    Found 8-bit register for signal <datach4_aux>.
    Found 8-bit register for signal <datach5_aux>.
    Found 4-bit register for signal <ch_cont_cur_state>.
    Found finite state machine <FSM_1> for signal <ram_contr_cur_state>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 28                                             |
    | Inputs             | 5                                              |
    | Outputs            | 16                                             |
    | Clock              | clk_main (rising_edge)                         |
    | Reset              | rst_bar_INV_48_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <ch_cont_cur_state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 21                                             |
    | Inputs             | 10                                             |
    | Outputs            | 4                                              |
    | Clock              | clk_main (rising_edge)                         |
    | Reset              | rst_bar_INV_48_o (positive)                    |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit adder for signal <count_pack[5]_GND_26_o_add_241_OUT> created at line 1241.
    Found 3-bit adder for signal <count_ch_byte[2]_GND_26_o_add_252_OUT> created at line 1241.
    Found 12-bit adder for signal <_n0507> created at line 302.
    Found 12-bit adder for signal <_n0508> created at line 302.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_61_OUT> created at line 302.
    Found 12-bit adder for signal <_n0512> created at line 304.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_67_OUT> created at line 304.
    Found 12-bit adder for signal <_n0516> created at line 341.
    Found 12-bit adder for signal <_n0517> created at line 341.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_102_OUT> created at line 341.
    Found 12-bit adder for signal <_n0521> created at line 343.
    Found 12-bit adder for signal <_n0522> created at line 343.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_108_OUT> created at line 343.
    Found 12-bit adder for signal <_n0526> created at line 380.
    Found 12-bit adder for signal <_n0527> created at line 380.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_143_OUT> created at line 380.
    Found 12-bit adder for signal <_n0531> created at line 382.
    Found 12-bit adder for signal <_n0532> created at line 382.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_149_OUT> created at line 382.
    Found 12-bit adder for signal <_n0536> created at line 419.
    Found 12-bit adder for signal <_n0537> created at line 419.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_184_OUT> created at line 419.
    Found 12-bit adder for signal <_n0541> created at line 421.
    Found 12-bit adder for signal <_n0542> created at line 421.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_190_OUT> created at line 421.
    Found 12-bit adder for signal <_n0546> created at line 458.
    Found 12-bit adder for signal <_n0547> created at line 458.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_225_OUT> created at line 458.
    Found 12-bit adder for signal <_n0551> created at line 460.
    Found 12-bit adder for signal <_n0552> created at line 460.
    Found 12-bit adder for signal <GND_26_o_GND_26_o_add_231_OUT> created at line 460.
    Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_257_OUT> created at line 540.
    Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_260_OUT> created at line 564.
    Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_263_OUT> created at line 588.
    Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_266_OUT> created at line 612.
    Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_269_OUT> created at line 636.
    Summary:
	inferred  31 Adder/Subtractor(s).
	inferred  51 D-type flip-flop(s).
	inferred  31 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <DtoDPRAM> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 44
 10-bit adder                                          : 1
 12-bit adder                                          : 34
 16-bit adder                                          : 1
 18-bit adder                                          : 1
 3-bit adder                                           : 6
 6-bit adder                                           : 1
# Registers                                            : 191
 1-bit register                                        : 140
 10-bit register                                       : 1
 12-bit register                                       : 10
 16-bit register                                       : 1
 18-bit register                                       : 1
 2-bit register                                        : 16
 24-bit register                                       : 5
 3-bit register                                        : 11
 6-bit register                                        : 1
 8-bit register                                        : 5
# Multiplexers                                         : 51
 1-bit 2-to-1 multiplexer                              : 5
 12-bit 2-to-1 multiplexer                             : 15
 24-bit 8-to-1 multiplexer                             : 5
 3-bit 2-to-1 multiplexer                              : 6
 40-bit 2-to-1 multiplexer                             : 5
 8-bit 2-to-1 multiplexer                              : 10
 8-bit 7-to-1 multiplexer                              : 5
# FSMs                                                 : 7

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <Data_Req_gen>.
The following registers are absorbed into counter <count_pulses>: 1 register on signal <count_pulses>.
The following registers are absorbed into counter <count_clock>: 1 register on signal <count_clock>.
Unit <Data_Req_gen> synthesized (advanced).

Synthesizing (advanced) Unit <DtoDPRAM>.
The following registers are absorbed into counter <count_ch_byte>: 1 register on signal <count_ch_byte>.
The following registers are absorbed into counter <count_pack>: 1 register on signal <count_pack>.
Unit <DtoDPRAM> synthesized (advanced).

Synthesizing (advanced) Unit <FrontEnd_Acq>.
The following registers are absorbed into counter <cont_200MHz>: 1 register on signal <cont_200MHz>.
Unit <FrontEnd_Acq> synthesized (advanced).

Synthesizing (advanced) Unit <joiner_samp>.
The following registers are absorbed into counter <samp_count>: 1 register on signal <samp_count>.
The following registers are absorbed into counter <dbits_counter>: 1 register on signal <dbits_counter>.
Unit <joiner_samp> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Adders/Subtractors                                   : 29
 12-bit adder                                          : 29
# Counters                                             : 15
 10-bit up counter                                     : 1
 12-bit up counter                                     : 5
 16-bit up counter                                     : 1
 18-bit up counter                                     : 1
 3-bit up counter                                      : 6
 6-bit up counter                                      : 1
# Registers                                            : 407
 Flip-Flops                                            : 407
# Multiplexers                                         : 82
 1-bit 2-to-1 multiplexer                              : 48
 12-bit 2-to-1 multiplexer                             : 15
 24-bit 8-to-1 multiplexer                             : 5
 40-bit 2-to-1 multiplexer                             : 5
 8-bit 2-to-1 multiplexer                              : 4
 8-bit 7-to-1 multiplexer                              : 5
# FSMs                                                 : 7

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <empa_ch1/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
Optimizing FSM <empa_ch2/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
Optimizing FSM <empa_ch3/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
Optimizing FSM <empa_ch4/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
Optimizing FSM <empa_ch5/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
-----------------------
 State     | Encoding
-----------------------
 idle      | 00
 data_pres | 01
 data_proc | 11
-----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <controlador_DPRAM/FSM_2> on signal <ch_cont_cur_state[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 idle          | 0000
 checking_ch1  | 0001
 attending_ch1 | 0010
 checking_ch2  | 0011
 attending_ch2 | 0100
 checking_ch3  | 0101
 attending_ch3 | 0110
 checking_ch4  | 0111
 attending_ch4 | 1000
 checking_ch5  | 1001
 attending_ch5 | 1010
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <controlador_DPRAM/FSM_1> on signal <ram_contr_cur_state[1:4]> with sequential encoding.
--------------------------
 State        | Encoding
--------------------------
 idle         | 0000
 pre_ch1      | 0001
 wr_ch1       | 0110
 end_wrt_ch_1 | 0111
 pre_ch2      | 0010
 wr_ch2       | 1000
 end_wrt_ch_2 | 1001
 pre_ch3      | 0011
 wr_ch3       | 1010
 end_wrt_ch_3 | 1011
 pre_ch4      | 0100
 wr_ch4       | 1100
 end_wrt_ch_4 | 1101
 pre_ch5      | 0101
 wr_ch5       | 1110
 end_wrt_ch_5 | 1111
--------------------------

Optimizing unit <FrontEnd_Acq> ...

Optimizing unit <joiner_samp> ...

Optimizing unit <Data_Req_gen> ...

Optimizing unit <DtoDPRAM> ...
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_0> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_0> <empa_ch3/samp_count_0> <empa_ch2/samp_count_0> <empa_ch1/samp_count_0> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_1> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_1> <empa_ch3/samp_count_1> <empa_ch2/samp_count_1> <empa_ch1/samp_count_1> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_2> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_2> <empa_ch3/samp_count_2> <empa_ch2/samp_count_2> <empa_ch1/samp_count_2> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_3> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_3> <empa_ch3/samp_count_3> <empa_ch2/samp_count_3> <empa_ch1/samp_count_3> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_4> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_4> <empa_ch3/samp_count_4> <empa_ch2/samp_count_4> <empa_ch1/samp_count_4> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_5> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_5> <empa_ch3/samp_count_5> <empa_ch2/samp_count_5> <empa_ch1/samp_count_5> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_6> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_6> <empa_ch3/samp_count_6> <empa_ch2/samp_count_6> <empa_ch1/samp_count_6> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_7> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_7> <empa_ch3/samp_count_7> <empa_ch2/samp_count_7> <empa_ch1/samp_count_7> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_8> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_8> <empa_ch3/samp_count_8> <empa_ch2/samp_count_8> <empa_ch1/samp_count_8> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_9> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_9> <empa_ch3/samp_count_9> <empa_ch2/samp_count_9> <empa_ch1/samp_count_9> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_10> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_10> <empa_ch3/samp_count_10> <empa_ch2/samp_count_10> <empa_ch1/samp_count_10> 
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_11> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_11> <empa_ch3/samp_count_11> <empa_ch2/samp_count_11> <empa_ch1/samp_count_11> 

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block FrontEnd_Acq, actual ratio is 16.
FlipFlop controlador_DPRAM/count_pack_0 has been replicated 1 time(s)
FlipFlop controlador_DPRAM/count_pack_1 has been replicated 1 time(s)
FlipFlop controlador_DPRAM/count_pack_2 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 508
 Flip-Flops                                            : 508

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : FrontEnd_Acq.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 947
#      GND                         : 1
#      INV                         : 10
#      LUT1                        : 52
#      LUT2                        : 47
#      LUT3                        : 76
#      LUT4                        : 64
#      LUT5                        : 190
#      LUT6                        : 206
#      MUXCY                       : 143
#      MUXF7                       : 7
#      VCC                         : 1
#      XORCY                       : 150
# FlipFlops/Latches                : 508
#      FD                          : 42
#      FDE                         : 196
#      FDR                         : 96
#      FDRE                        : 159
#      FDS                         : 15
# Clock Buffers                    : 2
#      BUFG                        : 2
# IO Buffers                       : 49
#      IBUF                        : 21
#      IBUFG                       : 1
#      OBUF                        : 27
# DCMs                             : 1
#      DCM_SP                      : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:             508  out of  11440     4%  
 Number of Slice LUTs:                  645  out of   5720    11%  
    Number used as Logic:               645  out of   5720    11%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    815
   Number with an unused Flip Flop:     307  out of    815    37%  
   Number with an unused LUT:           170  out of    815    20%  
   Number of fully used LUT-FF pairs:   338  out of    815    41%  
   Number of unique control sets:        22

IO Utilization: 
 Number of IOs:                          49
 Number of bonded IOBs:                  49  out of    102    48%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_main                           | DCM_SP:CLKFX           | 508   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 18.723ns (Maximum Frequency: 53.411MHz)
   Minimum input arrival time before clock: 1.903ns
   Maximum output required time after clock: 10.616ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_main'
  Clock period: 18.723ns (frequency: 53.411MHz)
  Total number of paths / destination ports: 4776 / 1112
-------------------------------------------------------------------------
Delay:               4.681ns (Levels of Logic = 4)
  Source:            generador_req/count_pulses_1 (FF)
  Destination:       generador_req/count_clock_16 (FF)
  Source Clock:      clk_main rising 4.0X
  Destination Clock: clk_main rising 4.0X

  Data Path: generador_req/count_pulses_1 to generador_req/count_clock_16
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q             3   0.447   0.995  generador_req/count_pulses_1 (generador_req/count_pulses_1)
     LUT5:I0->O            2   0.203   0.617  generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9>_SW0 (N9)
     LUT6:I5->O            3   0.205   0.651  generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9> (generador_req/PWR_8_o_count_pulses[9]_equal_4_o)
     LUT6:I5->O           18   0.205   1.050  generador_req/Mcount_count_clock_val (generador_req/Mcount_count_clock_val)
     LUT4:I3->O            1   0.205   0.000  generador_req/count_clock_16_rstpot (generador_req/count_clock_16_rstpot)
     FD:D                      0.102          generador_req/count_clock_16
    ----------------------------------------
    Total                      4.681ns (1.367ns logic, 3.314ns route)
                                       (29.2% logic, 70.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main'
  Total number of paths / destination ports: 21 / 21
-------------------------------------------------------------------------
Offset:              1.903ns (Levels of Logic = 1)
  Source:            clk_acq_ch5 (PAD)
  Destination:       empa_ch5/clk_acq_r_0 (FF)
  Destination Clock: clk_main rising 4.0X

  Data Path: clk_acq_ch5 to empa_ch5/clk_acq_r_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  clk_acq_ch5_IBUF (clk_acq_ch5_IBUF)
     FDS:D                     0.102          empa_ch5/clk_acq_r_0
    ----------------------------------------
    Total                      1.903ns (1.324ns logic, 0.579ns route)
                                       (69.6% logic, 30.4% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main'
  Total number of paths / destination ports: 3738 / 27
-------------------------------------------------------------------------
Offset:              10.616ns (Levels of Logic = 7)
  Source:            controlador_DPRAM/count_ch_byte_2 (FF)
  Destination:       addrA<7> (PAD)
  Source Clock:      clk_main rising 4.0X

  Data Path: controlador_DPRAM/count_ch_byte_2 to addrA<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q           103   0.447   1.990  controlador_DPRAM/count_ch_byte_2 (controlador_DPRAM/count_ch_byte_2)
     LUT3:I1->O           10   0.203   1.085  controlador_DPRAM/_n0517<5>21 (controlador_DPRAM/_n0517<5>2)
     LUT5:I2->O            1   0.205   0.000  controlador_DPRAM/_n0517<7>11 (controlador_DPRAM/_n0517<7>1)
     XORCY:LI->O           1   0.136   0.924  controlador_DPRAM/Madd_GND_26_o_GND_26_o_add_108_OUT_xor<7> (controlador_DPRAM/GND_26_o_GND_26_o_add_108_OUT<7>)
     LUT5:I0->O            1   0.203   0.944  controlador_DPRAM/Mmux_addrA103 (controlador_DPRAM/Mmux_addrA102)
     LUT6:I0->O            1   0.203   0.924  controlador_DPRAM/Mmux_addrA104 (controlador_DPRAM/Mmux_addrA103)
     LUT6:I1->O            1   0.203   0.579  controlador_DPRAM/Mmux_addrA106 (addrA_7_OBUF)
     OBUF:I->O                 2.571          addrA_7_OBUF (addrA<7>)
    ----------------------------------------
    Total                     10.616ns (4.171ns logic, 6.445ns route)
                                       (39.3% logic, 60.7% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk_main
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_main       |    4.681|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 11.00 secs
Total CPU time to Xst completion: 10.51 secs
 
--> 

Total memory usage is 251848 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :   12 (   0 filtered)