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-- Company: 
-- Engineer:
--
-- Create Date:   14:55:16 03/12/2015
-- Design Name:   
-- Module Name:   /home/shinobi/workspaces/roj/trunk/firmware/sources/processingEngine/cic/tb_int.vhd
-- Project Name:  cic
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: integrator
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
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LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;

use work.fix_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY tb_int IS
END tb_int;
 
ARCHITECTURE behavior OF tb_int IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT integrator
    PORT(
         clk : IN  std_logic;
         input : IN  sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
         output : OUT  sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');

 	--Outputs
   signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);

   -- Clock period definitions
   constant clk_period : time := 1 ms;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: integrator PORT MAP (
          clk => clk,
          input => input,
          output => output
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '1';
		wait for clk_period/2;
		clk <= '0';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
			wait for 1 ms;	
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait;
   end process;

END;