-- test_comb Template 

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;
use work.cic_utils.all;


  ENTITY test_decim IS
  END test_decim;

  ARCHITECTURE behavior OF test_decim IS 

  -- Component Declaration
          COMPONENT decimator
          Port ( clkin : in  STD_LOGIC;
					  clkout: out STD_LOGIC;
					  reset : in std_logic;
					  N : in  integer range 0 to 19;
					  input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
					  output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS));
          END COMPONENT;

			--Inputs
         signal clkin : std_logic := '0';
			signal reset : std_logic := '0';
			signal N : integer range 0 to 19:= 11;
			signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
			
			--Outputs
			signal clkout : std_logic := '0';
			signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
			
			-- Clock period definitions
			constant clk_period : time := 1 ms;	
  BEGIN

  -- Instantiate the Unit Under Test (UUT)
          uut: decimator PORT MAP(
           clkin => clkin,
			  clkout => clkout,
			  reset => reset,
           N => N,
           input => input,
           output => output
          );

  -- Clock process definitions
      clk_process :process
		begin
			clkin <= '1';
			wait for clk_period/2;
			clkin <= '0';
			wait for clk_period/2;
		end process;
	
  -- Stimulus process
		stim_proc: process
		begin		
			-- hold reset state for 1 ms.
			wait for clk_period;
			input <= to_sfixed(1,input);
			wait for clk_period;
			input <= to_sfixed(2,input);
			wait for clk_period;
			input <= to_sfixed(3,input);
			wait for clk_period;
			input <= to_sfixed(4,input);
			wait for clk_period;
			input <= to_sfixed(5,input);
			wait for clk_period;
			input <= to_sfixed(6,input);
			wait for clk_period;
			input <= to_sfixed(7,input);
			wait for clk_period;
			input <= to_sfixed(8,input);
			wait for clk_period;
			input <= to_sfixed(9,input);
			wait for clk_period;
			input <= to_sfixed(10,input);
			wait for clk_period;
			input <= to_sfixed(11,input);
			wait for clk_period;
			input <= to_sfixed(12,input);
			wait for clk_period;
			input <= to_sfixed(13,input);
			wait for clk_period;
			input <= to_sfixed(14,input);
			wait for clk_period;
			input <= to_sfixed(15,input);
			wait for clk_period;
			input <= to_sfixed(16,input);
			wait for clk_period;
			input <= to_sfixed(17,input);
			wait for clk_period;
			input <= to_sfixed(18,input);
			wait for clk_period;
			input <= to_sfixed(19,input);
			wait for clk_period;
			input <= to_sfixed(20,input);
		end process;
 

  END;