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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.cic_utils.all;



entity clk_div is
    Port ( clkin : in  STD_LOGIC;
			  clkout: out STD_LOGIC;
			  reset : in std_logic;
           N : in  integer range 0 to 19);
end clk_div;


architecture Behavioral of clk_div is
	 signal clktmp: STD_LOGIC := '0';
    signal cnt1: integer range 0 to 19 := 0;
begin
		process(clkin,reset)
		begin
			if reset = '1' then
				cnt1 <= 0;
				clktmp <= '0';
			elsif clkin'event and clkin = '1' then
				if cnt1 < N then
					if cnt1 >= N/2 then
						clktmp <= '0';
					end if;
					cnt1 <= cnt1 +1;
				else
					clktmp <= '1';
					cnt1 <= 0;
				end if;
			end if;
		end process;

		clkout <= clktmp;
end Behavioral;