library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.numeric_std.all; package cic_utils is -- parametros de diseƱo del filtro CIC ---------------------------------------- constant MANTISSA_BITS : integer := 24; constant NUMBER_BITS : integer := 32; -- incluye bit de signo constant FIXWIDTH : integer := NUMBER_BITS + MANTISSA_BITS; constant STAGES : integer := 5; -- orden del filtro CIC (numero de etapas) -- no modificar --------------------------------------------------------------- subtype fixpoint is std_logic_vector(FIXWIDTH-1 downto 0); function "*"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; function "/"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; function "+"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; function "-"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; function to_fix(a: integer) return std_logic_vector; constant MAX_M2_DEC : integer := 19; constant ONE: integer := 2**MANTISSA_BITS; end cic_utils; package body cic_utils is -- operaciones aritmeticas de punto fijo function "*" ( a: std_logic_vector ; b: std_logic_vector) return std_logic_vector is variable ret : std_logic_vector(2*FIXWIDTH-1 downto 0); begin ret := std_logic_vector(signed(a)*signed(b)); return ret(a'length+MANTISSA_BITS-1 downto MANTISSA_BITS); end "*"; function "/" (a: std_logic_vector ; b: std_logic_vector) return std_logic_vector is variable ret : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0); variable tmp : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0):=(others=>'0'); begin for i in 0 to a'length-1 loop tmp(i+MANTISSA_BITS ) := a(i); end loop; ret := std_logic_vector(signed(tmp)/signed(b)); return ret(a'length-1 downto 0); end "/"; function "+" (a: std_logic_vector ; b: std_logic_vector) return std_logic_vector is variable ret : std_logic_vector(a'length-1 downto 0); begin ret := std_logic_vector(signed(a)+signed(b)); return ret; end "+"; function "-" (a: std_logic_vector ; b: std_logic_vector) return std_logic_vector is variable ret : std_logic_vector(a'length-1 downto 0); begin ret := std_logic_vector(signed(a)-signed(b)); return ret; end "-"; -- function to_fix(a: integer) return std_logic_vector is variable ret : std_logic_vector(FIXWIDTH-1 downto 0); begin ret := std_logic_vector(to_signed(a,FIXWIDTH)); return ret; end to_fix; end cic_utils;