---------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;

use work.cic_utils.all;

--**********************************************************************************

entity Hr is
    Port ( clk : in  std_logic;
           reset: in std_logic;
           N : in  integer range 1 to MAX_M2_DEC;
           input : in std_logic_vector(FIXWIDTH-1 downto 0);
           output : out std_logic_vector(FIXWIDTH-1 downto 0)
           );
end Hr;

--**********************************************************************************

architecture filter of Hr is
		
		-------------------------------------------------------------
		component hr_block
			Port ( clk   : in std_logic;
					 reset : in std_logic;
					 input : in  std_logic_vector(FIXWIDTH-1 downto 0);
					 output : out std_logic_vector(FIXWIDTH-1 downto 0);
					 ka    : in std_logic_vector(4 downto 0);
					 kb    : in std_logic_vector(4 downto 0);
					 enb  : in std_logic);
		end component hr_block;
		-------------------------------------------------------------
		component clk_div
			 Port ( clkin : in  STD_LOGIC;
					  clkout: out STD_LOGIC;
					  reset : in std_logic;
					  N : in  integer range 1 to 19);
		end component clk_div;
		-------------------------------------------------------------
		type conn is array (0 to MAX_M2_DEC-1) of std_logic_vector(FIXWIDTH-1 downto 0);
		signal s1,s2,s3: conn;
		signal s4:std_logic_vector(FIXWIDTH-1 downto 0);
		signal clkd: std_logic;
		type enab is array (0 to MAX_M2_DEC-1) of std_logic;
		signal enb: enab;
		type k is array (0 to MAX_M2_DEC-1) of std_logic_vector(4 downto 0);
		constant ka:k := ("00000","00001","00010","00011",
								"00100","00101","00110","00111",
								"01000","01001","01010","01011",
								"01100","01101","01110","01111",
								"10000","10001","10010");
		signal kb:k;
		
begin
		s1(0) <= input;
		output <= s4;
		
		clkdiv: clk_div port map(
				clkin => clk,
				clkout => clkd,
				reset => reset,
				N => N
				);
						
		--/////////////////////////////////////////////////////////////////////////////////
		hr_filter: for i in 0 to MAX_M2_DEC-1 generate
		begin	
				-------------------------------------------------------------
			
				Gk: component hr_block
					-- (clk,reset,input,output,ka,kb,encb)
					port map (clkd,reset,s2(i),s3(i),ka(i),kb(i),enb(i));
				-------------------------------------------------------------
		end generate hr_filter;
		--/////////////////////////////////////////////////////////////////////////////////

	
		-- shift registers --
		process(clk,reset)
		begin
			if reset='1' then
				for i in 1 to MAX_M2_DEC-1 loop
					s1(i) <= (others=>'0');
				end loop;
			elsif clk'event and clk='1' then
				for i in MAX_M2_DEC-1 downto 1 loop
					s1(i) <= s1(i-1);
				end loop;
			end if;
		end process;
		
		
	
		-- implementa a los decimadores, cada vez que haya un flanco de subida
		-- en el clock clkd (clkd = clk / N), pasa una muestra al lado de baja
		-- frecuencia del filtro.
		--  la salida final del filtro es la suma de las salidas de los bloques.
		process(clkd,reset)
		begin
			if reset='1' then
				for i in 0 to MAX_M2_DEC-1 loop
					s2(i) <= (others=>'0');
				end loop;
			elsif clkd'event and clkd='1' then
				for i in 0 to MAX_M2_DEC-1 loop
					s2(i) <= s1(i);
				end loop;
			end if;
		end process;
		
	
--		process(s3)
--		variable acum : std_logic_vector(FIXWIDTH-1 downto 0);
--		begin
--			acum := s3(0);
--			for i in 1 to MAX_M2_DEC-1 loop
--				acum := acum+s3(i);
--			end loop;
--			s4 <= acum;
--		end process;
		
		s4 <= s3(0)+s3(1)+s3(2)+s3(3)+s3(4)+s3(5)+
				  s3(6)+s3(7)+s3(8)+s3(9)+s3(10)+s3(11)+
				  s3(12)+s3(13)+s3(14)+s3(15)+s3(16)+s3(17)+s3(18);
	
		process(N)
		begin
			for i in 0 to MAX_M2_DEC-1 loop
				if N-1 > i then
					kb(i) <= std_logic_vector(to_unsigned(N-i-2,kb(i)'length));
				else
					kb(i) <= std_logic_vector(to_unsigned(19,kb(i)'length));
				end if;
				
				if N-1 >= i then
					enb(i) <= '1';
				else
					enb(i) <= '0';
				end if;
			end loop;
		end process;
		
end filter;

--**********************************************************************************