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-- Company: 
-- Engineer: 
-- 
-- Create Date:    17:26:48 03/19/2015 
-- Design Name: 
-- Module Name:    integra_gain1 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

use work.cic_utils.all;

-- entity declaration --------------------------------


entity integra_gain1 is
		port (
			clk : in std_logic;
			N : in  integer range 1 to MAX_M2_DEC;
			input : in std_logic_vector(FIXWIDTH-1 downto 0);
			output : out std_logic_vector(FIXWIDTH-1 downto 0)
		);
end integra_gain1;

architecture Behavioral of integra_gain1 is
	component integrator
		port (
			clk : in std_logic;
			input : in std_logic_vector(FIXWIDTH-1 downto 0);
			output : out std_logic_vector(FIXWIDTH-1 downto 0)
		);
	end component;
	signal s1 ,s2: std_logic_vector(FIXWIDTH-1 downto 0);
begin
	inte: integrator port map(
				clk => clk,
				input => input,
				output => s1
				);

	s2 <= to_fix(ONE/N);
	output <= s2*s1;
end Behavioral;