----------------------------------------------------------------------------------
-- Company: company
-- Engineer: shinobi
-- 
-- Create Date:    Mar 9, 2015  -   5:10:57 PM
-- Design Name:  modulename
-- Module Name:  comb
-- Project Name:  projectname
-- Description: 
--
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;

use work.cic_utils.all;

-- entity declaration --------------------------------
entity comb is
	port (
		clk : in std_logic;
		input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
		output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
	);
end entity comb;


-- architecture declaration------------------------
architecture simple of comb is
	signal s_in_1 : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
	signal s_in : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
begin
	process(clk)
	begin
		if clk'event and clk = '1' then  
	      	s_in_1 <= s_in;
	   	end if;
	end process;
	output <= sust(input ,s_in_1);
	s_in <= input;
	
		
end architecture simple;