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<pin name="IO_L64N_SCP4_0" x="5.08" y="-25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L65P_SCP3_0" x="5.08" y="-27.94" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L65N_SCP2_0" x="5.08" y="-30.48" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L66P_SCP1_0" x="5.08" y="-33.02" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L66N_SCP0_0" x="5.08" y="-35.56" length="middle" swaplevel="1" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_1">
<wire x1="-10.16" y1="35.56" x2="0" y2="35.56" width="0.254" layer="94"/>
<wire x1="0" y1="35.56" x2="0" y2="-35.56" width="0.254" layer="94"/>
<wire x1="0" y1="-35.56" x2="-10.16" y2="-35.56" width="0.254" layer="94"/>
<text x="0" y="36.322" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-38.1" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="VCCO_1@0" x="5.08" y="33.02" length="middle" direction="in" rot="R180"/>
<pin name="VCCO_1@1" x="5.08" y="30.48" length="middle" direction="in" rot="R180"/>
<pin name="VCCO_1@2" x="5.08" y="27.94" length="middle" direction="in" rot="R180"/>
<pin name="IO_L1P_1" x="5.08" y="25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L1N_VREF_1" x="5.08" y="22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L32P_1" x="5.08" y="20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L32N_1" x="5.08" y="17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L33P_1" x="5.08" y="15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L33N_1" x="5.08" y="12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L34P_1" x="5.08" y="10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L34N_1" x="5.08" y="7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L40P_GCLK11_1" x="5.08" y="5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L40N_GCLK10_1" x="5.08" y="2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L41P_GCLK9_IRDY1_1" x="5.08" y="0" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L41N_GCLK8_1" x="5.08" y="-2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L42P_GCLK7_1" x="5.08" y="-5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L42N_GCLK6_TRDY1_1" x="5.08" y="-7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L43P_GCLK5_1" x="5.08" y="-10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L43N_GCLK4_1" x="5.08" y="-12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L45P_1" x="5.08" y="-15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L45N_1" x="5.08" y="-17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L46P_1" x="5.08" y="-20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L46N_1" x="5.08" y="-22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L47P_1" x="5.08" y="-25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L47N_1" x="5.08" y="-27.94" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L74P_AWAKE_1" x="5.08" y="-30.48" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L74N_DOUT_BUSY_1" x="5.08" y="-33.02" length="middle" swaplevel="1" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_2">
<wire x1="-10.16" y1="40.64" x2="0" y2="40.64" width="0.254" layer="94"/>
<wire x1="0" y1="40.64" x2="0" y2="-40.64" width="0.254" layer="94"/>
<wire x1="0" y1="-40.64" x2="-10.16" y2="-40.64" width="0.254" layer="94"/>
<text x="0" y="41.402" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-43.18" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="VCCO_2@0" x="5.08" y="38.1" length="middle" direction="in" rot="R180"/>
<pin name="VCCO_2@1" x="5.08" y="35.56" length="middle" direction="in" rot="R180"/>
<pin name="CMPCS_B_2" x="5.08" y="33.02" length="middle" rot="R180"/>
<pin name="DONE_2" x="5.08" y="30.48" length="middle" rot="R180"/>
<pin name="PROGRAM_B_2" x="5.08" y="27.94" length="middle" direction="in" rot="R180"/>
<pin name="IO_L1P_CCLK_2" x="5.08" y="25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L1N_M0_CMPMISO_2" x="5.08" y="22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L2P_CMPCLK_2" x="5.08" y="20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L2N_CMPMOSI_2" x="5.08" y="17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L3P_D0_DIN_MISO_MISO1_2" x="5.08" y="15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L3N_MOSI_CSI_B_MISO0_2" x="5.08" y="12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L12P_D1_MISO2_2" x="5.08" y="10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L12N_D2_MISO3_2" x="5.08" y="7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L13P_M1_2" x="5.08" y="5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L13N_D10_2" x="5.08" y="2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L14P_D11_2" x="5.08" y="0" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L14N_D12_2" x="5.08" y="-2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L30P_GCLK1_D13_2" x="5.08" y="-5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L30N_GCLK0_USERCCLK_2" x="5.08" y="-7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L31P_GCLK31_D14_2" x="5.08" y="-10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L31N_GCLK30_D15_2" x="5.08" y="-12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L48P_D7_2" x="5.08" y="-15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L48N_RDWR_B_VREF_2" x="5.08" y="-17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L49P_D3_2" x="5.08" y="-20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L49N_D4_2" x="5.08" y="-22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L62P_D5_2" x="5.08" y="-25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L62N_D6_2" x="5.08" y="-27.94" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L64P_D8_2" x="5.08" y="-30.48" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L64N_D9_2" x="5.08" y="-33.02" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L65P_INIT_B_2" x="5.08" y="-35.56" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L65N_CSO_B_2" x="5.08" y="-38.1" length="middle" swaplevel="1" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_3">
<wire x1="-10.16" y1="38.1" x2="0" y2="38.1" width="0.254" layer="94"/>
<wire x1="0" y1="38.1" x2="0" y2="-38.1" width="0.254" layer="94"/>
<wire x1="0" y1="-38.1" x2="-10.16" y2="-38.1" width="0.254" layer="94"/>
<text x="0" y="38.862" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-40.64" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="VCCO_3@0" x="5.08" y="35.56" length="middle" direction="in" rot="R180"/>
<pin name="VCCO_3@1" x="5.08" y="33.02" length="middle" direction="in" rot="R180"/>
<pin name="VCCO_3@2" x="5.08" y="30.48" length="middle" direction="in" rot="R180"/>
<pin name="IO_L1P_3" x="5.08" y="27.94" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L1N_VREF_3" x="5.08" y="25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L2P_3" x="5.08" y="22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L2N_3" x="5.08" y="20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L36P_3" x="5.08" y="17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L36N_3" x="5.08" y="15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L37P_3" x="5.08" y="12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L37N_3" x="5.08" y="10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L41P_GCLK27_3" x="5.08" y="7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L41N_GCLK26_3" x="5.08" y="5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L42P_GCLK25_TRDY2_3" x="5.08" y="2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L42N_GCLK24_3" x="5.08" y="0" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L43P_GCLK23_3" x="5.08" y="-2.54" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L43N_GCLK22_IRDY2_3" x="5.08" y="-5.08" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L44P_GCLK21_3" x="5.08" y="-7.62" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L44N_GCLK20_3" x="5.08" y="-10.16" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L49P_3" x="5.08" y="-12.7" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L49N_3" x="5.08" y="-15.24" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L50P_3" x="5.08" y="-17.78" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L50N_3" x="5.08" y="-20.32" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L51P_3" x="5.08" y="-22.86" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L51N_3" x="5.08" y="-25.4" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L52P_3" x="5.08" y="-27.94" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L52N_3" x="5.08" y="-30.48" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L83P_3" x="5.08" y="-33.02" length="middle" swaplevel="1" rot="R180"/>
<pin name="IO_L83N_VREF_3" x="5.08" y="-35.56" length="middle" swaplevel="1" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_GND">
<wire x1="-10.16" y1="17.78" x2="0" y2="17.78" width="0.254" layer="94"/>
<wire x1="0" y1="17.78" x2="0" y2="-17.78" width="0.254" layer="94"/>
<wire x1="0" y1="-17.78" x2="-10.16" y2="-17.78" width="0.254" layer="94"/>
<text x="0" y="18.542" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-20.32" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="GND@0" x="5.08" y="15.24" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@1" x="5.08" y="12.7" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@2" x="5.08" y="10.16" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@3" x="5.08" y="7.62" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@4" x="5.08" y="5.08" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@5" x="5.08" y="2.54" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@6" x="5.08" y="0" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@7" x="5.08" y="-2.54" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@8" x="5.08" y="-5.08" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@9" x="5.08" y="-7.62" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@10" x="5.08" y="-10.16" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@11" x="5.08" y="-12.7" length="middle" direction="pwr" rot="R180"/>
<pin name="GND@12" x="5.08" y="-15.24" length="middle" direction="pwr" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_NA">
<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/>
<wire x1="0" y1="7.62" x2="0" y2="-7.62" width="0.254" layer="94"/>
<wire x1="0" y1="-7.62" x2="-10.16" y2="-7.62" width="0.254" layer="94"/>
<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-10.16" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="SUSPEND" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/>
<pin name="TCK" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/>
<pin name="TDI" x="5.08" y="0" length="middle" direction="in" rot="R180"/>
<pin name="TDO" x="5.08" y="-2.54" length="middle" direction="out" rot="R180"/>
<pin name="TMS" x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_VCCAUX">
<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/>
<wire x1="0" y1="7.62" x2="0" y2="-7.62" width="0.254" layer="94"/>
<wire x1="0" y1="-7.62" x2="-10.16" y2="-7.62" width="0.254" layer="94"/>
<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-10.16" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="VCCAUX@0" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/>
<pin name="VCCAUX@1" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/>
<pin name="VCCAUX@2" x="5.08" y="0" length="middle" direction="in" rot="R180"/>
<pin name="VCCAUX@3" x="5.08" y="-2.54" length="middle" direction="in" rot="R180"/>
<pin name="VCCAUX@4" x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/>
</symbol>
<symbol name="6SLX9TQG144_VCCINT">
<wire x1="-10.16" y1="7.62" x2="0" y2="7.62" width="0.254" layer="94"/>
<wire x1="0" y1="7.62" x2="0" y2="-7.62" width="0.254" layer="94"/>
<wire x1="0" y1="-7.62" x2="-10.16" y2="-7.62" width="0.254" layer="94"/>
<text x="0" y="8.382" size="1.778" layer="95" rot="MR0">&gt;NAME</text>
<text x="0" y="-10.16" size="1.778" layer="96" rot="MR0">&gt;VALUE</text>
<pin name="VCCINT@0" x="5.08" y="5.08" length="middle" direction="in" rot="R180"/>
<pin name="VCCINT@1" x="5.08" y="2.54" length="middle" direction="in" rot="R180"/>
<pin name="VCCINT@2" x="5.08" y="0" length="middle" direction="in" rot="R180"/>
<pin name="VCCINT@3" x="5.08" y="-2.54" length="middle" direction="in" rot="R180"/>
<pin name="VCCINT@4" x="5.08" y="-5.08" length="middle" direction="in" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="6SLX9TQG144" prefix="U">
<description>Xilinx FPGA: 6SLX9TQG144</description>
<gates>
<gate name="B0" symbol="6SLX9TQG144_0" x="0" y="0"/>
<gate name="B1" symbol="6SLX9TQG144_1" x="45.72" y="0"/>
<gate name="B2" symbol="6SLX9TQG144_2" x="91.44" y="0"/>
<gate name="B3" symbol="6SLX9TQG144_3" x="137.16" y="0"/>
<gate name="BGND" symbol="6SLX9TQG144_GND" x="182.88" y="0"/>
<gate name="BNA" symbol="6SLX9TQG144_NA" x="228.6" y="0"/>
<gate name="BVCCAUX" symbol="6SLX9TQG144_VCCAUX" x="274.32" y="0"/>
<gate name="BVCCINT" symbol="6SLX9TQG144_VCCINT" x="320.04" y="0"/>
</gates>
<devices>
<device name="" package="TQ144">
<connects>
<connect gate="B0" pin="IO_L1N_VREF_0" pad="P143"/>
<connect gate="B0" pin="IO_L1P_HSWAPEN_0" pad="P144"/>
<connect gate="B0" pin="IO_L2N_0" pad="P141"/>
<connect gate="B0" pin="IO_L2P_0" pad="P142"/>
<connect gate="B0" pin="IO_L34N_GCLK18_0" pad="P133"/>
<connect gate="B0" pin="IO_L34P_GCLK19_0" pad="P134"/>
<connect gate="B0" pin="IO_L35N_GCLK16_0" pad="P131"/>
<connect gate="B0" pin="IO_L35P_GCLK17_0" pad="P132"/>
<connect gate="B0" pin="IO_L36N_GCLK14_0" pad="P126"/>
<connect gate="B0" pin="IO_L36P_GCLK15_0" pad="P127"/>
<connect gate="B0" pin="IO_L37N_GCLK12_0" pad="P123"/>
<connect gate="B0" pin="IO_L37P_GCLK13_0" pad="P124"/>
<connect gate="B0" pin="IO_L3N_0" pad="P139"/>
<connect gate="B0" pin="IO_L3P_0" pad="P140"/>
<connect gate="B0" pin="IO_L4N_0" pad="P137"/>
<connect gate="B0" pin="IO_L4P_0" pad="P138"/>
<connect gate="B0" pin="IO_L62N_VREF_0" pad="P120"/>
<connect gate="B0" pin="IO_L62P_0" pad="P121"/>
<connect gate="B0" pin="IO_L63N_SCP6_0" pad="P118"/>
<connect gate="B0" pin="IO_L63P_SCP7_0" pad="P119"/>
<connect gate="B0" pin="IO_L64N_SCP4_0" pad="P116"/>
<connect gate="B0" pin="IO_L64P_SCP5_0" pad="P117"/>
<connect gate="B0" pin="IO_L65N_SCP2_0" pad="P114"/>
<connect gate="B0" pin="IO_L65P_SCP3_0" pad="P115"/>
<connect gate="B0" pin="IO_L66N_SCP0_0" pad="P111"/>
<connect gate="B0" pin="IO_L66P_SCP1_0" pad="P112"/>
<connect gate="B0" pin="VCCO_0@0" pad="P122"/>
<connect gate="B0" pin="VCCO_0@1" pad="P125"/>
<connect gate="B0" pin="VCCO_0@2" pad="P135"/>
<connect gate="B1" pin="IO_L1N_VREF_1" pad="P104"/>
<connect gate="B1" pin="IO_L1P_1" pad="P105"/>
<connect gate="B1" pin="IO_L32N_1" pad="P101"/>
<connect gate="B1" pin="IO_L32P_1" pad="P102"/>
<connect gate="B1" pin="IO_L33N_1" pad="P99"/>
<connect gate="B1" pin="IO_L33P_1" pad="P100"/>
<connect gate="B1" pin="IO_L34N_1" pad="P97"/>
<connect gate="B1" pin="IO_L34P_1" pad="P98"/>
<connect gate="B1" pin="IO_L40N_GCLK10_1" pad="P94"/>
<connect gate="B1" pin="IO_L40P_GCLK11_1" pad="P95"/>
<connect gate="B1" pin="IO_L41N_GCLK8_1" pad="P92"/>
<connect gate="B1" pin="IO_L41P_GCLK9_IRDY1_1" pad="P93"/>
<connect gate="B1" pin="IO_L42N_GCLK6_TRDY1_1" pad="P87"/>
<connect gate="B1" pin="IO_L42P_GCLK7_1" pad="P88"/>
<connect gate="B1" pin="IO_L43N_GCLK4_1" pad="P84"/>
<connect gate="B1" pin="IO_L43P_GCLK5_1" pad="P85"/>
<connect gate="B1" pin="IO_L45N_1" pad="P82"/>
<connect gate="B1" pin="IO_L45P_1" pad="P83"/>
<connect gate="B1" pin="IO_L46N_1" pad="P80"/>
<connect gate="B1" pin="IO_L46P_1" pad="P81"/>
<connect gate="B1" pin="IO_L47N_1" pad="P78"/>
<connect gate="B1" pin="IO_L47P_1" pad="P79"/>
<connect gate="B1" pin="IO_L74N_DOUT_BUSY_1" pad="P74"/>
<connect gate="B1" pin="IO_L74P_AWAKE_1" pad="P75"/>
<connect gate="B1" pin="VCCO_1@0" pad="P76"/>
<connect gate="B1" pin="VCCO_1@1" pad="P86"/>
<connect gate="B1" pin="VCCO_1@2" pad="P103"/>
<connect gate="B2" pin="CMPCS_B_2" pad="P72"/>
<connect gate="B2" pin="DONE_2" pad="P71"/>
<connect gate="B2" pin="IO_L12N_D2_MISO3_2" pad="P61"/>
<connect gate="B2" pin="IO_L12P_D1_MISO2_2" pad="P62"/>
<connect gate="B2" pin="IO_L13N_D10_2" pad="P59"/>
<connect gate="B2" pin="IO_L13P_M1_2" pad="P60"/>
<connect gate="B2" pin="IO_L14N_D12_2" pad="P57"/>
<connect gate="B2" pin="IO_L14P_D11_2" pad="P58"/>
<connect gate="B2" pin="IO_L1N_M0_CMPMISO_2" pad="P69"/>
<connect gate="B2" pin="IO_L1P_CCLK_2" pad="P70"/>
<connect gate="B2" pin="IO_L2N_CMPMOSI_2" pad="P66"/>
<connect gate="B2" pin="IO_L2P_CMPCLK_2" pad="P67"/>
<connect gate="B2" pin="IO_L30N_GCLK0_USERCCLK_2" pad="P55"/>
<connect gate="B2" pin="IO_L30P_GCLK1_D13_2" pad="P56"/>
<connect gate="B2" pin="IO_L31N_GCLK30_D15_2" pad="P50"/>
<connect gate="B2" pin="IO_L31P_GCLK31_D14_2" pad="P51"/>
<connect gate="B2" pin="IO_L3N_MOSI_CSI_B_MISO0_2" pad="P64"/>
<connect gate="B2" pin="IO_L3P_D0_DIN_MISO_MISO1_2" pad="P65"/>
<connect gate="B2" pin="IO_L48N_RDWR_B_VREF_2" pad="P47"/>
<connect gate="B2" pin="IO_L48P_D7_2" pad="P48"/>
<connect gate="B2" pin="IO_L49N_D4_2" pad="P45"/>
<connect gate="B2" pin="IO_L49P_D3_2" pad="P46"/>
<connect gate="B2" pin="IO_L62N_D6_2" pad="P43"/>
<connect gate="B2" pin="IO_L62P_D5_2" pad="P44"/>
<connect gate="B2" pin="IO_L64N_D9_2" pad="P40"/>
<connect gate="B2" pin="IO_L64P_D8_2" pad="P41"/>
<connect gate="B2" pin="IO_L65N_CSO_B_2" pad="P38"/>
<connect gate="B2" pin="IO_L65P_INIT_B_2" pad="P39"/>
<connect gate="B2" pin="PROGRAM_B_2" pad="P37"/>
<connect gate="B2" pin="VCCO_2@0" pad="P42"/>
<connect gate="B2" pin="VCCO_2@1" pad="P63"/>
<connect gate="B3" pin="IO_L1N_VREF_3" pad="P34"/>
<connect gate="B3" pin="IO_L1P_3" pad="P35"/>
<connect gate="B3" pin="IO_L2N_3" pad="P32"/>
<connect gate="B3" pin="IO_L2P_3" pad="P33"/>
<connect gate="B3" pin="IO_L36N_3" pad="P29"/>
<connect gate="B3" pin="IO_L36P_3" pad="P30"/>
<connect gate="B3" pin="IO_L37N_3" pad="P26"/>
<connect gate="B3" pin="IO_L37P_3" pad="P27"/>
<connect gate="B3" pin="IO_L41N_GCLK26_3" pad="P23"/>
<connect gate="B3" pin="IO_L41P_GCLK27_3" pad="P24"/>
<connect gate="B3" pin="IO_L42N_GCLK24_3" pad="P21"/>
<connect gate="B3" pin="IO_L42P_GCLK25_TRDY2_3" pad="P22"/>
<connect gate="B3" pin="IO_L43N_GCLK22_IRDY2_3" pad="P16"/>
<connect gate="B3" pin="IO_L43P_GCLK23_3" pad="P17"/>
<connect gate="B3" pin="IO_L44N_GCLK20_3" pad="P14"/>
<connect gate="B3" pin="IO_L44P_GCLK21_3" pad="P15"/>
<connect gate="B3" pin="IO_L49N_3" pad="P11"/>
<connect gate="B3" pin="IO_L49P_3" pad="P12"/>
<connect gate="B3" pin="IO_L50N_3" pad="P9"/>
<connect gate="B3" pin="IO_L50P_3" pad="P10"/>
<connect gate="B3" pin="IO_L51N_3" pad="P7"/>
<connect gate="B3" pin="IO_L51P_3" pad="P8"/>
<connect gate="B3" pin="IO_L52N_3" pad="P5"/>
<connect gate="B3" pin="IO_L52P_3" pad="P6"/>
<connect gate="B3" pin="IO_L83N_VREF_3" pad="P1"/>
<connect gate="B3" pin="IO_L83P_3" pad="P2"/>
<connect gate="B3" pin="VCCO_3@0" pad="P4"/>
<connect gate="B3" pin="VCCO_3@1" pad="P18"/>
<connect gate="B3" pin="VCCO_3@2" pad="P31"/>
<connect gate="BGND" pin="GND@0" pad="P3"/>
<connect gate="BGND" pin="GND@1" pad="P13"/>
<connect gate="BGND" pin="GND@10" pad="P113"/>
<connect gate="BGND" pin="GND@11" pad="P130"/>
<connect gate="BGND" pin="GND@12" pad="P136"/>
<connect gate="BGND" pin="GND@2" pad="P25"/>
<connect gate="BGND" pin="GND@3" pad="P49"/>
<connect gate="BGND" pin="GND@4" pad="P54"/>
<connect gate="BGND" pin="GND@5" pad="P68"/>
<connect gate="BGND" pin="GND@6" pad="P77"/>
<connect gate="BGND" pin="GND@7" pad="P91"/>
<connect gate="BGND" pin="GND@8" pad="P96"/>
<connect gate="BGND" pin="GND@9" pad="P108"/>
<connect gate="BNA" pin="SUSPEND" pad="P73"/>
<connect gate="BNA" pin="TCK" pad="P109"/>
<connect gate="BNA" pin="TDI" pad="P110"/>
<connect gate="BNA" pin="TDO" pad="P106"/>
<connect gate="BNA" pin="TMS" pad="P107"/>
<connect gate="BVCCAUX" pin="VCCAUX@0" pad="P20"/>
<connect gate="BVCCAUX" pin="VCCAUX@1" pad="P36"/>
<connect gate="BVCCAUX" pin="VCCAUX@2" pad="P53"/>
<connect gate="BVCCAUX" pin="VCCAUX@3" pad="P90"/>
<connect gate="BVCCAUX" pin="VCCAUX@4" pad="P129"/>
<connect gate="BVCCINT" pin="VCCINT@0" pad="P19"/>
<connect gate="BVCCINT" pin="VCCINT@1" pad="P28"/>
<connect gate="BVCCINT" pin="VCCINT@2" pad="P52"/>
<connect gate="BVCCINT" pin="VCCINT@3" pad="P89"/>
<connect gate="BVCCINT" pin="VCCINT@4" pad="P128"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="SparkFun-DigitalIC">
<description>&lt;h3&gt;SparkFun Electronics' preferred foot prints&lt;/h3&gt;
In this library you'll find all manner of digital ICs- microcontrollers, memory chips, logic chips, FPGAs, etc.&lt;br&gt;&lt;br&gt;
We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com.
&lt;br&gt;&lt;br&gt;
&lt;b&gt;Licensing:&lt;/b&gt; Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/
&lt;br&gt;&lt;br&gt;
You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage.</description>
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</packages>
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<pin name="ADBUS6" x="22.86" y="22.86" length="middle" rot="R180"/>
<pin name="ADBUS5" x="22.86" y="25.4" length="middle" rot="R180"/>
<pin name="SI/WUA" x="22.86" y="5.08" length="middle" rot="R180"/>
<pin name="ACBUS3" x="22.86" y="7.62" length="middle" rot="R180"/>
<pin name="ADBUS4" x="22.86" y="27.94" length="middle" rot="R180"/>
<pin name="ADBUS3" x="22.86" y="30.48" length="middle" rot="R180"/>
<pin name="ADBUS2" x="22.86" y="33.02" length="middle" rot="R180"/>
<pin name="ADBUS1" x="22.86" y="35.56" length="middle" rot="R180"/>
<pin name="ADBUS0" x="22.86" y="38.1" length="middle" rot="R180"/>
<pin name="VCC1" x="-20.32" y="38.1" length="middle" direction="pwr"/>
<pin name="AVCC" x="-20.32" y="33.02" length="middle"/>
<pin name="VCCIOB" x="-20.32" y="27.94" length="middle"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="FT2232D">
<description>USB to USART/FIFO/JTAG/SPI/I2C</description>
<gates>
<gate name="G$1" symbol="FT2232D" x="0" y="0"/>
</gates>
<devices>
<device name="" package="LQFP-48">
<connects>
<connect gate="G$1" pin="3V3OUT" pad="6"/>
<connect gate="G$1" pin="ACBUS0" pad="15"/>
<connect gate="G$1" pin="ACBUS1" pad="13"/>
<connect gate="G$1" pin="ACBUS2" pad="12"/>
<connect gate="G$1" pin="ACBUS3" pad="11"/>
<connect gate="G$1" pin="ADBUS0" pad="24"/>
<connect gate="G$1" pin="ADBUS1" pad="23"/>
<connect gate="G$1" pin="ADBUS2" pad="22"/>
<connect gate="G$1" pin="ADBUS3" pad="21"/>
<connect gate="G$1" pin="ADBUS4" pad="20"/>
<connect gate="G$1" pin="ADBUS5" pad="19"/>
<connect gate="G$1" pin="ADBUS6" pad="17"/>
<connect gate="G$1" pin="ADBUS7" pad="16"/>
<connect gate="G$1" pin="AGND" pad="45"/>
<connect gate="G$1" pin="AVCC" pad="46"/>
<connect gate="G$1" pin="BCBUS0" pad="30"/>
<connect gate="G$1" pin="BCBUS1" pad="29"/>
<connect gate="G$1" pin="BCBUS2" pad="28"/>
<connect gate="G$1" pin="BCBUS3" pad="27"/>
<connect gate="G$1" pin="BDBUS0" pad="40"/>
<connect gate="G$1" pin="BDBUS1" pad="39"/>
<connect gate="G$1" pin="BDBUS2" pad="38"/>
<connect gate="G$1" pin="BDBUS3" pad="37"/>
<connect gate="G$1" pin="BDBUS4" pad="36"/>
<connect gate="G$1" pin="BDBUS5" pad="35"/>
<connect gate="G$1" pin="BDBUS6" pad="33"/>
<connect gate="G$1" pin="BDBUS7" pad="32"/>
<connect gate="G$1" pin="EECS" pad="48"/>
<connect gate="G$1" pin="EEDATA" pad="2"/>
<connect gate="G$1" pin="EESK" pad="1"/>
<connect gate="G$1" pin="GND1" pad="18"/>
<connect gate="G$1" pin="GND2" pad="25"/>
<connect gate="G$1" pin="GND3" pad="34"/>
<connect gate="G$1" pin="GND4" pad="9"/>
<connect gate="G$1" pin="PWEN#" pad="41"/>
<connect gate="G$1" pin="RESET#" pad="4"/>
<connect gate="G$1" pin="RSTOUT#" pad="5"/>
<connect gate="G$1" pin="SI/WUA" pad="10"/>
<connect gate="G$1" pin="SI/WUB" pad="26"/>
<connect gate="G$1" pin="TEST" pad="47"/>
<connect gate="G$1" pin="USBDM" pad="8"/>
<connect gate="G$1" pin="USBDP" pad="7"/>
<connect gate="G$1" pin="VCC1" pad="3"/>
<connect gate="G$1" pin="VCC2" pad="42"/>
<connect gate="G$1" pin="VCCIOA" pad="14"/>
<connect gate="G$1" pin="VCCIOB" pad="31"/>
<connect gate="G$1" pin="XTIN" pad="43"/>
<connect gate="G$1" pin="XTOUT" pad="44"/>
</connects>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="SparkFun-Aesthetics">
<description>&lt;h3&gt;SparkFun Electronics' preferred foot prints&lt;/h3&gt;
In this library you'll find non-functional items- supply symbols, logos, notations, frame blocks, etc.&lt;br&gt;&lt;br&gt;
We've spent an enormous amount of time creating and checking these footprints and parts, but it is the end user's responsibility to ensure correctness and suitablity for a given componet or application. If you enjoy using this library, please buy one of our products at www.sparkfun.com.
&lt;br&gt;&lt;br&gt;
&lt;b&gt;Licensing:&lt;/b&gt; Creative Commons ShareAlike 4.0 International - https://creativecommons.org/licenses/by-sa/4.0/
&lt;br&gt;&lt;br&gt;
You are welcome to use this library for commercial purposes. For attribution, we ask that when you begin to sell your device using our footprint, you email us with a link to the product being sold. We want bragging rights that we helped (in a very small part) to create your 8th world wonder. We would like the opportunity to feature your device on our homepage.</description>
<packages>
</packages>
<symbols>
<symbol name="DGND">
<wire x1="-1.905" y1="0" x2="1.905" y2="0" width="0.254" layer="94"/>
<text x="-2.54" y="-2.54" size="1.778" layer="96">&gt;VALUE</text>
<pin name="GND" x="0" y="2.54" visible="off" length="short" direction="sup" rot="R270"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="GND" prefix="GND">
<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
<gates>
<gate name="1" symbol="DGND" x="0" y="0"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
<library name="supply2">
<description>&lt;b&gt;Supply Symbols&lt;/b&gt;&lt;p&gt;
GND, VCC, 0V, +5V, -5V, etc.&lt;p&gt;
Please keep in mind, that these devices are necessary for the
automatic wiring of the supply signals.&lt;p&gt;
The pin name defined in the symbol is identical to the net which is to be wired automatically.&lt;p&gt;
In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.&lt;p&gt;
&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
<packages>
</packages>
<symbols>
<symbol name="VDD">
<circle x="0" y="1.27" radius="1.27" width="0.254" layer="94"/>
<text x="-1.905" y="3.175" size="1.778" layer="96">&gt;VALUE</text>
<pin name="VDD" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="VDD" prefix="SUPPLY">
<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
<gates>
<gate name="G$1" symbol="VDD" x="0" y="0"/>
</gates>
<devices>
<device name="">
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</libraries>
<attributes>
</attributes>
<variantdefs>
</variantdefs>
<classes>
<class number="0" name="default" width="0" drill="0">
</class>
</classes>
<parts>
<part name="U1" library="xilinx_devices_V6" deviceset="6SLX9TQG144" device=""/>
<part name="U$1" library="SparkFun-DigitalIC" deviceset="FT2232D" device=""/>
<part name="GND1" library="SparkFun-Aesthetics" deviceset="GND" device=""/>
<part name="SUPPLY1" library="supply2" deviceset="VDD" device=""/>
<part name="SUPPLY2" library="supply2" deviceset="VDD" device=""/>
<part name="SUPPLY3" library="supply2" deviceset="VDD" device=""/>
<part name="SUPPLY4" library="supply2" deviceset="VDD" device=""/>
</parts>
<sheets>
<sheet>
<plain>
</plain>
<instances>
<instance part="U1" gate="B0" x="-17.78" y="205.74"/>
<instance part="U1" gate="B1" x="-137.16" y="210.82"/>
<instance part="U1" gate="B2" x="-22.86" y="88.9"/>
<instance part="U1" gate="B3" x="-137.16" y="86.36"/>
<instance part="U1" gate="BGND" x="-134.62" y="299.72"/>
<instance part="U1" gate="BNA" x="-93.98" y="355.6"/>
<instance part="U1" gate="BVCCAUX" x="-93.98" y="312.42"/>
<instance part="U1" gate="BVCCINT" x="-93.98" y="289.56"/>
<instance part="U$1" gate="G$1" x="-12.7" y="439.42"/>
<instance part="GND1" gate="1" x="-121.92" y="279.4"/>
<instance part="SUPPLY1" gate="G$1" x="-127" y="248.92"/>
<instance part="SUPPLY2" gate="G$1" x="-7.62" y="246.38"/>
<instance part="SUPPLY3" gate="G$1" x="-127" y="127"/>
<instance part="SUPPLY4" gate="G$1" x="-12.7" y="132.08"/>
</instances>
<busses>
</busses>
<nets>
<net name="GND" class="0">
<segment>
<pinref part="U1" gate="BGND" pin="GND@0"/>
<pinref part="GND1" gate="1" pin="GND"/>
<wire x1="-129.54" y1="314.96" x2="-121.92" y2="314.96" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="314.96" x2="-121.92" y2="312.42" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@1"/>
<wire x1="-121.92" y1="312.42" x2="-121.92" y2="309.88" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="309.88" x2="-121.92" y2="307.34" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="307.34" x2="-121.92" y2="304.8" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="304.8" x2="-121.92" y2="302.26" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="302.26" x2="-121.92" y2="299.72" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="299.72" x2="-121.92" y2="297.18" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="297.18" x2="-121.92" y2="294.64" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="294.64" x2="-121.92" y2="292.1" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="292.1" x2="-121.92" y2="289.56" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="289.56" x2="-121.92" y2="287.02" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="287.02" x2="-121.92" y2="284.48" width="0.1524" layer="91"/>
<wire x1="-121.92" y1="284.48" x2="-121.92" y2="281.94" width="0.1524" layer="91"/>
<wire x1="-129.54" y1="312.42" x2="-121.92" y2="312.42" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@2"/>
<wire x1="-129.54" y1="309.88" x2="-121.92" y2="309.88" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@3"/>
<wire x1="-129.54" y1="307.34" x2="-121.92" y2="307.34" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@4"/>
<wire x1="-129.54" y1="304.8" x2="-121.92" y2="304.8" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@5"/>
<wire x1="-129.54" y1="302.26" x2="-121.92" y2="302.26" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@6"/>
<wire x1="-129.54" y1="299.72" x2="-121.92" y2="299.72" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@7"/>
<wire x1="-129.54" y1="297.18" x2="-121.92" y2="297.18" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@8"/>
<wire x1="-129.54" y1="294.64" x2="-121.92" y2="294.64" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@9"/>
<wire x1="-129.54" y1="292.1" x2="-121.92" y2="292.1" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@10"/>
<wire x1="-129.54" y1="289.56" x2="-121.92" y2="289.56" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@11"/>
<wire x1="-129.54" y1="287.02" x2="-121.92" y2="287.02" width="0.1524" layer="91"/>
<pinref part="U1" gate="BGND" pin="GND@12"/>
<wire x1="-129.54" y1="284.48" x2="-121.92" y2="284.48" width="0.1524" layer="91"/>
<junction x="-121.92" y="284.48"/>
<junction x="-121.92" y="287.02"/>
<junction x="-121.92" y="289.56"/>
<junction x="-121.92" y="292.1"/>
<junction x="-121.92" y="294.64"/>
<junction x="-121.92" y="297.18"/>
<junction x="-121.92" y="299.72"/>
<junction x="-121.92" y="302.26"/>
<junction x="-121.92" y="304.8"/>
<junction x="-121.92" y="307.34"/>
<junction x="-121.92" y="309.88"/>
<junction x="-121.92" y="312.42"/>
</segment>
</net>
<net name="VDD" class="0">
<segment>
<pinref part="U1" gate="B1" pin="VCCO_1@2"/>
<pinref part="SUPPLY1" gate="G$1" pin="VDD"/>
<wire x1="-132.08" y1="238.76" x2="-127" y2="238.76" width="0.1524" layer="91"/>
<wire x1="-127" y1="238.76" x2="-127" y2="241.3" width="0.1524" layer="91"/>
<pinref part="U1" gate="B1" pin="VCCO_1@1"/>
<wire x1="-127" y1="241.3" x2="-127" y2="243.84" width="0.1524" layer="91"/>
<wire x1="-127" y1="243.84" x2="-127" y2="246.38" width="0.1524" layer="91"/>
<wire x1="-132.08" y1="241.3" x2="-127" y2="241.3" width="0.1524" layer="91"/>
<pinref part="U1" gate="B1" pin="VCCO_1@0"/>
<wire x1="-132.08" y1="243.84" x2="-127" y2="243.84" width="0.1524" layer="91"/>
<junction x="-127" y="241.3"/>
<junction x="-127" y="243.84"/>
</segment>
<segment>
<pinref part="U1" gate="B0" pin="VCCO_0@2"/>
<pinref part="SUPPLY2" gate="G$1" pin="VDD"/>
<wire x1="-12.7" y1="236.22" x2="-7.62" y2="236.22" width="0.1524" layer="91"/>
<wire x1="-7.62" y1="236.22" x2="-7.62" y2="238.76" width="0.1524" layer="91"/>
<pinref part="U1" gate="B0" pin="VCCO_0@1"/>
<wire x1="-7.62" y1="238.76" x2="-7.62" y2="241.3" width="0.1524" layer="91"/>
<wire x1="-7.62" y1="241.3" x2="-7.62" y2="243.84" width="0.1524" layer="91"/>
<wire x1="-12.7" y1="238.76" x2="-7.62" y2="238.76" width="0.1524" layer="91"/>
<pinref part="U1" gate="B0" pin="VCCO_0@0"/>
<wire x1="-12.7" y1="241.3" x2="-7.62" y2="241.3" width="0.1524" layer="91"/>
<junction x="-7.62" y="241.3"/>
<junction x="-7.62" y="238.76"/>
</segment>
<segment>
<pinref part="U1" gate="B3" pin="VCCO_3@2"/>
<pinref part="SUPPLY3" gate="G$1" pin="VDD"/>
<wire x1="-132.08" y1="116.84" x2="-127" y2="116.84" width="0.1524" layer="91"/>
<wire x1="-127" y1="116.84" x2="-127" y2="119.38" width="0.1524" layer="91"/>
<pinref part="U1" gate="B3" pin="VCCO_3@1"/>
<wire x1="-127" y1="119.38" x2="-127" y2="121.92" width="0.1524" layer="91"/>
<wire x1="-127" y1="121.92" x2="-127" y2="124.46" width="0.1524" layer="91"/>
<wire x1="-132.08" y1="119.38" x2="-127" y2="119.38" width="0.1524" layer="91"/>
<pinref part="U1" gate="B3" pin="VCCO_3@0"/>
<wire x1="-132.08" y1="121.92" x2="-127" y2="121.92" width="0.1524" layer="91"/>
<junction x="-127" y="119.38"/>
<junction x="-127" y="121.92"/>
</segment>
<segment>
<pinref part="U1" gate="B2" pin="VCCO_2@1"/>
<pinref part="SUPPLY4" gate="G$1" pin="VDD"/>
<wire x1="-17.78" y1="124.46" x2="-12.7" y2="124.46" width="0.1524" layer="91"/>
<wire x1="-12.7" y1="124.46" x2="-12.7" y2="127" width="0.1524" layer="91"/>
<pinref part="U1" gate="B2" pin="VCCO_2@0"/>
<wire x1="-12.7" y1="127" x2="-12.7" y2="129.54" width="0.1524" layer="91"/>
<wire x1="-17.78" y1="127" x2="-12.7" y2="127" width="0.1524" layer="91"/>
<junction x="-12.7" y="127"/>
</segment>
</net>
</nets>
</sheet>
</sheets>
</schematic>
</drawing>
</eagle>