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Release 14.7 - xst P.20131013 (nt64)
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Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--> Parameter TMPDIR set to xst/projnav.tmp
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Parameter xsthdpdir set to xst
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Total REAL time to Xst completion: 1.00 secs
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Total CPU time to Xst completion: 0.13 secs
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--> Reading design: FrontEnd_Acq.prj
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TABLE OF CONTENTS
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1) Synthesis Options Summary
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2) HDL Parsing
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3) HDL Elaboration
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4) HDL Synthesis
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4.1) HDL Synthesis Report
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5) Advanced HDL Synthesis
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5.1) Advanced HDL Synthesis Report
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6) Low Level Synthesis
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7) Partition Report
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8) Design Summary
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8.1) Primitive and Black Box Usage
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8.2) Device utilization summary
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8.3) Partition Resource Summary
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8.4) Timing Report
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8.4.1) Clock Information
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8.4.2) Asynchronous Control Signals Information
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8.4.3) Timing Summary
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8.4.4) Timing Details
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8.4.5) Cross Clock Domains Report
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=========================================================================
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* Synthesis Options Summary *
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=========================================================================
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---- Source Parameters
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Input File Name : "FrontEnd_Acq.prj"
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Ignore Synthesis Constraint File : NO
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---- Target Parameters
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Output File Name : "FrontEnd_Acq"
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Output Format : NGC
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Target Device : xc6slx9-3-tqg144
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---- Source Options
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Top Module Name : FrontEnd_Acq
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Automatic FSM Extraction : YES
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FSM Encoding Algorithm : Auto
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Safe Implementation : No
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FSM Style : LUT
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RAM Extraction : Yes
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RAM Style : Auto
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ROM Extraction : Yes
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Shift Register Extraction : YES
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ROM Style : Auto
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Resource Sharing : YES
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Asynchronous To Synchronous : NO
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Shift Register Minimum Size : 2
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Use DSP Block : Auto
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Automatic Register Balancing : No
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---- Target Options
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LUT Combining : Auto
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Reduce Control Sets : Auto
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Add IO Buffers : YES
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Global Maximum Fanout : 100000
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Add Generic Clock Buffer(BUFG) : 16
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Register Duplication : YES
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Optimize Instantiated Primitives : NO
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Use Clock Enable : Auto
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Use Synchronous Set : Auto
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Use Synchronous Reset : Auto
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Pack IO Registers into IOBs : Auto
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Equivalent register Removal : YES
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---- General Options
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Optimization Goal : Speed
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Optimization Effort : 1
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Power Reduction : NO
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Keep Hierarchy : No
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Netlist Hierarchy : As_Optimized
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RTL Output : Yes
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Global Optimization : AllClockNets
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Read Cores : YES
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Write Timing Constraints : NO
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Cross Clock Analysis : NO
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Hierarchy Separator : /
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Bus Delimiter : <>
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Case Specifier : Maintain
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Slice Utilization Ratio : 100
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BRAM Utilization Ratio : 100
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DSP48 Utilization Ratio : 100
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Auto BRAM Packing : NO
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Slice Utilization Ratio Delta : 5
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=========================================================================
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=========================================================================
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* HDL Parsing *
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=========================================================================
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Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" into library work
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Parsing entity <joiner_samp>.
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Parsing architecture <Behavioral> of entity <joiner_samp>.
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Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" into library work
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Parsing entity <DtoDPRAM>.
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Parsing architecture <Behavioral> of entity <dtodpram>.
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Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd" into library work
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Parsing entity <DCM_fwd_int>.
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Parsing architecture <Behavioral> of entity <dcm_fwd_int>.
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Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd" into library work
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Parsing entity <Data_Req_gen>.
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Parsing architecture <Behavioral> of entity <data_req_gen>.
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Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd" into library work
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Parsing entity <FrontEnd_Acq>.
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Parsing architecture <Behavioral> of entity <frontend_acq>.
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=========================================================================
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* HDL Elaboration *
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=========================================================================
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Elaborating entity <FrontEnd_Acq> (architecture <Behavioral>) with generics from library <work>.
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Elaborating entity <DCM_fwd_int> (architecture <Behavioral>) from library <work>.
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Elaborating entity <Data_Req_gen> (architecture <Behavioral>) with generics from library <work>.
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Elaborating entity <joiner_samp> (architecture <Behavioral>) with generics from library <work>.
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INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 183. Case statement is complete. others clause is never selected
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INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 220. Case statement is complete. others clause is never selected
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INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 315. Case statement is complete. others clause is never selected
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Elaborating entity <DtoDPRAM> (architecture <Behavioral>) with generics from library <work>.
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INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 228. Case statement is complete. others clause is never selected
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INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 469. Case statement is complete. others clause is never selected
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=========================================================================
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* HDL Synthesis *
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=========================================================================
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Synthesizing Unit <FrontEnd_Acq>.
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Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd".
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DBIT_SZ = 3
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ADDR_LENGTH = 12
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DATAOUT_LENGTH = 8
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CH_SZ = 5
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NBITS_PERIOD = 18
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NBITS_DUTY = 12
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NBITS_PULSES = 10
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RESUL_NP_SZ = 40
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ID_CH_SZ = 4
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Found 16-bit register for signal <cont_200MHz>.
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Found 1-bit register for signal <lock_rst_bar>.
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Found 16-bit adder for signal <cont_200MHz[15]_GND_5_o_add_1_OUT> created at line 1241.
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Summary:
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inferred 1 Adder/Subtractor(s).
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inferred 17 D-type flip-flop(s).
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Unit <FrontEnd_Acq> synthesized.
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Synthesizing Unit <DCM_fwd_int>.
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Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd".
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Summary:
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no macro.
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Unit <DCM_fwd_int> synthesized.
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Synthesizing Unit <Data_Req_gen>.
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Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd".
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NBITS_PERIOD = 18
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NBITS_DUTY = 12
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NBITS_PULSES = 10
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Found 1-bit register for signal <pps_rising>.
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Found 1-bit register for signal <data_req_s>.
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Found 18-bit register for signal <count_clock>.
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Found 10-bit register for signal <count_pulses>.
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Found 2-bit register for signal <pps_r>.
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Found 10-bit adder for signal <count_pulses[9]_GND_11_o_add_5_OUT> created at line 1241.
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Found 18-bit adder for signal <count_clock[17]_GND_11_o_add_10_OUT> created at line 1241.
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Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 32 D-type flip-flop(s).
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Unit <Data_Req_gen> synthesized.
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Synthesizing Unit <joiner_samp>.
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Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd".
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DBIT_SZ = 3
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BITS_COUNT_SZ = 3
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RESUL_NP_SZ = 40
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SAMPLE_SZ = 24
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SAMPLE_COUNT_SZ = 12
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HEADER_NIB_SZ = 4
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DATA_HEADER_NIB_SZ = 4
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CH_COUNT_SZ = 4
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Found 2-bit register for signal <chn_bits_acq_bit1>.
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Found 2-bit register for signal <chn_bits_acq_bit2>.
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Found 3-bit register for signal <clk_acq_r>.
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Found 1-bit register for signal <clk_acq_rise>.
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Found 1-bit register for signal <pack_cur_state>.
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Found 3-bit register for signal <dbits_counter>.
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Found 24-bit register for signal <resul_mem_internal>.
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Found 1-bit register for signal <resul_mem_internal_aux<35>>.
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Found 1-bit register for signal <resul_mem_internal_aux<34>>.
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Found 1-bit register for signal <resul_mem_internal_aux<33>>.
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Found 1-bit register for signal <resul_mem_internal_aux<32>>.
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Found 1-bit register for signal <resul_mem_internal_aux<31>>.
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Found 1-bit register for signal <resul_mem_internal_aux<30>>.
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Found 1-bit register for signal <resul_mem_internal_aux<29>>.
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Found 1-bit register for signal <resul_mem_internal_aux<28>>.
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Found 1-bit register for signal <resul_mem_internal_aux<27>>.
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Found 1-bit register for signal <resul_mem_internal_aux<26>>.
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Found 1-bit register for signal <resul_mem_internal_aux<25>>.
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Found 1-bit register for signal <resul_mem_internal_aux<24>>.
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Found 1-bit register for signal <resul_mem_internal_aux<23>>.
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Found 1-bit register for signal <resul_mem_internal_aux<22>>.
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Found 1-bit register for signal <resul_mem_internal_aux<21>>.
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Found 1-bit register for signal <resul_mem_internal_aux<20>>.
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Found 1-bit register for signal <resul_mem_internal_aux<19>>.
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Found 1-bit register for signal <resul_mem_internal_aux<18>>.
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Found 1-bit register for signal <resul_mem_internal_aux<17>>.
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Found 1-bit register for signal <resul_mem_internal_aux<16>>.
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Found 1-bit register for signal <resul_mem_internal_aux<15>>.
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Found 1-bit register for signal <resul_mem_internal_aux<14>>.
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Found 1-bit register for signal <resul_mem_internal_aux<13>>.
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Found 1-bit register for signal <resul_mem_internal_aux<12>>.
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Found 1-bit register for signal <resul_mem_internal_aux<11>>.
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Found 1-bit register for signal <resul_mem_internal_aux<10>>.
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Found 1-bit register for signal <resul_mem_internal_aux<9>>.
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Found 1-bit register for signal <resul_mem_internal_aux<8>>.
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Found 1-bit register for signal <resul_mem_internal_aux<7>>.
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Found 1-bit register for signal <resul_mem_internal_aux<6>>.
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Found 1-bit register for signal <resul_mem_internal_aux<5>>.
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Found 1-bit register for signal <resul_mem_internal_aux<4>>.
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Found 1-bit register for signal <resul_mem_internal_aux<3>>.
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Found 1-bit register for signal <resul_mem_internal_aux<2>>.
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Found 1-bit register for signal <resul_mem_internal_aux<1>>.
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Found 1-bit register for signal <resul_mem_internal_aux<0>>.
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Found 12-bit register for signal <samp_count>.
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Found 1-bit register for signal <rdy_mem_aux>.
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Found 2-bit register for signal <data_cur_state>.
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Found 2-bit register for signal <chn_bits_acq_bit0>.
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Found finite state machine <FSM_0> for signal <data_cur_state>.
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-----------------------------------------------------------------------
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| States | 3 |
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| Transitions | 6 |
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| Inputs | 2 |
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| Outputs | 4 |
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| Clock | clk_main (rising_edge) |
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| Reset | rst_bar_INV_14_o (positive) |
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| Reset type | synchronous |
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| Reset State | idle |
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| Power Up State | idle |
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| Encoding | auto |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 3-bit adder for signal <dbits_counter[2]_GND_12_o_add_13_OUT> created at line 1241.
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Found 12-bit adder for signal <samp_count[11]_GND_12_o_add_29_OUT> created at line 1241.
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Found 24-bit 8-to-1 multiplexer for signal <dbits_counter[2]_resul_mem_internal[23]_wide_mux_14_OUT> created at line 202.
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Summary:
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inferred 2 Adder/Subtractor(s).
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inferred 87 D-type flip-flop(s).
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inferred 4 Multiplexer(s).
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inferred 1 Finite State Machine(s).
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Unit <joiner_samp> synthesized.
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Synthesizing Unit <DtoDPRAM>.
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Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd".
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ADDR_LENGTH = 12
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DATAOUT_LENGTH = 8
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DATAIN_LENGTH = 40
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CHAN_NUM = 5
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COUNT_BYTE_SZ = 3
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COUNT_PACK_SZ = 6
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Found 4-bit register for signal <ram_contr_cur_state>.
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Found 6-bit register for signal <count_pack>.
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Found 1-bit register for signal <sel_buf>.
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Found 1-bit register for signal <rpi_req>.
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Found 3-bit register for signal <count_ch_byte>.
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Found 8-bit register for signal <datach1_aux>.
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Found 8-bit register for signal <datach2_aux>.
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Found 8-bit register for signal <datach3_aux>.
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Found 8-bit register for signal <datach4_aux>.
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Found 8-bit register for signal <datach5_aux>.
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Found 4-bit register for signal <ch_cont_cur_state>.
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Found finite state machine <FSM_1> for signal <ram_contr_cur_state>.
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-----------------------------------------------------------------------
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| States | 16 |
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| Transitions | 28 |
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| Inputs | 5 |
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| Outputs | 16 |
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| Clock | clk_main (rising_edge) |
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| Reset | rst_bar_INV_48_o (positive) |
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| Reset type | synchronous |
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| Reset State | idle |
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| Power Up State | idle |
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| Encoding | auto |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found finite state machine <FSM_2> for signal <ch_cont_cur_state>.
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-----------------------------------------------------------------------
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| States | 11 |
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| Transitions | 21 |
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| Inputs | 10 |
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| Outputs | 4 |
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| Clock | clk_main (rising_edge) |
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| Reset | rst_bar_INV_48_o (positive) |
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| Reset type | synchronous |
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| Reset State | idle |
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| Power Up State | idle |
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| Encoding | auto |
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| Implementation | LUT |
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-----------------------------------------------------------------------
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Found 6-bit adder for signal <count_pack[5]_GND_26_o_add_241_OUT> created at line 1241.
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Found 3-bit adder for signal <count_ch_byte[2]_GND_26_o_add_252_OUT> created at line 1241.
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Found 12-bit adder for signal <_n0507> created at line 302.
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Found 12-bit adder for signal <_n0508> created at line 302.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_61_OUT> created at line 302.
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Found 12-bit adder for signal <_n0512> created at line 304.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_67_OUT> created at line 304.
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Found 12-bit adder for signal <_n0516> created at line 341.
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Found 12-bit adder for signal <_n0517> created at line 341.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_102_OUT> created at line 341.
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Found 12-bit adder for signal <_n0521> created at line 343.
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Found 12-bit adder for signal <_n0522> created at line 343.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_108_OUT> created at line 343.
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Found 12-bit adder for signal <_n0526> created at line 380.
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Found 12-bit adder for signal <_n0527> created at line 380.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_143_OUT> created at line 380.
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Found 12-bit adder for signal <_n0531> created at line 382.
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Found 12-bit adder for signal <_n0532> created at line 382.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_149_OUT> created at line 382.
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Found 12-bit adder for signal <_n0536> created at line 419.
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Found 12-bit adder for signal <_n0537> created at line 419.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_184_OUT> created at line 419.
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Found 12-bit adder for signal <_n0541> created at line 421.
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Found 12-bit adder for signal <_n0542> created at line 421.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_190_OUT> created at line 421.
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Found 12-bit adder for signal <_n0546> created at line 458.
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Found 12-bit adder for signal <_n0547> created at line 458.
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Found 12-bit adder for signal <GND_26_o_GND_26_o_add_225_OUT> created at line 458.
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Found 12-bit adder for signal <_n0551> created at line 460.
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|
Found 12-bit adder for signal <_n0552> created at line 460.
|
|
|
Found 12-bit adder for signal <GND_26_o_GND_26_o_add_231_OUT> created at line 460.
|
|
|
Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_257_OUT> created at line 540.
|
|
|
Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_260_OUT> created at line 564.
|
|
|
Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_263_OUT> created at line 588.
|
|
|
Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_266_OUT> created at line 612.
|
|
|
Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_269_OUT> created at line 636.
|
|
|
Summary:
|
|
|
inferred 31 Adder/Subtractor(s).
|
|
|
inferred 51 D-type flip-flop(s).
|
|
|
inferred 31 Multiplexer(s).
|
|
|
inferred 2 Finite State Machine(s).
|
|
|
Unit <DtoDPRAM> synthesized.
|
|
|
|
|
|
=========================================================================
|
|
|
HDL Synthesis Report
|
|
|
|
|
|
Macro Statistics
|
|
|
# Adders/Subtractors : 44
|
|
|
10-bit adder : 1
|
|
|
12-bit adder : 34
|
|
|
16-bit adder : 1
|
|
|
18-bit adder : 1
|
|
|
3-bit adder : 6
|
|
|
6-bit adder : 1
|
|
|
# Registers : 191
|
|
|
1-bit register : 140
|
|
|
10-bit register : 1
|
|
|
12-bit register : 10
|
|
|
16-bit register : 1
|
|
|
18-bit register : 1
|
|
|
2-bit register : 16
|
|
|
24-bit register : 5
|
|
|
3-bit register : 11
|
|
|
6-bit register : 1
|
|
|
8-bit register : 5
|
|
|
# Multiplexers : 51
|
|
|
1-bit 2-to-1 multiplexer : 5
|
|
|
12-bit 2-to-1 multiplexer : 15
|
|
|
24-bit 8-to-1 multiplexer : 5
|
|
|
3-bit 2-to-1 multiplexer : 6
|
|
|
40-bit 2-to-1 multiplexer : 5
|
|
|
8-bit 2-to-1 multiplexer : 10
|
|
|
8-bit 7-to-1 multiplexer : 5
|
|
|
# FSMs : 7
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
|
* Advanced HDL Synthesis *
|
|
|
=========================================================================
|
|
|
|
|
|
|
|
|
Synthesizing (advanced) Unit <Data_Req_gen>.
|
|
|
The following registers are absorbed into counter <count_pulses>: 1 register on signal <count_pulses>.
|
|
|
The following registers are absorbed into counter <count_clock>: 1 register on signal <count_clock>.
|
|
|
Unit <Data_Req_gen> synthesized (advanced).
|
|
|
|
|
|
Synthesizing (advanced) Unit <DtoDPRAM>.
|
|
|
The following registers are absorbed into counter <count_ch_byte>: 1 register on signal <count_ch_byte>.
|
|
|
The following registers are absorbed into counter <count_pack>: 1 register on signal <count_pack>.
|
|
|
Unit <DtoDPRAM> synthesized (advanced).
|
|
|
|
|
|
Synthesizing (advanced) Unit <FrontEnd_Acq>.
|
|
|
The following registers are absorbed into counter <cont_200MHz>: 1 register on signal <cont_200MHz>.
|
|
|
Unit <FrontEnd_Acq> synthesized (advanced).
|
|
|
|
|
|
Synthesizing (advanced) Unit <joiner_samp>.
|
|
|
The following registers are absorbed into counter <samp_count>: 1 register on signal <samp_count>.
|
|
|
The following registers are absorbed into counter <dbits_counter>: 1 register on signal <dbits_counter>.
|
|
|
Unit <joiner_samp> synthesized (advanced).
|
|
|
|
|
|
=========================================================================
|
|
|
Advanced HDL Synthesis Report
|
|
|
|
|
|
Macro Statistics
|
|
|
# Adders/Subtractors : 29
|
|
|
12-bit adder : 29
|
|
|
# Counters : 15
|
|
|
10-bit up counter : 1
|
|
|
12-bit up counter : 5
|
|
|
16-bit up counter : 1
|
|
|
18-bit up counter : 1
|
|
|
3-bit up counter : 6
|
|
|
6-bit up counter : 1
|
|
|
# Registers : 407
|
|
|
Flip-Flops : 407
|
|
|
# Multiplexers : 82
|
|
|
1-bit 2-to-1 multiplexer : 48
|
|
|
12-bit 2-to-1 multiplexer : 15
|
|
|
24-bit 8-to-1 multiplexer : 5
|
|
|
40-bit 2-to-1 multiplexer : 5
|
|
|
8-bit 2-to-1 multiplexer : 4
|
|
|
8-bit 7-to-1 multiplexer : 5
|
|
|
# FSMs : 7
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
|
* Low Level Synthesis *
|
|
|
=========================================================================
|
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
|
Optimizing FSM <empa_ch1/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
|
|
|
Optimizing FSM <empa_ch2/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
|
|
|
Optimizing FSM <empa_ch3/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
|
|
|
Optimizing FSM <empa_ch4/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
|
|
|
Optimizing FSM <empa_ch5/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
|
|
|
-----------------------
|
|
|
State | Encoding
|
|
|
-----------------------
|
|
|
idle | 00
|
|
|
data_pres | 01
|
|
|
data_proc | 11
|
|
|
-----------------------
|
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
|
Optimizing FSM <controlador_DPRAM/FSM_2> on signal <ch_cont_cur_state[1:4]> with user encoding.
|
|
|
---------------------------
|
|
|
State | Encoding
|
|
|
---------------------------
|
|
|
idle | 0000
|
|
|
checking_ch1 | 0001
|
|
|
attending_ch1 | 0010
|
|
|
checking_ch2 | 0011
|
|
|
attending_ch2 | 0100
|
|
|
checking_ch3 | 0101
|
|
|
attending_ch3 | 0110
|
|
|
checking_ch4 | 0111
|
|
|
attending_ch4 | 1000
|
|
|
checking_ch5 | 1001
|
|
|
attending_ch5 | 1010
|
|
|
---------------------------
|
|
|
Analyzing FSM <MFsm> for best encoding.
|
|
|
Optimizing FSM <controlador_DPRAM/FSM_1> on signal <ram_contr_cur_state[1:4]> with sequential encoding.
|
|
|
--------------------------
|
|
|
State | Encoding
|
|
|
--------------------------
|
|
|
idle | 0000
|
|
|
pre_ch1 | 0001
|
|
|
wr_ch1 | 0110
|
|
|
end_wrt_ch_1 | 0111
|
|
|
pre_ch2 | 0010
|
|
|
wr_ch2 | 1000
|
|
|
end_wrt_ch_2 | 1001
|
|
|
pre_ch3 | 0011
|
|
|
wr_ch3 | 1010
|
|
|
end_wrt_ch_3 | 1011
|
|
|
pre_ch4 | 0100
|
|
|
wr_ch4 | 1100
|
|
|
end_wrt_ch_4 | 1101
|
|
|
pre_ch5 | 0101
|
|
|
wr_ch5 | 1110
|
|
|
end_wrt_ch_5 | 1111
|
|
|
--------------------------
|
|
|
|
|
|
Optimizing unit <FrontEnd_Acq> ...
|
|
|
|
|
|
Optimizing unit <joiner_samp> ...
|
|
|
|
|
|
Optimizing unit <Data_Req_gen> ...
|
|
|
|
|
|
Optimizing unit <DtoDPRAM> ...
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_0> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_0> <empa_ch3/samp_count_0> <empa_ch2/samp_count_0> <empa_ch1/samp_count_0>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_1> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_1> <empa_ch3/samp_count_1> <empa_ch2/samp_count_1> <empa_ch1/samp_count_1>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_2> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_2> <empa_ch3/samp_count_2> <empa_ch2/samp_count_2> <empa_ch1/samp_count_2>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_3> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_3> <empa_ch3/samp_count_3> <empa_ch2/samp_count_3> <empa_ch1/samp_count_3>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_4> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_4> <empa_ch3/samp_count_4> <empa_ch2/samp_count_4> <empa_ch1/samp_count_4>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_5> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_5> <empa_ch3/samp_count_5> <empa_ch2/samp_count_5> <empa_ch1/samp_count_5>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_6> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_6> <empa_ch3/samp_count_6> <empa_ch2/samp_count_6> <empa_ch1/samp_count_6>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_7> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_7> <empa_ch3/samp_count_7> <empa_ch2/samp_count_7> <empa_ch1/samp_count_7>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_8> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_8> <empa_ch3/samp_count_8> <empa_ch2/samp_count_8> <empa_ch1/samp_count_8>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_9> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_9> <empa_ch3/samp_count_9> <empa_ch2/samp_count_9> <empa_ch1/samp_count_9>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_10> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_10> <empa_ch3/samp_count_10> <empa_ch2/samp_count_10> <empa_ch1/samp_count_10>
|
|
|
INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_11> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_11> <empa_ch3/samp_count_11> <empa_ch2/samp_count_11> <empa_ch1/samp_count_11>
|
|
|
|
|
|
Mapping all equations...
|
|
|
Building and optimizing final netlist ...
|
|
|
Found area constraint ratio of 100 (+ 5) on block FrontEnd_Acq, actual ratio is 16.
|
|
|
FlipFlop controlador_DPRAM/count_pack_0 has been replicated 1 time(s)
|
|
|
FlipFlop controlador_DPRAM/count_pack_1 has been replicated 1 time(s)
|
|
|
FlipFlop controlador_DPRAM/count_pack_2 has been replicated 1 time(s)
|
|
|
|
|
|
Final Macro Processing ...
|
|
|
|
|
|
=========================================================================
|
|
|
Final Register Report
|
|
|
|
|
|
Macro Statistics
|
|
|
# Registers : 508
|
|
|
Flip-Flops : 508
|
|
|
|
|
|
=========================================================================
|
|
|
|
|
|
=========================================================================
|
|
|
* Partition Report *
|
|
|
=========================================================================
|
|
|
|
|
|
Partition Implementation Status
|
|
|
-------------------------------
|
|
|
|
|
|
No Partitions were found in this design.
|
|
|
|
|
|
-------------------------------
|
|
|
|
|
|
=========================================================================
|
|
|
* Design Summary *
|
|
|
=========================================================================
|
|
|
|
|
|
Top Level Output File Name : FrontEnd_Acq.ngc
|
|
|
|
|
|
Primitive and Black Box Usage:
|
|
|
------------------------------
|
|
|
# BELS : 947
|
|
|
# GND : 1
|
|
|
# INV : 10
|
|
|
# LUT1 : 52
|
|
|
# LUT2 : 47
|
|
|
# LUT3 : 76
|
|
|
# LUT4 : 64
|
|
|
# LUT5 : 190
|
|
|
# LUT6 : 206
|
|
|
# MUXCY : 143
|
|
|
# MUXF7 : 7
|
|
|
# VCC : 1
|
|
|
# XORCY : 150
|
|
|
# FlipFlops/Latches : 508
|
|
|
# FD : 42
|
|
|
# FDE : 196
|
|
|
# FDR : 96
|
|
|
# FDRE : 159
|
|
|
# FDS : 15
|
|
|
# Clock Buffers : 2
|
|
|
# BUFG : 2
|
|
|
# IO Buffers : 49
|
|
|
# IBUF : 21
|
|
|
# IBUFG : 1
|
|
|
# OBUF : 27
|
|
|
# DCMs : 1
|
|
|
# DCM_SP : 1
|
|
|
|
|
|
Device utilization summary:
|
|
|
---------------------------
|
|
|
|
|
|
Selected Device : 6slx9tqg144-3
|
|
|
|
|
|
|
|
|
Slice Logic Utilization:
|
|
|
Number of Slice Registers: 508 out of 11440 4%
|
|
|
Number of Slice LUTs: 645 out of 5720 11%
|
|
|
Number used as Logic: 645 out of 5720 11%
|
|
|
|
|
|
Slice Logic Distribution:
|
|
|
Number of LUT Flip Flop pairs used: 815
|
|
|
Number with an unused Flip Flop: 307 out of 815 37%
|
|
|
Number with an unused LUT: 170 out of 815 20%
|
|
|
Number of fully used LUT-FF pairs: 338 out of 815 41%
|
|
|
Number of unique control sets: 22
|
|
|
|
|
|
IO Utilization:
|
|
|
Number of IOs: 49
|
|
|
Number of bonded IOBs: 49 out of 102 48%
|
|
|
|
|
|
Specific Feature Utilization:
|
|
|
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
|
|
|
|
|
|
---------------------------
|
|
|
Partition Resource Summary:
|
|
|
---------------------------
|
|
|
|
|
|
No Partitions were found in this design.
|
|
|
|
|
|
---------------------------
|
|
|
|
|
|
|
|
|
=========================================================================
|
|
|
Timing Report
|
|
|
|
|
|
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
|
|
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
|
|
GENERATED AFTER PLACE-and-ROUTE.
|
|
|
|
|
|
Clock Information:
|
|
|
------------------
|
|
|
-----------------------------------+------------------------+-------+
|
|
|
Clock Signal | Clock buffer(FF name) | Load |
|
|
|
-----------------------------------+------------------------+-------+
|
|
|
clk_main | DCM_SP:CLKFX | 508 |
|
|
|
-----------------------------------+------------------------+-------+
|
|
|
|
|
|
Asynchronous Control Signals Information:
|
|
|
----------------------------------------
|
|
|
No asynchronous control signals found in this design
|
|
|
|
|
|
Timing Summary:
|
|
|
---------------
|
|
|
Speed Grade: -3
|
|
|
|
|
|
Minimum period: 18.723ns (Maximum Frequency: 53.411MHz)
|
|
|
Minimum input arrival time before clock: 1.903ns
|
|
|
Maximum output required time after clock: 10.616ns
|
|
|
Maximum combinational path delay: No path found
|
|
|
|
|
|
Timing Details:
|
|
|
---------------
|
|
|
All values displayed in nanoseconds (ns)
|
|
|
|
|
|
=========================================================================
|
|
|
Timing constraint: Default period analysis for Clock 'clk_main'
|
|
|
Clock period: 18.723ns (frequency: 53.411MHz)
|
|
|
Total number of paths / destination ports: 4776 / 1112
|
|
|
-------------------------------------------------------------------------
|
|
|
Delay: 4.681ns (Levels of Logic = 4)
|
|
|
Source: generador_req/count_pulses_1 (FF)
|
|
|
Destination: generador_req/count_clock_16 (FF)
|
|
|
Source Clock: clk_main rising 4.0X
|
|
|
Destination Clock: clk_main rising 4.0X
|
|
|
|
|
|
Data Path: generador_req/count_pulses_1 to generador_req/count_clock_16
|
|
|
Gate Net
|
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
|
---------------------------------------- ------------
|
|
|
FDRE:C->Q 3 0.447 0.995 generador_req/count_pulses_1 (generador_req/count_pulses_1)
|
|
|
LUT5:I0->O 2 0.203 0.617 generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9>_SW0 (N9)
|
|
|
LUT6:I5->O 3 0.205 0.651 generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9> (generador_req/PWR_8_o_count_pulses[9]_equal_4_o)
|
|
|
LUT6:I5->O 18 0.205 1.050 generador_req/Mcount_count_clock_val (generador_req/Mcount_count_clock_val)
|
|
|
LUT4:I3->O 1 0.205 0.000 generador_req/count_clock_16_rstpot (generador_req/count_clock_16_rstpot)
|
|
|
FD:D 0.102 generador_req/count_clock_16
|
|
|
----------------------------------------
|
|
|
Total 4.681ns (1.367ns logic, 3.314ns route)
|
|
|
(29.2% logic, 70.8% route)
|
|
|
|
|
|
=========================================================================
|
|
|
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main'
|
|
|
Total number of paths / destination ports: 21 / 21
|
|
|
-------------------------------------------------------------------------
|
|
|
Offset: 1.903ns (Levels of Logic = 1)
|
|
|
Source: clk_acq_ch5 (PAD)
|
|
|
Destination: empa_ch5/clk_acq_r_0 (FF)
|
|
|
Destination Clock: clk_main rising 4.0X
|
|
|
|
|
|
Data Path: clk_acq_ch5 to empa_ch5/clk_acq_r_0
|
|
|
Gate Net
|
|
|
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
|
|
---------------------------------------- ------------
|
|
|
IBUF:I->O 1 1.222 0.579 clk_acq_ch5_IBUF (clk_acq_ch5_IBUF)
|
|
|
FDS:D 0.102 empa_ch5/clk_acq_r_0
|
|
|
----------------------------------------
|
|
|
Total 1.903ns (1.324ns logic, 0.579ns route)
|
|
|
(69.6% logic, 30.4% route)
|
|
|
|
|
|
=========================================================================
|
|
|
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main'
|
|
|
Total number of paths / destination ports: 3738 / 27
|
|
|
-------------------------------------------------------------------------
|
|
|
Offset: 10.616ns (Levels of Logic = 7)
|
|
|
Source: controlador_DPRAM/count_ch_byte_2 (FF)
|
|
|
Destination: addrA<7> (PAD)
|
|
|
Source Clock: clk_main rising 4.0X
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Data Path: controlador_DPRAM/count_ch_byte_2 to addrA<7>
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Gate Net
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Cell:in->out fanout Delay Delay Logical Name (Net Name)
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---------------------------------------- ------------
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FDRE:C->Q 103 0.447 1.990 controlador_DPRAM/count_ch_byte_2 (controlador_DPRAM/count_ch_byte_2)
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LUT3:I1->O 10 0.203 1.085 controlador_DPRAM/_n0517<5>21 (controlador_DPRAM/_n0517<5>2)
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LUT5:I2->O 1 0.205 0.000 controlador_DPRAM/_n0517<7>11 (controlador_DPRAM/_n0517<7>1)
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XORCY:LI->O 1 0.136 0.924 controlador_DPRAM/Madd_GND_26_o_GND_26_o_add_108_OUT_xor<7> (controlador_DPRAM/GND_26_o_GND_26_o_add_108_OUT<7>)
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LUT5:I0->O 1 0.203 0.944 controlador_DPRAM/Mmux_addrA103 (controlador_DPRAM/Mmux_addrA102)
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LUT6:I0->O 1 0.203 0.924 controlador_DPRAM/Mmux_addrA104 (controlador_DPRAM/Mmux_addrA103)
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LUT6:I1->O 1 0.203 0.579 controlador_DPRAM/Mmux_addrA106 (addrA_7_OBUF)
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OBUF:I->O 2.571 addrA_7_OBUF (addrA<7>)
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----------------------------------------
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Total 10.616ns (4.171ns logic, 6.445ns route)
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(39.3% logic, 60.7% route)
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=========================================================================
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Cross Clock Domains Report:
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--------------------------
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Clock to Setup on destination clock clk_main
|
|
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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clk_main | 4.681| | | |
|
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---------------+---------+---------+---------+---------+
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=========================================================================
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|
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Total REAL time to Xst completion: 11.00 secs
|
|
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Total CPU time to Xst completion: 10.51 secs
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-->
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Total memory usage is 251848 kilobytes
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Number of errors : 0 ( 0 filtered)
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Number of warnings : 0 ( 0 filtered)
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Number of infos : 12 ( 0 filtered)
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|
