|
|
----------------------------------------------------------------------------------
|
|
|
-- Company:
|
|
|
-- Engineer:
|
|
|
--
|
|
|
-- Create Date: 16:24:04 02/21/2017
|
|
|
-- Design Name:
|
|
|
-- Module Name: DtoDPRAM - Behavioral
|
|
|
-- Project Name:
|
|
|
-- Target Devices:
|
|
|
-- Tool versions:
|
|
|
-- Description:
|
|
|
--
|
|
|
-- Dependencies:
|
|
|
--
|
|
|
-- Revision:
|
|
|
-- Revision 0.01 - File Created
|
|
|
-- Additional Comments:
|
|
|
--
|
|
|
----------------------------------------------------------------------------------
|
|
|
library IEEE;
|
|
|
use IEEE.STD_LOGIC_1164.ALL;
|
|
|
|
|
|
-- Uncomment the following library declaration if using
|
|
|
-- arithmetic functions with Signed or Unsigned values
|
|
|
use IEEE.NUMERIC_STD.ALL;
|
|
|
|
|
|
-- Uncomment the following library declaration if instantiating
|
|
|
-- any Xilinx primitives in this code.
|
|
|
--library UNISIM;
|
|
|
--use UNISIM.VComponents.all;
|
|
|
|
|
|
entity DtoDPRAM is
|
|
|
GENERIC(
|
|
|
ADDR_LENGTH: INTEGER := 12;
|
|
|
DATAOUT_LENGTH: INTEGER := 8;
|
|
|
DATAIN_LENGTH: INTEGER := 40;
|
|
|
CHAN_NUM: INTEGER := 5;
|
|
|
COUNT_BYTE_SZ: INTEGER := 3;
|
|
|
COUNT_PACK_SZ: INTEGER := 6
|
|
|
|
|
|
);
|
|
|
|
|
|
PORT(
|
|
|
--Reset general
|
|
|
rst_bar: IN std_logic;
|
|
|
|
|
|
--Reset general
|
|
|
data_req: IN std_logic;
|
|
|
|
|
|
--Entrada de reloj principal
|
|
|
clk_main: IN std_logic;
|
|
|
|
|
|
--Entradas para indicar dato preparado por leer
|
|
|
--Desde los nibble to packets
|
|
|
ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
|
|
|
|
|
|
--Senhal para que indica que termino con una peticion
|
|
|
--Hacia los nibble to packets
|
|
|
ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
|
|
|
|
|
|
--Data IN
|
|
|
datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
|
|
|
datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
|
|
|
datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
|
|
|
datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
|
|
|
datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
|
|
|
|
|
|
--DPRAM senhales de control, direccion y data
|
|
|
--Direccion de escritura/lectura
|
|
|
addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0);
|
|
|
dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0);
|
|
|
enA: OUT std_logic;
|
|
|
--Aviso de Paquete de 40 muestras solicitadas a los 5 canales
|
|
|
rpi_req: OUT std_logic
|
|
|
|
|
|
);
|
|
|
end DtoDPRAM;
|
|
|
|
|
|
architecture Behavioral of DtoDPRAM is
|
|
|
SIGNAL datach1_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
SIGNAL datach2_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
SIGNAL datach3_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
SIGNAL datach4_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
SIGNAL datach5_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
|
|
|
--Estados del controlador de memoria
|
|
|
--Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria
|
|
|
--espera de pedido y estados para proceder a una lectura
|
|
|
TYPE ram_cont_states IS (idle,
|
|
|
|
|
|
------------------------------------------
|
|
|
pre_ch1, wr_ch1, end_wrt_ch_1,
|
|
|
------------------------------------------
|
|
|
pre_ch2, wr_ch2, end_wrt_ch_2,
|
|
|
------------------------------------------
|
|
|
pre_ch3, wr_ch3, end_wrt_ch_3,
|
|
|
------------------------------------------
|
|
|
pre_ch4, wr_ch4, end_wrt_ch_4,
|
|
|
------------------------------------------
|
|
|
pre_ch5, wr_ch5, end_wrt_ch_5
|
|
|
|
|
|
);
|
|
|
|
|
|
SIGNAL ram_contr_cur_state: ram_cont_states := idle;
|
|
|
SIGNAL ram_contr_next_state: ram_cont_states := idle;
|
|
|
|
|
|
----------------------------------
|
|
|
--Estados de la atencion a ready's
|
|
|
TYPE chn_cont_states IS ( idle,
|
|
|
checking_ch1, attending_ch1,
|
|
|
checking_ch2, attending_ch2,
|
|
|
checking_ch3, attending_ch3,
|
|
|
checking_ch4, attending_ch4,
|
|
|
checking_ch5, attending_ch5
|
|
|
);
|
|
|
|
|
|
SIGNAL ch_cont_cur_state: chn_cont_states := idle;
|
|
|
SIGNAL ch_cont_next_state: chn_cont_states := idle;
|
|
|
|
|
|
SIGNAL count_ch_byte: std_logic_vector((COUNT_BYTE_SZ-1) downto 0) := (OTHERS=>'0');
|
|
|
|
|
|
--Direcciones base por canal
|
|
|
CONSTANT BASE_ADDR_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0');
|
|
|
CONSTANT BASE_ADDR_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000011001000"; --200
|
|
|
CONSTANT BASE_ADDR_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000110010000"; --400
|
|
|
CONSTANT BASE_ADDR_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001001011000"; --600
|
|
|
CONSTANT BASE_ADDR_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001100100000"; --800
|
|
|
|
|
|
CONSTANT BASE_BUFFER_2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "010000000000"; --1024
|
|
|
|
|
|
SIGNAL sel_buf: std_logic := '0';
|
|
|
SIGNAL count_pack: std_logic_vector((COUNT_PACK_SZ-1) downto 0) := (OTHERS => '0');
|
|
|
begin
|
|
|
|
|
|
---------------------
|
|
|
--Estados para atencion de canales
|
|
|
ch_cont_cambio_estados: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main)) THEN
|
|
|
IF(rst_bar = '0') THEN
|
|
|
ch_cont_cur_state <= idle;
|
|
|
ELSE
|
|
|
ch_cont_cur_state <= ch_cont_next_state;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
ch_salidas_estados: PROCESS(ch_cont_cur_state,
|
|
|
ch_rdy_vector,
|
|
|
ram_contr_cur_state
|
|
|
)
|
|
|
BEGIN
|
|
|
|
|
|
CASE ch_cont_cur_state IS
|
|
|
WHEN idle =>
|
|
|
ch_cont_next_state <= checking_ch1;
|
|
|
|
|
|
WHEN checking_ch1 =>
|
|
|
IF(ch_rdy_vector(0) = '1') THEN
|
|
|
ch_cont_next_state <= attending_ch1;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= checking_ch2;
|
|
|
END IF;
|
|
|
|
|
|
WHEN attending_ch1 =>
|
|
|
IF(ram_contr_cur_state = end_wrt_ch_1) THEN
|
|
|
ch_cont_next_state <= checking_ch2;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= attending_ch1;
|
|
|
END IF;
|
|
|
|
|
|
WHEN checking_ch2 =>
|
|
|
IF(ch_rdy_vector(1) = '1') THEN
|
|
|
ch_cont_next_state <= attending_ch2;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= checking_ch3;
|
|
|
END IF;
|
|
|
|
|
|
WHEN attending_ch2 =>
|
|
|
IF(ram_contr_cur_state = end_wrt_ch_2) THEN
|
|
|
ch_cont_next_state <= checking_ch3;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= attending_ch2;
|
|
|
END IF;
|
|
|
|
|
|
WHEN checking_ch3 =>
|
|
|
IF(ch_rdy_vector(2) = '1') THEN
|
|
|
ch_cont_next_state <= attending_ch3;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= checking_ch4;
|
|
|
END IF;
|
|
|
|
|
|
WHEN attending_ch3 =>
|
|
|
IF(ram_contr_cur_state = end_wrt_ch_3) THEN
|
|
|
ch_cont_next_state <= checking_ch4;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= attending_ch3;
|
|
|
END IF;
|
|
|
|
|
|
WHEN checking_ch4 =>
|
|
|
IF(ch_rdy_vector(3) = '1') THEN
|
|
|
ch_cont_next_state <= attending_ch4;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= checking_ch5;
|
|
|
END IF;
|
|
|
|
|
|
WHEN attending_ch4 =>
|
|
|
IF(ram_contr_cur_state = end_wrt_ch_4) THEN
|
|
|
ch_cont_next_state <= checking_ch5;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= attending_ch4;
|
|
|
END IF;
|
|
|
|
|
|
WHEN checking_ch5 =>
|
|
|
IF(ch_rdy_vector(4) = '1') THEN
|
|
|
ch_cont_next_state <= attending_ch5;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= checking_ch1;
|
|
|
END IF;
|
|
|
|
|
|
WHEN attending_ch5 =>
|
|
|
IF(ram_contr_cur_state = end_wrt_ch_5) THEN
|
|
|
ch_cont_next_state <= checking_ch1;
|
|
|
ELSE
|
|
|
ch_cont_next_state <= attending_ch5;
|
|
|
END IF;
|
|
|
|
|
|
WHEN OTHERS =>
|
|
|
|
|
|
ch_cont_next_state <= idle;
|
|
|
|
|
|
END CASE;
|
|
|
END PROCESS;
|
|
|
|
|
|
--------------------------------------------------
|
|
|
--Estados de m�quina principal para control de RAM
|
|
|
|
|
|
ctrl_cambio_estados: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main)) THEN
|
|
|
IF(rst_bar = '0') THEN
|
|
|
ram_contr_cur_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_cur_state <= ram_contr_next_state;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
--Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set s�.
|
|
|
ctrl_salidas_estados: PROCESS(ram_contr_cur_state, ch_cont_cur_state,
|
|
|
count_pack, count_ch_byte, sel_buf,
|
|
|
datach1_aux, datach2_aux, datach3_aux, datach4_aux, datach5_aux
|
|
|
)
|
|
|
BEGIN
|
|
|
CASE ram_contr_cur_state IS
|
|
|
WHEN idle =>
|
|
|
enA <= '0';
|
|
|
dataA <= (OTHERS=>'0');
|
|
|
addrA <= (OTHERS=>'0');
|
|
|
ch_ack_vector <= (OTHERS=>'0');
|
|
|
IF (ch_cont_cur_state=attending_ch1) THEN
|
|
|
ram_contr_next_state <= pre_ch1;
|
|
|
ELSIF (ch_cont_cur_state=attending_ch2) THEN
|
|
|
ram_contr_next_state <= pre_ch2;
|
|
|
ELSIF (ch_cont_cur_state=attending_ch3) THEN
|
|
|
ram_contr_next_state <= pre_ch3;
|
|
|
ELSIF (ch_cont_cur_state=attending_ch4) THEN
|
|
|
ram_contr_next_state <= pre_ch4;
|
|
|
ELSIF (ch_cont_cur_state=attending_ch5) THEN
|
|
|
ram_contr_next_state <= pre_ch5;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= idle;
|
|
|
END IF;
|
|
|
|
|
|
WHEN pre_ch1 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach1_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= wr_ch1;
|
|
|
|
|
|
WHEN wr_ch1 =>
|
|
|
enA <= '1';
|
|
|
dataA <= datach1_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= end_wrt_ch_1;
|
|
|
|
|
|
WHEN end_wrt_ch_1 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach1_aux;
|
|
|
ch_ack_vector <= "00001";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
IF (count_ch_byte = "100") THEN
|
|
|
ram_contr_next_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= pre_ch1;
|
|
|
END IF;
|
|
|
|
|
|
---------------------------------------
|
|
|
|
|
|
WHEN pre_ch2 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach2_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= wr_ch2;
|
|
|
|
|
|
WHEN wr_ch2 =>
|
|
|
enA <= '1';
|
|
|
dataA <= datach2_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= end_wrt_ch_2;
|
|
|
|
|
|
WHEN end_wrt_ch_2 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach2_aux;
|
|
|
ch_ack_vector <= "00010";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
IF (count_ch_byte = "100") THEN
|
|
|
ram_contr_next_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= pre_ch2;
|
|
|
END IF;
|
|
|
|
|
|
------------------------------
|
|
|
|
|
|
WHEN pre_ch3 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach3_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= wr_ch3;
|
|
|
|
|
|
WHEN wr_ch3 =>
|
|
|
enA <= '1';
|
|
|
dataA <= datach3_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= end_wrt_ch_3;
|
|
|
|
|
|
WHEN end_wrt_ch_3 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach3_aux;
|
|
|
ch_ack_vector <= "00100";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
IF (count_ch_byte = "100") THEN
|
|
|
ram_contr_next_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= pre_ch3;
|
|
|
END IF;
|
|
|
|
|
|
--------------------------------------------------
|
|
|
|
|
|
WHEN pre_ch4 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach4_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= wr_ch4;
|
|
|
|
|
|
WHEN wr_ch4 =>
|
|
|
enA <= '1';
|
|
|
dataA <= datach4_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= end_wrt_ch_4;
|
|
|
|
|
|
WHEN end_wrt_ch_4 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach4_aux;
|
|
|
ch_ack_vector <= "01000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
IF (count_ch_byte = "100") THEN
|
|
|
ram_contr_next_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= pre_ch4;
|
|
|
END IF;
|
|
|
|
|
|
------------------------------------------
|
|
|
|
|
|
WHEN pre_ch5 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach5_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= wr_ch5;
|
|
|
|
|
|
WHEN wr_ch5 =>
|
|
|
enA <= '1';
|
|
|
dataA <= datach5_aux;
|
|
|
ch_ack_vector <= "00000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
ram_contr_next_state <= end_wrt_ch_5;
|
|
|
|
|
|
WHEN end_wrt_ch_5 =>
|
|
|
enA <= '0';
|
|
|
dataA <= datach5_aux;
|
|
|
ch_ack_vector <= "10000";
|
|
|
IF ( sel_buf = '1' ) THEN
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
ELSE
|
|
|
addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
|
|
|
END IF;
|
|
|
IF (count_ch_byte = "100") THEN
|
|
|
ram_contr_next_state <= idle;
|
|
|
ELSE
|
|
|
ram_contr_next_state <= pre_ch5;
|
|
|
END IF;
|
|
|
|
|
|
|
|
|
WHEN OTHERS =>
|
|
|
|
|
|
enA <= '0';
|
|
|
dataA <= (OTHERS=>'0');
|
|
|
addrA <= (OTHERS=>'0');
|
|
|
ch_ack_vector <= (OTHERS=>'0');
|
|
|
ram_contr_next_state <= idle;
|
|
|
|
|
|
END CASE;
|
|
|
END PROCESS;
|
|
|
|
|
|
--Contador de paquetes
|
|
|
wr_bytes_dpram: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF(rising_edge(clk_main)) THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
--count_req <= (OTHERS => '0');
|
|
|
count_pack <= (OTHERS => '1');
|
|
|
ELSE
|
|
|
--IF (data_req = '1') THEN
|
|
|
-- count_req <= std_logic_vector(unsigned(count_req) + 1);
|
|
|
--END IF;
|
|
|
|
|
|
IF (data_req = '1') THEN
|
|
|
IF (count_pack = "100111") THEN
|
|
|
count_pack <= (OTHERS => '0');
|
|
|
sel_buf <= NOT(sel_buf);
|
|
|
rpi_req <= '1';
|
|
|
ELSE
|
|
|
count_pack <= std_logic_vector(unsigned(count_pack) + 1);
|
|
|
rpi_req <= '0';
|
|
|
END IF;
|
|
|
ELSE
|
|
|
rpi_req <= '0';
|
|
|
END IF;
|
|
|
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
|
|
|
--Contador de bytes
|
|
|
count_ch_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF(rising_edge(clk_main)) THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
count_ch_byte <= (OTHERS => '0');
|
|
|
ELSE
|
|
|
IF (ram_contr_cur_state = idle) THEN
|
|
|
count_ch_byte <= (OTHERS => '0');
|
|
|
ELSE
|
|
|
IF (ram_contr_cur_state = end_wrt_ch_1 OR
|
|
|
ram_contr_cur_state = end_wrt_ch_2 OR
|
|
|
ram_contr_cur_state = end_wrt_ch_3 OR
|
|
|
ram_contr_cur_state = end_wrt_ch_4 OR
|
|
|
ram_contr_cur_state = end_wrt_ch_5
|
|
|
) THEN
|
|
|
count_ch_byte <= std_logic_vector(unsigned(count_ch_byte) + 1);
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
-----------------------------------------
|
|
|
datach1_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main))THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
datach1_aux <= (OTHERS =>'0');
|
|
|
ELSE
|
|
|
CASE count_ch_byte IS
|
|
|
WHEN "000" =>
|
|
|
datach1_aux <= datach1(39 downto 32);
|
|
|
WHEN "001" =>
|
|
|
datach1_aux <= datach1(31 downto 24);
|
|
|
WHEN "010" =>
|
|
|
datach1_aux <= datach1(23 downto 16);
|
|
|
WHEN "011" =>
|
|
|
datach1_aux <= datach1(15 downto 8);
|
|
|
WHEN "100" =>
|
|
|
datach1_aux <= datach1(7 downto 0);
|
|
|
WHEN OTHERS =>
|
|
|
datach1_aux <= (OTHERS =>'0');
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
datach2_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main))THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
datach2_aux <= (OTHERS =>'0');
|
|
|
ELSE
|
|
|
CASE count_ch_byte IS
|
|
|
WHEN "000" =>
|
|
|
datach2_aux <= datach2(39 downto 32);
|
|
|
WHEN "001" =>
|
|
|
datach2_aux <= datach2(31 downto 24);
|
|
|
WHEN "010" =>
|
|
|
datach2_aux <= datach2(23 downto 16);
|
|
|
WHEN "011" =>
|
|
|
datach2_aux <= datach2(15 downto 8);
|
|
|
WHEN "100" =>
|
|
|
datach2_aux <= datach2(7 downto 0);
|
|
|
WHEN OTHERS =>
|
|
|
datach2_aux <= (OTHERS =>'0');
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
datach3_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main))THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
datach3_aux <= (OTHERS =>'0');
|
|
|
ELSE
|
|
|
CASE count_ch_byte IS
|
|
|
WHEN "000" =>
|
|
|
datach3_aux <= datach3(39 downto 32);
|
|
|
WHEN "001" =>
|
|
|
datach3_aux <= datach3(31 downto 24);
|
|
|
WHEN "010" =>
|
|
|
datach3_aux <= datach3(23 downto 16);
|
|
|
WHEN "011" =>
|
|
|
datach3_aux <= datach3(15 downto 8);
|
|
|
WHEN "100" =>
|
|
|
datach3_aux <= datach3(7 downto 0);
|
|
|
WHEN OTHERS =>
|
|
|
datach3_aux <= (OTHERS =>'0');
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
datach4_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main))THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
datach4_aux <= (OTHERS =>'0');
|
|
|
ELSE
|
|
|
CASE count_ch_byte IS
|
|
|
WHEN "000" =>
|
|
|
datach4_aux <= datach4(39 downto 32);
|
|
|
WHEN "001" =>
|
|
|
datach4_aux <= datach4(31 downto 24);
|
|
|
WHEN "010" =>
|
|
|
datach4_aux <= datach4(23 downto 16);
|
|
|
WHEN "011" =>
|
|
|
datach4_aux <= datach4(15 downto 8);
|
|
|
WHEN "100" =>
|
|
|
datach4_aux <= datach4(7 downto 0);
|
|
|
WHEN OTHERS =>
|
|
|
datach4_aux <= (OTHERS =>'0');
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
datach5_bytes: PROCESS(clk_main)
|
|
|
BEGIN
|
|
|
IF (rising_edge(clk_main))THEN
|
|
|
IF (rst_bar = '0') THEN
|
|
|
datach5_aux <= (OTHERS =>'0');
|
|
|
ELSE
|
|
|
CASE count_ch_byte IS
|
|
|
WHEN "000" =>
|
|
|
datach5_aux <= datach5(39 downto 32);
|
|
|
WHEN "001" =>
|
|
|
datach5_aux <= datach5(31 downto 24);
|
|
|
WHEN "010" =>
|
|
|
datach5_aux <= datach5(23 downto 16);
|
|
|
WHEN "011" =>
|
|
|
datach5_aux <= datach5(15 downto 8);
|
|
|
WHEN "100" =>
|
|
|
datach5_aux <= datach5(7 downto 0);
|
|
|
WHEN OTHERS =>
|
|
|
datach5_aux <= (OTHERS =>'0');
|
|
|
END CASE;
|
|
|
END IF;
|
|
|
END IF;
|
|
|
END PROCESS;
|
|
|
|
|
|
|
|
|
end Behavioral;
|
|
|
|
|
|
|
