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-- test_hr Template
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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library IEEE_proposed;
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use IEEE_proposed.fixed_pkg.all;
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use work.cic_utils.all;
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ENTITY test_hr IS
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END test_hr;
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ARCHITECTURE behavior OF test_hr IS
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-- Component Declaration
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COMPONENT Hr_block
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Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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Cb : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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Ca : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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acum : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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clk : in std_logic;
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last : in std_logic);
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END COMPONENT;
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signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal Cb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal Ca : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal acum : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal clk : std_logic;
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signal last : std_logic;
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-- Clock period definitions
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constant clk_period : time := 1 ms;
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BEGIN
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-- Component Instantiation
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uut: Hr_block PORT MAP(
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input => input,
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output => output,
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Cb => Cb,
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Ca => Ca,
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acum => acum,
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clk => clk,
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last => last
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);
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Cb <= to_sfixed(2,Cb);
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Ca <= to_sfixed(3,Ca);
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acum <= to_sfixed(10,Ca);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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end process;
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-- Test Bench Statements
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tb : PROCESS
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BEGIN
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-- hold reset state for 1 ms.
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last <= '1';
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input <= to_sfixed(100,input);
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wait for clk_period;
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last <= '0';
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input <= to_sfixed(100,input);
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wait for clk_period;
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wait;
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END PROCESS tb;
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-- End Test Bench
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END;
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