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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 14:55:16 03/12/2015
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-- Design Name:
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-- Module Name: /home/shinobi/workspaces/roj/trunk/firmware/sources/processingEngine/cic/tb_int.vhd
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-- Project Name: cic
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: integrator
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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library IEEE_proposed;
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use IEEE_proposed.fixed_pkg.all;
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use work.fix_arith.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY tb_int IS
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END tb_int;
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ARCHITECTURE behavior OF tb_int IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT integrator
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PORT(
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clk : IN std_logic;
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input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
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--Outputs
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signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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-- Clock period definitions
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constant clk_period : time := 1 ms;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: integrator PORT MAP (
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clk => clk,
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input => input,
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output => output
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 1 ms;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(1,input);
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wait;
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end process;
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END;
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