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-- test_comb Template
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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library IEEE_proposed;
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use IEEE_proposed.fixed_pkg.all;
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use work.cic_utils.all;
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ENTITY test_comb IS
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END test_comb;
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ARCHITECTURE behavior OF test_comb IS
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-- Component Declaration
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COMPONENT comb
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PORT(
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clk : in std_logic;
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input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
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);
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END COMPONENT;
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--Inputs
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signal clk : std_logic := '0';
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signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
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--Outputs
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signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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-- Clock period definitions
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constant clk_period : time := 1 ms;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: comb PORT MAP(
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clk => clk,
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input => input,
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output => output
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);
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-- Clock process definitions
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clk_process :process
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begin
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clk <= '1';
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wait for clk_period/2;
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clk <= '0';
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wait for clk_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 1 ms.
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wait for 1 ms;
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input <= to_sfixed(1,input);
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wait for clk_period;
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input <= to_sfixed(2,input);
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wait for clk_period;
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input <= to_sfixed(3,input);
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wait for clk_period;
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input <= to_sfixed(5,input);
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wait for clk_period;
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input <= to_sfixed(8,input);
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wait for clk_period;
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input <= to_sfixed(13,input);
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wait for clk_period;
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input <= to_sfixed(21,input);
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wait for clk_period;
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input <= to_sfixed(34,input);
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wait for clk_period;
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input <= to_sfixed(55,input);
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wait for clk_period;
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input <= to_sfixed(89,input);
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wait;
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end process;
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END;
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