jro_hard/gen_acq Files · trunk/firmware/sources/processingEngine/comb.vhd

aaguilar - - Load All Authors

File last commit:

r214:215


                r221:222

Download file

             comb.vhd
        
                    47 lines
            
             | 1.1 KiB
            
                | text/x-vhdl
            
             |
                VhdlLexer
            
             / trunk / firmware / sources / processingEngine / comb.vhd
          
                    History
                
                 |
                  Annotation
                 | Raw
                 |Copy content
                 |Copy permalink

      ----------------------------------------------------------------------------------

      -- Company: company

      -- Engineer: shinobi

      -- 

      -- Create Date:    Mar 9, 2015  -   5:10:57 PM

      -- Design Name:  modulename

      -- Module Name:  comb

      -- Project Name:  projectname

      -- Description: 

      --

      --

      --

      ----------------------------------------------------------------------------------

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      library IEEE_proposed;

      use IEEE_proposed.fixed_pkg.all;

      use work.cic_utils.all;

      -- entity declaration --------------------------------

      entity comb is

      	port (

      		clk : in std_logic;

      		input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);

      		output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)

      	);

      end entity comb;

      -- architecture declaration------------------------

      architecture simple of comb is

      	signal s_in_1 : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);

      	signal s_in : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);

      begin

      	process(clk)

      	begin

      		if clk'event and clk = '1' then  

      	      	s_in_1 <= s_in;

      	   	end if;

      	end process;

      	output <= sust(input ,s_in_1);

      	s_in <= input;

      end architecture simple;

	Site-wide shortcuts
/	Use quick search box
g h	Goto home page
g g	Goto my private gists page
g G	Goto my public gists page
g 0-9	Goto bookmarked items from 0-9
n r	New repository page
n g	New gist page

	Repositories
g s	Goto summary page
g c	Goto changelog page
g f	Goto files page
g F	Goto files page with file search activated
g p	Goto pull requests page
g o	Goto repository settings
g O	Goto repository access permissions settings
t s	Toggle sidebar on some pages

				----------------------------------------------------------------------------------
				-- Company: company
				-- Engineer: shinobi
				--
				-- Create Date: Mar 9, 2015 - 5:10:57 PM
				-- Design Name: modulename
				-- Module Name: comb
				-- Project Name: projectname
				-- Description:
				--
				--
				--
				----------------------------------------------------------------------------------
				library IEEE;
				use IEEE.std_logic_1164.all;
				use IEEE.numeric_std.all;
				library IEEE_proposed;
				use IEEE_proposed.fixed_pkg.all;

				use work.cic_utils.all;

				-- entity declaration --------------------------------
				entity comb is
				port (
				clk : in std_logic;
				input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
				output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
				);
				end entity comb;


				-- architecture declaration------------------------
				architecture simple of comb is
				signal s_in_1 : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
				signal s_in : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
				begin
				process(clk)
				begin
				if clk'event and clk = '1' then
				s_in_1 <= s_in;
				end if;
				end process;
				output <= sust(input ,s_in_1);
				s_in <= input;


				end architecture simple;