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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:48:08 03/12/2015
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-- Design Name:
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-- Module Name: cic - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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library IEEE_proposed;
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use IEEE_proposed.fixed_pkg.all;
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use work.cic_utils.all;
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entity cic is
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Port ( clk : in STD_LOGIC;
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M1 : in integer(8 downto 0); -- factor de decimacion
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M2 : in integer(8 downto 0);
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input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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end cic;
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architecture Behavioral of cic is
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-- componentes del cic
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COMPONENT integrator
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PORT(
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clk : IN std_logic;
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input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
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);
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END COMPONENT;
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COMPONENT comb
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PORT(
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clk : in std_logic;
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input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
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);
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END COMPONENT;
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constant K: integer := 3;-- numero de etapas del filtro CIC
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type conn is array (2*(K+1)-1 downto 0) of sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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signal connector : conn;
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begin
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cic_arc: for i in 0 to (K-1) generate
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int: integrator port map(clk=>clk, input=>connector(i), output=>connector(i+1) );
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cmb: comb port map(clk=>clk, input=>connector(i+K), output=>connector(i+K+1) );
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end generate cic_arc;
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end Behavioral;
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