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Hr_block.vhd
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/ trunk / firmware / sources / processingEngine / Hr_block.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.cic_utils.all;
-- Este modulo implementa el bloque Gk del filtro Hr
entity hr_block is
Port ( clk : in std_logic;
reset : in std_logic;
input : in std_logic_vector(FIXWIDTH-1 downto 0);
output : out std_logic_vector(FIXWIDTH-1 downto 0);
ka : in std_logic_vector(4 downto 0);
kb : in std_logic_vector(4 downto 0);
enb : in std_logic);
end hr_block;
architecture simple_block of Hr_block is
signal s1,s2,s3 : std_logic_vector(FIXWIDTH-1 downto 0);
signal Ca,Cb : std_logic_vector(FIXWIDTH-1 downto 0);
type ROM is array (0 to 19) of std_logic_vector(FIXWIDTH-1 downto 0);
constant coeffs : ROM:= ( to_fix(2**MANTISSA_BITS),
to_fix((196875 *(2**MANTISSA_BITS))/100000),
to_fix((284375 *(2**MANTISSA_BITS))/100000),
to_fix((362500 *(2**MANTISSA_BITS))/100000),
to_fix((425000 *(2**MANTISSA_BITS))/100000),
to_fix((475000 *(2**MANTISSA_BITS))/100000),
to_fix((503125 *(2**MANTISSA_BITS))/100000),
to_fix((512500 *(2**MANTISSA_BITS))/100000),
to_fix((503125 *(2**MANTISSA_BITS))/100000),
to_fix((475000 *(2**MANTISSA_BITS))/100000),
to_fix((425000 *(2**MANTISSA_BITS))/100000),
to_fix((362500 *(2**MANTISSA_BITS))/100000),
to_fix((284375 *(2**MANTISSA_BITS))/100000),
to_fix((196875 *(2**MANTISSA_BITS))/100000),
to_fix(2**MANTISSA_BITS),
to_fix(0),
to_fix((-100000 *(2**MANTISSA_BITS))/100000),
to_fix((-196875 *(2**MANTISSA_BITS))/100000),
to_fix((-284375 *(2**MANTISSA_BITS))/100000),
to_fix(0));-- el coeficieente 19 no existe, solo es para anular un tap
begin
Ca <= coeffs(to_integer(unsigned(ka)));
Cb <= coeffs(to_integer(unsigned(kb)));
process (clk,enb,reset)
begin
if (enb = '0') or (reset='1') then
s2 <= (others =>'0');
elsif clk'event and clk='1' then
s2 <= s1;
end if;
end process;
s1 <= input*Cb;
with enb select
s3 <= input*Ca when '1',
(others=>'0') when others;
output <= s2+s3;
end simple_block;