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---------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.all;
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use work.cic_utils.all;
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--**********************************************************************************
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entity Hr is
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Port ( clk : in std_logic;
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reset: in std_logic;
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N : in integer range 1 to MAX_M2_DEC;
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input : in std_logic_vector(FIXWIDTH-1 downto 0);
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output : out std_logic_vector(FIXWIDTH-1 downto 0)
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);
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end Hr;
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--**********************************************************************************
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architecture filter of Hr is
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-------------------------------------------------------------
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component hr_block
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Port ( clk : in std_logic;
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reset : in std_logic;
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input : in std_logic_vector(FIXWIDTH-1 downto 0);
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output : out std_logic_vector(FIXWIDTH-1 downto 0);
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ka : in std_logic_vector(4 downto 0);
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kb : in std_logic_vector(4 downto 0);
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enb : in std_logic);
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end component hr_block;
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-------------------------------------------------------------
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component clk_div
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Port ( clkin : in STD_LOGIC;
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clkout: out STD_LOGIC;
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reset : in std_logic;
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N : in integer range 1 to 19);
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end component clk_div;
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-------------------------------------------------------------
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type conn is array (0 to MAX_M2_DEC-1) of std_logic_vector(FIXWIDTH-1 downto 0);
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signal s1,s2,s3: conn;
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signal s4:std_logic_vector(FIXWIDTH-1 downto 0);
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signal clkd: std_logic;
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type enab is array (0 to MAX_M2_DEC-1) of std_logic;
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signal enb: enab;
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type k is array (0 to MAX_M2_DEC-1) of std_logic_vector(4 downto 0);
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constant ka:k := ("00000","00001","00010","00011",
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"00100","00101","00110","00111",
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"01000","01001","01010","01011",
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"01100","01101","01110","01111",
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"10000","10001","10010");
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signal kb:k;
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begin
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s1(0) <= input;
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output <= s4;
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clkdiv: clk_div port map(
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clkin => clk,
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clkout => clkd,
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reset => reset,
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N => N
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);
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--/////////////////////////////////////////////////////////////////////////////////
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hr_filter: for i in 0 to MAX_M2_DEC-1 generate
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begin
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-------------------------------------------------------------
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Gk: component hr_block
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-- (clk,reset,input,output,ka,kb,encb)
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port map (clkd,reset,s2(i),s3(i),ka(i),kb(i),enb(i));
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-------------------------------------------------------------
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end generate hr_filter;
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--/////////////////////////////////////////////////////////////////////////////////
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-- shift registers --
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process(clk,reset)
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begin
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if reset='1' then
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for i in 1 to MAX_M2_DEC-1 loop
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s1(i) <= (others=>'0');
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end loop;
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elsif clk'event and clk='1' then
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for i in MAX_M2_DEC-1 downto 1 loop
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s1(i) <= s1(i-1);
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end loop;
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end if;
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end process;
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-- implementa a los decimadores, cada vez que haya un flanco de subida
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-- en el clock clkd (clkd = clk / N), pasa una muestra al lado de baja
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-- frecuencia del filtro.
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-- la salida final del filtro es la suma de las salidas de los bloques.
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process(clkd,reset)
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begin
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if reset='1' then
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for i in 0 to MAX_M2_DEC-1 loop
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s2(i) <= (others=>'0');
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end loop;
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elsif clkd'event and clkd='1' then
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for i in 0 to MAX_M2_DEC-1 loop
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s2(i) <= s1(i);
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end loop;
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end if;
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end process;
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-- process(s3)
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-- variable acum : std_logic_vector(FIXWIDTH-1 downto 0);
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-- begin
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-- acum := s3(0);
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-- for i in 1 to MAX_M2_DEC-1 loop
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-- acum := acum+s3(i);
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-- end loop;
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-- s4 <= acum;
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-- end process;
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s4 <= s3(0)+s3(1)+s3(2)+s3(3)+s3(4)+s3(5)+
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s3(6)+s3(7)+s3(8)+s3(9)+s3(10)+s3(11)+
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s3(12)+s3(13)+s3(14)+s3(15)+s3(16)+s3(17)+s3(18);
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process(N)
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begin
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for i in 0 to MAX_M2_DEC-1 loop
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if N-1 > i then
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kb(i) <= std_logic_vector(to_unsigned(N-i-2,kb(i)'length));
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else
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kb(i) <= std_logic_vector(to_unsigned(19,kb(i)'length));
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end if;
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if N-1 >= i then
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enb(i) <= '1';
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else
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enb(i) <= '0';
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end if;
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end loop;
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end process;
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end filter;
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--**********************************************************************************
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