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/*-----------------------------------------------------*\
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| USI I2C Slave Driver |
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| This library provides a robust, interrupt-driven I2C |
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| slave implementation built on the ATTiny Universal |
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| Serial Interface (USI) hardware. Slave operation is |
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| implemented as a register bank, where each 'register' |
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| is a pointer to an 8-bit variable in the main code. |
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| This was chosen to make I2C integration transparent |
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| to the mainline code and making I2C reads simple. |
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| This library also works well with the Linux I2C-Tools |
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| utilities i2cdetect, i2cget, i2cset, and i2cdump. |
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| |
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| Adam Honse (GitHub: CalcProgrammer1) - 7/29/2012 |
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| -calcprogrammer1@gmail.com |
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\*-----------------------------------------------------*/
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#include "usi_i2c_slave.h"
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char usi_i2c_slave_internal_address;
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char usi_i2c_slave_address;
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char usi_i2c_mode;
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///////////////////////////////////////////////////////////////////////////////////////////////////
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////USI Slave States///////////////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////////////////////////////////
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// The I2C register file is stored as an array of pointers, point these to whatever your I2C registers
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// need to read/write in your code. This abstracts the buffer and makes it easier to write directly
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// to values in your code.
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char* USI_Slave_register_buffer[USI_SLAVE_REGISTER_COUNT];
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char USI_Slave_internal_address = 0;
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char USI_Slave_internal_address_set = 0;
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enum
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{
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USI_SLAVE_CHECK_ADDRESS,
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USI_SLAVE_SEND_DATA,
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USI_SLAVE_SEND_DATA_ACK_WAIT,
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USI_SLAVE_SEND_DATA_ACK_CHECK,
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USI_SLAVE_RECV_DATA_WAIT,
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USI_SLAVE_RECV_DATA_ACK_SEND
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} USI_I2C_Slave_State;
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/////////////////////////////////////////////////
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////USI Register Setup Values////////////////////
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/////////////////////////////////////////////////
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#define USI_SLAVE_COUNT_ACK_USISR 0b01110000 | (0x0E << USICNT0) //Counts one clock (ACK)
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#define USI_SLAVE_COUNT_BYTE_USISR 0b01110000 | (0x00 << USICNT0) //Counts 8 clocks (BYTE)
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#define USI_SLAVE_CLEAR_START_USISR 0b11110000 | (0x00 << USICNT0) //Clears START flag
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#define USI_SLAVE_SET_START_COND_USISR 0b01110000 | (0x00 << USICNT0)
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#define USI_SLAVE_SET_START_COND_USICR 0b10101000
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#define USI_SLAVE_STOP_DID_OCCUR_USICR 0b10111000
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#define USI_SLAVE_STOP_NOT_OCCUR_USICR 0b11101000
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/////////////////////////////////////////////////
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////USI Direction Macros/////////////////////////
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/////////////////////////////////////////////////
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#define USI_SET_SDA_OUTPUT() { DDR_USI |= (1 << PORT_USI_SDA); }
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#define USI_SET_SDA_INPUT() { DDR_USI &= ~(1 << PORT_USI_SDA); }
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#define USI_SET_SCL_OUTPUT() { DDR_USI |= (1 << PORT_USI_SCL); }
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#define USI_SET_SCL_INPUT() { DDR_USI &= ~(1 << PORT_USI_SCL); }
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#define USI_SET_BOTH_OUTPUT() { DDR_USI |= (1 << PORT_USI_SDA) | (1 << PORT_USI_SCL); }
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#define USI_SET_BOTH_INPUT() { DDR_USI &= ~((1 << PORT_USI_SDA) | (1 << PORT_USI_SCL)); }
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////////////////////////////////////////////////////////////////////////////////////////////////////
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void USI_I2C_Init(char address)
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{
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PORT_USI &= ~(1 << PORT_USI_SCL);
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PORT_USI &= ~(1 << PORT_USI_SDA);
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usi_i2c_slave_address = address;
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USI_SET_BOTH_INPUT();
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USICR = (1 << USISIE) | (0 << USIOIE) | (1 << USIWM1) | (0 << USIWM0) | (1 << USICS1) | (0 << USICS0) | (0 << USICLK) | (0 << USITC);
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USISR = (1 << USISIF) | (1 << USIOIF) | (1 << USIPF) | (1 << USIDC);
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}
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/////////////////////////////////////////////////////////////////////////////////
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// ISR USI_START_vect - USI Start Condition Detector Interrupt //
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// //
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// This interrupt occurs when the USI Start Condition Detector detects a //
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// start condition. A start condition marks the beginning of an I2C //
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// transmission and occurs when SDA has a high->low transition followed by an //
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// SCL high->low transition. When a start condition occurs, the I2C slave //
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// state is set to check address mode and the counter is set to wait 8 clocks //
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// (enough for the address/rw byte to be transmitted) before overflowing and //
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// triggering the first state table interrupt. If a stop condition occurs, //
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// reset the start condition detector to detect the next start condition. //
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/////////////////////////////////////////////////////////////////////////////////
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ISR(USI_START_vect)
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{
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USI_I2C_Slave_State = USI_SLAVE_CHECK_ADDRESS;
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USI_SET_SDA_INPUT();
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// wait for SCL to go low to ensure the Start Condition has completed (the
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// start detector will hold SCL low ) - if a Stop Condition arises then leave
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// the interrupt to prevent waiting forever - don't use USISR to test for Stop
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// Condition as in Application Note AVR312 because the Stop Condition Flag is
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// going to be set from the last TWI sequence
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while((PIN_USI & (1 << PIN_USI_SCL)) && !((PIN_USI & (1 << PIN_USI_SDA))));
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if(!(PIN_USI & (1 << PIN_USI_SDA)))
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{
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// a Stop Condition did not occur
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USICR = USI_SLAVE_STOP_NOT_OCCUR_USICR;
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}
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else
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{
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// a Stop Condition did occur
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USICR = USI_SLAVE_STOP_DID_OCCUR_USICR;
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}
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USISR = USI_SLAVE_CLEAR_START_USISR;
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}
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/////////////////////////////////////////////////////////////////////////////////
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// ISR USI_OVERFLOW_vect - USI Overflow Interrupt //
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// //
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// This interrupt occurs when the USI counter overflows. By setting this //
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// counter to 8, the USI can be commanded to wait one byte length before //
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// causing another interrupt (and thus state change). To wait for an ACK, //
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// set the counter to 1 (actually -1, or 0x0E) it will wait one clock. //
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// This is used to set up a state table of I2C transmission states that fits //
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// the I2C protocol for proper transmission. //
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/////////////////////////////////////////////////////////////////////////////////
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ISR(USI_OVERFLOW_vect)
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{
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switch (USI_I2C_Slave_State)
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{
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_CHECK_ADDRESS //
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// //
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// The first state after the start condition, this state checks the //
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// received byte against the stored slave address as well as the //
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// global transmission address of 0x00. If there is a match, the R/W //
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// bit is checked to branch either to sending or receiving modes. //
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// If the address was not for this device, the USI system is //
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// re-initialized for start condition. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_CHECK_ADDRESS:
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if((USIDR == 0) || ((USIDR >> 1) == usi_i2c_slave_address))
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{
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if (USIDR & 0x01)
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{
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USI_I2C_Slave_State = USI_SLAVE_SEND_DATA;
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}
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else
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{
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USI_Slave_internal_address_set = 0;
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USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_WAIT;
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}
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//Set USI to send ACK
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USIDR = 0;
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USI_SET_SDA_OUTPUT();
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USISR = USI_SLAVE_COUNT_ACK_USISR;
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}
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else
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{
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//Set USI to Start Condition Mode
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USICR = USI_SLAVE_SET_START_COND_USICR;
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USISR = USI_SLAVE_SET_START_COND_USISR;
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}
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break;
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_SEND_DATA_ACK_WAIT //
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// //
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// Wait 1 clock period for the master to ACK or NACK the sent data //
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// If master NACK's, it means that master doesn't want any more data. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_SEND_DATA_ACK_WAIT:
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//After sending, immediately shut off PORT = 1 to prevent driving
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//the line high (I2C should *NEVER* drive high, and could damage
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//connected devices if operating at different voltage levels)
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PORT_USI &= ~(1 << PORT_USI_SDA);
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USI_I2C_Slave_State = USI_SLAVE_SEND_DATA_ACK_CHECK;
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USI_SET_SDA_INPUT();
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USISR = USI_SLAVE_COUNT_ACK_USISR;
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break;
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_SEND_DATA_ACK_CHECK //
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// //
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// Check USIDR to see if master sent ACK or NACK. If NACK, set up //
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// a reset to START conditions, if ACK, fall through into SEND_DATA //
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// to continue sending data. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_SEND_DATA_ACK_CHECK:
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if(USIDR)
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{
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//The master sent a NACK, indicating that it will not accept
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//more data. Reset into START condition state
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USICR = USI_SLAVE_SET_START_COND_USICR;
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USISR = USI_SLAVE_SET_START_COND_USISR;
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return;
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}
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//else: fall through into SEND_DATA
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_SEND_DATA //
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// //
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// Set USIDR to the data to be sent, then set up SDA registers to //
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// enable data transmission in the next 8 clocks. Set to wait 8 //
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// clocks and proceed to wait for ACK. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_SEND_DATA:
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if(USI_Slave_internal_address <= USI_SLAVE_REGISTER_COUNT)
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{
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USIDR = *(USI_Slave_register_buffer[USI_Slave_internal_address]);
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}
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else
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{
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USIDR = 0x00;
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}
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USI_Slave_internal_address++;
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USI_I2C_Slave_State = USI_SLAVE_SEND_DATA_ACK_WAIT;
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//To send data, DDR for SDA must be 1 (Output) and PORT for SDA
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//must also be 1 (line drives low on USIDR MSB = 0 or PORT = 0)
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USI_SET_SDA_OUTPUT();
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PORT_USI |= (1 << PORT_USI_SDA);
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USISR = USI_SLAVE_COUNT_BYTE_USISR;
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break;
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_RECV_DATA_WAIT //
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// //
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// Prepares to wait 8 clocks to receive a data byte from the master. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_RECV_DATA_WAIT:
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USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_ACK_SEND;
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USI_SET_SDA_INPUT();
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USISR = USI_SLAVE_COUNT_BYTE_USISR;
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break;
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/////////////////////////////////////////////////////////////////////////
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// Case USI_SLAVE_RECV_DATA_ACK_SEND //
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// //
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// After waiting for the master to finish transmission, this reads //
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// USIDR into either the i2c buffer or internal address, then sends //
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// an acknowledgement to the master. //
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/////////////////////////////////////////////////////////////////////////
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case USI_SLAVE_RECV_DATA_ACK_SEND:
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USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_WAIT;
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if(USI_Slave_internal_address_set == 0)
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{
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USI_Slave_internal_address = USIDR;
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USI_Slave_internal_address_set = 1;
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}
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else if(USI_Slave_internal_address <= USI_SLAVE_REGISTER_COUNT)
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{
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*(USI_Slave_register_buffer[USI_Slave_internal_address]) = USIDR;
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}
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USIDR = 0;
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USI_SET_SDA_OUTPUT();
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USISR = USI_SLAVE_COUNT_ACK_USISR;
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break;
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}
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}
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