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diagramas de firmware de power_engine y update de time_engine
diagramas de firmware de power_engine y update de time_engine
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main.vhd
15 lines | 191 B | text/x-vhdl | VhdlLexer
/ trunk / firmware / sources / processingEngine / main.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity main is
port (
clk : in std_logic;
rst : in std_logic
);
end entity main;
architecture RTL of main is
begin
end architecture RTL;