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/*
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* https://github.com/Wallacoloo/Raspberry-Pi-DMA-Example : DMA Raspberry Pi Examples
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* Author: Colin Wallace
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This is free and unencumbered software released into the public domain.
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Anyone is free to copy, modify, publish, use, compile, sell, or
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distribute this software, either in source code form or as a compiled
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binary, for any purpose, commercial or non-commercial, and by any
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means.
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In jurisdictions that recognize copyright laws, the author or authors
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of this software dedicate any and all copyright interest in the
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software to the public domain. We make this dedication for the benefit
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of the public at large and to the detriment of our heirs and
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successors. We intend this dedication to be an overt act of
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relinquishment in perpetuity of all present and future rights to this
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software under copyright law.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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OTHER DEALINGS IN THE SOFTWARE.
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For more information, please refer to <http://unlicense.org/>
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*/
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/*
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* processor documentation is at: http://www.raspberrypi.org/wp-content/uploads/2012/02/BCM2835-ARM-Peripherals.pdf
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* pg 38 for DMA
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*/
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#include <sys/mman.h> //for mmap
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#include <unistd.h> //for NULL
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#include <stdio.h> //for printf
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#include <stdlib.h> //for exit
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#include <fcntl.h> //for file opening
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#include <stdint.h> //for uint32_t
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#include <string.h> //for memset
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#define PAGE_SIZE 4096 //mmap maps pages of memory, so we must give it multiples of this size
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//physical addresses for the DMA peripherals, as found in the processor documentation:
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#define DMA_BASE 0x20007000
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//DMA Channel register sets (format of these registers is found in DmaChannelHeader struct):
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#define DMACH0 0x20007000
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#define DMACH1 0x20007100
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#define DMACH2 0x20007200
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#define DMACH3 0x20007300
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//...
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#define DMACH(n) (DMACH0 + (n)*0x100)
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//Each DMA channel has some associated registers, but only CS (control and status), CONBLK_AD (control block address), and DEBUG are writeable
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//DMA is started by writing address of the first Control Block to the DMA channel's CONBLK_AD register and then setting the ACTIVE bit inside the CS register (bit 0)
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//Note: DMA channels are connected directly to peripherals, so physical addresses should be used (affects control block's SOURCE, DEST and NEXTCONBK addresses).
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#define DMAENABLE 0x20007ff0 //bit 0 should be set to 1 to enable channel 0. bit 1 enables channel 1, etc.
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//flags used in the DmaChannelHeader struct:
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#define DMA_CS_RESET (1<<31)
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#define DMA_CS_ACTIVE (1<<0)
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#define DMA_DEBUG_READ_ERROR (1<<2)
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#define DMA_DEBUG_FIFO_ERROR (1<<1)
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#define DMA_DEBUG_READ_LAST_NOT_SET_ERROR (1<<0)
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//flags used in the DmaControlBlock struct:
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#define DMA_CB_TI_DEST_INC (1<<4)
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#define DMA_CB_TI_SRC_INC (1<<8)
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//set bits designated by (mask) at the address (dest) to (value), without affecting the other bits
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//eg if x = 0b11001100
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// writeBitmasked(&x, 0b00000110, 0b11110011),
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// then x now = 0b11001110
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void writeBitmasked(volatile uint32_t *dest, uint32_t mask, uint32_t value) {
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uint32_t cur = *dest;
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uint32_t new = (cur & (~mask)) | (value & mask);
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*dest = new;
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*dest = new; //added safety for when crossing memory barriers.
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}
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struct DmaChannelHeader {
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uint32_t CS; //Control and Status
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//31 RESET; set to 1 to reset DMA
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//30 ABORT; set to 1 to abort current DMA control block (next one will be loaded & continue)
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//29 DISDEBUG; set to 1 and DMA won't be paused when debug signal is sent
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//28 WAIT_FOR_OUTSTANDING_WRITES; set to 1 and DMA will wait until peripheral says all writes have gone through before loading next CB
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//24-74 reserved
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//20-23 PANIC_PRIORITY; 0 is lowest priority
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//16-19 PRIORITY; bus scheduling priority. 0 is lowest
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//9-15 reserved
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//8 ERROR; read as 1 when error is encountered. error can be found in DEBUG register.
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//7 reserved
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//6 WAITING_FOR_OUTSTANDING_WRITES; read as 1 when waiting for outstanding writes
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//5 DREQ_STOPS_DMA; read as 1 if DREQ is currently preventing DMA
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//4 PAUSED; read as 1 if DMA is paused
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//3 DREQ; copy of the data request signal from the peripheral, if DREQ is enabled. reads as 1 if data is being requested, else 0
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//2 INT; set when current CB ends and its INTEN=1. Write a 1 to this register to clear it
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//1 END; set when the transfer defined by current CB is complete. Write 1 to clear.
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//0 ACTIVE; write 1 to activate DMA (load the CB before hand)
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uint32_t CONBLK_AD; //Control Block Address
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uint32_t TI; //transfer information; see DmaControlBlock.TI for description
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uint32_t SOURCE_AD; //Source address
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uint32_t DEST_AD; //Destination address
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uint32_t TXFR_LEN; //transfer length.
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uint32_t STRIDE; //2D Mode Stride. Only used if TI.TDMODE = 1
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uint32_t NEXTCONBK; //Next control block. Must be 256-bit aligned (32 bytes; 8 words)
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uint32_t DEBUG; //controls debug settings
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};
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struct DmaControlBlock {
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uint32_t TI; //transfer information
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//31:27 unused
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//26 NO_WIDE_BURSTS
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//21:25 WAITS; number of cycles to wait between each DMA read/write operation
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//16:20 PERMAP; peripheral number to be used for DREQ signal (pacing). set to 0 for unpaced DMA.
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//12:15 BURST_LENGTH
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//11 SRC_IGNORE; set to 1 to not perform reads. Used to manually fill caches
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//10 SRC_DREQ; set to 1 to have the DREQ from PERMAP gate requests.
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//9 SRC_WIDTH; set to 1 for 128-bit moves, 0 for 32-bit moves
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//8 SRC_INC; set to 1 to automatically increment the source address after each read (you'll want this if you're copying a range of memory)
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//7 DEST_IGNORE; set to 1 to not perform writes.
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//6 DEST_DREG; set to 1 to have the DREQ from PERMAP gate *writes*
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//5 DEST_WIDTH; set to 1 for 128-bit moves, 0 for 32-bit moves
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//4 DEST_INC; set to 1 to automatically increment the destination address after each read (Tyou'll want this if you're copying a range of memory)
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//3 WAIT_RESP; make DMA wait for a response from the peripheral during each write. Ensures multiple writes don't get stacked in the pipeline
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//2 unused (0)
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//1 TDMODE; set to 1 to enable 2D mode
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//0 INTEN; set to 1 to generate an interrupt upon completion
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uint32_t SOURCE_AD; //Source address
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uint32_t DEST_AD; //Destination address
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uint32_t TXFR_LEN; //transfer length.
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uint32_t STRIDE; //2D Mode Stride. Only used if TI.TDMODE = 1
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uint32_t NEXTCONBK; //Next control block. Must be 256-bit aligned (32 bytes; 8 words)
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uint32_t _reserved[2];
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};
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//allocate a page & simultaneously determine its physical address.
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//virtAddr and physAddr are essentially passed by-reference.
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//this allows for:
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//void *virt, *phys;
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//makeVirtPhysPage(&virt, &phys)
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//now, virt[N] exists for 0 <= N < PAGE_SIZE,
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// and phys+N is the physical address for virt[N]
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//based on http://www.raspians.com/turning-the-raspberry-pi-into-an-fm-transmitter/
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void makeVirtPhysPage(void** virtAddr, void** physAddr) {
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*virtAddr = valloc(PAGE_SIZE); //allocate one page of RAM
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//force page into RAM and then lock it there:
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((int*)*virtAddr)[0] = 1;
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mlock(*virtAddr, PAGE_SIZE);
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memset(*virtAddr, 0, PAGE_SIZE); //zero-fill the page for convenience
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//Magic to determine the physical address for this page:
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uint64_t pageInfo;
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int file = open("/proc/self/pagemap", 'r');
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lseek(file, ((uint32_t)*virtAddr)/PAGE_SIZE*8, SEEK_SET);
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read(file, &pageInfo, 8);
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*physAddr = (void*)(uint32_t)(pageInfo*PAGE_SIZE);
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printf("makeVirtPhysPage virtual to phys: %p -> %p\n", *virtAddr, *physAddr);
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}
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//call with virtual address to deallocate a page allocated with makeVirtPhysPage
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void freeVirtPhysPage(void* virtAddr) {
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munlock(virtAddr, PAGE_SIZE);
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free(virtAddr);
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}
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//map a physical address into our virtual address space. memfd is the file descriptor for /dev/mem
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volatile uint32_t* mapPeripheral(int memfd, int addr) {
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///dev/mem behaves as a file. We need to map that file into memory:
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void *mapped = mmap(NULL, PAGE_SIZE, PROT_READ|PROT_WRITE, MAP_SHARED, memfd, addr);
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//now, *mapped = memory at physical address of addr.
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if (mapped == MAP_FAILED) {
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printf("failed to map memory (did you remember to run as root?)\n");
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exit(1);
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} else {
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printf("mapped: %p\n", mapped);
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}
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return (volatile uint32_t*)mapped;
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}
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int main() {
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//cat /sys/module/dma/parameters/dmachans gives a bitmask of DMA channels that are not used by GPU. Results: ch 1, 3, 6, 7 are reserved.
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//dmesg | grep "DMA"; results: Ch 2 is used by SDHC host
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//ch 0 is known to be used for graphics acceleration
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//Thus, applications can use ch 4, 5, or the LITE channels @ 8 and beyond.
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int dmaChNum = 5;
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//First, open the linux device, /dev/mem
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//dev/mem provides access to the physical memory of the entire processor+ram
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//This is needed because Linux uses virtual memory, thus the process's memory at 0x00000000 will NOT have the same contents as the physical memory at 0x00000000
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int memfd = open("/dev/mem", O_RDWR | O_SYNC);
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if (memfd < 0) {
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printf("Failed to open /dev/mem (did you remember to run as root?)\n");
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exit(1);
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}
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//now map /dev/mem into memory, but only map specific peripheral sections:
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volatile uint32_t *dmaBaseMem = mapPeripheral(memfd, DMA_BASE);
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//configure DMA:
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//allocate 1 page for the source and 1 page for the destination:
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void *virtSrcPage, *physSrcPage;
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makeVirtPhysPage(&virtSrcPage, &physSrcPage);
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void *virtDestPage, *physDestPage;
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makeVirtPhysPage(&virtDestPage, &physDestPage);
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//write a few bytes to the source page:
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char *srcArray = (char*)virtSrcPage;
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srcArray[0] = 'h';
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srcArray[1] = 'e';
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srcArray[2] = 'l';
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srcArray[3] = 'l';
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srcArray[4] = 'o';
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srcArray[5] = ' ';
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srcArray[6] = 'w';
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srcArray[7] = 'o';
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srcArray[8] = 'r';
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srcArray[9] = 'l';
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srcArray[10] = 'd';
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srcArray[11] = 0; //null terminator used for printf call.
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//allocate 1 page for the control blocks
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void *virtCbPage, *physCbPage;
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makeVirtPhysPage(&virtCbPage, &physCbPage);
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//dedicate the first 8 words of this page to holding the cb.
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struct DmaControlBlock *cb1 = (struct DmaControlBlock*)virtCbPage;
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//fill the control block:
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cb1->TI = DMA_CB_TI_SRC_INC | DMA_CB_TI_DEST_INC; //after each byte copied, we want to increment the source and destination address of the copy, otherwise we'll be copying to the same address.
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cb1->SOURCE_AD = (uint32_t)physSrcPage; //set source and destination DMA address
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cb1->DEST_AD = (uint32_t)physDestPage;
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cb1->TXFR_LEN = 12; //transfer 12 bytes
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cb1->STRIDE = 0; //no 2D stride
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cb1->NEXTCONBK = 0; //no next control block
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printf("destination was initially: '%s'\n", (char*)virtDestPage);
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//enable DMA channel (it's probably already enabled, but we want to be sure):
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writeBitmasked(dmaBaseMem + DMAENABLE - DMA_BASE, 1 << dmaChNum, 1 << dmaChNum);
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//configure the DMA header to point to our control block:
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volatile struct DmaChannelHeader *dmaHeader = (volatile struct DmaChannelHeader*)(dmaBaseMem + (DMACH(dmaChNum) - DMA_BASE)/4); //dmaBaseMem is a uint32_t ptr, so divide by 4 before adding byte offset
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dmaHeader->CS = DMA_CS_RESET; //make sure to disable dma first.
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sleep(1); //give time for the reset command to be handled.
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dmaHeader->DEBUG = DMA_DEBUG_READ_ERROR | DMA_DEBUG_FIFO_ERROR | DMA_DEBUG_READ_LAST_NOT_SET_ERROR; // clear debug error flags
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dmaHeader->CONBLK_AD = (uint32_t)physCbPage; //we have to point it to the PHYSICAL address of the control block (cb1)
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dmaHeader->CS = DMA_CS_ACTIVE; //set active bit, but everything else is 0.
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sleep(1); //give time for copy to happen
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printf("destination reads: '%s'\n", (char*)virtDestPage);
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//cleanup
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freeVirtPhysPage(virtCbPage);
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freeVirtPhysPage(virtDestPage);
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freeVirtPhysPage(virtSrcPage);
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return 0;
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}
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