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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 17:23:06 02/16/2016 | |
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6 | -- Design Name: | |
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7 | -- Module Name: DCM_fwd_int - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
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12 | -- | |
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13 | -- Dependencies: | |
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14 | -- | |
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15 | -- Revision: | |
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16 | -- Revision 0.01 - File Created | |
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17 | -- Additional Comments: | |
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18 | -- | |
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19 | ---------------------------------------------------------------------------------- | |
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20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | ||
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23 | -- Uncomment the following library declaration if using | |
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24 | -- arithmetic functions with Signed or Unsigned values | |
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25 | --use IEEE.NUMERIC_STD.ALL; | |
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26 | ||
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27 | -- Uncomment the following library declaration if instantiating | |
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28 | -- any Xilinx primitives in this code. | |
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29 | library UNISIM; | |
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30 | use UNISIM.VComponents.all; | |
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31 | ||
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32 | entity DCM_fwd_int is | |
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33 | PORT( | |
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34 | clk_main_io: IN std_logic; | |
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35 | c_200MHz_in: OUT std_logic | |
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36 | ); | |
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37 | end DCM_fwd_int; | |
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38 | ||
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39 | architecture Behavioral of DCM_fwd_int is | |
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40 | SIGNAL clk_main: std_logic; | |
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41 | SIGNAL c_16MHz: std_logic; | |
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42 | ||
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43 | SIGNAL clk_fb_aux: std_logic; | |
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44 | SIGNAL clk_fb_aux_200MHz: std_logic; | |
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45 | ||
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46 | SIGNAL c_16MHz_inv: std_logic; | |
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47 | ||
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48 | begin | |
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49 | ||
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50 | ||
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51 | ||
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52 | DCM_SP_inst_int : DCM_SP | |
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53 | generic map ( | |
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54 | CLKDV_DIVIDE => 2.0, -- CLKDV divide value | |
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55 | -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). | |
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56 | CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32) | |
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57 | CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32) | |
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58 | CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE) | |
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59 | CLKIN_PERIOD => 16.667, -- Input clock period specified in nS | |
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60 | CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE) | |
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61 | CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X) | |
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62 | DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS | |
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63 | DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value | |
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64 | DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value | |
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65 | DSS_MODE => "NONE", -- Unsupported - Do not change value | |
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66 | DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value | |
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67 | FACTORY_JF => X"c080", -- Unsupported - Do not change value | |
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68 | PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255) | |
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69 | STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) | |
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70 | ) | |
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71 | port map ( | |
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72 | CLK0 => clk_fb_aux_200MHz, -- 1-bit output: 0 degree clock output | |
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73 | CLK180 => open, -- 1-bit output: 180 degree clock output | |
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74 | CLK270 => open, -- 1-bit output: 270 degree clock output | |
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75 | CLK2X => open, -- 1-bit output: 2X clock frequency clock output | |
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76 | CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output | |
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77 | CLK90 => open, -- 1-bit output: 90 degree clock output | |
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78 | CLKDV => open, -- 1-bit output: Divided clock output | |
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79 | CLKFX => c_200MHz_in, -- 1-bit output: Digital Frequency Synthesizer output (DFS) | |
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80 | CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output | |
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81 | LOCKED => open, -- 1-bit output: DCM_SP Lock Output | |
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82 | PSDONE => open, -- 1-bit output: Phase shift done output | |
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83 | STATUS => open, -- 8-bit output: DCM_SP status output | |
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84 | CLKFB => clk_fb_aux_200MHz, -- 1-bit input: Clock feedback input | |
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85 | CLKIN => clk_main_io, -- 1-bit input: Clock input | |
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86 | DSSEN => '0', -- 1-bit input: Unsupported, specify to GND. | |
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87 | PSCLK => '1', -- 1-bit input: Phase shift clock input | |
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88 | PSEN => '0', -- 1-bit input: Phase shift enable | |
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89 | PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input | |
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90 | RST => '0' -- 1-bit input: Active high reset input | |
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91 | ); | |
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92 | ||
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93 | end Behavioral; No newline at end of file | |
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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 15:47:34 02/08/2017 | |
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6 | -- Design Name: | |
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7 | -- Module Name: Data_Req_gen - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
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12 | -- | |
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13 | -- Dependencies: | |
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14 | -- | |
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15 | -- Revision: | |
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16 | -- Revision 0.01 - File Created | |
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17 | -- Additional Comments: | |
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18 | -- | |
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19 | ---------------------------------------------------------------------------------- | |
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20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | ||
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23 | -- Uncomment the following library declaration if using | |
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24 | -- arithmetic functions with Signed or Unsigned values | |
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25 | use IEEE.NUMERIC_STD.ALL; | |
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26 | ||
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27 | -- Uncomment the following library declaration if instantiating | |
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28 | -- any Xilinx primitives in this code. | |
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29 | --library UNISIM; | |
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30 | --use UNISIM.VComponents.all; | |
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31 | ||
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32 | entity Data_Req_gen is | |
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33 | GENERIC ( | |
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34 | --CLOCKS_COUNT_1KSPS: INTEGER :=240000; --For 240 000 | |
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35 | --CYCLES_COUNT_DUTY_1KSPS: INTEGER :=2400; --For 2400 | |
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36 | --PULSES_COUNT_1KSPS: INTEGER :=1000; --For 1 000 | |
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37 | ||
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38 | NBITS_PERIOD: INTEGER :=18; | |
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39 | NBITS_DUTY: INTEGER :=12; | |
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40 | NBITS_PULSES: INTEGER :=10 | |
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41 | ); | |
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42 | PORT( | |
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43 | c_200MHz_in : IN std_logic; | |
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44 | reset_int : IN std_logic; | |
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45 | pps : IN std_logic; | |
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46 | data_req : OUT std_logic | |
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47 | ); | |
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48 | end Data_Req_gen; | |
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49 | ||
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50 | architecture Behavioral of Data_Req_gen is | |
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51 | --Constantes | |
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52 | CONSTANT LIM_COUNT_PERIOD : std_logic_vector((NBITS_PERIOD-1) downto 0) := "111010100100000000"; --240000 | |
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53 | --CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_DUTY-1) downto 0) := "100101100000"; --2400 | |
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54 | CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_PERIOD-1) downto 0) := "011101010011000000"; | |
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55 | CONSTANT LIM_COUNT_PULSES : std_logic_vector((NBITS_PULSES-1) downto 0) := "1111101001"; --1000 | |
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56 | --CONSTANT LIM_COUNT_PULSES : std_logic_vector((2-1) downto 0) := "11"; | |
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57 | --Contadores de ciclos de reloj(count_clock) y pulsos generados(count_cycle) | |
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58 | SIGNAL count_clock : std_logic_vector((NBITS_PERIOD-1) downto 0) :="000000000000000000"; --"00 0000 0000 0000 0000" | |
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59 | SIGNAL count_pulses : std_logic_vector(9 downto 0) :="0000000000"; --"00 0000 0000" | |
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60 | --SIGNAL count_pulses : std_logic_vector(1 downto 0) :=(OTHERS =>'0'); --"00" | |
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61 | --Registro para deteccion de flanco | |
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62 | SIGNAL pps_r: std_logic_vector(1 downto 0) :="00"; | |
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63 | SIGNAL pps_rising : std_logic := '0'; | |
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64 | SIGNAL data_req_s: std_logic :='0'; | |
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65 | ||
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66 | begin | |
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67 | ||
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68 | --Deteccion de flanco de pps | |
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69 | pps_bloco: PROCESS(c_200MHz_in) | |
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70 | BEGIN | |
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71 | IF (rising_edge(c_200MHz_in)) THEN | |
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72 | IF(reset_int = '0') THEN | |
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73 | pps_r <= (OTHERS=>'0'); | |
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74 | ELSE | |
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75 | pps_r <= pps_r(0) & pps; | |
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76 | IF(pps_r(1 downto 0) = "01") THEN | |
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77 | pps_rising <= '1'; | |
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78 | ELSE | |
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79 | pps_rising <= '0'; | |
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80 | END IF; | |
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81 | END IF; | |
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82 | END IF; | |
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83 | END PROCESS; | |
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84 | ||
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85 | ||
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86 | out_generator: PROCESS(c_200MHz_in) | |
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87 | BEGIN | |
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88 | IF(rising_edge(c_200MHz_in)) THEN | |
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89 | IF(pps_rising = '1') THEN | |
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90 | data_req_s <= '1'; | |
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91 | count_clock <= (OTHERS=>'0'); | |
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92 | count_pulses <= "0000000001"; | |
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93 | ELSE | |
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94 | IF(count_pulses = LIM_COUNT_PULSES) THEN | |
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95 | data_req_s<= '0'; | |
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96 | ELSE | |
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97 | IF(count_clock = LIM_COUNT_PERIOD) THEN | |
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98 | --data_req<= '1'; | |
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99 | count_clock <= (OTHERS=>'0'); | |
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100 | count_pulses <= std_logic_vector(unsigned(count_pulses)+1); | |
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101 | ELSIF(count_clock = LIM_COUNT_DUTY) THEN | |
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102 | data_req_s<= '0'; | |
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103 | count_clock <= std_logic_vector(unsigned(count_clock)+1); | |
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104 | ELSIF(count_clock = "000000000000000000" AND count_pulses /= "00") THEN | |
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105 | data_req_s<= '1'; | |
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106 | count_clock <= std_logic_vector(unsigned(count_clock)+1); | |
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107 | ELSE | |
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108 | count_clock <= std_logic_vector(unsigned(count_clock)+1); | |
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109 | END IF; | |
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110 | END IF; | |
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111 | END IF; | |
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112 | END IF; | |
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113 | END PROCESS; | |
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114 | ||
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115 | data_req <= data_req_s; | |
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116 | end Behavioral; No newline at end of file | |
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1 | ---------------------------------------------------------------------------------- | |
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2 | -- Company: | |
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3 | -- Engineer: | |
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4 | -- | |
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5 | -- Create Date: 16:24:04 02/21/2017 | |
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6 | -- Design Name: | |
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7 | -- Module Name: DtoDPRAM - Behavioral | |
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8 | -- Project Name: | |
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9 | -- Target Devices: | |
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10 | -- Tool versions: | |
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11 | -- Description: | |
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12 | -- | |
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13 | -- Dependencies: | |
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14 | -- | |
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15 | -- Revision: | |
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16 | -- Revision 0.01 - File Created | |
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17 | -- Additional Comments: | |
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18 | -- | |
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19 | ---------------------------------------------------------------------------------- | |
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20 | library IEEE; | |
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21 | use IEEE.STD_LOGIC_1164.ALL; | |
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22 | ||
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23 | -- Uncomment the following library declaration if using | |
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24 | -- arithmetic functions with Signed or Unsigned values | |
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25 | use IEEE.NUMERIC_STD.ALL; | |
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26 | ||
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27 | -- Uncomment the following library declaration if instantiating | |
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28 | -- any Xilinx primitives in this code. | |
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29 | --library UNISIM; | |
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30 | --use UNISIM.VComponents.all; | |
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31 | ||
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32 | entity DtoDPRAM is | |
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33 | GENERIC( | |
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34 | ADDR_LENGTH: INTEGER := 12; | |
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35 | DATAOUT_LENGTH: INTEGER := 8; | |
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36 | DATAIN_LENGTH: INTEGER := 40; | |
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37 | CHAN_NUM: INTEGER := 5; | |
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38 | COUNT_BYTE_SZ: INTEGER := 3; | |
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39 | COUNT_PACK_SZ: INTEGER := 6 | |
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40 | ||
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41 | ); | |
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42 | ||
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43 | PORT( | |
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44 | --Reset general | |
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45 | rst_bar: IN std_logic; | |
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46 | ||
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47 | --Reset general | |
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48 | data_req: IN std_logic; | |
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49 | ||
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50 | --Entrada de reloj principal | |
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51 | clk_main: IN std_logic; | |
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52 | ||
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53 | --Entradas para indicar dato preparado por leer | |
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54 | --Desde los nibble to packets | |
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55 | ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0); | |
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56 | ||
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57 | --Senhal para que indica que termino con una peticion | |
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58 | --Hacia los nibble to packets | |
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59 | ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0); | |
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60 | ||
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61 | --Data IN | |
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62 | datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0); | |
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63 | datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0); | |
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64 | datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0); | |
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65 | datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0); | |
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66 | datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0); | |
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67 | ||
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68 | --DPRAM senhales de control, direccion y data | |
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69 | --Direccion de escritura/lectura | |
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70 | addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); | |
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71 | dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0); | |
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72 | enA: OUT std_logic; | |
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73 | --Aviso de Paquete de 40 muestras solicitadas a los 5 canales | |
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74 | rpi_req: OUT std_logic | |
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75 | ||
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76 | ); | |
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77 | end DtoDPRAM; | |
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78 | ||
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79 | architecture Behavioral of DtoDPRAM is | |
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80 | SIGNAL datach1_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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81 | SIGNAL datach2_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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82 | SIGNAL datach3_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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83 | SIGNAL datach4_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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84 | SIGNAL datach5_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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85 | ||
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86 | --Estados del controlador de memoria | |
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87 | --Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria | |
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88 | --espera de pedido y estados para proceder a una lectura | |
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89 | TYPE ram_cont_states IS (idle, | |
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90 | ||
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91 | ------------------------------------------ | |
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92 | pre_ch1, wr_ch1, end_wrt_ch_1, | |
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93 | ------------------------------------------ | |
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94 | pre_ch2, wr_ch2, end_wrt_ch_2, | |
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95 | ------------------------------------------ | |
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96 | pre_ch3, wr_ch3, end_wrt_ch_3, | |
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97 | ------------------------------------------ | |
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98 | pre_ch4, wr_ch4, end_wrt_ch_4, | |
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99 | ------------------------------------------ | |
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100 | pre_ch5, wr_ch5, end_wrt_ch_5 | |
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101 | ||
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102 | ); | |
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103 | ||
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104 | SIGNAL ram_contr_cur_state: ram_cont_states := idle; | |
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105 | SIGNAL ram_contr_next_state: ram_cont_states := idle; | |
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106 | ||
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107 | ---------------------------------- | |
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108 | --Estados de la atencion a ready's | |
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109 | TYPE chn_cont_states IS ( idle, | |
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110 | checking_ch1, attending_ch1, | |
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111 | checking_ch2, attending_ch2, | |
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112 | checking_ch3, attending_ch3, | |
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113 | checking_ch4, attending_ch4, | |
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114 | checking_ch5, attending_ch5 | |
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115 | ); | |
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116 | ||
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117 | SIGNAL ch_cont_cur_state: chn_cont_states := idle; | |
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118 | SIGNAL ch_cont_next_state: chn_cont_states := idle; | |
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119 | ||
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120 | SIGNAL count_ch_byte: std_logic_vector((COUNT_BYTE_SZ-1) downto 0) := (OTHERS=>'0'); | |
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121 | ||
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122 | --Direcciones base por canal | |
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123 | CONSTANT BASE_ADDR_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0'); | |
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124 | CONSTANT BASE_ADDR_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000011001000"; --200 | |
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125 | CONSTANT BASE_ADDR_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000110010000"; --400 | |
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126 | CONSTANT BASE_ADDR_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001001011000"; --600 | |
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127 | CONSTANT BASE_ADDR_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001100100000"; --800 | |
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128 | ||
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129 | CONSTANT BASE_BUFFER_2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "010000000000"; --1024 | |
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130 | ||
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131 | SIGNAL sel_buf: std_logic := '0'; | |
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132 | SIGNAL count_pack: std_logic_vector((COUNT_PACK_SZ-1) downto 0) := (OTHERS => '0'); | |
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133 | begin | |
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134 | ||
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135 | --------------------- | |
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136 | --Estados para atencion de canales | |
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137 | ch_cont_cambio_estados: PROCESS(clk_main) | |
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138 | BEGIN | |
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139 | IF (rising_edge(clk_main)) THEN | |
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140 | IF(rst_bar = '0') THEN | |
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141 | ch_cont_cur_state <= idle; | |
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142 | ELSE | |
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143 | ch_cont_cur_state <= ch_cont_next_state; | |
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144 | END IF; | |
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145 | END IF; | |
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146 | END PROCESS; | |
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147 | ||
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148 | ch_salidas_estados: PROCESS(ch_cont_cur_state, | |
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149 | ch_rdy_vector, | |
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150 | ram_contr_cur_state | |
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151 | ) | |
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152 | BEGIN | |
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153 | ||
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154 | CASE ch_cont_cur_state IS | |
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155 | WHEN idle => | |
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156 | ch_cont_next_state <= checking_ch1; | |
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157 | ||
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158 | WHEN checking_ch1 => | |
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159 | IF(ch_rdy_vector(0) = '1') THEN | |
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160 | ch_cont_next_state <= attending_ch1; | |
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161 | ELSE | |
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162 | ch_cont_next_state <= checking_ch2; | |
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163 | END IF; | |
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164 | ||
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165 | WHEN attending_ch1 => | |
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166 | IF(ram_contr_cur_state = end_wrt_ch_1) THEN | |
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167 | ch_cont_next_state <= checking_ch2; | |
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168 | ELSE | |
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169 | ch_cont_next_state <= attending_ch1; | |
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170 | END IF; | |
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171 | ||
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172 | WHEN checking_ch2 => | |
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173 | IF(ch_rdy_vector(1) = '1') THEN | |
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174 | ch_cont_next_state <= attending_ch2; | |
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175 | ELSE | |
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176 | ch_cont_next_state <= checking_ch3; | |
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177 | END IF; | |
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178 | ||
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179 | WHEN attending_ch2 => | |
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180 | IF(ram_contr_cur_state = end_wrt_ch_2) THEN | |
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181 | ch_cont_next_state <= checking_ch3; | |
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182 | ELSE | |
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183 | ch_cont_next_state <= attending_ch2; | |
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184 | END IF; | |
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185 | ||
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186 | WHEN checking_ch3 => | |
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187 | IF(ch_rdy_vector(2) = '1') THEN | |
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188 | ch_cont_next_state <= attending_ch3; | |
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189 | ELSE | |
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190 | ch_cont_next_state <= checking_ch4; | |
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191 | END IF; | |
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192 | ||
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193 | WHEN attending_ch3 => | |
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194 | IF(ram_contr_cur_state = end_wrt_ch_3) THEN | |
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195 | ch_cont_next_state <= checking_ch4; | |
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196 | ELSE | |
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197 | ch_cont_next_state <= attending_ch3; | |
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198 | END IF; | |
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199 | ||
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200 | WHEN checking_ch4 => | |
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201 | IF(ch_rdy_vector(3) = '1') THEN | |
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202 | ch_cont_next_state <= attending_ch4; | |
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203 | ELSE | |
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204 | ch_cont_next_state <= checking_ch5; | |
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205 | END IF; | |
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206 | ||
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207 | WHEN attending_ch4 => | |
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208 | IF(ram_contr_cur_state = end_wrt_ch_4) THEN | |
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209 | ch_cont_next_state <= checking_ch5; | |
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210 | ELSE | |
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211 | ch_cont_next_state <= attending_ch4; | |
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212 | END IF; | |
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213 | ||
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214 | WHEN checking_ch5 => | |
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215 | IF(ch_rdy_vector(4) = '1') THEN | |
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216 | ch_cont_next_state <= attending_ch5; | |
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217 | ELSE | |
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218 | ch_cont_next_state <= checking_ch1; | |
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219 | END IF; | |
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220 | ||
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221 | WHEN attending_ch5 => | |
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222 | IF(ram_contr_cur_state = end_wrt_ch_5) THEN | |
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223 | ch_cont_next_state <= checking_ch1; | |
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224 | ELSE | |
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225 | ch_cont_next_state <= attending_ch5; | |
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226 | END IF; | |
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227 | ||
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228 | WHEN OTHERS => | |
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229 | ||
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230 | ch_cont_next_state <= idle; | |
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231 | ||
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232 | END CASE; | |
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233 | END PROCESS; | |
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234 | ||
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235 | -------------------------------------------------- | |
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236 | --Estados de m�quina principal para control de RAM | |
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237 | ||
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238 | ctrl_cambio_estados: PROCESS(clk_main) | |
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239 | BEGIN | |
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240 | IF (rising_edge(clk_main)) THEN | |
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241 | IF(rst_bar = '0') THEN | |
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242 | ram_contr_cur_state <= idle; | |
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243 | ELSE | |
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244 | ram_contr_cur_state <= ram_contr_next_state; | |
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245 | END IF; | |
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246 | END IF; | |
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247 | END PROCESS; | |
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248 | ||
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249 | --Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set s�. | |
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250 | ctrl_salidas_estados: PROCESS(ram_contr_cur_state, ch_cont_cur_state, | |
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251 | count_pack, count_ch_byte, sel_buf, | |
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252 | datach1_aux, datach2_aux, datach3_aux, datach4_aux, datach5_aux | |
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253 | ) | |
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254 | BEGIN | |
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255 | CASE ram_contr_cur_state IS | |
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256 | WHEN idle => | |
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257 | enA <= '0'; | |
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258 | dataA <= (OTHERS=>'0'); | |
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259 | addrA <= (OTHERS=>'0'); | |
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260 | ch_ack_vector <= (OTHERS=>'0'); | |
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261 | IF (ch_cont_cur_state=attending_ch1) THEN | |
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262 | ram_contr_next_state <= pre_ch1; | |
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263 | ELSIF (ch_cont_cur_state=attending_ch2) THEN | |
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264 | ram_contr_next_state <= pre_ch2; | |
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265 | ELSIF (ch_cont_cur_state=attending_ch3) THEN | |
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266 | ram_contr_next_state <= pre_ch3; | |
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267 | ELSIF (ch_cont_cur_state=attending_ch4) THEN | |
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268 | ram_contr_next_state <= pre_ch4; | |
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269 | ELSIF (ch_cont_cur_state=attending_ch5) THEN | |
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270 | ram_contr_next_state <= pre_ch5; | |
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271 | ELSE | |
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272 | ram_contr_next_state <= idle; | |
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273 | END IF; | |
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274 | ||
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275 | WHEN pre_ch1 => | |
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276 | enA <= '0'; | |
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277 | dataA <= datach1_aux; | |
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278 | ch_ack_vector <= "00000"; | |
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279 | IF ( sel_buf = '1' ) THEN | |
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280 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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281 | ELSE | |
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282 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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283 | END IF; | |
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284 | ram_contr_next_state <= wr_ch1; | |
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285 | ||
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286 | WHEN wr_ch1 => | |
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287 | enA <= '1'; | |
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288 | dataA <= datach1_aux; | |
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289 | ch_ack_vector <= "00000"; | |
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290 | IF ( sel_buf = '1' ) THEN | |
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291 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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292 | ELSE | |
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293 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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294 | END IF; | |
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295 | ram_contr_next_state <= end_wrt_ch_1; | |
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296 | ||
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297 | WHEN end_wrt_ch_1 => | |
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298 | enA <= '0'; | |
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299 | dataA <= datach1_aux; | |
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300 | ch_ack_vector <= "00001"; | |
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301 | IF ( sel_buf = '1' ) THEN | |
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302 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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303 | ELSE | |
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304 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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305 | END IF; | |
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306 | IF (count_ch_byte = "100") THEN | |
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307 | ram_contr_next_state <= idle; | |
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308 | ELSE | |
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|
309 | ram_contr_next_state <= pre_ch1; | |
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310 | END IF; | |
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311 | ||
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312 | --------------------------------------- | |
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313 | ||
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314 | WHEN pre_ch2 => | |
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315 | enA <= '0'; | |
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316 | dataA <= datach2_aux; | |
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317 | ch_ack_vector <= "00000"; | |
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318 | IF ( sel_buf = '1' ) THEN | |
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319 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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320 | ELSE | |
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|
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321 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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322 | END IF; | |
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323 | ram_contr_next_state <= wr_ch2; | |
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|
324 | ||
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325 | WHEN wr_ch2 => | |
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|
326 | enA <= '1'; | |
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327 | dataA <= datach2_aux; | |
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328 | ch_ack_vector <= "00000"; | |
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329 | IF ( sel_buf = '1' ) THEN | |
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|
|
330 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
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331 | ELSE | |
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|
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|
|
332 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
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|
333 | END IF; | |
|
|
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|
|
334 | ram_contr_next_state <= end_wrt_ch_2; | |
|
|
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|
|
335 | ||
|
|
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|
|
336 | WHEN end_wrt_ch_2 => | |
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|
|
337 | enA <= '0'; | |
|
|
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|
|
338 | dataA <= datach2_aux; | |
|
|
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|
|
339 | ch_ack_vector <= "00010"; | |
|
|
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|
|
340 | IF ( sel_buf = '1' ) THEN | |
|
|
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|
|
341 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
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|
|
342 | ELSE | |
|
|
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|
|
343 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
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|
344 | END IF; | |
|
|
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|
|
345 | IF (count_ch_byte = "100") THEN | |
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|
|
346 | ram_contr_next_state <= idle; | |
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|
|
347 | ELSE | |
|
|
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|
|
348 | ram_contr_next_state <= pre_ch2; | |
|
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|
|
349 | END IF; | |
|
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|
|
350 | ||
|
|
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|
|
351 | ------------------------------ | |
|
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|
|
352 | ||
|
|
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|
|
353 | WHEN pre_ch3 => | |
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|
|
354 | enA <= '0'; | |
|
|
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|
|
355 | dataA <= datach3_aux; | |
|
|
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|
|
356 | ch_ack_vector <= "00000"; | |
|
|
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|
|
357 | IF ( sel_buf = '1' ) THEN | |
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|
|
358 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
359 | ELSE | |
|
|
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|
|
360 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
361 | END IF; | |
|
|
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|
|
362 | ram_contr_next_state <= wr_ch3; | |
|
|
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|
|
363 | ||
|
|
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|
|
364 | WHEN wr_ch3 => | |
|
|
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|
|
365 | enA <= '1'; | |
|
|
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|
|
366 | dataA <= datach3_aux; | |
|
|
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|
|
367 | ch_ack_vector <= "00000"; | |
|
|
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|
|
368 | IF ( sel_buf = '1' ) THEN | |
|
|
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|
|
369 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
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|
|
370 | ELSE | |
|
|
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|
|
371 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
372 | END IF; | |
|
|
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|
|
373 | ram_contr_next_state <= end_wrt_ch_3; | |
|
|
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|
|
374 | ||
|
|
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|
|
375 | WHEN end_wrt_ch_3 => | |
|
|
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|
|
376 | enA <= '0'; | |
|
|
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|
|
377 | dataA <= datach3_aux; | |
|
|
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|
|
378 | ch_ack_vector <= "00100"; | |
|
|
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|
|
379 | IF ( sel_buf = '1' ) THEN | |
|
|
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|
|
380 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
381 | ELSE | |
|
|
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|
|
382 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
383 | END IF; | |
|
|
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|
|
384 | IF (count_ch_byte = "100") THEN | |
|
|
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|
|
385 | ram_contr_next_state <= idle; | |
|
|
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|
|
386 | ELSE | |
|
|
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|
|
387 | ram_contr_next_state <= pre_ch3; | |
|
|
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|
|
388 | END IF; | |
|
|
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|
|
389 | ||
|
|
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|
|
390 | -------------------------------------------------- | |
|
|
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|
|
391 | ||
|
|
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|
|
392 | WHEN pre_ch4 => | |
|
|
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|
|
393 | enA <= '0'; | |
|
|
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|
|
394 | dataA <= datach4_aux; | |
|
|
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|
|
395 | ch_ack_vector <= "00000"; | |
|
|
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|
|
396 | IF ( sel_buf = '1' ) THEN | |
|
|
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|
|
397 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
398 | ELSE | |
|
|
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|
|
399 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
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|
|
400 | END IF; | |
|
|
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|
|
401 | ram_contr_next_state <= wr_ch4; | |
|
|
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|
|
402 | ||
|
|
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|
|
403 | WHEN wr_ch4 => | |
|
|
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|
|
404 | enA <= '1'; | |
|
|
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|
|
405 | dataA <= datach4_aux; | |
|
|
No newline at end of file | ||
|
|
406 | ch_ack_vector <= "00000"; | |
|
|
No newline at end of file | ||
|
|
407 | IF ( sel_buf = '1' ) THEN | |
|
|
No newline at end of file | ||
|
|
408 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
409 | ELSE | |
|
|
No newline at end of file | ||
|
|
410 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
411 | END IF; | |
|
|
No newline at end of file | ||
|
|
412 | ram_contr_next_state <= end_wrt_ch_4; | |
|
|
No newline at end of file | ||
|
|
413 | ||
|
|
No newline at end of file | ||
|
|
414 | WHEN end_wrt_ch_4 => | |
|
|
No newline at end of file | ||
|
|
415 | enA <= '0'; | |
|
|
No newline at end of file | ||
|
|
416 | dataA <= datach4_aux; | |
|
|
No newline at end of file | ||
|
|
417 | ch_ack_vector <= "01000"; | |
|
|
No newline at end of file | ||
|
|
418 | IF ( sel_buf = '1' ) THEN | |
|
|
No newline at end of file | ||
|
|
419 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
420 | ELSE | |
|
|
No newline at end of file | ||
|
|
421 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
422 | END IF; | |
|
|
No newline at end of file | ||
|
|
423 | IF (count_ch_byte = "100") THEN | |
|
|
No newline at end of file | ||
|
|
424 | ram_contr_next_state <= idle; | |
|
|
No newline at end of file | ||
|
|
425 | ELSE | |
|
|
No newline at end of file | ||
|
|
426 | ram_contr_next_state <= pre_ch4; | |
|
|
No newline at end of file | ||
|
|
427 | END IF; | |
|
|
No newline at end of file | ||
|
|
428 | ||
|
|
No newline at end of file | ||
|
|
429 | ------------------------------------------ | |
|
|
No newline at end of file | ||
|
|
430 | ||
|
|
No newline at end of file | ||
|
|
431 | WHEN pre_ch5 => | |
|
|
No newline at end of file | ||
|
|
432 | enA <= '0'; | |
|
|
No newline at end of file | ||
|
|
433 | dataA <= datach5_aux; | |
|
|
No newline at end of file | ||
|
|
434 | ch_ack_vector <= "00000"; | |
|
|
No newline at end of file | ||
|
|
435 | IF ( sel_buf = '1' ) THEN | |
|
|
No newline at end of file | ||
|
|
436 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
437 | ELSE | |
|
|
No newline at end of file | ||
|
|
438 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
439 | END IF; | |
|
|
No newline at end of file | ||
|
|
440 | ram_contr_next_state <= wr_ch5; | |
|
|
No newline at end of file | ||
|
|
441 | ||
|
|
No newline at end of file | ||
|
|
442 | WHEN wr_ch5 => | |
|
|
No newline at end of file | ||
|
|
443 | enA <= '1'; | |
|
|
No newline at end of file | ||
|
|
444 | dataA <= datach5_aux; | |
|
|
No newline at end of file | ||
|
|
445 | ch_ack_vector <= "00000"; | |
|
|
No newline at end of file | ||
|
|
446 | IF ( sel_buf = '1' ) THEN | |
|
|
No newline at end of file | ||
|
|
447 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
448 | ELSE | |
|
|
No newline at end of file | ||
|
|
449 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
450 | END IF; | |
|
|
No newline at end of file | ||
|
|
451 | ram_contr_next_state <= end_wrt_ch_5; | |
|
|
No newline at end of file | ||
|
|
452 | ||
|
|
No newline at end of file | ||
|
|
453 | WHEN end_wrt_ch_5 => | |
|
|
No newline at end of file | ||
|
|
454 | enA <= '0'; | |
|
|
No newline at end of file | ||
|
|
455 | dataA <= datach5_aux; | |
|
|
No newline at end of file | ||
|
|
456 | ch_ack_vector <= "10000"; | |
|
|
No newline at end of file | ||
|
|
457 | IF ( sel_buf = '1' ) THEN | |
|
|
No newline at end of file | ||
|
|
458 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
459 | ELSE | |
|
|
No newline at end of file | ||
|
|
460 | addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte)); | |
|
|
No newline at end of file | ||
|
|
461 | END IF; | |
|
|
No newline at end of file | ||
|
|
462 | IF (count_ch_byte = "100") THEN | |
|
|
No newline at end of file | ||
|
|
463 | ram_contr_next_state <= idle; | |
|
|
No newline at end of file | ||
|
|
464 | ELSE | |
|
|
No newline at end of file | ||
|
|
465 | ram_contr_next_state <= pre_ch5; | |
|
|
No newline at end of file | ||
|
|
466 | END IF; | |
|
|
No newline at end of file | ||
|
|
467 | ||
|
|
No newline at end of file | ||
|
|
468 | ||
|
|
No newline at end of file | ||
|
|
469 | WHEN OTHERS => | |
|
|
No newline at end of file | ||
|
|
470 | ||
|
|
No newline at end of file | ||
|
|
471 | enA <= '0'; | |
|
|
No newline at end of file | ||
|
|
472 | dataA <= (OTHERS=>'0'); | |
|
|
No newline at end of file | ||
|
|
473 | addrA <= (OTHERS=>'0'); | |
|
|
No newline at end of file | ||
|
|
474 | ch_ack_vector <= (OTHERS=>'0'); | |
|
|
No newline at end of file | ||
|
|
475 | ram_contr_next_state <= idle; | |
|
|
No newline at end of file | ||
|
|
476 | ||
|
|
No newline at end of file | ||
|
|
477 | END CASE; | |
|
|
No newline at end of file | ||
|
|
478 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
479 | ||
|
|
No newline at end of file | ||
|
|
480 | --Contador de paquetes | |
|
|
No newline at end of file | ||
|
|
481 | wr_bytes_dpram: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
482 | BEGIN | |
|
|
No newline at end of file | ||
|
|
483 | IF(rising_edge(clk_main)) THEN | |
|
|
No newline at end of file | ||
|
|
484 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
485 | --count_req <= (OTHERS => '0'); | |
|
|
No newline at end of file | ||
|
|
486 | count_pack <= (OTHERS => '1'); | |
|
|
No newline at end of file | ||
|
|
487 | ELSE | |
|
|
No newline at end of file | ||
|
|
488 | --IF (data_req = '1') THEN | |
|
|
No newline at end of file | ||
|
|
489 | -- count_req <= std_logic_vector(unsigned(count_req) + 1); | |
|
|
No newline at end of file | ||
|
|
490 | --END IF; | |
|
|
No newline at end of file | ||
|
|
491 | ||
|
|
No newline at end of file | ||
|
|
492 | IF (data_req = '1') THEN | |
|
|
No newline at end of file | ||
|
|
493 | IF (count_pack = "100111") THEN | |
|
|
No newline at end of file | ||
|
|
494 | count_pack <= (OTHERS => '0'); | |
|
|
No newline at end of file | ||
|
|
495 | sel_buf <= NOT(sel_buf); | |
|
|
No newline at end of file | ||
|
|
496 | rpi_req <= '1'; | |
|
|
No newline at end of file | ||
|
|
497 | ELSE | |
|
|
No newline at end of file | ||
|
|
498 | count_pack <= std_logic_vector(unsigned(count_pack) + 1); | |
|
|
No newline at end of file | ||
|
|
499 | rpi_req <= '0'; | |
|
|
No newline at end of file | ||
|
|
500 | END IF; | |
|
|
No newline at end of file | ||
|
|
501 | ELSE | |
|
|
No newline at end of file | ||
|
|
502 | rpi_req <= '0'; | |
|
|
No newline at end of file | ||
|
|
503 | END IF; | |
|
|
No newline at end of file | ||
|
|
504 | ||
|
|
No newline at end of file | ||
|
|
505 | END IF; | |
|
|
No newline at end of file | ||
|
|
506 | END IF; | |
|
|
No newline at end of file | ||
|
|
507 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
508 | ||
|
|
No newline at end of file | ||
|
|
509 | ||
|
|
No newline at end of file | ||
|
|
510 | --Contador de bytes | |
|
|
No newline at end of file | ||
|
|
511 | count_ch_bytes: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
512 | BEGIN | |
|
|
No newline at end of file | ||
|
|
513 | IF(rising_edge(clk_main)) THEN | |
|
|
No newline at end of file | ||
|
|
514 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
515 | count_ch_byte <= (OTHERS => '0'); | |
|
|
No newline at end of file | ||
|
|
516 | ELSE | |
|
|
No newline at end of file | ||
|
|
517 | IF (ram_contr_cur_state = idle) THEN | |
|
|
No newline at end of file | ||
|
|
518 | count_ch_byte <= (OTHERS => '0'); | |
|
|
No newline at end of file | ||
|
|
519 | ELSE | |
|
|
No newline at end of file | ||
|
|
520 | IF (ram_contr_cur_state = end_wrt_ch_1 OR | |
|
|
No newline at end of file | ||
|
|
521 | ram_contr_cur_state = end_wrt_ch_2 OR | |
|
|
No newline at end of file | ||
|
|
522 | ram_contr_cur_state = end_wrt_ch_3 OR | |
|
|
No newline at end of file | ||
|
|
523 | ram_contr_cur_state = end_wrt_ch_4 OR | |
|
|
No newline at end of file | ||
|
|
524 | ram_contr_cur_state = end_wrt_ch_5 | |
|
|
No newline at end of file | ||
|
|
525 | ) THEN | |
|
|
No newline at end of file | ||
|
|
526 | count_ch_byte <= std_logic_vector(unsigned(count_ch_byte) + 1); | |
|
|
No newline at end of file | ||
|
|
527 | END IF; | |
|
|
No newline at end of file | ||
|
|
528 | END IF; | |
|
|
No newline at end of file | ||
|
|
529 | END IF; | |
|
|
No newline at end of file | ||
|
|
530 | END IF; | |
|
|
No newline at end of file | ||
|
|
531 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
532 | ||
|
|
No newline at end of file | ||
|
|
533 | ----------------------------------------- | |
|
|
No newline at end of file | ||
|
|
534 | datach1_bytes: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
535 | BEGIN | |
|
|
No newline at end of file | ||
|
|
536 | IF (rising_edge(clk_main))THEN | |
|
|
No newline at end of file | ||
|
|
537 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
538 | datach1_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
539 | ELSE | |
|
|
No newline at end of file | ||
|
|
540 | CASE count_ch_byte IS | |
|
|
No newline at end of file | ||
|
|
541 | WHEN "000" => | |
|
|
No newline at end of file | ||
|
|
542 | datach1_aux <= datach1(39 downto 32); | |
|
|
No newline at end of file | ||
|
|
543 | WHEN "001" => | |
|
|
No newline at end of file | ||
|
|
544 | datach1_aux <= datach1(31 downto 24); | |
|
|
No newline at end of file | ||
|
|
545 | WHEN "010" => | |
|
|
No newline at end of file | ||
|
|
546 | datach1_aux <= datach1(23 downto 16); | |
|
|
No newline at end of file | ||
|
|
547 | WHEN "011" => | |
|
|
No newline at end of file | ||
|
|
548 | datach1_aux <= datach1(15 downto 8); | |
|
|
No newline at end of file | ||
|
|
549 | WHEN "100" => | |
|
|
No newline at end of file | ||
|
|
550 | datach1_aux <= datach1(7 downto 0); | |
|
|
No newline at end of file | ||
|
|
551 | WHEN OTHERS => | |
|
|
No newline at end of file | ||
|
|
552 | datach1_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
553 | END CASE; | |
|
|
No newline at end of file | ||
|
|
554 | END IF; | |
|
|
No newline at end of file | ||
|
|
555 | END IF; | |
|
|
No newline at end of file | ||
|
|
556 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
557 | ||
|
|
No newline at end of file | ||
|
|
558 | datach2_bytes: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
559 | BEGIN | |
|
|
No newline at end of file | ||
|
|
560 | IF (rising_edge(clk_main))THEN | |
|
|
No newline at end of file | ||
|
|
561 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
562 | datach2_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
563 | ELSE | |
|
|
No newline at end of file | ||
|
|
564 | CASE count_ch_byte IS | |
|
|
No newline at end of file | ||
|
|
565 | WHEN "000" => | |
|
|
No newline at end of file | ||
|
|
566 | datach2_aux <= datach2(39 downto 32); | |
|
|
No newline at end of file | ||
|
|
567 | WHEN "001" => | |
|
|
No newline at end of file | ||
|
|
568 | datach2_aux <= datach2(31 downto 24); | |
|
|
No newline at end of file | ||
|
|
569 | WHEN "010" => | |
|
|
No newline at end of file | ||
|
|
570 | datach2_aux <= datach2(23 downto 16); | |
|
|
No newline at end of file | ||
|
|
571 | WHEN "011" => | |
|
|
No newline at end of file | ||
|
|
572 | datach2_aux <= datach2(15 downto 8); | |
|
|
No newline at end of file | ||
|
|
573 | WHEN "100" => | |
|
|
No newline at end of file | ||
|
|
574 | datach2_aux <= datach2(7 downto 0); | |
|
|
No newline at end of file | ||
|
|
575 | WHEN OTHERS => | |
|
|
No newline at end of file | ||
|
|
576 | datach2_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
577 | END CASE; | |
|
|
No newline at end of file | ||
|
|
578 | END IF; | |
|
|
No newline at end of file | ||
|
|
579 | END IF; | |
|
|
No newline at end of file | ||
|
|
580 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
581 | ||
|
|
No newline at end of file | ||
|
|
582 | datach3_bytes: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
583 | BEGIN | |
|
|
No newline at end of file | ||
|
|
584 | IF (rising_edge(clk_main))THEN | |
|
|
No newline at end of file | ||
|
|
585 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
586 | datach3_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
587 | ELSE | |
|
|
No newline at end of file | ||
|
|
588 | CASE count_ch_byte IS | |
|
|
No newline at end of file | ||
|
|
589 | WHEN "000" => | |
|
|
No newline at end of file | ||
|
|
590 | datach3_aux <= datach3(39 downto 32); | |
|
|
No newline at end of file | ||
|
|
591 | WHEN "001" => | |
|
|
No newline at end of file | ||
|
|
592 | datach3_aux <= datach3(31 downto 24); | |
|
|
No newline at end of file | ||
|
|
593 | WHEN "010" => | |
|
|
No newline at end of file | ||
|
|
594 | datach3_aux <= datach3(23 downto 16); | |
|
|
No newline at end of file | ||
|
|
595 | WHEN "011" => | |
|
|
No newline at end of file | ||
|
|
596 | datach3_aux <= datach3(15 downto 8); | |
|
|
No newline at end of file | ||
|
|
597 | WHEN "100" => | |
|
|
No newline at end of file | ||
|
|
598 | datach3_aux <= datach3(7 downto 0); | |
|
|
No newline at end of file | ||
|
|
599 | WHEN OTHERS => | |
|
|
No newline at end of file | ||
|
|
600 | datach3_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
601 | END CASE; | |
|
|
No newline at end of file | ||
|
|
602 | END IF; | |
|
|
No newline at end of file | ||
|
|
603 | END IF; | |
|
|
No newline at end of file | ||
|
|
604 | END PROCESS; | |
|
|
No newline at end of file | ||
|
|
605 | ||
|
|
No newline at end of file | ||
|
|
606 | datach4_bytes: PROCESS(clk_main) | |
|
|
No newline at end of file | ||
|
|
607 | BEGIN | |
|
|
No newline at end of file | ||
|
|
608 | IF (rising_edge(clk_main))THEN | |
|
|
No newline at end of file | ||
|
|
609 | IF (rst_bar = '0') THEN | |
|
|
No newline at end of file | ||
|
|
610 | datach4_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
|
|
611 | ELSE | |
|
|
No newline at end of file | ||
|
|
612 | CASE count_ch_byte IS | |
|
|
No newline at end of file | ||
|
|
613 | WHEN "000" => | |
|
|
No newline at end of file | ||
|
|
614 | datach4_aux <= datach4(39 downto 32); | |
|
|
No newline at end of file | ||
|
|
615 | WHEN "001" => | |
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|
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|
|
616 | datach4_aux <= datach4(31 downto 24); | |
|
|
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|
|
617 | WHEN "010" => | |
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|
No newline at end of file | ||
|
|
618 | datach4_aux <= datach4(23 downto 16); | |
|
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No newline at end of file | ||
|
|
619 | WHEN "011" => | |
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|
620 | datach4_aux <= datach4(15 downto 8); | |
|
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No newline at end of file | ||
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621 | WHEN "100" => | |
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622 | datach4_aux <= datach4(7 downto 0); | |
|
|
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|
623 | WHEN OTHERS => | |
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|
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|
|
624 | datach4_aux <= (OTHERS =>'0'); | |
|
|
No newline at end of file | ||
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|
625 | END CASE; | |
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No newline at end of file | ||
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|
626 | END IF; | |
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No newline at end of file | ||
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627 | END IF; | |
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No newline at end of file | ||
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628 | END PROCESS; | |
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629 | ||
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No newline at end of file | ||
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630 | datach5_bytes: PROCESS(clk_main) | |
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No newline at end of file | ||
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631 | BEGIN | |
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632 | IF (rising_edge(clk_main))THEN | |
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633 | IF (rst_bar = '0') THEN | |
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634 | datach5_aux <= (OTHERS =>'0'); | |
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635 | ELSE | |
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636 | CASE count_ch_byte IS | |
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637 | WHEN "000" => | |
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638 | datach5_aux <= datach5(39 downto 32); | |
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No newline at end of file | ||
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639 | WHEN "001" => | |
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640 | datach5_aux <= datach5(31 downto 24); | |
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No newline at end of file | ||
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641 | WHEN "010" => | |
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642 | datach5_aux <= datach5(23 downto 16); | |
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643 | WHEN "011" => | |
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644 | datach5_aux <= datach5(15 downto 8); | |
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No newline at end of file | ||
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645 | WHEN "100" => | |
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No newline at end of file | ||
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646 | datach5_aux <= datach5(7 downto 0); | |
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647 | WHEN OTHERS => | |
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648 | datach5_aux <= (OTHERS =>'0'); | |
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649 | END CASE; | |
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No newline at end of file | ||
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650 | END IF; | |
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651 | END IF; | |
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No newline at end of file | ||
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652 | END PROCESS; | |
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653 | ||
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654 | ||
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655 | end Behavioral; | |
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656 | No newline at end of file | |
| @@ -0,0 +1,13 | |||
|
|
1 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
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No newline at end of file | ||
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2 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
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No newline at end of file | ||
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3 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
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No newline at end of file | ||
|
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4 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
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No newline at end of file | ||
|
|
5 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
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No newline at end of file | ||
|
|
6 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
7 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
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No newline at end of file | ||
|
|
8 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
9 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
10 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
11 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
12 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" | |
|
|
No newline at end of file | ||
|
|
13 | xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr" No newline at end of file | |
| @@ -0,0 +1,118 | |||
|
|
1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?> | |
|
|
No newline at end of file | ||
|
|
2 | <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> | |
|
|
No newline at end of file | ||
|
|
3 | ||
|
|
No newline at end of file | ||
|
|
4 | <!-- --> | |
|
|
No newline at end of file | ||
|
|
5 | ||
|
|
No newline at end of file | ||
|
|
6 | <!-- For tool use only. Do not edit. --> | |
|
|
No newline at end of file | ||
|
|
7 | ||
|
|
No newline at end of file | ||
|
|
8 | <!-- --> | |
|
|
No newline at end of file | ||
|
|
9 | ||
|
|
No newline at end of file | ||
|
|
10 | <!-- ProjectNavigator created generated project file. --> | |
|
|
No newline at end of file | ||
|
|
11 | ||
|
|
No newline at end of file | ||
|
|
12 | <!-- For use in tracking generated file and other information --> | |
|
|
No newline at end of file | ||
|
|
13 | ||
|
|
No newline at end of file | ||
|
|
14 | <!-- allowing preservation of process status. --> | |
|
|
No newline at end of file | ||
|
|
15 | ||
|
|
No newline at end of file | ||
|
|
16 | <!-- --> | |
|
|
No newline at end of file | ||
|
|
17 | ||
|
|
No newline at end of file | ||
|
|
18 | <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> | |
|
|
No newline at end of file | ||
|
|
19 | ||
|
|
No newline at end of file | ||
|
|
20 | <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version> | |
|
|
No newline at end of file | ||
|
|
21 | ||
|
|
No newline at end of file | ||
|
|
22 | <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FrontEnd_Acq.xise"/> | |
|
|
No newline at end of file | ||
|
|
23 | ||
|
|
No newline at end of file | ||
|
|
24 | <files xmlns="http://www.xilinx.com/XMLSchema"> | |
|
|
No newline at end of file | ||
|
|
25 | <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="FrontEnd_Acq.cmd_log"/> | |
|
|
No newline at end of file | ||
|
|
26 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="FrontEnd_Acq.lso"/> | |
|
|
No newline at end of file | ||
|
|
27 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="FrontEnd_Acq.ngc"/> | |
|
|
No newline at end of file | ||
|
|
28 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="FrontEnd_Acq.ngr"/> | |
|
|
No newline at end of file | ||
|
|
29 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FrontEnd_Acq.prj"/> | |
|
|
No newline at end of file | ||
|
|
30 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="FrontEnd_Acq.stx"/> | |
|
|
No newline at end of file | ||
|
|
31 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="FrontEnd_Acq.syr"/> | |
|
|
No newline at end of file | ||
|
|
32 | <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="FrontEnd_Acq.xst"/> | |
|
|
No newline at end of file | ||
|
|
33 | <file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_envsettings.html"/> | |
|
|
No newline at end of file | ||
|
|
34 | <file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_summary.html"/> | |
|
|
No newline at end of file | ||
|
|
35 | <file xil_pn:fileType="FILE_XRPT" xil_pn:name="FrontEnd_Acq_xst.xrpt"/> | |
|
|
No newline at end of file | ||
|
|
36 | <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> | |
|
|
No newline at end of file | ||
|
|
37 | <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> | |
|
|
No newline at end of file | ||
|
|
38 | <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/> | |
|
|
No newline at end of file | ||
|
|
39 | <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> | |
|
|
No newline at end of file | ||
|
|
40 | <file xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/> | |
|
|
No newline at end of file | ||
|
|
41 | <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> | |
|
|
No newline at end of file | ||
|
|
42 | </files> | |
|
|
No newline at end of file | ||
|
|
43 | ||
|
|
No newline at end of file | ||
|
|
44 | <transforms xmlns="http://www.xilinx.com/XMLSchema"> | |
|
|
No newline at end of file | ||
|
|
45 | <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1487967396"> | |
|
|
No newline at end of file | ||
|
|
46 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
47 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
48 | </transform> | |
|
|
No newline at end of file | ||
|
|
49 | <transform xil_pn:end_ts="1487969891" xil_pn:in_ck="3689099153043928551" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1487969891"> | |
|
|
No newline at end of file | ||
|
|
50 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
51 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
52 | <outfile xil_pn:name="DCM_fwd_int.vhd"/> | |
|
|
No newline at end of file | ||
|
|
53 | <outfile xil_pn:name="Data_Req_gen.vhd"/> | |
|
|
No newline at end of file | ||
|
|
54 | <outfile xil_pn:name="DtoDPRAM.vhd"/> | |
|
|
No newline at end of file | ||
|
|
55 | <outfile xil_pn:name="FrontEnd_Acq.vhd"/> | |
|
|
No newline at end of file | ||
|
|
56 | <outfile xil_pn:name="joiner_samp.vhd"/> | |
|
|
No newline at end of file | ||
|
|
57 | <outfile xil_pn:name="tb_FrontEnd_Acq.vhd"/> | |
|
|
No newline at end of file | ||
|
|
58 | </transform> | |
|
|
No newline at end of file | ||
|
|
59 | <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9044832904953873877" xil_pn:start_ts="1487967396"> | |
|
|
No newline at end of file | ||
|
|
60 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
61 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
62 | <status xil_pn:value="OutOfDateForProperties"/> | |
|
|
No newline at end of file | ||
|
|
63 | </transform> | |
|
|
No newline at end of file | ||
|
|
64 | <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2793873426928892759" xil_pn:start_ts="1487967396"> | |
|
|
No newline at end of file | ||
|
|
65 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
66 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
67 | <status xil_pn:value="OutOfDateForProperties"/> | |
|
|
No newline at end of file | ||
|
|
68 | </transform> | |
|
|
No newline at end of file | ||
|
|
69 | <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487967396"> | |
|
|
No newline at end of file | ||
|
|
70 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
71 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
72 | </transform> | |
|
|
No newline at end of file | ||
|
|
73 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
74 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
75 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
76 | </transform> | |
|
|
No newline at end of file | ||
|
|
77 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3768900233016590667" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
78 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
79 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
80 | </transform> | |
|
|
No newline at end of file | ||
|
|
81 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
82 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
83 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
84 | </transform> | |
|
|
No newline at end of file | ||
|
|
85 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
86 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
87 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
88 | </transform> | |
|
|
No newline at end of file | ||
|
|
89 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7509621194074287415" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
90 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
91 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
92 | </transform> | |
|
|
No newline at end of file | ||
|
|
93 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
94 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
95 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
96 | </transform> | |
|
|
No newline at end of file | ||
|
|
97 | <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3361842800594627215" xil_pn:start_ts="1487953541"> | |
|
|
No newline at end of file | ||
|
|
98 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
99 | <status xil_pn:value="ReadyToRun"/> | |
|
|
No newline at end of file | ||
|
|
100 | </transform> | |
|
|
No newline at end of file | ||
|
|
101 | <transform xil_pn:end_ts="1487968498" xil_pn:in_ck="-1660920062075515250" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2407589981579732958" xil_pn:start_ts="1487968485"> | |
|
|
No newline at end of file | ||
|
|
102 | <status xil_pn:value="SuccessfullyRun"/> | |
|
|
No newline at end of file | ||
|
|
103 | <status xil_pn:value="ReadyToRun"/> | |
|
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No newline at end of file | ||
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104 | <outfile xil_pn:name="FrontEnd_Acq.lso"/> | |
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No newline at end of file | ||
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105 | <outfile xil_pn:name="FrontEnd_Acq.ngc"/> | |
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No newline at end of file | ||
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106 | <outfile xil_pn:name="FrontEnd_Acq.ngr"/> | |
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No newline at end of file | ||
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107 | <outfile xil_pn:name="FrontEnd_Acq.prj"/> | |
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No newline at end of file | ||
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108 | <outfile xil_pn:name="FrontEnd_Acq.stx"/> | |
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No newline at end of file | ||
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109 | <outfile xil_pn:name="FrontEnd_Acq.syr"/> | |
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No newline at end of file | ||
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110 | <outfile xil_pn:name="FrontEnd_Acq.xst"/> | |
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No newline at end of file | ||
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111 | <outfile xil_pn:name="FrontEnd_Acq_xst.xrpt"/> | |
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No newline at end of file | ||
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112 | <outfile xil_pn:name="_xmsgs/xst.xmsgs"/> | |
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No newline at end of file | ||
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113 | <outfile xil_pn:name="webtalk_pn.xml"/> | |
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No newline at end of file | ||
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114 | <outfile xil_pn:name="xst"/> | |
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No newline at end of file | ||
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115 | </transform> | |
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No newline at end of file | ||
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116 | </transforms> | |
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No newline at end of file | ||
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117 | ||
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No newline at end of file | ||
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118 | </generated_project> No newline at end of file | |
| @@ -0,0 +1,1 | |||
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1 | work No newline at end of file | |
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1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
|
|
1 | NO CONTENT: new file 10644 | |
| The requested commit or file is too big and content was truncated. Show full diff | |||
General Comments 0
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