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trunk/firmware/sources/Processing2017/FrontEnd_Acq/DCM_fwd_int.vhd created 10644 +93 0

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		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 17:23:06 02/16/2016
		6	-- Design Name:
		7	-- Module Name: DCM_fwd_int - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	--use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	library UNISIM;
		30	use UNISIM.VComponents.all;
		31
		32	entity DCM_fwd_int is
		33	PORT(
		34	clk_main_io: IN std_logic;
		35	c_200MHz_in: OUT std_logic
		36	);
		37	end DCM_fwd_int;
		38
		39	architecture Behavioral of DCM_fwd_int is
		40	SIGNAL clk_main: std_logic;
		41	SIGNAL c_16MHz: std_logic;
		42
		43	SIGNAL clk_fb_aux: std_logic;
		44	SIGNAL clk_fb_aux_200MHz: std_logic;
		45
		46	SIGNAL c_16MHz_inv: std_logic;
		47
		48	begin
		49
		50
		51
		52	DCM_SP_inst_int : DCM_SP
		53	generic map (
		54	CLKDV_DIVIDE => 2.0, -- CLKDV divide value
		55	-- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
		56	CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
		57	CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
		58	CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
		59	CLKIN_PERIOD => 16.667, -- Input clock period specified in nS
		60	CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
		61	CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
		62	DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
		63	DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
		64	DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
		65	DSS_MODE => "NONE", -- Unsupported - Do not change value
		66	DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
		67	FACTORY_JF => X"c080", -- Unsupported - Do not change value
		68	PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
		69	STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
		70	)
		71	port map (
		72	CLK0 => clk_fb_aux_200MHz, -- 1-bit output: 0 degree clock output
		73	CLK180 => open, -- 1-bit output: 180 degree clock output
		74	CLK270 => open, -- 1-bit output: 270 degree clock output
		75	CLK2X => open, -- 1-bit output: 2X clock frequency clock output
		76	CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
		77	CLK90 => open, -- 1-bit output: 90 degree clock output
		78	CLKDV => open, -- 1-bit output: Divided clock output
		79	CLKFX => c_200MHz_in, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
		80	CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
		81	LOCKED => open, -- 1-bit output: DCM_SP Lock Output
		82	PSDONE => open, -- 1-bit output: Phase shift done output
		83	STATUS => open, -- 8-bit output: DCM_SP status output
		84	CLKFB => clk_fb_aux_200MHz, -- 1-bit input: Clock feedback input
		85	CLKIN => clk_main_io, -- 1-bit input: Clock input
		86	DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
		87	PSCLK => '1', -- 1-bit input: Phase shift clock input
		88	PSEN => '0', -- 1-bit input: Phase shift enable
		89	PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
		90	RST => '0' -- 1-bit input: Active high reset input
		91	);
		92
		93	end Behavioral;

trunk/firmware/sources/Processing2017/FrontEnd_Acq/Data_Req_gen.vhd created 10644 +116 0

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		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 15:47:34 02/08/2017
		6	-- Design Name:
		7	-- Module Name: Data_Req_gen - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	--library UNISIM;
		30	--use UNISIM.VComponents.all;
		31
		32	entity Data_Req_gen is
		33	GENERIC (
		34	--CLOCKS_COUNT_1KSPS: INTEGER :=240000; --For 240 000
		35	--CYCLES_COUNT_DUTY_1KSPS: INTEGER :=2400; --For 2400
		36	--PULSES_COUNT_1KSPS: INTEGER :=1000; --For 1 000
		37
		38	NBITS_PERIOD: INTEGER :=18;
		39	NBITS_DUTY: INTEGER :=12;
		40	NBITS_PULSES: INTEGER :=10
		41	);
		42	PORT(
		43	c_200MHz_in : IN std_logic;
		44	reset_int : IN std_logic;
		45	pps : IN std_logic;
		46	data_req : OUT std_logic
		47	);
		48	end Data_Req_gen;
		49
		50	architecture Behavioral of Data_Req_gen is
		51	--Constantes
		52	CONSTANT LIM_COUNT_PERIOD : std_logic_vector((NBITS_PERIOD-1) downto 0) := "111010100100000000"; --240000
		53	--CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_DUTY-1) downto 0) := "100101100000"; --2400
		54	CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_PERIOD-1) downto 0) := "011101010011000000";
		55	CONSTANT LIM_COUNT_PULSES : std_logic_vector((NBITS_PULSES-1) downto 0) := "1111101001"; --1000
		56	--CONSTANT LIM_COUNT_PULSES : std_logic_vector((2-1) downto 0) := "11";
		57	--Contadores de ciclos de reloj(count_clock) y pulsos generados(count_cycle)
		58	SIGNAL count_clock : std_logic_vector((NBITS_PERIOD-1) downto 0) :="000000000000000000"; --"00 0000 0000 0000 0000"
		59	SIGNAL count_pulses : std_logic_vector(9 downto 0) :="0000000000"; --"00 0000 0000"
		60	--SIGNAL count_pulses : std_logic_vector(1 downto 0) :=(OTHERS =>'0'); --"00"
		61	--Registro para deteccion de flanco
		62	SIGNAL pps_r: std_logic_vector(1 downto 0) :="00";
		63	SIGNAL pps_rising : std_logic := '0';
		64	SIGNAL data_req_s: std_logic :='0';
		65
		66	begin
		67
		68	--Deteccion de flanco de pps
		69	pps_bloco: PROCESS(c_200MHz_in)
		70	BEGIN
		71	IF (rising_edge(c_200MHz_in)) THEN
		72	IF(reset_int = '0') THEN
		73	pps_r <= (OTHERS=>'0');
		74	ELSE
		75	pps_r <= pps_r(0) & pps;
		76	IF(pps_r(1 downto 0) = "01") THEN
		77	pps_rising <= '1';
		78	ELSE
		79	pps_rising <= '0';
		80	END IF;
		81	END IF;
		82	END IF;
		83	END PROCESS;
		84
		85
		86	out_generator: PROCESS(c_200MHz_in)
		87	BEGIN
		88	IF(rising_edge(c_200MHz_in)) THEN
		89	IF(pps_rising = '1') THEN
		90	data_req_s <= '1';
		91	count_clock <= (OTHERS=>'0');
		92	count_pulses <= "0000000001";
		93	ELSE
		94	IF(count_pulses = LIM_COUNT_PULSES) THEN
		95	data_req_s<= '0';
		96	ELSE
		97	IF(count_clock = LIM_COUNT_PERIOD) THEN
		98	--data_req<= '1';
		99	count_clock <= (OTHERS=>'0');
		100	count_pulses <= std_logic_vector(unsigned(count_pulses)+1);
		101	ELSIF(count_clock = LIM_COUNT_DUTY) THEN
		102	data_req_s<= '0';
		103	count_clock <= std_logic_vector(unsigned(count_clock)+1);
		104	ELSIF(count_clock = "000000000000000000" AND count_pulses /= "00") THEN
		105	data_req_s<= '1';
		106	count_clock <= std_logic_vector(unsigned(count_clock)+1);
		107	ELSE
		108	count_clock <= std_logic_vector(unsigned(count_clock)+1);
		109	END IF;
		110	END IF;
		111	END IF;
		112	END IF;
		113	END PROCESS;
		114
		115	data_req <= data_req_s;
		116	end Behavioral; No newline at end of file

trunk/firmware/sources/Processing2017/FrontEnd_Acq/DtoDPRAM.vhd created 10644 +656 0

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	1	----------------------------------------------------------------------------------
	2	-- Company:
	3	-- Engineer:
	4	--
	5	-- Create Date: 16:24:04 02/21/2017
	6	-- Design Name:
	7	-- Module Name: DtoDPRAM - Behavioral
	8	-- Project Name:
	9	-- Target Devices:
	10	-- Tool versions:
	11	-- Description:
	12	--
	13	-- Dependencies:
	14	--
	15	-- Revision:
	16	-- Revision 0.01 - File Created
	17	-- Additional Comments:
	18	--
	19	----------------------------------------------------------------------------------
	20	library IEEE;
	21	use IEEE.STD_LOGIC_1164.ALL;
	22
	23	-- Uncomment the following library declaration if using
	24	-- arithmetic functions with Signed or Unsigned values
	25	use IEEE.NUMERIC_STD.ALL;
	26
	27	-- Uncomment the following library declaration if instantiating
	28	-- any Xilinx primitives in this code.
	29	--library UNISIM;
	30	--use UNISIM.VComponents.all;
	31
	32	entity DtoDPRAM is
	33	GENERIC(
	34	ADDR_LENGTH: INTEGER := 12;
	35	DATAOUT_LENGTH: INTEGER := 8;
	36	DATAIN_LENGTH: INTEGER := 40;
	37	CHAN_NUM: INTEGER := 5;
	38	COUNT_BYTE_SZ: INTEGER := 3;
	39	COUNT_PACK_SZ: INTEGER := 6
	40
	41	);
	42
	43	PORT(
	44	--Reset general
	45	rst_bar: IN std_logic;
	46
	47	--Reset general
	48	data_req: IN std_logic;
	49
	50	--Entrada de reloj principal
	51	clk_main: IN std_logic;
	52
	53	--Entradas para indicar dato preparado por leer
	54	--Desde los nibble to packets
	55	ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
	56
	57	--Senhal para que indica que termino con una peticion
	58	--Hacia los nibble to packets
	59	ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
	60
	61	--Data IN
	62	datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
	63	datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
	64	datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
	65	datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
	66	datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
	67
	68	--DPRAM senhales de control, direccion y data
	69	--Direccion de escritura/lectura
	70	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0);
	71	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0);
	72	enA: OUT std_logic;
	73	--Aviso de Paquete de 40 muestras solicitadas a los 5 canales
	74	rpi_req: OUT std_logic
	75
	76	);
	77	end DtoDPRAM;
	78
	79	architecture Behavioral of DtoDPRAM is
	80	SIGNAL datach1_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
	81	SIGNAL datach2_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
	82	SIGNAL datach3_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
	83	SIGNAL datach4_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
	84	SIGNAL datach5_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
	85
	86	--Estados del controlador de memoria
	87	--Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria
	88	--espera de pedido y estados para proceder a una lectura
	89	TYPE ram_cont_states IS (idle,
	90
	91	------------------------------------------
	92	pre_ch1, wr_ch1, end_wrt_ch_1,
	93	------------------------------------------
	94	pre_ch2, wr_ch2, end_wrt_ch_2,
	95	------------------------------------------
	96	pre_ch3, wr_ch3, end_wrt_ch_3,
	97	------------------------------------------
	98	pre_ch4, wr_ch4, end_wrt_ch_4,
	99	------------------------------------------
	100	pre_ch5, wr_ch5, end_wrt_ch_5
	101
	102	);
	103
	104	SIGNAL ram_contr_cur_state: ram_cont_states := idle;
	105	SIGNAL ram_contr_next_state: ram_cont_states := idle;
	106
	107	----------------------------------
	108	--Estados de la atencion a ready's
	109	TYPE chn_cont_states IS ( idle,
	110	checking_ch1, attending_ch1,
	111	checking_ch2, attending_ch2,
	112	checking_ch3, attending_ch3,
	113	checking_ch4, attending_ch4,
	114	checking_ch5, attending_ch5
	115	);
	116
	117	SIGNAL ch_cont_cur_state: chn_cont_states := idle;
	118	SIGNAL ch_cont_next_state: chn_cont_states := idle;
	119
	120	SIGNAL count_ch_byte: std_logic_vector((COUNT_BYTE_SZ-1) downto 0) := (OTHERS=>'0');
	121
	122	--Direcciones base por canal
	123	CONSTANT BASE_ADDR_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0');
	124	CONSTANT BASE_ADDR_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000011001000"; --200
	125	CONSTANT BASE_ADDR_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000110010000"; --400
	126	CONSTANT BASE_ADDR_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001001011000"; --600
	127	CONSTANT BASE_ADDR_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001100100000"; --800
	128
	129	CONSTANT BASE_BUFFER_2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "010000000000"; --1024
	130
	131	SIGNAL sel_buf: std_logic := '0';
	132	SIGNAL count_pack: std_logic_vector((COUNT_PACK_SZ-1) downto 0) := (OTHERS => '0');
	133	begin
	134
	135	---------------------
	136	--Estados para atencion de canales
	137	ch_cont_cambio_estados: PROCESS(clk_main)
	138	BEGIN
	139	IF (rising_edge(clk_main)) THEN
	140	IF(rst_bar = '0') THEN
	141	ch_cont_cur_state <= idle;
	142	ELSE
	143	ch_cont_cur_state <= ch_cont_next_state;
	144	END IF;
	145	END IF;
	146	END PROCESS;
	147
	148	ch_salidas_estados: PROCESS(ch_cont_cur_state,
	149	ch_rdy_vector,
	150	ram_contr_cur_state
	151	)
	152	BEGIN
	153
	154	CASE ch_cont_cur_state IS
	155	WHEN idle =>
	156	ch_cont_next_state <= checking_ch1;
	157
	158	WHEN checking_ch1 =>
	159	IF(ch_rdy_vector(0) = '1') THEN
	160	ch_cont_next_state <= attending_ch1;
	161	ELSE
	162	ch_cont_next_state <= checking_ch2;
	163	END IF;
	164
	165	WHEN attending_ch1 =>
	166	IF(ram_contr_cur_state = end_wrt_ch_1) THEN
	167	ch_cont_next_state <= checking_ch2;
	168	ELSE
	169	ch_cont_next_state <= attending_ch1;
	170	END IF;
	171
	172	WHEN checking_ch2 =>
	173	IF(ch_rdy_vector(1) = '1') THEN
	174	ch_cont_next_state <= attending_ch2;
	175	ELSE
	176	ch_cont_next_state <= checking_ch3;
	177	END IF;
	178
	179	WHEN attending_ch2 =>
	180	IF(ram_contr_cur_state = end_wrt_ch_2) THEN
	181	ch_cont_next_state <= checking_ch3;
	182	ELSE
	183	ch_cont_next_state <= attending_ch2;
	184	END IF;
	185
	186	WHEN checking_ch3 =>
	187	IF(ch_rdy_vector(2) = '1') THEN
	188	ch_cont_next_state <= attending_ch3;
	189	ELSE
	190	ch_cont_next_state <= checking_ch4;
	191	END IF;
	192
	193	WHEN attending_ch3 =>
	194	IF(ram_contr_cur_state = end_wrt_ch_3) THEN
	195	ch_cont_next_state <= checking_ch4;
	196	ELSE
	197	ch_cont_next_state <= attending_ch3;
	198	END IF;
	199
	200	WHEN checking_ch4 =>
	201	IF(ch_rdy_vector(3) = '1') THEN
	202	ch_cont_next_state <= attending_ch4;
	203	ELSE
	204	ch_cont_next_state <= checking_ch5;
	205	END IF;
	206
	207	WHEN attending_ch4 =>
	208	IF(ram_contr_cur_state = end_wrt_ch_4) THEN
	209	ch_cont_next_state <= checking_ch5;
	210	ELSE
	211	ch_cont_next_state <= attending_ch4;
	212	END IF;
	213
	214	WHEN checking_ch5 =>
	215	IF(ch_rdy_vector(4) = '1') THEN
	216	ch_cont_next_state <= attending_ch5;
	217	ELSE
	218	ch_cont_next_state <= checking_ch1;
	219	END IF;
	220
	221	WHEN attending_ch5 =>
	222	IF(ram_contr_cur_state = end_wrt_ch_5) THEN
	223	ch_cont_next_state <= checking_ch1;
	224	ELSE
	225	ch_cont_next_state <= attending_ch5;
	226	END IF;
	227
	228	WHEN OTHERS =>
	229
	230	ch_cont_next_state <= idle;
	231
	232	END CASE;
	233	END PROCESS;
	234
	235	--------------------------------------------------
	236	--Estados de m�quina principal para control de RAM
	237
	238	ctrl_cambio_estados: PROCESS(clk_main)
	239	BEGIN
	240	IF (rising_edge(clk_main)) THEN
	241	IF(rst_bar = '0') THEN
	242	ram_contr_cur_state <= idle;
	243	ELSE
	244	ram_contr_cur_state <= ram_contr_next_state;
	245	END IF;
	246	END IF;
	247	END PROCESS;
	248
	249	--Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set s�.
	250	ctrl_salidas_estados: PROCESS(ram_contr_cur_state, ch_cont_cur_state,
	251	count_pack, count_ch_byte, sel_buf,
	252	datach1_aux, datach2_aux, datach3_aux, datach4_aux, datach5_aux
	253	)
	254	BEGIN
	255	CASE ram_contr_cur_state IS
	256	WHEN idle =>
	257	enA <= '0';
	258	dataA <= (OTHERS=>'0');
	259	addrA <= (OTHERS=>'0');
	260	ch_ack_vector <= (OTHERS=>'0');
	261	IF (ch_cont_cur_state=attending_ch1) THEN
	262	ram_contr_next_state <= pre_ch1;
	263	ELSIF (ch_cont_cur_state=attending_ch2) THEN
	264	ram_contr_next_state <= pre_ch2;
	265	ELSIF (ch_cont_cur_state=attending_ch3) THEN
	266	ram_contr_next_state <= pre_ch3;
	267	ELSIF (ch_cont_cur_state=attending_ch4) THEN
	268	ram_contr_next_state <= pre_ch4;
	269	ELSIF (ch_cont_cur_state=attending_ch5) THEN
	270	ram_contr_next_state <= pre_ch5;
	271	ELSE
	272	ram_contr_next_state <= idle;
	273	END IF;
	274
	275	WHEN pre_ch1 =>
	276	enA <= '0';
	277	dataA <= datach1_aux;
	278	ch_ack_vector <= "00000";
	279	IF ( sel_buf = '1' ) THEN
	280	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	281	ELSE
	282	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	283	END IF;
	284	ram_contr_next_state <= wr_ch1;
	285
	286	WHEN wr_ch1 =>
	287	enA <= '1';
	288	dataA <= datach1_aux;
	289	ch_ack_vector <= "00000";
	290	IF ( sel_buf = '1' ) THEN
	291	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	292	ELSE
	293	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	294	END IF;
	295	ram_contr_next_state <= end_wrt_ch_1;
	296
	297	WHEN end_wrt_ch_1 =>
	298	enA <= '0';
	299	dataA <= datach1_aux;
	300	ch_ack_vector <= "00001";
	301	IF ( sel_buf = '1' ) THEN
	302	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	303	ELSE
	304	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	305	END IF;
	306	IF (count_ch_byte = "100") THEN
	307	ram_contr_next_state <= idle;
	308	ELSE
	309	ram_contr_next_state <= pre_ch1;
	310	END IF;
	311
	312	---------------------------------------
	313
	314	WHEN pre_ch2 =>
	315	enA <= '0';
	316	dataA <= datach2_aux;
	317	ch_ack_vector <= "00000";
	318	IF ( sel_buf = '1' ) THEN
	319	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	320	ELSE
	321	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	322	END IF;
	323	ram_contr_next_state <= wr_ch2;
	324
	325	WHEN wr_ch2 =>
	326	enA <= '1';
	327	dataA <= datach2_aux;
	328	ch_ack_vector <= "00000";
	329	IF ( sel_buf = '1' ) THEN
	330	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	331	ELSE
	332	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	333	END IF;
	334	ram_contr_next_state <= end_wrt_ch_2;
	335
	336	WHEN end_wrt_ch_2 =>
	337	enA <= '0';
	338	dataA <= datach2_aux;
	339	ch_ack_vector <= "00010";
	340	IF ( sel_buf = '1' ) THEN
	341	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	342	ELSE
	343	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	344	END IF;
	345	IF (count_ch_byte = "100") THEN
	346	ram_contr_next_state <= idle;
	347	ELSE
	348	ram_contr_next_state <= pre_ch2;
	349	END IF;
	350
	351	------------------------------
	352
	353	WHEN pre_ch3 =>
	354	enA <= '0';
	355	dataA <= datach3_aux;
	356	ch_ack_vector <= "00000";
	357	IF ( sel_buf = '1' ) THEN
	358	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	359	ELSE
	360	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	361	END IF;
	362	ram_contr_next_state <= wr_ch3;
	363
	364	WHEN wr_ch3 =>
	365	enA <= '1';
	366	dataA <= datach3_aux;
	367	ch_ack_vector <= "00000";
	368	IF ( sel_buf = '1' ) THEN
	369	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	370	ELSE
	371	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	372	END IF;
	373	ram_contr_next_state <= end_wrt_ch_3;
	374
	375	WHEN end_wrt_ch_3 =>
	376	enA <= '0';
	377	dataA <= datach3_aux;
	378	ch_ack_vector <= "00100";
	379	IF ( sel_buf = '1' ) THEN
	380	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	381	ELSE
	382	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	383	END IF;
	384	IF (count_ch_byte = "100") THEN
	385	ram_contr_next_state <= idle;
	386	ELSE
	387	ram_contr_next_state <= pre_ch3;
	388	END IF;
	389
	390	--------------------------------------------------
	391
	392	WHEN pre_ch4 =>
	393	enA <= '0';
	394	dataA <= datach4_aux;
	395	ch_ack_vector <= "00000";
	396	IF ( sel_buf = '1' ) THEN
	397	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	398	ELSE
	399	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	400	END IF;
	401	ram_contr_next_state <= wr_ch4;
	402
	403	WHEN wr_ch4 =>
	404	enA <= '1';
	405	dataA <= datach4_aux;
	406	ch_ack_vector <= "00000";
	407	IF ( sel_buf = '1' ) THEN
	408	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	409	ELSE
	410	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	411	END IF;
	412	ram_contr_next_state <= end_wrt_ch_4;
	413
	414	WHEN end_wrt_ch_4 =>
	415	enA <= '0';
	416	dataA <= datach4_aux;
	417	ch_ack_vector <= "01000";
	418	IF ( sel_buf = '1' ) THEN
	419	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	420	ELSE
	421	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	422	END IF;
	423	IF (count_ch_byte = "100") THEN
	424	ram_contr_next_state <= idle;
	425	ELSE
	426	ram_contr_next_state <= pre_ch4;
	427	END IF;
	428
	429	------------------------------------------
	430
	431	WHEN pre_ch5 =>
	432	enA <= '0';
	433	dataA <= datach5_aux;
	434	ch_ack_vector <= "00000";
	435	IF ( sel_buf = '1' ) THEN
	436	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	437	ELSE
	438	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	439	END IF;
	440	ram_contr_next_state <= wr_ch5;
	441
	442	WHEN wr_ch5 =>
	443	enA <= '1';
	444	dataA <= datach5_aux;
	445	ch_ack_vector <= "00000";
	446	IF ( sel_buf = '1' ) THEN
	447	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	448	ELSE
	449	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	450	END IF;
	451	ram_contr_next_state <= end_wrt_ch_5;
	452
	453	WHEN end_wrt_ch_5 =>
	454	enA <= '0';
	455	dataA <= datach5_aux;
	456	ch_ack_vector <= "10000";
	457	IF ( sel_buf = '1' ) THEN
	458	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	459	ELSE
	460	addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
	461	END IF;
	462	IF (count_ch_byte = "100") THEN
	463	ram_contr_next_state <= idle;
	464	ELSE
	465	ram_contr_next_state <= pre_ch5;
	466	END IF;
	467
	468
	469	WHEN OTHERS =>
	470
	471	enA <= '0';
	472	dataA <= (OTHERS=>'0');
	473	addrA <= (OTHERS=>'0');
	474	ch_ack_vector <= (OTHERS=>'0');
	475	ram_contr_next_state <= idle;
	476
	477	END CASE;
	478	END PROCESS;
	479
	480	--Contador de paquetes
	481	wr_bytes_dpram: PROCESS(clk_main)
	482	BEGIN
	483	IF(rising_edge(clk_main)) THEN
	484	IF (rst_bar = '0') THEN
	485	--count_req <= (OTHERS => '0');
	486	count_pack <= (OTHERS => '1');
	487	ELSE
	488	--IF (data_req = '1') THEN
	489	-- count_req <= std_logic_vector(unsigned(count_req) + 1);
	490	--END IF;
	491
	492	IF (data_req = '1') THEN
	493	IF (count_pack = "100111") THEN
	494	count_pack <= (OTHERS => '0');
	495	sel_buf <= NOT(sel_buf);
	496	rpi_req <= '1';
	497	ELSE
	498	count_pack <= std_logic_vector(unsigned(count_pack) + 1);
	499	rpi_req <= '0';
	500	END IF;
	501	ELSE
	502	rpi_req <= '0';
	503	END IF;
	504
	505	END IF;
	506	END IF;
	507	END PROCESS;
	508
	509
	510	--Contador de bytes
	511	count_ch_bytes: PROCESS(clk_main)
	512	BEGIN
	513	IF(rising_edge(clk_main)) THEN
	514	IF (rst_bar = '0') THEN
	515	count_ch_byte <= (OTHERS => '0');
	516	ELSE
	517	IF (ram_contr_cur_state = idle) THEN
	518	count_ch_byte <= (OTHERS => '0');
	519	ELSE
	520	IF (ram_contr_cur_state = end_wrt_ch_1 OR
	521	ram_contr_cur_state = end_wrt_ch_2 OR
	522	ram_contr_cur_state = end_wrt_ch_3 OR
	523	ram_contr_cur_state = end_wrt_ch_4 OR
	524	ram_contr_cur_state = end_wrt_ch_5
	525	) THEN
	526	count_ch_byte <= std_logic_vector(unsigned(count_ch_byte) + 1);
	527	END IF;
	528	END IF;
	529	END IF;
	530	END IF;
	531	END PROCESS;
	532
	533	-----------------------------------------
	534	datach1_bytes: PROCESS(clk_main)
	535	BEGIN
	536	IF (rising_edge(clk_main))THEN
	537	IF (rst_bar = '0') THEN
	538	datach1_aux <= (OTHERS =>'0');
	539	ELSE
	540	CASE count_ch_byte IS
	541	WHEN "000" =>
	542	datach1_aux <= datach1(39 downto 32);
	543	WHEN "001" =>
	544	datach1_aux <= datach1(31 downto 24);
	545	WHEN "010" =>
	546	datach1_aux <= datach1(23 downto 16);
	547	WHEN "011" =>
	548	datach1_aux <= datach1(15 downto 8);
	549	WHEN "100" =>
	550	datach1_aux <= datach1(7 downto 0);
	551	WHEN OTHERS =>
	552	datach1_aux <= (OTHERS =>'0');
	553	END CASE;
	554	END IF;
	555	END IF;
	556	END PROCESS;
	557
	558	datach2_bytes: PROCESS(clk_main)
	559	BEGIN
	560	IF (rising_edge(clk_main))THEN
	561	IF (rst_bar = '0') THEN
	562	datach2_aux <= (OTHERS =>'0');
	563	ELSE
	564	CASE count_ch_byte IS
	565	WHEN "000" =>
	566	datach2_aux <= datach2(39 downto 32);
	567	WHEN "001" =>
	568	datach2_aux <= datach2(31 downto 24);
	569	WHEN "010" =>
	570	datach2_aux <= datach2(23 downto 16);
	571	WHEN "011" =>
	572	datach2_aux <= datach2(15 downto 8);
	573	WHEN "100" =>
	574	datach2_aux <= datach2(7 downto 0);
	575	WHEN OTHERS =>
	576	datach2_aux <= (OTHERS =>'0');
	577	END CASE;
	578	END IF;
	579	END IF;
	580	END PROCESS;
	581
	582	datach3_bytes: PROCESS(clk_main)
	583	BEGIN
	584	IF (rising_edge(clk_main))THEN
	585	IF (rst_bar = '0') THEN
	586	datach3_aux <= (OTHERS =>'0');
	587	ELSE
	588	CASE count_ch_byte IS
	589	WHEN "000" =>
	590	datach3_aux <= datach3(39 downto 32);
	591	WHEN "001" =>
	592	datach3_aux <= datach3(31 downto 24);
	593	WHEN "010" =>
	594	datach3_aux <= datach3(23 downto 16);
	595	WHEN "011" =>
	596	datach3_aux <= datach3(15 downto 8);
	597	WHEN "100" =>
	598	datach3_aux <= datach3(7 downto 0);
	599	WHEN OTHERS =>
	600	datach3_aux <= (OTHERS =>'0');
	601	END CASE;
	602	END IF;
	603	END IF;
	604	END PROCESS;
	605
	606	datach4_bytes: PROCESS(clk_main)
	607	BEGIN
	608	IF (rising_edge(clk_main))THEN
	609	IF (rst_bar = '0') THEN
	610	datach4_aux <= (OTHERS =>'0');
	611	ELSE
	612	CASE count_ch_byte IS
	613	WHEN "000" =>
	614	datach4_aux <= datach4(39 downto 32);
	615	WHEN "001" =>
	616	datach4_aux <= datach4(31 downto 24);
	617	WHEN "010" =>
	618	datach4_aux <= datach4(23 downto 16);
	619	WHEN "011" =>
	620	datach4_aux <= datach4(15 downto 8);
	621	WHEN "100" =>
	622	datach4_aux <= datach4(7 downto 0);
	623	WHEN OTHERS =>
	624	datach4_aux <= (OTHERS =>'0');
	625	END CASE;
	626	END IF;
	627	END IF;
	628	END PROCESS;
	629
	630	datach5_bytes: PROCESS(clk_main)
	631	BEGIN
	632	IF (rising_edge(clk_main))THEN
	633	IF (rst_bar = '0') THEN
	634	datach5_aux <= (OTHERS =>'0');
	635	ELSE
	636	CASE count_ch_byte IS
	637	WHEN "000" =>
	638	datach5_aux <= datach5(39 downto 32);
	639	WHEN "001" =>
	640	datach5_aux <= datach5(31 downto 24);
	641	WHEN "010" =>
	642	datach5_aux <= datach5(23 downto 16);
	643	WHEN "011" =>
	644	datach5_aux <= datach5(15 downto 8);
	645	WHEN "100" =>
	646	datach5_aux <= datach5(7 downto 0);
	647	WHEN OTHERS =>
	648	datach5_aux <= (OTHERS =>'0');
	649	END CASE;
	650	END IF;
	651	END IF;
	652	END PROCESS;
	653
	654
	655	end Behavioral;
	656

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.cmd_log created 10644 +13 0

			@@ -0,0 +1,13
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		2	xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
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		4	xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
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		10	xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
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trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.gise created 10644 +118 0

			@@ -0,0 +1,118
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		2	<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
		3
		4	<!-- -->
		5
		6	<!-- For tool use only. Do not edit. -->
		7
		8	<!-- -->
		9
		10	<!-- ProjectNavigator created generated project file. -->
		11
		12	<!-- For use in tracking generated file and other information -->
		13
		14	<!-- allowing preservation of process status. -->
		15
		16	<!-- -->
		17
		18	<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
		19
		20	<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
		21
		22	<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FrontEnd_Acq.xise"/>
		23
		24	<files xmlns="http://www.xilinx.com/XMLSchema">
		25	<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="FrontEnd_Acq.cmd_log"/>
		26	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="FrontEnd_Acq.lso"/>
		27	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="FrontEnd_Acq.ngc"/>
		28	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="FrontEnd_Acq.ngr"/>
		29	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FrontEnd_Acq.prj"/>
		30	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="FrontEnd_Acq.stx"/>
		31	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="FrontEnd_Acq.syr"/>
		32	<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="FrontEnd_Acq.xst"/>
		33	<file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_envsettings.html"/>
		34	<file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_summary.html"/>
		35	<file xil_pn:fileType="FILE_XRPT" xil_pn:name="FrontEnd_Acq_xst.xrpt"/>
		36	<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
		37	<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
		38	<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/>
		39	<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
		40	<file xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
		41	<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
		42	</files>
		43
		44	<transforms xmlns="http://www.xilinx.com/XMLSchema">
		45	<transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1487967396">
		46	<status xil_pn:value="SuccessfullyRun"/>
		47	<status xil_pn:value="ReadyToRun"/>
		48	</transform>
		49	<transform xil_pn:end_ts="1487969891" xil_pn:in_ck="3689099153043928551" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1487969891">
		50	<status xil_pn:value="SuccessfullyRun"/>
		51	<status xil_pn:value="ReadyToRun"/>
		52	<outfile xil_pn:name="DCM_fwd_int.vhd"/>
		53	<outfile xil_pn:name="Data_Req_gen.vhd"/>
		54	<outfile xil_pn:name="DtoDPRAM.vhd"/>
		55	<outfile xil_pn:name="FrontEnd_Acq.vhd"/>
		56	<outfile xil_pn:name="joiner_samp.vhd"/>
		57	<outfile xil_pn:name="tb_FrontEnd_Acq.vhd"/>
		58	</transform>
		59	<transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9044832904953873877" xil_pn:start_ts="1487967396">
		60	<status xil_pn:value="SuccessfullyRun"/>
		61	<status xil_pn:value="ReadyToRun"/>
		62	<status xil_pn:value="OutOfDateForProperties"/>
		63	</transform>
		64	<transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2793873426928892759" xil_pn:start_ts="1487967396">
		65	<status xil_pn:value="SuccessfullyRun"/>
		66	<status xil_pn:value="ReadyToRun"/>
		67	<status xil_pn:value="OutOfDateForProperties"/>
		68	</transform>
		69	<transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487967396">
		70	<status xil_pn:value="SuccessfullyRun"/>
		71	<status xil_pn:value="ReadyToRun"/>
		72	</transform>
		73	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487953541">
		74	<status xil_pn:value="SuccessfullyRun"/>
		75	<status xil_pn:value="ReadyToRun"/>
		76	</transform>
		77	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3768900233016590667" xil_pn:start_ts="1487953541">
		78	<status xil_pn:value="SuccessfullyRun"/>
		79	<status xil_pn:value="ReadyToRun"/>
		80	</transform>
		81	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487953541">
		82	<status xil_pn:value="SuccessfullyRun"/>
		83	<status xil_pn:value="ReadyToRun"/>
		84	</transform>
		85	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1487953541">
		86	<status xil_pn:value="SuccessfullyRun"/>
		87	<status xil_pn:value="ReadyToRun"/>
		88	</transform>
		89	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7509621194074287415" xil_pn:start_ts="1487953541">
		90	<status xil_pn:value="SuccessfullyRun"/>
		91	<status xil_pn:value="ReadyToRun"/>
		92	</transform>
		93	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1487953541">
		94	<status xil_pn:value="SuccessfullyRun"/>
		95	<status xil_pn:value="ReadyToRun"/>
		96	</transform>
		97	<transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3361842800594627215" xil_pn:start_ts="1487953541">
		98	<status xil_pn:value="SuccessfullyRun"/>
		99	<status xil_pn:value="ReadyToRun"/>
		100	</transform>
		101	<transform xil_pn:end_ts="1487968498" xil_pn:in_ck="-1660920062075515250" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2407589981579732958" xil_pn:start_ts="1487968485">
		102	<status xil_pn:value="SuccessfullyRun"/>
		103	<status xil_pn:value="ReadyToRun"/>
		104	<outfile xil_pn:name="FrontEnd_Acq.lso"/>
		105	<outfile xil_pn:name="FrontEnd_Acq.ngc"/>
		106	<outfile xil_pn:name="FrontEnd_Acq.ngr"/>
		107	<outfile xil_pn:name="FrontEnd_Acq.prj"/>
		108	<outfile xil_pn:name="FrontEnd_Acq.stx"/>
		109	<outfile xil_pn:name="FrontEnd_Acq.syr"/>
		110	<outfile xil_pn:name="FrontEnd_Acq.xst"/>
		111	<outfile xil_pn:name="FrontEnd_Acq_xst.xrpt"/>
		112	<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
		113	<outfile xil_pn:name="webtalk_pn.xml"/>
		114	<outfile xil_pn:name="xst"/>
		115	</transform>
		116	</transforms>
		117
		118	</generated_project>

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.lso created 10644 +1 0

			@@ -0,0 +1,1
		1	work

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.ngc created 10644 +3 0

			@@ -0,0 +1,3
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trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.ngr created 10644 +3 0

			@@ -0,0 +1,3
		1	XILINX-XDB 0.1 STUB 0.1 ASCII
		2	XILINX-XDM V1.6e
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6>728;j7c=8f;48?l77i3:1(>6?:03b?k50n3?07d?>6;29 6>728;j7c=8f;68?l76?3:1(>6?:03b?k50n3907d?>8;29 6>728;j7c=8f;08?l7613:1(>6?:03b?k50n3;07d?>b;29 6>728;j7c=8f;28?l76n3:1(>6?:06;?k50n3=07d?=b;29 6>728>37c=8f;48?l7403:1(>6?:06;?k50n3?07d?;4;29 6>728>37c=8f;68?l73=3:1(>6?:06;?k50n3907d?;6;29 6>728>37c=8f;08?l73?3:1(>6?:06;?k50n3;07d?;9;29 6>728>37c=8f;28?l73k3:1(>6?:041?k50n3=07d?:7;29 6>728<97c=8f;48?l72l3:1(>6?:041?k50n3?07d?:e;29 6>728<97c=8f;68?l72n3:1(>6?:041?k50n3907d?90;29 6>728<97c=8f;08?l7193:1(>6?:041?k50n3;07d?93;29 6>728<97c=8f;28?l71>3:1(>6?:05`?k50n3=07d?81;29 6>728=h7c=8f;48?l70?3:1(>6?:05`?k50n3?07d?88;29 6>728=h7c=8f;68?l7013:1(>6?:05`?k50n3907d?8a;29 6>728=h7c=8f;08?l70j3:1(>6?:05`?k50n3;07d?8d;29 6>728=h7c=8f;28?l7?83:1(>6?:0;5?k50n3=07d?7b;29 6>7283=7c=8f;48?l7>93:1(>6?:0;5?k50n3?07d?62;29 6>7283=7c=8f;68?l7>;3:1(>6?:0;5?k50n3907d?64;29 6>7283=7c=8f;08?l7>=3:1(>6?:0;5?k50n3;07d?67;29 6>7283=7c=8f;28?l7>i3:1(>6?:0`3?k50n3=07d?n5;29 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trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.prj created 10644 +5 0

			@@ -0,0 +1,5
		1	vhdl work "joiner_samp.vhd"
		2	vhdl work "DtoDPRAM.vhd"
		3	vhdl work "DCM_fwd_int.vhd"
		4	vhdl work "Data_Req_gen.vhd"
		5	vhdl work "FrontEnd_Acq.vhd"

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.stx created 10644 0 0

NO CONTENT: new file 10644

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.syr created 10644 +746 0

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		@@ -0,0 +1,746
	1	Release 14.7 - xst P.20131013 (nt64)
	2	Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
	3	--> Parameter TMPDIR set to xst/projnav.tmp
	4
	5
	6	Total REAL time to Xst completion: 1.00 secs
	7	Total CPU time to Xst completion: 0.13 secs
	8
	9	--> Parameter xsthdpdir set to xst
	10
	11
	12	Total REAL time to Xst completion: 1.00 secs
	13	Total CPU time to Xst completion: 0.13 secs
	14
	15	--> Reading design: FrontEnd_Acq.prj
	16
	17	TABLE OF CONTENTS
	18	1) Synthesis Options Summary
	19	2) HDL Parsing
	20	3) HDL Elaboration
	21	4) HDL Synthesis
	22	4.1) HDL Synthesis Report
	23	5) Advanced HDL Synthesis
	24	5.1) Advanced HDL Synthesis Report
	25	6) Low Level Synthesis
	26	7) Partition Report
	27	8) Design Summary
	28	8.1) Primitive and Black Box Usage
	29	8.2) Device utilization summary
	30	8.3) Partition Resource Summary
	31	8.4) Timing Report
	32	8.4.1) Clock Information
	33	8.4.2) Asynchronous Control Signals Information
	34	8.4.3) Timing Summary
	35	8.4.4) Timing Details
	36	8.4.5) Cross Clock Domains Report
	37
	38
	39	=========================================================================
	40	* Synthesis Options Summary *
	41	=========================================================================
	42	---- Source Parameters
	43	Input File Name : "FrontEnd_Acq.prj"
	44	Ignore Synthesis Constraint File : NO
	45
	46	---- Target Parameters
	47	Output File Name : "FrontEnd_Acq"
	48	Output Format : NGC
	49	Target Device : xc6slx9-3-tqg144
	50
	51	---- Source Options
	52	Top Module Name : FrontEnd_Acq
	53	Automatic FSM Extraction : YES
	54	FSM Encoding Algorithm : Auto
	55	Safe Implementation : No
	56	FSM Style : LUT
	57	RAM Extraction : Yes
	58	RAM Style : Auto
	59	ROM Extraction : Yes
	60	Shift Register Extraction : YES
	61	ROM Style : Auto
	62	Resource Sharing : YES
	63	Asynchronous To Synchronous : NO
	64	Shift Register Minimum Size : 2
	65	Use DSP Block : Auto
	66	Automatic Register Balancing : No
	67
	68	---- Target Options
	69	LUT Combining : Auto
	70	Reduce Control Sets : Auto
	71	Add IO Buffers : YES
	72	Global Maximum Fanout : 100000
	73	Add Generic Clock Buffer(BUFG) : 16
	74	Register Duplication : YES
	75	Optimize Instantiated Primitives : NO
	76	Use Clock Enable : Auto
	77	Use Synchronous Set : Auto
	78	Use Synchronous Reset : Auto
	79	Pack IO Registers into IOBs : Auto
	80	Equivalent register Removal : YES
	81
	82	---- General Options
	83	Optimization Goal : Speed
	84	Optimization Effort : 1
	85	Power Reduction : NO
	86	Keep Hierarchy : No
	87	Netlist Hierarchy : As_Optimized
	88	RTL Output : Yes
	89	Global Optimization : AllClockNets
	90	Read Cores : YES
	91	Write Timing Constraints : NO
	92	Cross Clock Analysis : NO
	93	Hierarchy Separator : /
	94	Bus Delimiter : <>
	95	Case Specifier : Maintain
	96	Slice Utilization Ratio : 100
	97	BRAM Utilization Ratio : 100
	98	DSP48 Utilization Ratio : 100
	99	Auto BRAM Packing : NO
	100	Slice Utilization Ratio Delta : 5
	101
	102	=========================================================================
	103
	104
	105	=========================================================================
	106	* HDL Parsing *
	107	=========================================================================
	108	Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" into library work
	109	Parsing entity <joiner_samp>.
	110	Parsing architecture <Behavioral> of entity <joiner_samp>.
	111	Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" into library work
	112	Parsing entity <DtoDPRAM>.
	113	Parsing architecture <Behavioral> of entity <dtodpram>.
	114	Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd" into library work
	115	Parsing entity <DCM_fwd_int>.
	116	Parsing architecture <Behavioral> of entity <dcm_fwd_int>.
	117	Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd" into library work
	118	Parsing entity <Data_Req_gen>.
	119	Parsing architecture <Behavioral> of entity <data_req_gen>.
	120	Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd" into library work
	121	Parsing entity <FrontEnd_Acq>.
	122	Parsing architecture <Behavioral> of entity <frontend_acq>.
	123
	124	=========================================================================
	125	* HDL Elaboration *
	126	=========================================================================
	127
	128	Elaborating entity <FrontEnd_Acq> (architecture <Behavioral>) with generics from library <work>.
	129
	130	Elaborating entity <DCM_fwd_int> (architecture <Behavioral>) from library <work>.
	131
	132	Elaborating entity <Data_Req_gen> (architecture <Behavioral>) with generics from library <work>.
	133
	134	Elaborating entity <joiner_samp> (architecture <Behavioral>) with generics from library <work>.
	135	INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 183. Case statement is complete. others clause is never selected
	136	INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 220. Case statement is complete. others clause is never selected
	137	INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd" Line 315. Case statement is complete. others clause is never selected
	138
	139	Elaborating entity <DtoDPRAM> (architecture <Behavioral>) with generics from library <work>.
	140	INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 228. Case statement is complete. others clause is never selected
	141	INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd" Line 469. Case statement is complete. others clause is never selected
	142
	143	=========================================================================
	144	* HDL Synthesis *
	145	=========================================================================
	146
	147	Synthesizing Unit <FrontEnd_Acq>.
	148	Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\FrontEnd_Acq.vhd".
	149	DBIT_SZ = 3
	150	ADDR_LENGTH = 12
	151	DATAOUT_LENGTH = 8
	152	CH_SZ = 5
	153	NBITS_PERIOD = 18
	154	NBITS_DUTY = 12
	155	NBITS_PULSES = 10
	156	RESUL_NP_SZ = 40
	157	ID_CH_SZ = 4
	158	Found 16-bit register for signal <cont_200MHz>.
	159	Found 1-bit register for signal <lock_rst_bar>.
	160	Found 16-bit adder for signal <cont_200MHz[15]_GND_5_o_add_1_OUT> created at line 1241.
	161	Summary:
	162	inferred 1 Adder/Subtractor(s).
	163	inferred 17 D-type flip-flop(s).
	164	Unit <FrontEnd_Acq> synthesized.
	165
	166	Synthesizing Unit <DCM_fwd_int>.
	167	Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DCM_fwd_int.vhd".
	168	Summary:
	169	no macro.
	170	Unit <DCM_fwd_int> synthesized.
	171
	172	Synthesizing Unit <Data_Req_gen>.
	173	Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\Data_Req_gen.vhd".
	174	NBITS_PERIOD = 18
	175	NBITS_DUTY = 12
	176	NBITS_PULSES = 10
	177	Found 1-bit register for signal <pps_rising>.
	178	Found 1-bit register for signal <data_req_s>.
	179	Found 18-bit register for signal <count_clock>.
	180	Found 10-bit register for signal <count_pulses>.
	181	Found 2-bit register for signal <pps_r>.
	182	Found 10-bit adder for signal <count_pulses[9]_GND_11_o_add_5_OUT> created at line 1241.
	183	Found 18-bit adder for signal <count_clock[17]_GND_11_o_add_10_OUT> created at line 1241.
	184	Summary:
	185	inferred 2 Adder/Subtractor(s).
	186	inferred 32 D-type flip-flop(s).
	187	Unit <Data_Req_gen> synthesized.
	188
	189	Synthesizing Unit <joiner_samp>.
	190	Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\joiner_samp.vhd".
	191	DBIT_SZ = 3
	192	BITS_COUNT_SZ = 3
	193	RESUL_NP_SZ = 40
	194	SAMPLE_SZ = 24
	195	SAMPLE_COUNT_SZ = 12
	196	HEADER_NIB_SZ = 4
	197	DATA_HEADER_NIB_SZ = 4
	198	CH_COUNT_SZ = 4
	199	Found 2-bit register for signal <chn_bits_acq_bit1>.
	200	Found 2-bit register for signal <chn_bits_acq_bit2>.
	201	Found 3-bit register for signal <clk_acq_r>.
	202	Found 1-bit register for signal <clk_acq_rise>.
	203	Found 1-bit register for signal <pack_cur_state>.
	204	Found 3-bit register for signal <dbits_counter>.
	205	Found 24-bit register for signal <resul_mem_internal>.
	206	Found 1-bit register for signal <resul_mem_internal_aux<35>>.
	207	Found 1-bit register for signal <resul_mem_internal_aux<34>>.
	208	Found 1-bit register for signal <resul_mem_internal_aux<33>>.
	209	Found 1-bit register for signal <resul_mem_internal_aux<32>>.
	210	Found 1-bit register for signal <resul_mem_internal_aux<31>>.
	211	Found 1-bit register for signal <resul_mem_internal_aux<30>>.
	212	Found 1-bit register for signal <resul_mem_internal_aux<29>>.
	213	Found 1-bit register for signal <resul_mem_internal_aux<28>>.
	214	Found 1-bit register for signal <resul_mem_internal_aux<27>>.
	215	Found 1-bit register for signal <resul_mem_internal_aux<26>>.
	216	Found 1-bit register for signal <resul_mem_internal_aux<25>>.
	217	Found 1-bit register for signal <resul_mem_internal_aux<24>>.
	218	Found 1-bit register for signal <resul_mem_internal_aux<23>>.
	219	Found 1-bit register for signal <resul_mem_internal_aux<22>>.
	220	Found 1-bit register for signal <resul_mem_internal_aux<21>>.
	221	Found 1-bit register for signal <resul_mem_internal_aux<20>>.
	222	Found 1-bit register for signal <resul_mem_internal_aux<19>>.
	223	Found 1-bit register for signal <resul_mem_internal_aux<18>>.
	224	Found 1-bit register for signal <resul_mem_internal_aux<17>>.
	225	Found 1-bit register for signal <resul_mem_internal_aux<16>>.
	226	Found 1-bit register for signal <resul_mem_internal_aux<15>>.
	227	Found 1-bit register for signal <resul_mem_internal_aux<14>>.
	228	Found 1-bit register for signal <resul_mem_internal_aux<13>>.
	229	Found 1-bit register for signal <resul_mem_internal_aux<12>>.
	230	Found 1-bit register for signal <resul_mem_internal_aux<11>>.
	231	Found 1-bit register for signal <resul_mem_internal_aux<10>>.
	232	Found 1-bit register for signal <resul_mem_internal_aux<9>>.
	233	Found 1-bit register for signal <resul_mem_internal_aux<8>>.
	234	Found 1-bit register for signal <resul_mem_internal_aux<7>>.
	235	Found 1-bit register for signal <resul_mem_internal_aux<6>>.
	236	Found 1-bit register for signal <resul_mem_internal_aux<5>>.
	237	Found 1-bit register for signal <resul_mem_internal_aux<4>>.
	238	Found 1-bit register for signal <resul_mem_internal_aux<3>>.
	239	Found 1-bit register for signal <resul_mem_internal_aux<2>>.
	240	Found 1-bit register for signal <resul_mem_internal_aux<1>>.
	241	Found 1-bit register for signal <resul_mem_internal_aux<0>>.
	242	Found 12-bit register for signal <samp_count>.
	243	Found 1-bit register for signal <rdy_mem_aux>.
	244	Found 2-bit register for signal <data_cur_state>.
	245	Found 2-bit register for signal <chn_bits_acq_bit0>.
	246	Found finite state machine <FSM_0> for signal <data_cur_state>.
	247	-----------------------------------------------------------------------
	248	\| States \| 3 \|
	249	\| Transitions \| 6 \|
	250	\| Inputs \| 2 \|
	251	\| Outputs \| 4 \|
	252	\| Clock \| clk_main (rising_edge) \|
	253	\| Reset \| rst_bar_INV_14_o (positive) \|
	254	\| Reset type \| synchronous \|
	255	\| Reset State \| idle \|
	256	\| Power Up State \| idle \|
	257	\| Encoding \| auto \|
	258	\| Implementation \| LUT \|
	259	-----------------------------------------------------------------------
	260	Found 3-bit adder for signal <dbits_counter[2]_GND_12_o_add_13_OUT> created at line 1241.
	261	Found 12-bit adder for signal <samp_count[11]_GND_12_o_add_29_OUT> created at line 1241.
	262	Found 24-bit 8-to-1 multiplexer for signal <dbits_counter[2]_resul_mem_internal[23]_wide_mux_14_OUT> created at line 202.
	263	Summary:
	264	inferred 2 Adder/Subtractor(s).
	265	inferred 87 D-type flip-flop(s).
	266	inferred 4 Multiplexer(s).
	267	inferred 1 Finite State Machine(s).
	268	Unit <joiner_samp> synthesized.
	269
	270	Synthesizing Unit <DtoDPRAM>.
	271	Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\FrontEnd_Acq\DtoDPRAM.vhd".
	272	ADDR_LENGTH = 12
	273	DATAOUT_LENGTH = 8
	274	DATAIN_LENGTH = 40
	275	CHAN_NUM = 5
	276	COUNT_BYTE_SZ = 3
	277	COUNT_PACK_SZ = 6
	278	Found 4-bit register for signal <ram_contr_cur_state>.
	279	Found 6-bit register for signal <count_pack>.
	280	Found 1-bit register for signal <sel_buf>.
	281	Found 1-bit register for signal <rpi_req>.
	282	Found 3-bit register for signal <count_ch_byte>.
	283	Found 8-bit register for signal <datach1_aux>.
	284	Found 8-bit register for signal <datach2_aux>.
	285	Found 8-bit register for signal <datach3_aux>.
	286	Found 8-bit register for signal <datach4_aux>.
	287	Found 8-bit register for signal <datach5_aux>.
	288	Found 4-bit register for signal <ch_cont_cur_state>.
	289	Found finite state machine <FSM_1> for signal <ram_contr_cur_state>.
	290	-----------------------------------------------------------------------
	291	\| States \| 16 \|
	292	\| Transitions \| 28 \|
	293	\| Inputs \| 5 \|
	294	\| Outputs \| 16 \|
	295	\| Clock \| clk_main (rising_edge) \|
	296	\| Reset \| rst_bar_INV_48_o (positive) \|
	297	\| Reset type \| synchronous \|
	298	\| Reset State \| idle \|
	299	\| Power Up State \| idle \|
	300	\| Encoding \| auto \|
	301	\| Implementation \| LUT \|
	302	-----------------------------------------------------------------------
	303	Found finite state machine <FSM_2> for signal <ch_cont_cur_state>.
	304	-----------------------------------------------------------------------
	305	\| States \| 11 \|
	306	\| Transitions \| 21 \|
	307	\| Inputs \| 10 \|
	308	\| Outputs \| 4 \|
	309	\| Clock \| clk_main (rising_edge) \|
	310	\| Reset \| rst_bar_INV_48_o (positive) \|
	311	\| Reset type \| synchronous \|
	312	\| Reset State \| idle \|
	313	\| Power Up State \| idle \|
	314	\| Encoding \| auto \|
	315	\| Implementation \| LUT \|
	316	-----------------------------------------------------------------------
	317	Found 6-bit adder for signal <count_pack[5]_GND_26_o_add_241_OUT> created at line 1241.
	318	Found 3-bit adder for signal <count_ch_byte[2]_GND_26_o_add_252_OUT> created at line 1241.
	319	Found 12-bit adder for signal <_n0507> created at line 302.
	320	Found 12-bit adder for signal <_n0508> created at line 302.
	321	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_61_OUT> created at line 302.
	322	Found 12-bit adder for signal <_n0512> created at line 304.
	323	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_67_OUT> created at line 304.
	324	Found 12-bit adder for signal <_n0516> created at line 341.
	325	Found 12-bit adder for signal <_n0517> created at line 341.
	326	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_102_OUT> created at line 341.
	327	Found 12-bit adder for signal <_n0521> created at line 343.
	328	Found 12-bit adder for signal <_n0522> created at line 343.
	329	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_108_OUT> created at line 343.
	330	Found 12-bit adder for signal <_n0526> created at line 380.
	331	Found 12-bit adder for signal <_n0527> created at line 380.
	332	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_143_OUT> created at line 380.
	333	Found 12-bit adder for signal <_n0531> created at line 382.
	334	Found 12-bit adder for signal <_n0532> created at line 382.
	335	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_149_OUT> created at line 382.
	336	Found 12-bit adder for signal <_n0536> created at line 419.
	337	Found 12-bit adder for signal <_n0537> created at line 419.
	338	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_184_OUT> created at line 419.
	339	Found 12-bit adder for signal <_n0541> created at line 421.
	340	Found 12-bit adder for signal <_n0542> created at line 421.
	341	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_190_OUT> created at line 421.
	342	Found 12-bit adder for signal <_n0546> created at line 458.
	343	Found 12-bit adder for signal <_n0547> created at line 458.
	344	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_225_OUT> created at line 458.
	345	Found 12-bit adder for signal <_n0551> created at line 460.
	346	Found 12-bit adder for signal <_n0552> created at line 460.
	347	Found 12-bit adder for signal <GND_26_o_GND_26_o_add_231_OUT> created at line 460.
	348	Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_257_OUT> created at line 540.
	349	Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_260_OUT> created at line 564.
	350	Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_263_OUT> created at line 588.
	351	Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_266_OUT> created at line 612.
	352	Found 8-bit 7-to-1 multiplexer for signal <count_ch_byte[2]_GND_26_o_wide_mux_269_OUT> created at line 636.
	353	Summary:
	354	inferred 31 Adder/Subtractor(s).
	355	inferred 51 D-type flip-flop(s).
	356	inferred 31 Multiplexer(s).
	357	inferred 2 Finite State Machine(s).
	358	Unit <DtoDPRAM> synthesized.
	359
	360	=========================================================================
	361	HDL Synthesis Report
	362
	363	Macro Statistics
	364	# Adders/Subtractors : 44
	365	10-bit adder : 1
	366	12-bit adder : 34
	367	16-bit adder : 1
	368	18-bit adder : 1
	369	3-bit adder : 6
	370	6-bit adder : 1
	371	# Registers : 191
	372	1-bit register : 140
	373	10-bit register : 1
	374	12-bit register : 10
	375	16-bit register : 1
	376	18-bit register : 1
	377	2-bit register : 16
	378	24-bit register : 5
	379	3-bit register : 11
	380	6-bit register : 1
	381	8-bit register : 5
	382	# Multiplexers : 51
	383	1-bit 2-to-1 multiplexer : 5
	384	12-bit 2-to-1 multiplexer : 15
	385	24-bit 8-to-1 multiplexer : 5
	386	3-bit 2-to-1 multiplexer : 6
	387	40-bit 2-to-1 multiplexer : 5
	388	8-bit 2-to-1 multiplexer : 10
	389	8-bit 7-to-1 multiplexer : 5
	390	# FSMs : 7
	391
	392	=========================================================================
	393
	394	=========================================================================
	395	* Advanced HDL Synthesis *
	396	=========================================================================
	397
	398
	399	Synthesizing (advanced) Unit <Data_Req_gen>.
	400	The following registers are absorbed into counter <count_pulses>: 1 register on signal <count_pulses>.
	401	The following registers are absorbed into counter <count_clock>: 1 register on signal <count_clock>.
	402	Unit <Data_Req_gen> synthesized (advanced).
	403
	404	Synthesizing (advanced) Unit <DtoDPRAM>.
	405	The following registers are absorbed into counter <count_ch_byte>: 1 register on signal <count_ch_byte>.
	406	The following registers are absorbed into counter <count_pack>: 1 register on signal <count_pack>.
	407	Unit <DtoDPRAM> synthesized (advanced).
	408
	409	Synthesizing (advanced) Unit <FrontEnd_Acq>.
	410	The following registers are absorbed into counter <cont_200MHz>: 1 register on signal <cont_200MHz>.
	411	Unit <FrontEnd_Acq> synthesized (advanced).
	412
	413	Synthesizing (advanced) Unit <joiner_samp>.
	414	The following registers are absorbed into counter <samp_count>: 1 register on signal <samp_count>.
	415	The following registers are absorbed into counter <dbits_counter>: 1 register on signal <dbits_counter>.
	416	Unit <joiner_samp> synthesized (advanced).
	417
	418	=========================================================================
	419	Advanced HDL Synthesis Report
	420
	421	Macro Statistics
	422	# Adders/Subtractors : 29
	423	12-bit adder : 29
	424	# Counters : 15
	425	10-bit up counter : 1
	426	12-bit up counter : 5
	427	16-bit up counter : 1
	428	18-bit up counter : 1
	429	3-bit up counter : 6
	430	6-bit up counter : 1
	431	# Registers : 407
	432	Flip-Flops : 407
	433	# Multiplexers : 82
	434	1-bit 2-to-1 multiplexer : 48
	435	12-bit 2-to-1 multiplexer : 15
	436	24-bit 8-to-1 multiplexer : 5
	437	40-bit 2-to-1 multiplexer : 5
	438	8-bit 2-to-1 multiplexer : 4
	439	8-bit 7-to-1 multiplexer : 5
	440	# FSMs : 7
	441
	442	=========================================================================
	443
	444	=========================================================================
	445	* Low Level Synthesis *
	446	=========================================================================
	447	Analyzing FSM <MFsm> for best encoding.
	448	Optimizing FSM <empa_ch1/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
	449	Optimizing FSM <empa_ch2/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
	450	Optimizing FSM <empa_ch3/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
	451	Optimizing FSM <empa_ch4/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
	452	Optimizing FSM <empa_ch5/FSM_0> on signal <data_cur_state[1:2]> with gray encoding.
	453	-----------------------
	454	State \| Encoding
	455	-----------------------
	456	idle \| 00
	457	data_pres \| 01
	458	data_proc \| 11
	459	-----------------------
	460	Analyzing FSM <MFsm> for best encoding.
	461	Optimizing FSM <controlador_DPRAM/FSM_2> on signal <ch_cont_cur_state[1:4]> with user encoding.
	462	---------------------------
	463	State \| Encoding
	464	---------------------------
	465	idle \| 0000
	466	checking_ch1 \| 0001
	467	attending_ch1 \| 0010
	468	checking_ch2 \| 0011
	469	attending_ch2 \| 0100
	470	checking_ch3 \| 0101
	471	attending_ch3 \| 0110
	472	checking_ch4 \| 0111
	473	attending_ch4 \| 1000
	474	checking_ch5 \| 1001
	475	attending_ch5 \| 1010
	476	---------------------------
	477	Analyzing FSM <MFsm> for best encoding.
	478	Optimizing FSM <controlador_DPRAM/FSM_1> on signal <ram_contr_cur_state[1:4]> with sequential encoding.
	479	--------------------------
	480	State \| Encoding
	481	--------------------------
	482	idle \| 0000
	483	pre_ch1 \| 0001
	484	wr_ch1 \| 0110
	485	end_wrt_ch_1 \| 0111
	486	pre_ch2 \| 0010
	487	wr_ch2 \| 1000
	488	end_wrt_ch_2 \| 1001
	489	pre_ch3 \| 0011
	490	wr_ch3 \| 1010
	491	end_wrt_ch_3 \| 1011
	492	pre_ch4 \| 0100
	493	wr_ch4 \| 1100
	494	end_wrt_ch_4 \| 1101
	495	pre_ch5 \| 0101
	496	wr_ch5 \| 1110
	497	end_wrt_ch_5 \| 1111
	498	--------------------------
	499
	500	Optimizing unit <FrontEnd_Acq> ...
	501
	502	Optimizing unit <joiner_samp> ...
	503
	504	Optimizing unit <Data_Req_gen> ...
	505
	506	Optimizing unit <DtoDPRAM> ...
	507	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_0> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_0> <empa_ch3/samp_count_0> <empa_ch2/samp_count_0> <empa_ch1/samp_count_0>
	508	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_1> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_1> <empa_ch3/samp_count_1> <empa_ch2/samp_count_1> <empa_ch1/samp_count_1>
	509	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_2> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_2> <empa_ch3/samp_count_2> <empa_ch2/samp_count_2> <empa_ch1/samp_count_2>
	510	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_3> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_3> <empa_ch3/samp_count_3> <empa_ch2/samp_count_3> <empa_ch1/samp_count_3>
	511	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_4> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_4> <empa_ch3/samp_count_4> <empa_ch2/samp_count_4> <empa_ch1/samp_count_4>
	512	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_5> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_5> <empa_ch3/samp_count_5> <empa_ch2/samp_count_5> <empa_ch1/samp_count_5>
	513	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_6> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_6> <empa_ch3/samp_count_6> <empa_ch2/samp_count_6> <empa_ch1/samp_count_6>
	514	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_7> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_7> <empa_ch3/samp_count_7> <empa_ch2/samp_count_7> <empa_ch1/samp_count_7>
	515	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_8> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_8> <empa_ch3/samp_count_8> <empa_ch2/samp_count_8> <empa_ch1/samp_count_8>
	516	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_9> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_9> <empa_ch3/samp_count_9> <empa_ch2/samp_count_9> <empa_ch1/samp_count_9>
	517	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_10> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_10> <empa_ch3/samp_count_10> <empa_ch2/samp_count_10> <empa_ch1/samp_count_10>
	518	INFO:Xst:2261 - The FF/Latch <empa_ch5/samp_count_11> in Unit <FrontEnd_Acq> is equivalent to the following 4 FFs/Latches, which will be removed : <empa_ch4/samp_count_11> <empa_ch3/samp_count_11> <empa_ch2/samp_count_11> <empa_ch1/samp_count_11>
	519
	520	Mapping all equations...
	521	Building and optimizing final netlist ...
	522	Found area constraint ratio of 100 (+ 5) on block FrontEnd_Acq, actual ratio is 16.
	523	FlipFlop controlador_DPRAM/count_pack_0 has been replicated 1 time(s)
	524	FlipFlop controlador_DPRAM/count_pack_1 has been replicated 1 time(s)
	525	FlipFlop controlador_DPRAM/count_pack_2 has been replicated 1 time(s)
	526
	527	Final Macro Processing ...
	528
	529	=========================================================================
	530	Final Register Report
	531
	532	Macro Statistics
	533	# Registers : 508
	534	Flip-Flops : 508
	535
	536	=========================================================================
	537
	538	=========================================================================
	539	* Partition Report *
	540	=========================================================================
	541
	542	Partition Implementation Status
	543	-------------------------------
	544
	545	No Partitions were found in this design.
	546
	547	-------------------------------
	548
	549	=========================================================================
	550	* Design Summary *
	551	=========================================================================
	552
	553	Top Level Output File Name : FrontEnd_Acq.ngc
	554
	555	Primitive and Black Box Usage:
	556	------------------------------
	557	# BELS : 947
	558	# GND : 1
	559	# INV : 10
	560	# LUT1 : 52
	561	# LUT2 : 47
	562	# LUT3 : 76
	563	# LUT4 : 64
	564	# LUT5 : 190
	565	# LUT6 : 206
	566	# MUXCY : 143
	567	# MUXF7 : 7
	568	# VCC : 1
	569	# XORCY : 150
	570	# FlipFlops/Latches : 508
	571	# FD : 42
	572	# FDE : 196
	573	# FDR : 96
	574	# FDRE : 159
	575	# FDS : 15
	576	# Clock Buffers : 2
	577	# BUFG : 2
	578	# IO Buffers : 49
	579	# IBUF : 21
	580	# IBUFG : 1
	581	# OBUF : 27
	582	# DCMs : 1
	583	# DCM_SP : 1
	584
	585	Device utilization summary:
	586	---------------------------
	587
	588	Selected Device : 6slx9tqg144-3
	589
	590
	591	Slice Logic Utilization:
	592	Number of Slice Registers: 508 out of 11440 4%
	593	Number of Slice LUTs: 645 out of 5720 11%
	594	Number used as Logic: 645 out of 5720 11%
	595
	596	Slice Logic Distribution:
	597	Number of LUT Flip Flop pairs used: 815
	598	Number with an unused Flip Flop: 307 out of 815 37%
	599	Number with an unused LUT: 170 out of 815 20%
	600	Number of fully used LUT-FF pairs: 338 out of 815 41%
	601	Number of unique control sets: 22
	602
	603	IO Utilization:
	604	Number of IOs: 49
	605	Number of bonded IOBs: 49 out of 102 48%
	606
	607	Specific Feature Utilization:
	608	Number of BUFG/BUFGCTRLs: 2 out of 16 12%
	609
	610	---------------------------
	611	Partition Resource Summary:
	612	---------------------------
	613
	614	No Partitions were found in this design.
	615
	616	---------------------------
	617
	618
	619	=========================================================================
	620	Timing Report
	621
	622	NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
	623	FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
	624	GENERATED AFTER PLACE-and-ROUTE.
	625
	626	Clock Information:
	627	------------------
	628	-----------------------------------+------------------------+-------+
	629	Clock Signal \| Clock buffer(FF name) \| Load \|
	630	-----------------------------------+------------------------+-------+
	631	clk_main \| DCM_SP:CLKFX \| 508 \|
	632	-----------------------------------+------------------------+-------+
	633
	634	Asynchronous Control Signals Information:
	635	----------------------------------------
	636	No asynchronous control signals found in this design
	637
	638	Timing Summary:
	639	---------------
	640	Speed Grade: -3
	641
	642	Minimum period: 18.723ns (Maximum Frequency: 53.411MHz)
	643	Minimum input arrival time before clock: 1.903ns
	644	Maximum output required time after clock: 10.616ns
	645	Maximum combinational path delay: No path found
	646
	647	Timing Details:
	648	---------------
	649	All values displayed in nanoseconds (ns)
	650
	651	=========================================================================
	652	Timing constraint: Default period analysis for Clock 'clk_main'
	653	Clock period: 18.723ns (frequency: 53.411MHz)
	654	Total number of paths / destination ports: 4776 / 1112
	655	-------------------------------------------------------------------------
	656	Delay: 4.681ns (Levels of Logic = 4)
	657	Source: generador_req/count_pulses_1 (FF)
	658	Destination: generador_req/count_clock_16 (FF)
	659	Source Clock: clk_main rising 4.0X
	660	Destination Clock: clk_main rising 4.0X
	661
	662	Data Path: generador_req/count_pulses_1 to generador_req/count_clock_16
	663	Gate Net
	664	Cell:in->out fanout Delay Delay Logical Name (Net Name)
	665	---------------------------------------- ------------
	666	FDRE:C->Q 3 0.447 0.995 generador_req/count_pulses_1 (generador_req/count_pulses_1)
	667	LUT5:I0->O 2 0.203 0.617 generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9>_SW0 (N9)
	668	LUT6:I5->O 3 0.205 0.651 generador_req/PWR_8_o_count_pulses[9]_equal_4_o<9> (generador_req/PWR_8_o_count_pulses[9]_equal_4_o)
	669	LUT6:I5->O 18 0.205 1.050 generador_req/Mcount_count_clock_val (generador_req/Mcount_count_clock_val)
	670	LUT4:I3->O 1 0.205 0.000 generador_req/count_clock_16_rstpot (generador_req/count_clock_16_rstpot)
	671	FD:D 0.102 generador_req/count_clock_16
	672	----------------------------------------
	673	Total 4.681ns (1.367ns logic, 3.314ns route)
	674	(29.2% logic, 70.8% route)
	675
	676	=========================================================================
	677	Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main'
	678	Total number of paths / destination ports: 21 / 21
	679	-------------------------------------------------------------------------
	680	Offset: 1.903ns (Levels of Logic = 1)
	681	Source: clk_acq_ch5 (PAD)
	682	Destination: empa_ch5/clk_acq_r_0 (FF)
	683	Destination Clock: clk_main rising 4.0X
	684
	685	Data Path: clk_acq_ch5 to empa_ch5/clk_acq_r_0
	686	Gate Net
	687	Cell:in->out fanout Delay Delay Logical Name (Net Name)
	688	---------------------------------------- ------------
	689	IBUF:I->O 1 1.222 0.579 clk_acq_ch5_IBUF (clk_acq_ch5_IBUF)
	690	FDS:D 0.102 empa_ch5/clk_acq_r_0
	691	----------------------------------------
	692	Total 1.903ns (1.324ns logic, 0.579ns route)
	693	(69.6% logic, 30.4% route)
	694
	695	=========================================================================
	696	Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main'
	697	Total number of paths / destination ports: 3738 / 27
	698	-------------------------------------------------------------------------
	699	Offset: 10.616ns (Levels of Logic = 7)
	700	Source: controlador_DPRAM/count_ch_byte_2 (FF)
	701	Destination: addrA<7> (PAD)
	702	Source Clock: clk_main rising 4.0X
	703
	704	Data Path: controlador_DPRAM/count_ch_byte_2 to addrA<7>
	705	Gate Net
	706	Cell:in->out fanout Delay Delay Logical Name (Net Name)
	707	---------------------------------------- ------------
	708	FDRE:C->Q 103 0.447 1.990 controlador_DPRAM/count_ch_byte_2 (controlador_DPRAM/count_ch_byte_2)
	709	LUT3:I1->O 10 0.203 1.085 controlador_DPRAM/_n0517<5>21 (controlador_DPRAM/_n0517<5>2)
	710	LUT5:I2->O 1 0.205 0.000 controlador_DPRAM/_n0517<7>11 (controlador_DPRAM/_n0517<7>1)
	711	XORCY:LI->O 1 0.136 0.924 controlador_DPRAM/Madd_GND_26_o_GND_26_o_add_108_OUT_xor<7> (controlador_DPRAM/GND_26_o_GND_26_o_add_108_OUT<7>)
	712	LUT5:I0->O 1 0.203 0.944 controlador_DPRAM/Mmux_addrA103 (controlador_DPRAM/Mmux_addrA102)
	713	LUT6:I0->O 1 0.203 0.924 controlador_DPRAM/Mmux_addrA104 (controlador_DPRAM/Mmux_addrA103)
	714	LUT6:I1->O 1 0.203 0.579 controlador_DPRAM/Mmux_addrA106 (addrA_7_OBUF)
	715	OBUF:I->O 2.571 addrA_7_OBUF (addrA<7>)
	716	----------------------------------------
	717	Total 10.616ns (4.171ns logic, 6.445ns route)
	718	(39.3% logic, 60.7% route)
	719
	720	=========================================================================
	721
	722	Cross Clock Domains Report:
	723	--------------------------
	724
	725	Clock to Setup on destination clock clk_main
	726	---------------+---------+---------+---------+---------+
	727	\| Src:Rise\| Src:Fall\| Src:Rise\| Src:Fall\|
	728	Source Clock \|Dest:Rise\|Dest:Rise\|Dest:Fall\|Dest:Fall\|
	729	---------------+---------+---------+---------+---------+
	730	clk_main \| 4.681\| \| \| \|
	731	---------------+---------+---------+---------+---------+
	732
	733	=========================================================================
	734
	735
	736	Total REAL time to Xst completion: 11.00 secs
	737	Total CPU time to Xst completion: 10.51 secs
	738
	739	-->
	740
	741	Total memory usage is 251848 kilobytes
	742
	743	Number of errors : 0 ( 0 filtered)
	744	Number of warnings : 0 ( 0 filtered)
	745	Number of infos : 12 ( 0 filtered)
	746

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.vhd created 10644 +406 0

			@@ -0,0 +1,406
		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 09:10:02 02/24/2017
		6	-- Design Name:
		7	-- Module Name: FrontEnd_Acq - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	library UNISIM;
		30	use UNISIM.VComponents.all;
		31
		32	entity FrontEnd_Acq is
		33	GENERIC(
		34	DBIT_SZ: INTEGER := 3;
		35	ADDR_LENGTH: INTEGER := 12;
		36	DATAOUT_LENGTH: INTEGER := 8;
		37	CH_SZ: INTEGER :=5;
		38	NBITS_PERIOD: INTEGER :=18;
		39	NBITS_DUTY: INTEGER :=12;
		40	NBITS_PULSES: INTEGER :=10;
		41	RESUL_NP_SZ: INTEGER :=40;
		42	ID_CH_SZ: INTEGER := 4
		43
		44	);
		45	PORT(
		46	clk_main: IN std_logic; --Reloj principal de 60MHz
		47	pps: IN std_logic; --Senhal de sincronismo
		48	pck_rdy: OUT std_logic; --Senhal de aviso de paquete de 40 muestras por canal(200total) a la RPi
		49
		50	--Senhales de empaquetadores
		51	data_req_ch1: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		52	data_ch1: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		53	clk_acq_ch1: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		54
		55	data_req_ch2: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		56	data_ch2: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		57	clk_acq_ch2: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		58
		59	data_req_ch3: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		60	data_ch3: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		61	clk_acq_ch3: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		62
		63	data_req_ch4: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		64	data_ch4: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		65	clk_acq_ch4: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		66
		67	data_req_ch5: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		68	data_ch5: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		69	clk_acq_ch5: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		70
		71	--DPRAM senhales de control, direccion y data
		72	--Direccion de escritura
		73	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); --Direccion puerto A a escribir en DPRAM
		74	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0); --Datopuerto A a escribir en DPRAM
		75	enA: OUT std_logic --Habilitacion de escritura del puerto A
		76	);
		77	end FrontEnd_Acq;
		78
		79	architecture Behavioral of FrontEnd_Acq is
		80
		81	--COMPONENT joiner_samp_1 is
		82	--GENERIC(
		83	-- DBIT_SZ: INTEGER :=3;
		84	-- BITS_COUNT_SZ: INTEGER :=3;
		85	-- RESUL_NP_SZ: INTEGER :=40;
		86	-- SAMPLE_SZ: INTEGER :=24;
		87	-- SAMPLE_COUNT_SZ: INTEGER := 12;
		88	-- HEADER_NIB_SZ: INTEGER := 4;
		89	-- DATA_HEADER_NIB_SZ: INTEGER := 4;
		90	-- CH_COUNT_SZ: INTEGER :=4
		91	-- );
		92	--
		93	--PORT(
		94	--
		95	-- --Channel number
		96	-- --chn_id_acq: IN STD_LOGIC_VECTOR((CH_COUNT_SZ-1) downto 0);
		97	--
		98	-- --Reset del sistema
		99	-- rst_bar: IN STD_LOGIC;
		100	--
		101	-- --Reloj principal
		102	-- clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n
		103	--
		104	-- --Senhales con el microcontrolador
		105	-- clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del m�dulo de adquisici�n
		106	-- chn_bits_acq: IN STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del m�dulo de adquisici�n
		107	--
		108	-- --Data req
		109	-- dat_req_ch: IN STD_LOGIC;
		110	--
		111	-- --Senhales hacia el sistema
		112	-- resul_samp: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos
		113	-- rdy_samp: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria
		114	-- ack_in: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no
		115	--
		116	--);
		117	--END COMPONENT;
		118
		119	COMPONENT joiner_samp is
		120	GENERIC(
		121	DBIT_SZ: INTEGER :=3;
		122	BITS_COUNT_SZ: INTEGER :=3;
		123	RESUL_NP_SZ: INTEGER :=40;
		124	SAMPLE_SZ: INTEGER :=24;
		125	SAMPLE_COUNT_SZ: INTEGER := 12;
		126	HEADER_NIB_SZ: INTEGER := 4;
		127	DATA_HEADER_NIB_SZ: INTEGER := 4;
		128	CH_COUNT_SZ: INTEGER :=4
		129	);
		130
		131	PORT(
		132
		133	--Channel number
		134	chn_id_acq: IN STD_LOGIC_VECTOR((CH_COUNT_SZ-1) downto 0);
		135
		136	--Reset del sistema
		137	rst_bar: IN STD_LOGIC;
		138
		139	--Reloj principal
		140	clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n
		141
		142	--Senhales con el microcontrolador
		143	clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del m�dulo de adquisici�n
		144	chn_bits_acq: IN STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del m�dulo de adquisici�n
		145
		146	--Data req
		147	dat_req_ch: IN STD_LOGIC;
		148
		149	--Senhales hacia el sistema
		150	resul_samp: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos
		151	rdy_samp: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria
		152	ack_in: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no
		153
		154	);
		155	END COMPONENT;
		156
		157	COMPONENT DtoDPRAM is
		158	GENERIC(
		159	ADDR_LENGTH: INTEGER := 12;
		160	DATAOUT_LENGTH: INTEGER := 8;
		161	DATAIN_LENGTH: INTEGER := 40;
		162	CHAN_NUM: INTEGER := 5;
		163	COUNT_BYTE_SZ: INTEGER := 3;
		164	COUNT_PACK_SZ: INTEGER := 6
		165
		166	);
		167
		168	PORT(
		169	--Reset general
		170	rst_bar: IN std_logic;
		171
		172	--Reset general
		173	data_req: IN std_logic;
		174
		175	--Entrada de reloj principal
		176	clk_main: IN std_logic;
		177
		178	--Entradas para indicar dato preparado por leer
		179	--Desde los nibble to packets
		180	ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
		181
		182	--Senhal para que indica que termino con una peticion
		183	--Hacia los nibble to packets
		184	ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
		185
		186	--Data IN
		187	datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		188	datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		189	datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		190	datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		191	datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		192
		193	--DPRAM senhales de control, direccion y data
		194	--Direccion de escritura/lectura
		195	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0);
		196	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0);
		197	enA: OUT std_logic;
		198	--Aviso de Paquete de 40 muestras solicitadas a los 5 canales
		199	rpi_req: OUT std_logic
		200
		201	);
		202	END COMPONENT;
		203
		204	COMPONENT DCM_fwd_int IS
		205	PORT(
		206	clk_main_io : IN std_logic;
		207	c_200MHz_in : OUT std_logic
		208	);
		209	END COMPONENT;
		210
		211	COMPONENT Data_Req_gen IS
		212	GENERIC (
		213	NBITS_PERIOD: INTEGER :=18;
		214	NBITS_DUTY: INTEGER :=12;
		215	NBITS_PULSES: INTEGER :=10
		216	);
		217	PORT(
		218	c_200MHz_in : IN std_logic;
		219	reset_int : IN std_logic;
		220	pps : IN std_logic;
		221	data_req : OUT std_logic
		222	);
		223	END COMPONENT;
		224
		225	--Senhal de solicitud de dato
		226	SIGNAL data_req: std_logic := '0';
		227
		228	--Senhales para enlazar resultados de empaquetadores a DPRAM controller
		229	SIGNAL smppackage_ch1: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		230	SIGNAL rdy_samp_ch1: std_logic := '0';
		231	--SIGNAL ack_ch1: std_logic := '0';
		232
		233	SIGNAL smppackage_ch2: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		234	SIGNAL rdy_samp_ch2: std_logic := '0';
		235	--SIGNAL ack_ch2: std_logic := '0';
		236
		237	SIGNAL smppackage_ch3: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		238	SIGNAL rdy_samp_ch3: std_logic := '0';
		239	--SIGNAL ack_ch3: std_logic := '0';
		240
		241	SIGNAL smppackage_ch4: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		242	SIGNAL rdy_samp_ch4: std_logic := '0';
		243	--SIGNAL ack_ch4: std_logic := '0';
		244
		245	SIGNAL smppackage_ch5: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		246	SIGNAL rdy_samp_ch5: std_logic := '0';
		247	--SIGNAL ack_ch5: std_logic := '0';
		248
		249	SIGNAL ack_vector: std_logic_vector((CH_SZ-1)downto 0) := (OTHERS=>'0');
		250	SIGNAL rdy_samp_vector: std_logic_vector((CH_SZ-1)downto 0) := (OTHERS=>'0');
		251
		252	--Constante para canales
		253	CONSTANT canal_1: std_logic_vector((ID_CH_SZ-1)downto 0) := "0001";
		254	CONSTANT canal_2: std_logic_vector((ID_CH_SZ-1)downto 0) := "0010";
		255	CONSTANT canal_3: std_logic_vector((ID_CH_SZ-1)downto 0) := "0011";
		256	CONSTANT canal_4: std_logic_vector((ID_CH_SZ-1)downto 0) := "0100";
		257	CONSTANT canal_5: std_logic_vector((ID_CH_SZ-1)downto 0) := "0101";
		258
		259	--Senhales para DCM
		260	SIGNAL clk_u_proc: std_logic := '0';
		261	SIGNAL clk_main_io: std_logic :='1';
		262
		263	--Senhal de reset interna formada de rst_bar y pps_r
		264	SIGNAL cont_200MHz: std_logic_vector(15 downto 0) :="0000000000000000"; --"0000 0000 0000 0000": 16 bits a 240MHz 5ns*65535=327.675u
		265	SIGNAL lock_rst_bar: std_logic := '0';
		266
		267	begin
		268
		269	--Buffer entrada de Clock
		270	IBUFG_inst : IBUFG
		271	generic map (
		272	IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
		273	IOSTANDARD => "DEFAULT")
		274	port map (
		275	O => clk_main_io, -- Clock buffer output
		276	I => clk_main -- Clock buffer input (connect directly to top-level port)
		277	);
		278
		279	--Generacion de relojes
		280	clk_mang: DCM_fwd_int PORT MAP(
		281	clk_main_io => clk_main_io,
		282	c_200MHz_in => clk_u_proc
		283	);
		284
		285	--Generacion de reset
		286	reset_gen: PROCESS(clk_u_proc)
		287
		288	BEGIN
		289	IF(rising_edge(clk_u_proc)) THEN
		290	IF (cont_200MHz = "1111111111111111") THEN --"1111 1111 1111 1111" <> 65536
		291	lock_rst_bar <= '1';
		292	ELSE
		293	cont_200MHz <= std_logic_vector(unsigned(cont_200MHz)+1);
		294	lock_rst_bar <= '0';
		295	END IF;
		296	END IF;
		297	END PROCESS;
		298
		299
		300	--Bloque de generacion de solicitudes
		301	generador_req: Data_Req_gen
		302	GENERIC MAP(
		303	NBITS_PERIOD => NBITS_PERIOD,
		304	NBITS_DUTY => NBITS_DUTY,
		305	NBITS_PULSES => NBITS_PULSES
		306	)
		307
		308	PORT MAP(
		309	c_200MHz_in => clk_u_proc,
		310	reset_int => lock_rst_bar,
		311	pps => pps,
		312	data_req => data_req
		313	);
		314
		315	--Bloques de empaquetadores
		316	empa_ch1: joiner_samp PORT MAP(
		317	rst_bar => lock_rst_bar,
		318	clk_main => clk_u_proc,
		319	dat_req_ch => data_req,
		320	chn_id_acq => canal_1,
		321	clk_acq => clk_acq_ch1,
		322	chn_bits_acq => data_ch1,
		323	resul_samp => smppackage_ch1,
		324	rdy_samp => rdy_samp_ch1,
		325	ack_in => ack_vector(0)
		326	);
		327	data_req_ch1 <= data_req;
		328
		329	empa_ch2: joiner_samp PORT MAP(
		330	rst_bar => lock_rst_bar,
		331	clk_main => clk_u_proc,
		332	dat_req_ch => data_req,
		333	chn_id_acq => canal_2,
		334	clk_acq => clk_acq_ch2,
		335	chn_bits_acq => data_ch2,
		336	resul_samp => smppackage_ch2,
		337	rdy_samp => rdy_samp_ch2,
		338	ack_in => ack_vector(1)
		339	);
		340	data_req_ch2 <= data_req;
		341
		342	empa_ch3: joiner_samp PORT MAP(
		343	rst_bar => lock_rst_bar,
		344	clk_main => clk_u_proc,
		345	dat_req_ch => data_req,
		346	chn_id_acq => canal_3,
		347	clk_acq => clk_acq_ch3,
		348	chn_bits_acq => data_ch3,
		349	resul_samp => smppackage_ch3,
		350	rdy_samp => rdy_samp_ch3,
		351	ack_in => ack_vector(2)
		352	);
		353	data_req_ch3 <= data_req;
		354
		355	empa_ch4: joiner_samp PORT MAP(
		356	rst_bar => lock_rst_bar,
		357	clk_main => clk_u_proc,
		358	dat_req_ch => data_req,
		359	chn_id_acq => canal_4,
		360	clk_acq => clk_acq_ch4,
		361	chn_bits_acq => data_ch4,
		362	resul_samp => smppackage_ch4,
		363	rdy_samp => rdy_samp_ch4,
		364	ack_in => ack_vector(3)
		365	);
		366	data_req_ch4 <= data_req;
		367
		368	empa_ch5: joiner_samp PORT MAP(
		369	rst_bar => lock_rst_bar,
		370	clk_main => clk_u_proc,
		371	dat_req_ch => data_req,
		372	chn_id_acq => canal_5,
		373	clk_acq => clk_acq_ch5,
		374	chn_bits_acq => data_ch5,
		375	resul_samp => smppackage_ch5,
		376	rdy_samp => rdy_samp_ch5,
		377	ack_in => ack_vector(4)
		378	);
		379	data_req_ch5 <= data_req;
		380
		381	--Union de senhales rdy y ack para DPRAM
		382
		383	rdy_samp_vector <= rdy_samp_ch5 & rdy_samp_ch4 & rdy_samp_ch3 & rdy_samp_ch2 & rdy_samp_ch1;
		384
		385	--Bloque de DPRAM controller
		386	controlador_DPRAM: DtoDPRAM PORT MAP(
		387
		388	rst_bar => lock_rst_bar,
		389	data_req => data_req,
		390	clk_main => clk_u_proc,
		391	ch_rdy_vector => rdy_samp_vector,
		392	ch_ack_vector => ack_vector,
		393	datach1 => smppackage_ch1,
		394	datach2 => smppackage_ch2,
		395	datach3 => smppackage_ch3,
		396	datach4 => smppackage_ch4,
		397	datach5 => smppackage_ch5,
		398	addrA => addrA,
		399	dataA => dataA,
		400	enA => enA,
		401	rpi_req => pck_rdy
		402
		403	);
		404
		405	end Behavioral;
		406

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.xise created 10644 +383 0

			@@ -0,0 +1,383
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		4	<header>
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		8	<!-- project source files, project and process properties. This file, -->
		9	<!-- along with the project source files, is sufficient to open and -->
		10	<!-- implement in ISE Project Navigator. -->
		11	<!-- -->
		12	<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
		13	</header>
		14
		15	<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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		132	<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
		133	<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
		134	<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
		135	<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
		136	<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
		137	<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
		138	<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
		139	<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
		140	<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
		141	<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
		142	<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
		143	<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
		144	<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
		145	<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
		146	<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
		147	<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
		148	<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
		149	<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
		150	<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
		151	<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
		152	<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
		153	<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
		154	<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
		155	<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
		156	<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
		157	<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
		158	<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
		159	<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
		160	<property xil_pn:name="Implementation Top" xil_pn:value="Architecture\|FrontEnd_Acq\|Behavioral" xil_pn:valueState="non-default"/>
		161	<property xil_pn:name="Implementation Top File" xil_pn:value="FrontEnd_Acq.vhd" xil_pn:valueState="non-default"/>
		162	<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FrontEnd_Acq" xil_pn:valueState="non-default"/>
		163	<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
		164	<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
		165	<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
		166	<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
		167	<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
		168	<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
		169	<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
		170	<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
		171	<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
		172	<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
		173	<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
		174	<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
		175	<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
		176	<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
		177	<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
		178	<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
		179	<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
		180	<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
		181	<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
		182	<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
		183	<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
		184	<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
		185	<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
		186	<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
		187	<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
		188	<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
		189	<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
		190	<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
		191	<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
		192	<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
		193	<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
		194	<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
		195	<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
		196	<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
		197	<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
		198	<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
		199	<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
		200	<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
		201	<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
		202	<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
		203	<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
		204	<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
		205	<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
		206	<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
		207	<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		208	<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
		209	<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
		210	<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
		211	<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
		212	<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
		213	<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		214	<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		215	<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		216	<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		217	<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		218	<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
		219	<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
		220	<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
		221	<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
		222	<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		223	<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
		224	<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
		225	<property xil_pn:name="Output File Name" xil_pn:value="FrontEnd_Acq" xil_pn:valueState="default"/>
		226	<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
		227	<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
		228	<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
		229	<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
		230	<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
		231	<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
		232	<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
		233	<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
		234	<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
		235	<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
		236	<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
		237	<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
		238	<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="FrontEnd_Acq_map.vhd" xil_pn:valueState="default"/>
		239	<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="FrontEnd_Acq_timesim.vhd" xil_pn:valueState="default"/>
		240	<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FrontEnd_Acq_synthesis.vhd" xil_pn:valueState="default"/>
		241	<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FrontEnd_Acq_translate.vhd" xil_pn:valueState="default"/>
		242	<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
		243	<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
		244	<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
		245	<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
		246	<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
		247	<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
		248	<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
		249	<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		250	<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
		251	<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		252	<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
		253	<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
		254	<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
		255	<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
		256	<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
		257	<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
		258	<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
		259	<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
		260	<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
		261	<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
		262	<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
		263	<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="FrontEnd_Acq" xil_pn:valueState="default"/>
		264	<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
		265	<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
		266	<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
		267	<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
		268	<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
		269	<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
		270	<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
		271	<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
		272	<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
		273	<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
		274	<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
		275	<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
		276	<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
		277	<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
		278	<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
		279	<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
		280	<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
		281	<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
		282	<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
		283	<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
		284	<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
		285	<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
		286	<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
		287	<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
		288	<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
		289	<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
		290	<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
		291	<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
		292	<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
		293	<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
		294	<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
		295	<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
		296	<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
		297	<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
		298	<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		299	<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		300	<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		301	<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
		302	<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
		303	<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
		304	<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
		305	<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
		306	<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
		307	<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
		308	<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
		309	<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
		310	<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
		311	<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
		312	<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
		313	<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
		314	<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
		315	<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
		316	<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
		317	<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
		318	<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
		319	<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
		320	<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
		321	<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
		322	<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
		323	<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
		324	<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
		325	<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		326	<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
		327	<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
		328	<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
		329	<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		330	<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
		331	<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
		332	<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
		333	<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
		334	<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
		335	<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
		336	<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
		337	<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
		338	<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
		339	<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
		340	<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
		341	<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
		342	<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
		343	<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
		344	<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
		345	<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
		346	<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
		347	<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
		348	<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
		349	<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
		350	<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
		351	<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
		352	<!-- -->
		353	<!-- The following properties are for internal use only. These should not be modified.-->
		354	<!-- -->
		355	<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture\|testbench\|behavior" xil_pn:valueState="non-default"/>
		356	<property xil_pn:name="PROP_DesignName" xil_pn:value="FrontEnd_Acq" xil_pn:valueState="non-default"/>
		357	<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
		358	<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
		359	<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		360	<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		361	<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		362	<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
		363	<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
		364	<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-02-24T09:09:37" xil_pn:valueState="non-default"/>
		365	<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="38F2FF6F00714A1EAD1B63342807D3E9" xil_pn:valueState="non-default"/>
		366	<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
		367	<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
		368	</properties>
		369
		370	<bindings/>
		371
		372	<libraries/>
		373
		374	<autoManagedFiles>
		375	<!-- The following files are identified by `include statements in verilog -->
		376	<!-- source files and are automatically managed by Project Navigator. -->
		377	<!-- -->
		378	<!-- Do not hand-edit this section, as it will be overwritten when the -->
		379	<!-- project is analyzed based on files automatically identified as -->
		380	<!-- include files. -->
		381	</autoManagedFiles>
		382
		383	</project>

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq.xst created 10644 +52 0

			@@ -0,0 +1,52
		1	set -tmpdir "xst/projnav.tmp"
		2	set -xsthdpdir "xst"
		3	run
		4	-ifn FrontEnd_Acq.prj
		5	-ofn FrontEnd_Acq
		6	-ofmt NGC
		7	-p xc6slx9-3-tqg144
		8	-top FrontEnd_Acq
		9	-opt_mode Speed
		10	-opt_level 1
		11	-power NO
		12	-iuc NO
		13	-keep_hierarchy No
		14	-netlist_hierarchy As_Optimized
		15	-rtlview Yes
		16	-glob_opt AllClockNets
		17	-read_cores YES
		18	-write_timing_constraints NO
		19	-cross_clock_analysis NO
		20	-hierarchy_separator /
		21	-bus_delimiter <>
		22	-case Maintain
		23	-slice_utilization_ratio 100
		24	-bram_utilization_ratio 100
		25	-dsp_utilization_ratio 100
		26	-lc Auto
		27	-reduce_control_sets Auto
		28	-fsm_extract YES -fsm_encoding Auto
		29	-safe_implementation No
		30	-fsm_style LUT
		31	-ram_extract Yes
		32	-ram_style Auto
		33	-rom_extract Yes
		34	-shreg_extract YES
		35	-rom_style Auto
		36	-auto_bram_packing NO
		37	-resource_sharing YES
		38	-async_to_sync NO
		39	-shreg_min_size 2
		40	-use_dsp48 Auto
		41	-iobuf YES
		42	-max_fanout 100000
		43	-bufg 16
		44	-register_duplication YES
		45	-register_balancing No
		46	-optimize_primitives NO
		47	-use_clock_enable Auto
		48	-use_sync_set Auto
		49	-use_sync_reset Auto
		50	-iob Auto
		51	-equivalent_register_removal YES
		52	-slice_utilization_ratio_maxmargin 5

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq_b.vhd created 10644 +254 0

			@@ -0,0 +1,254
		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 09:10:02 02/24/2017
		6	-- Design Name:
		7	-- Module Name: FrontEnd_Acq - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	library UNISIM;
		30	use UNISIM.VComponents.all;
		31
		32	entity FrontEnd_Acq is
		33	GENERIC(
		34	DBIT_SZ: INTEGER := 3;
		35	ADDR_LENGTH: INTEGER := 12;
		36	DATAOUT_LENGTH: INTEGER := 8;
		37	CH_SZ: INTEGER :=5;
		38	NBITS_PERIOD: INTEGER :=18;
		39	NBITS_DUTY: INTEGER :=12;
		40	NBITS_PULSES: INTEGER :=10
		41
		42	);
		43	PORT(
		44	clk_main: IN std_logic; --Reloj principal de 60MHz
		45	pps: IN std_logic; --Senhal de sincronismo
		46	pck_rdy: OUT std_logic; --Senhal de aviso de paquete de 40 muestras por canal(200total) a la RPi
		47
		48	--Senhales de empaquetadores
		49	data_req_ch1: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		50	data_ch1: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		51	clk_acq_ch1: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		52
		53	data_req_ch2: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		54	data_ch2: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		55	clk_acq_ch2: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		56
		57	data_req_ch3: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		58	data_ch3: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		59	clk_acq_ch3: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		60
		61	data_req_ch4: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		62	data_ch4: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		63	clk_acq_ch4: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		64
		65	data_req_ch5: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		66	data_ch5: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		67	clk_acq_ch5: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		68
		69	--DPRAM senhales de control, direccion y data
		70	--Direccion de escritura
		71	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); --Direccion puerto A a escribir en DPRAM
		72	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0); --Datopuerto A a escribir en DPRAM
		73	enA: OUT std_logic --Habilitacion de escritura del puerto A
		74	);
		75	end FrontEnd_Acq;
		76
		77	architecture Behavioral of FrontEnd_Acq is
		78
		79	COMPONENT joiner_samp is
		80	GENERIC(
		81	DBIT_SZ: INTEGER :=3;
		82	BITS_COUNT_SZ: INTEGER :=3;
		83	RESUL_NP_SZ: INTEGER :=40;
		84	SAMPLE_SZ: INTEGER :=24;
		85	SAMPLE_COUNT_SZ: INTEGER := 12;
		86	HEADER_NIB_SZ: INTEGER := 4;
		87	DATA_HEADER_NIB_SZ: INTEGER := 4;
		88	CH_COUNT_SZ: INTEGER :=4
		89	);
		90
		91	PORT(
		92
		93	--Channel number
		94	chn_id_acq: IN STD_LOGIC_VECTOR((CH_COUNT_SZ-1) downto 0);
		95
		96	--Reset del sistema
		97	rst_bar: IN STD_LOGIC;
		98
		99	--Reloj principal
		100	clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n
		101
		102	--Senhales con el microcontrolador
		103	clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del m�dulo de adquisici�n
		104	chn_bits_acq: IN STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del m�dulo de adquisici�n
		105
		106	--Data req
		107	dat_req_ch: IN STD_LOGIC;
		108
		109	--Senhales hacia el sistema
		110	resul_samp: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos
		111	rdy_samp: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria
		112	ack_in: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no
		113
		114	);
		115	END COMPONENT;
		116
		117	COMPONENT DtoDPRAM is
		118	GENERIC(
		119	ADDR_LENGTH: INTEGER := 12;
		120	DATAOUT_LENGTH: INTEGER := 8;
		121	DATAIN_LENGTH: INTEGER := 40;
		122	CHAN_NUM: INTEGER := 5;
		123	COUNT_BYTE_SZ: INTEGER := 3;
		124	COUNT_PACK_SZ: INTEGER := 6
		125
		126	);
		127
		128	PORT(
		129	--Reset general
		130	rst_bar: IN std_logic;
		131
		132	--Reset general
		133	data_req: IN std_logic;
		134
		135	--Entrada de reloj principal
		136	clk_main: IN std_logic;
		137
		138	--Entradas para indicar dato preparado por leer
		139	--Desde los nibble to packets
		140	ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
		141
		142	--Senhal para que indica que termino con una peticion
		143	--Hacia los nibble to packets
		144	ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
		145
		146	--Data IN
		147	datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		148	datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		149	datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		150	datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		151	datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
		152
		153	--DPRAM senhales de control, direccion y data
		154	--Direccion de escritura/lectura
		155	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0);
		156	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0);
		157	enA: OUT std_logic;
		158	--Aviso de Paquete de 40 muestras solicitadas a los 5 canales
		159	rpi_req: OUT std_logic
		160
		161	);
		162	END COMPONENT;
		163
		164	COMPONENT DCM_fwd_int IS
		165	PORT(
		166	clk_main_io : IN std_logic;
		167	c_200MHz_in : OUT std_logic
		168	);
		169
		170	COMPONENT Data_Req_gen IS
		171	GENERIC (
		172	NBITS_PERIOD: INTEGER :=18;
		173	NBITS_DUTY: INTEGER :=12;
		174	NBITS_PULSES: INTEGER :=10
		175	);
		176	PORT(
		177	c_200MHz_in : IN std_logic;
		178	reset_int : IN std_logic;
		179	pps : IN std_logic;
		180	data_req : OUT std_logic
		181	);
		182	END COMPONENT;
		183
		184	--Senhal de solicitud de dato
		185
		186	--Senhales para enlazar resultados de empaquetadores a DPRAM controller
		187	--Constante para canales
		188	CONSTANT canal_1: std_logic_vector((CH_SZ-1)downto 0) := "00001";
		189	CONSTANT canal_2: std_logic_vector((CH_SZ-1)downto 0) := "00010";
		190	CONSTANT canal_3: std_logic_vector((CH_SZ-1)downto 0) := "00100";
		191	CONSTANT canal_4: std_logic_vector((CH_SZ-1)downto 0) := "01000";
		192	CONSTANT canal_5: std_logic_vector((CH_SZ-1)downto 0) := "10000";
		193
		194	--Senhales para DCM
		195	SIGNAL clk_u_proc: std_logic := '0';
		196	SIGNAL clk_main_io: std_logic :='1';
		197
		198	--Senhal de reset interna formada de rst_bar y pps_r
		199	SIGNAL cont_200MHz: std_logic_vector(15 downto 0) :="0000000000000000"; --"0000 0000 0000 0000": 16 bits a 240MHz 5ns*65535=327.675u
		200	SIGNAL lock_rst_bar: std_logic := '0';
		201
		202
		203	begin
		204
		205	--Buffer entrada de Clock
		206	IBUFG_inst : IBUFG
		207	generic map (
		208	IBUF_LOW_PWR => FALSE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
		209	IOSTANDARD => "DEFAULT")
		210	port map (
		211	O => clk_main_io, -- Clock buffer output
		212	I => clk_main -- Clock buffer input (connect directly to top-level port)
		213	);
		214
		215	--Generacion de relojes
		216	clk_mang: DCM_fwd_int PORT MAP(
		217	clk_main_io => clk_main_io,
		218	c_200MHz_in => clk_u_proc
		219	);
		220
		221	--Generacion de reset
		222	reset_gen: PROCESS(clk_u_proc)
		223
		224	BEGIN
		225	IF(rising_edge(clk_u_proc)) THEN
		226	IF (cont_200MHz = "1111111111111111") THEN --"1111 1111 1111 1111" <> 65536
		227	lock_rst_bar <= '1';
		228	ELSE
		229	cont_200MHz <= std_logic_vector(unsigned(cont_200MHz)+1);
		230	lock_rst_bar <= '0';
		231	END IF;
		232	END IF;
		233	END PROCESS;
		234
		235	--Bloque de generacion de solicitudes
		236
		237
		238	--Bloques de empaquetadores
		239	empa_ch1: joiner_samp PORT MAP(
		240
		241	chn_id_acq => canal_1,
		242	rst_bar => lock_rst_bar,
		243	clk_main => clk_u_proc,
		244	clk_acq => clk_acq_ch1,
		245	chn_bits_acq => data_ch1,
		246	dat_req_ch => ,
		247	resul_samp => ,
		248	rdy_samp => ,
		249	ack_in =>
		250	);
		251
		252
		253	end Behavioral;
		254

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq_envsettings.html created 10644 +388 0

			@@ -0,0 +1,388
		1	<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
		2	<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
		3	<center><big><big><b>System Settings</b></big></big></center><br>
		4	<A NAME="Environment Settings"></A>
		5	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		6	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
		7	<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
		8	</tr>
		9	<tr bgcolor='#ffff99'>
		10	<td><b>Environment Variable</b></td>
		11	<td><b>xst</b></td>
		12	<td><b>ngdbuild</b></td>
		13	<td><b>map</b></td>
		14	<td><b>par</b></td>
		15	</tr>
		16	<tr>
		17	<td>PATHEXT</td>
		18	<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
		19	<td><font color=gray>< data not available ></font></td>
		20	<td><font color=gray>< data not available ></font></td>
		21	<td><font color=gray>< data not available ></font></td>
		22	</tr>
		23	<tr>
		24	<td>Path</td>
		25	<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Program Files\ImageMagick-7.0.2-Q16;<br>C:\Python27\;<br>C:\ProgramData\Oracle\Java\javapath;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\Users\Francisco\AppData\Local\GitHub\PortableGit_d76a6a98c9315931ec4927243517bc09e9b731a0;<br>C:\Cadence\SPB_16.2\tools\bin;<br>C:\Cadence\SPB_16.2\tools\libutil\bin;<br>C:\Cadence\SPB_16.2\tools\fet\bin;<br>C:\Cadence\SPB_16.2\tools\pcb\bin;<br>C:\Cadence\SPB_16.2\tools\PSpice;<br>C:\Cadence\SPB_16.2\tools\PSpice\Library;<br>C:\Cadence\SPB_16.2\tools\Capture;<br>C:\Cadence\SPB_16.2\tools\specctra\bin;<br>C:\Program Files (x86)\HI-TECH Software\PICC\9.82\bin;<br>C:\Program Files (x86)\HI-TECH Software\PICC-Lite\9.50\bin;<br>C:\PROGRA~2\PICC;<br>C:\Users\Francisco\Documents\Francisco_tesis\REDACCIONES_IMPLEMENTACION\TFT_display\opencv\opencv\build\x64\vc12\bin;<br>C:\Program Files (x86)\Anaconda3;<br>C:\Program Files (x86)\Anaconda3\Scripts;<br>C:\Program Files (x86)\Anaconda3\Library\bin;<br>C:\Program Files (x86)\Anaconda2;<br>C:\Program Files (x86)\Anaconda2\Scripts;<br>C:\Program Files (x86)\Anaconda2\Library\bin;<br>C:\Users\Francisco\AppData\Local\Programs\Python\Python35-32\Scripts\;<br>C:\Users\Francisco\AppData\Local\Programs\Python\Python35-32\;<br>c:\MinGW\bin;<br>c:\MinGW\include;<br>c:\MinGW\lib;<br>c:\MinGW\MSYS\1.0\bin;<br>C:\Program Files (x86)\ATMEL Corporation\AT91-ISP v1.12\SAM-BA v2.8;<br>C:\Program Files (x86)\ATMEL Corporation\AT91-ISP v1.12\Library\;<br>C:\Users\Francisco\AppData\Local\.meteor\;<br>C:\Users\Francisco\AppData\Local\atom\bin</td>
		26	<td><font color=gray>< data not available ></font></td>
		27	<td><font color=gray>< data not available ></font></td>
		28	<td><font color=gray>< data not available ></font></td>
		29	</tr>
		30	<tr>
		31	<td>XILINX</td>
		32	<td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
		33	<td><font color=gray>< data not available ></font></td>
		34	<td><font color=gray>< data not available ></font></td>
		35	<td><font color=gray>< data not available ></font></td>
		36	</tr>
		37	<tr>
		38	<td>XILINX_DSP</td>
		39	<td>C:\Xilinx\14.7\ISE_DS\ISE</td>
		40	<td><font color=gray>< data not available ></font></td>
		41	<td><font color=gray>< data not available ></font></td>
		42	<td><font color=gray>< data not available ></font></td>
		43	</tr>
		44	<tr>
		45	<td>XILINX_EDK</td>
		46	<td>C:\Xilinx\14.7\ISE_DS\EDK</td>
		47	<td><font color=gray>< data not available ></font></td>
		48	<td><font color=gray>< data not available ></font></td>
		49	<td><font color=gray>< data not available ></font></td>
		50	</tr>
		51	<tr>
		52	<td>XILINX_PLANAHEAD</td>
		53	<td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
		54	<td><font color=gray>< data not available ></font></td>
		55	<td><font color=gray>< data not available ></font></td>
		56	<td><font color=gray>< data not available ></font></td>
		57	</tr>
		58	</TABLE>
		59	<A NAME="Synthesis Property Settings"></A>
		60	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		61	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
		62	<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
		63	</tr>
		64	<tr bgcolor='#ffff99'>
		65	<td><b>Switch Name</b></td>
		66	<td><b>Property Name</b></td>
		67	<td><b>Value</b></td>
		68	<td><b>Default Value</b></td>
		69	</tr>
		70	<tr>
		71	<td>-ifn</td>
		72	<td> </td>
		73	<td>FrontEnd_Acq.prj</td>
		74	<td> </td>
		75	</tr>
		76	<tr>
		77	<td>-ofn</td>
		78	<td> </td>
		79	<td>FrontEnd_Acq</td>
		80	<td> </td>
		81	</tr>
		82	<tr>
		83	<td>-ofmt</td>
		84	<td> </td>
		85	<td>NGC</td>
		86	<td>NGC</td>
		87	</tr>
		88	<tr>
		89	<td>-p</td>
		90	<td> </td>
		91	<td>xc6slx9-3-tqg144</td>
		92	<td> </td>
		93	</tr>
		94	<tr>
		95	<td>-top</td>
		96	<td> </td>
		97	<td>FrontEnd_Acq</td>
		98	<td> </td>
		99	</tr>
		100	<tr>
		101	<td>-opt_mode</td>
		102	<td>Optimization Goal</td>
		103	<td>Speed</td>
		104	<td>Speed</td>
		105	</tr>
		106	<tr>
		107	<td>-opt_level</td>
		108	<td>Optimization Effort</td>
		109	<td>1</td>
		110	<td>1</td>
		111	</tr>
		112	<tr>
		113	<td>-power</td>
		114	<td>Power Reduction</td>
		115	<td>NO</td>
		116	<td>No</td>
		117	</tr>
		118	<tr>
		119	<td>-iuc</td>
		120	<td>Use synthesis Constraints File</td>
		121	<td>NO</td>
		122	<td>No</td>
		123	</tr>
		124	<tr>
		125	<td>-keep_hierarchy</td>
		126	<td>Keep Hierarchy</td>
		127	<td>No</td>
		128	<td>No</td>
		129	</tr>
		130	<tr>
		131	<td>-netlist_hierarchy</td>
		132	<td>Netlist Hierarchy</td>
		133	<td>As_Optimized</td>
		134	<td>As_Optimized</td>
		135	</tr>
		136	<tr>
		137	<td>-rtlview</td>
		138	<td>Generate RTL Schematic</td>
		139	<td>Yes</td>
		140	<td>No</td>
		141	</tr>
		142	<tr>
		143	<td>-glob_opt</td>
		144	<td>Global Optimization Goal</td>
		145	<td>AllClockNets</td>
		146	<td>AllClockNets</td>
		147	</tr>
		148	<tr>
		149	<td>-read_cores</td>
		150	<td>Read Cores</td>
		151	<td>YES</td>
		152	<td>Yes</td>
		153	</tr>
		154	<tr>
		155	<td>-write_timing_constraints</td>
		156	<td>Write Timing Constraints</td>
		157	<td>NO</td>
		158	<td>No</td>
		159	</tr>
		160	<tr>
		161	<td>-cross_clock_analysis</td>
		162	<td>Cross Clock Analysis</td>
		163	<td>NO</td>
		164	<td>No</td>
		165	</tr>
		166	<tr>
		167	<td>-bus_delimiter</td>
		168	<td>Bus Delimiter</td>
		169	<td><></td>
		170	<td><></td>
		171	</tr>
		172	<tr>
		173	<td>-slice_utilization_ratio</td>
		174	<td>Slice Utilization Ratio</td>
		175	<td>100</td>
		176	<td>100</td>
		177	</tr>
		178	<tr>
		179	<td>-bram_utilization_ratio</td>
		180	<td>BRAM Utilization Ratio</td>
		181	<td>100</td>
		182	<td>100</td>
		183	</tr>
		184	<tr>
		185	<td>-dsp_utilization_ratio</td>
		186	<td>DSP Utilization Ratio</td>
		187	<td>100</td>
		188	<td>100</td>
		189	</tr>
		190	<tr>
		191	<td>-reduce_control_sets</td>
		192	<td> </td>
		193	<td>Auto</td>
		194	<td>Auto</td>
		195	</tr>
		196	<tr>
		197	<td>-fsm_extract</td>
		198	<td> </td>
		199	<td>YES</td>
		200	<td>Yes</td>
		201	</tr>
		202	<tr>
		203	<td>-fsm_encoding</td>
		204	<td> </td>
		205	<td>Auto</td>
		206	<td>Auto</td>
		207	</tr>
		208	<tr>
		209	<td>-safe_implementation</td>
		210	<td> </td>
		211	<td>No</td>
		212	<td>No</td>
		213	</tr>
		214	<tr>
		215	<td>-fsm_style</td>
		216	<td> </td>
		217	<td>LUT</td>
		218	<td>LUT</td>
		219	</tr>
		220	<tr>
		221	<td>-ram_extract</td>
		222	<td> </td>
		223	<td>Yes</td>
		224	<td>Yes</td>
		225	</tr>
		226	<tr>
		227	<td>-ram_style</td>
		228	<td> </td>
		229	<td>Auto</td>
		230	<td>Auto</td>
		231	</tr>
		232	<tr>
		233	<td>-rom_extract</td>
		234	<td> </td>
		235	<td>Yes</td>
		236	<td>Yes</td>
		237	</tr>
		238	<tr>
		239	<td>-shreg_extract</td>
		240	<td> </td>
		241	<td>YES</td>
		242	<td>Yes</td>
		243	</tr>
		244	<tr>
		245	<td>-rom_style</td>
		246	<td> </td>
		247	<td>Auto</td>
		248	<td>Auto</td>
		249	</tr>
		250	<tr>
		251	<td>-auto_bram_packing</td>
		252	<td> </td>
		253	<td>NO</td>
		254	<td>No</td>
		255	</tr>
		256	<tr>
		257	<td>-resource_sharing</td>
		258	<td> </td>
		259	<td>YES</td>
		260	<td>Yes</td>
		261	</tr>
		262	<tr>
		263	<td>-async_to_sync</td>
		264	<td> </td>
		265	<td>NO</td>
		266	<td>No</td>
		267	</tr>
		268	<tr>
		269	<td>-use_dsp48</td>
		270	<td> </td>
		271	<td>Auto</td>
		272	<td>Auto</td>
		273	</tr>
		274	<tr>
		275	<td>-iobuf</td>
		276	<td> </td>
		277	<td>YES</td>
		278	<td>Yes</td>
		279	</tr>
		280	<tr>
		281	<td>-max_fanout</td>
		282	<td> </td>
		283	<td>100000</td>
		284	<td>100000</td>
		285	</tr>
		286	<tr>
		287	<td>-bufg</td>
		288	<td> </td>
		289	<td>16</td>
		290	<td>16</td>
		291	</tr>
		292	<tr>
		293	<td>-register_duplication</td>
		294	<td> </td>
		295	<td>YES</td>
		296	<td>Yes</td>
		297	</tr>
		298	<tr>
		299	<td>-register_balancing</td>
		300	<td> </td>
		301	<td>No</td>
		302	<td>No</td>
		303	</tr>
		304	<tr>
		305	<td>-optimize_primitives</td>
		306	<td> </td>
		307	<td>NO</td>
		308	<td>No</td>
		309	</tr>
		310	<tr>
		311	<td>-use_clock_enable</td>
		312	<td> </td>
		313	<td>Auto</td>
		314	<td>Auto</td>
		315	</tr>
		316	<tr>
		317	<td>-use_sync_set</td>
		318	<td> </td>
		319	<td>Auto</td>
		320	<td>Auto</td>
		321	</tr>
		322	<tr>
		323	<td>-use_sync_reset</td>
		324	<td> </td>
		325	<td>Auto</td>
		326	<td>Auto</td>
		327	</tr>
		328	<tr>
		329	<td>-iob</td>
		330	<td> </td>
		331	<td>Auto</td>
		332	<td>Auto</td>
		333	</tr>
		334	<tr>
		335	<td>-equivalent_register_removal</td>
		336	<td> </td>
		337	<td>YES</td>
		338	<td>Yes</td>
		339	</tr>
		340	<tr>
		341	<td>-slice_utilization_ratio_maxmargin</td>
		342	<td> </td>
		343	<td>5</td>
		344	<td>0</td>
		345	</tr>
		346	</TABLE>
		347	<A NAME="Operating System Information"></A>
		348	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		349	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
		350	<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
		351	</tr>
		352	<tr bgcolor='#ffff99'>
		353	<td><b>Operating System Information</b></td>
		354	<td><b>xst</b></td>
		355	<td><b>ngdbuild</b></td>
		356	<td><b>map</b></td>
		357	<td><b>par</b></td>
		358	</tr>
		359	<tr>
		360	<td>CPU Architecture/Speed</td>
		361	<td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
		362	<td><font color=gray><  data not available  ></font></td>
		363	<td><font color=gray><  data not available  ></font></td>
		364	<td><font color=gray><  data not available  ></font></td>
		365	</tr>
		366	<tr>
		367	<td>Host</td>
		368	<td>Lenovo-PC</td>
		369	<td><font color=gray><  data not available  ></font></td>
		370	<td><font color=gray><  data not available  ></font></td>
		371	<td><font color=gray><  data not available  ></font></td>
		372	</tr>
		373	<tr>
		374	<td>OS Name</td>
		375	<td>Microsoft , 64-bit</td>
		376	<td><font color=gray><  data not available  ></font></td>
		377	<td><font color=gray><  data not available  ></font></td>
		378	<td><font color=gray><  data not available  ></font></td>
		379	</tr>
		380	<tr>
		381	<td>OS Release</td>
		382	<td>major release (build 9200)</td>
		383	<td><font color=gray><  data not available  ></font></td>
		384	<td><font color=gray><  data not available  ></font></td>
		385	<td><font color=gray><  data not available  ></font></td>
		386	</tr>
		387	</TABLE>
		388	</BODY> </HTML> No newline at end of file

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq_summary.html created 10644 +112 0

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		1	<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
		2	<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
		3	<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		4	<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
		5	<TD ALIGN=CENTER COLSPAN='4'><B>FrontEnd_Acq Project Status (02/24/2017 - 11:29:08)</B></TD></TR>
		6	<TR ALIGN=LEFT>
		7	<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
		8	<TD>FrontEnd_Acq.xise</TD>
		9	<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
		10	<TD> No Errors </TD>
		11	</TR>
		12	<TR ALIGN=LEFT>
		13	<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
		14	<TD>FrontEnd_Acq</TD>
		15	<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
		16	<TD>Synthesized</TD>
		17	</TR>
		18	<TR ALIGN=LEFT>
		19	<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
		20	<TD>xc6slx9-3tqg144</TD>
		21	<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
		22	<TD>
		23	No Errors</TD>
		24	</TR>
		25	<TR ALIGN=LEFT>
		26	<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
		27	<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
		28	<TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\_xmsgs/*.xmsgs?&DataKey=Warning'>51 Warnings (46 new)</A></TD>
		29	</TR>
		30	<TR ALIGN=LEFT>
		31	<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
		32	<TD>Balanced</TD>
		33	<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
		34	<TD>
		35	</TD>
		36	</TR>
		37	<TR ALIGN=LEFT>
		38	<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
		39	<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
		40	<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
		41	<TD> </TD>
		42	</TR>
		43	<TR ALIGN=LEFT>
		44	<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
		45	<TD>
		46	<A HREF_DISABLED='C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\FrontEnd_Acq_envsettings.html'>
		47	System Settings</A>
		48	</TD>
		49	<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
		50	<TD>  </TD>
		51	</TR>
		52	</TABLE>
		53
		54
		55
		56	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		57	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
		58	<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
		59	<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
		60	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice Registers</TD>
		61	<TD ALIGN=RIGHT>508</TD>
		62	<TD ALIGN=RIGHT>11440</TD>
		63	<TD ALIGN=RIGHT COLSPAN='2'>4%</TD>
		64	</TR>
		65	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
		66	<TD ALIGN=RIGHT>637</TD>
		67	<TD ALIGN=RIGHT>5720</TD>
		68	<TD ALIGN=RIGHT COLSPAN='2'>11%</TD>
		69	</TR>
		70	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
		71	<TD ALIGN=RIGHT>338</TD>
		72	<TD ALIGN=RIGHT>807</TD>
		73	<TD ALIGN=RIGHT COLSPAN='2'>41%</TD>
		74	</TR>
		75	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
		76	<TD ALIGN=RIGHT>44</TD>
		77	<TD ALIGN=RIGHT>102</TD>
		78	<TD ALIGN=RIGHT COLSPAN='2'>43%</TD>
		79	</TR>
		80	<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFG/BUFGCTRLs</TD>
		81	<TD ALIGN=RIGHT>2</TD>
		82	<TD ALIGN=RIGHT>16</TD>
		83	<TD ALIGN=RIGHT COLSPAN='2'>12%</TD>
		84	</TR>
		85	</TABLE>
		86
		87
		88
		89
		90
		91
		92
		93	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		94	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
		95	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
		96	<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
		97	<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\FrontEnd_Acq.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>vie 24. feb 11:29:06 2017</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\_xmsgs/xst.xmsgs?&DataKey=Warning'>51 Warnings (46 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\_xmsgs/xst.xmsgs?&DataKey=Info'>15 Infos (15 new)</A></TD></TR>
		98	<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		99	<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		100	<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		101	<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		102	<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		103	<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
		104	</TABLE>
		105	<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
		106	<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
		107	<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
		108	</TABLE>
		109
		110
		111	<br><center><b>Date Generated:</b> 02/24/2017 - 11:29:08</center>
		112	</BODY></HTML> No newline at end of file

trunk/firmware/sources/Processing2017/FrontEnd_Acq/FrontEnd_Acq_xst.xrpt created 10644 +218 0

			@@ -0,0 +1,218
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trunk/firmware/sources/Processing2017/FrontEnd_Acq/_xmsgs/pn_parser.xmsgs created 10644 +15 0

			@@ -0,0 +1,15
		1	<?xml version="1.0" encoding="UTF-8"?>
		2	<!-- IMPORTANT: This is an internal file that has been generated -->
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		9
		10	<messages>
		11	<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/tb_FrontEnd_Acq.vhd" into library work</arg>
		12	</msg>
		13
		14	</messages>
		15

trunk/firmware/sources/Processing2017/FrontEnd_Acq/_xmsgs/xst.xmsgs created 10644 +45 0

			@@ -0,0 +1,45
		1	<?xml version="1.0" encoding="UTF-8"?>
		2	<!-- IMPORTANT: This is an internal file that has been generated
		3	by the Xilinx ISE software. Any direct editing or
		4	changes made to this file may result in unpredictable
		5	behavior or data corruption. It is strongly advised that
		6	users do not edit the contents of this file. -->
		7	<messages>
		8	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_0</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_0> <empa_ch3/samp_count_0> <empa_ch2/samp_count_0> <empa_ch1/samp_count_0> </arg>
		9	</msg>
		10
		11	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_1</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_1> <empa_ch3/samp_count_1> <empa_ch2/samp_count_1> <empa_ch1/samp_count_1> </arg>
		12	</msg>
		13
		14	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_2</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_2> <empa_ch3/samp_count_2> <empa_ch2/samp_count_2> <empa_ch1/samp_count_2> </arg>
		15	</msg>
		16
		17	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_3</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_3> <empa_ch3/samp_count_3> <empa_ch2/samp_count_3> <empa_ch1/samp_count_3> </arg>
		18	</msg>
		19
		20	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_4</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_4> <empa_ch3/samp_count_4> <empa_ch2/samp_count_4> <empa_ch1/samp_count_4> </arg>
		21	</msg>
		22
		23	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_5</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_5> <empa_ch3/samp_count_5> <empa_ch2/samp_count_5> <empa_ch1/samp_count_5> </arg>
		24	</msg>
		25
		26	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_6</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_6> <empa_ch3/samp_count_6> <empa_ch2/samp_count_6> <empa_ch1/samp_count_6> </arg>
		27	</msg>
		28
		29	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_7</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_7> <empa_ch3/samp_count_7> <empa_ch2/samp_count_7> <empa_ch1/samp_count_7> </arg>
		30	</msg>
		31
		32	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_8</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_8> <empa_ch3/samp_count_8> <empa_ch2/samp_count_8> <empa_ch1/samp_count_8> </arg>
		33	</msg>
		34
		35	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_9</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_9> <empa_ch3/samp_count_9> <empa_ch2/samp_count_9> <empa_ch1/samp_count_9> </arg>
		36	</msg>
		37
		38	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_10</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_10> <empa_ch3/samp_count_10> <empa_ch2/samp_count_10> <empa_ch1/samp_count_10> </arg>
		39	</msg>
		40
		41	<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">empa_ch5/samp_count_11</arg>> in Unit <<arg fmt="%s" index="2">FrontEnd_Acq</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><empa_ch4/samp_count_11> <empa_ch3/samp_count_11> <empa_ch2/samp_count_11> <empa_ch1/samp_count_11> </arg>
		42	</msg>
		43
		44	</messages>
		45

trunk/firmware/sources/Processing2017/FrontEnd_Acq/fuse.xmsgs created 10644 +9 0

			@@ -0,0 +1,9
		1	<?xml version="1.0" encoding="UTF-8"?>
		2	<!-- IMPORTANT: This is an internal file that has been generated
		3	by the Xilinx ISE software. Any direct editing or
		4	changes made to this file may result in unpredictable
		5	behavior or data corruption. It is strongly advised that
		6	users do not edit the contents of this file. -->
		7	<messages>
		8	</messages>
		9

trunk/firmware/sources/Processing2017/FrontEnd_Acq/iseconfig/FrontEnd_Acq.projectmgr created 10644 +77 0

			@@ -0,0 +1,77
		1	<?xml version="1.0" encoding="utf-8"?>
		2	<!--This is an ISE project configuration file.-->
		3	<!--It holds project specific layout data for the projectmgr plugin.-->
		4	<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
		5	<Project version="2" owner="projectmgr" name="FrontEnd_Acq" >
		6	<!--This is an ISE project configuration file.-->
		7	<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
		8	<ClosedNodes>
		9	<ClosedNodesVersion>2</ClosedNodesVersion>
		10	</ClosedNodes>
		11	<SelectedItems>
		12	<SelectedItem>xc6slx9-3tqg144</SelectedItem>
		13	</SelectedItems>
		14	<ScrollbarPosition orientation="vertical" >1</ScrollbarPosition>
		15	<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
		16	<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001c7000000020000000100000000000000000200000064ffffffff000000810000000300000002000001c70000000100000003000000000000000100000003</ViewHeaderState>
		17	<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
		18	<CurrentItem>xc6slx9-3tqg144</CurrentItem>
		19	</ItemView>
		20	<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
		21	<ClosedNodes>
		22	<ClosedNodesVersion>1</ClosedNodesVersion>
		23	<ClosedNode>Design Utilities</ClosedNode>
		24	</ClosedNodes>
		25	<SelectedItems>
		26	<SelectedItem></SelectedItem>
		27	</SelectedItems>
		28	<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
		29	<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
		30	<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000</ViewHeaderState>
		31	<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
		32	<CurrentItem></CurrentItem>
		33	</ItemView>
		34	<ItemView guiview="File" >
		35	<ClosedNodes>
		36	<ClosedNodesVersion>1</ClosedNodesVersion>
		37	</ClosedNodes>
		38	<SelectedItems/>
		39	<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
		40	<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
		41	<ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001c20000000100000000</ViewHeaderState>
		42	<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
		43	<CurrentItem></CurrentItem>
		44	</ItemView>
		45	<ItemView guiview="Library" >
		46	<ClosedNodes>
		47	<ClosedNodesVersion>1</ClosedNodesVersion>
		48	<ClosedNode>work</ClosedNode>
		49	</ClosedNodes>
		50	<SelectedItems/>
		51	<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
		52	<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
		53	<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
		54	<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
		55	<CurrentItem>work</CurrentItem>
		56	</ItemView>
		57	<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
		58	<ClosedNodes>
		59	<ClosedNodesVersion>1</ClosedNodesVersion>
		60	<ClosedNode>Configure Target Device</ClosedNode>
		61	<ClosedNode>Design Utilities</ClosedNode>
		62	<ClosedNode>Implement Design</ClosedNode>
		63	<ClosedNode>Synthesize - XST</ClosedNode>
		64	<ClosedNode>User Constraints</ClosedNode>
		65	</ClosedNodes>
		66	<SelectedItems>
		67	<SelectedItem></SelectedItem>
		68	</SelectedItems>
		69	<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
		70	<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
		71	<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000</ViewHeaderState>
		72	<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
		73	<CurrentItem></CurrentItem>
		74	</ItemView>
		75	<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
		76	<CurrentView>Implementation</CurrentView>
		77	</Project>

trunk/firmware/sources/Processing2017/FrontEnd_Acq/iseconfig/FrontEnd_Acq.xreport created 10644 +215 0

			@@ -0,0 +1,215
		1	<?xml version='1.0' encoding='UTF-8'?>
		2	<report-views version="2.0" >
		3	<header>
		4	<DateModified>2017-02-24T09:53:03</DateModified>
		5	<ModuleName>FrontEnd_Acq</ModuleName>
		6	<SummaryTimeStamp>Unknown</SummaryTimeStamp>
		7	<SavedFilePath>C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/iseconfig/FrontEnd_Acq.xreport</SavedFilePath>
		8	<ImplementationReportsDirectory>C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq\</ImplementationReportsDirectory>
		9	<DateInitialized>2017-02-24T09:10:02</DateInitialized>
		10	<EnableMessageFiltering>false</EnableMessageFiltering>
		11	</header>
		12	<body>
		13	<viewgroup label="Design Overview" >
		14	<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="FrontEnd_Acq_summary.html" label="Summary" >
		15	<toc-item title="Design Overview" target="Design Overview" />
		16	<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
		17	<toc-item title="Performance Summary" target="Performance Summary" />
		18	<toc-item title="Failing Constraints" target="Failing Constraints" />
		19	<toc-item title="Detailed Reports" target="Detailed Reports" />
		20	</view>
		21	<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="FrontEnd_Acq_envsettings.html" label="System Settings" />
		22	<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="FrontEnd_Acq_map.xrpt" label="IOB Properties" />
		23	<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="FrontEnd_Acq_map.xrpt" label="Control Set Information" />
		24	<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="FrontEnd_Acq_map.xrpt" label="Module Level Utilization" />
		25	<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="FrontEnd_Acq.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
		26	<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="FrontEnd_Acq_par.xrpt" label="Pinout Report" />
		27	<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="FrontEnd_Acq_par.xrpt" label="Clock Report" />
		28	<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="FrontEnd_Acq.twx" label="Static Timing" />
		29	<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FrontEnd_Acq_html/fit/report.htm" label="CPLD Fitter Report" />
		30	<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="FrontEnd_Acq_html/tim/report.htm" label="CPLD Timing Report" />
		31	</viewgroup>
		32	<viewgroup label="XPS Errors and Warnings" >
		33	<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
		34	<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
		35	<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
		36	</viewgroup>
		37	<viewgroup label="XPS Reports" >
		38	<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
		39	<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
		40	<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
		41	<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="FrontEnd_Acq.log" label="System Log File" />
		42	</viewgroup>
		43	<viewgroup label="Errors and Warnings" >
		44	<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
		45	<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
		46	<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
		47	<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
		48	<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
		49	<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
		50	<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
		51	<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
		52	<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
		53	<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
		54	<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
		55	</viewgroup>
		56	<viewgroup label="Detailed Reports" >
		57	<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="FrontEnd_Acq.syr" label="Synthesis Report" >
		58	<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
		59	<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
		60	<toc-item title="HDL Compilation" target=" HDL Compilation " />
		61	<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
		62	<toc-item title="HDL Analysis" target=" HDL Analysis " />
		63	<toc-item title="HDL Parsing" target=" HDL Parsing " />
		64	<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
		65	<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
		66	<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
		67	<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
		68	<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
		69	<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
		70	<toc-item title="Partition Report" target=" Partition Report " />
		71	<toc-item title="Final Report" target=" Final Report " />
		72	<toc-item title="Design Summary" target=" Design Summary " />
		73	<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
		74	<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
		75	<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
		76	<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
		77	<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
		78	<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
		79	<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
		80	<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
		81	<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
		82	</view>
		83	<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="FrontEnd_Acq.srr" label="Synplify Report" />
		84	<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="FrontEnd_Acq.prec_log" label="Precision Report" />
		85	<view inputState="Synthesized" program="ngdbuild" type="Report" file="FrontEnd_Acq.bld" label="Translation Report" >
		86	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		87	<toc-item title="Command Line" target="Command Line:" />
		88	<toc-item title="Partition Status" target="Partition Implementation Status" />
		89	<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
		90	</view>
		91	<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="FrontEnd_Acq_map.mrp" label="Map Report" >
		92	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		93	<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
		94	<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
		95	<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
		96	<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
		97	<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
		98	<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
		99	<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
		100	<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
		101	<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
		102	<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
		103	<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
		104	<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
		105	<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
		106	</view>
		107	<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="FrontEnd_Acq.par" label="Place and Route Report" >
		108	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		109	<toc-item title="Device Utilization" target="Device Utilization Summary:" />
		110	<toc-item title="Router Information" target="Starting Router" />
		111	<toc-item title="Partition Status" target="Partition Implementation Status" />
		112	<toc-item title="Clock Report" target="Generating Clock Report" />
		113	<toc-item title="Timing Results" target="Timing Score:" />
		114	<toc-item title="Final Summary" target="Peak Memory Usage:" />
		115	</view>
		116	<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="FrontEnd_Acq.twr" label="Post-PAR Static Timing Report" >
		117	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		118	<toc-item title="Timing Report Description" target="Device,package,speed:" />
		119	<toc-item title="Informational Messages" target="INFO:" />
		120	<toc-item title="Warning Messages" target="WARNING:" />
		121	<toc-item title="Timing Constraints" target="Timing constraint:" />
		122	<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
		123	<toc-item title="Data Sheet Report" target="Data Sheet report:" />
		124	<toc-item title="Timing Summary" target="Timing summary:" />
		125	<toc-item title="Trace Settings" target="Trace Settings:" />
		126	</view>
		127	<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FrontEnd_Acq.rpt" label="CPLD Fitter Report (Text)" >
		128	<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
		129	<toc-item title="Resources Summary" target=" Mapped Resource Summary " />
		130	<toc-item title="Pin Resources" target=" Pin Resources " />
		131	<toc-item title="Global Resources" target=" Global Control Resources " />
		132	</view>
		133	<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="FrontEnd_Acq.tim" label="CPLD Timing Report (Text)" >
		134	<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
		135	<toc-item title="Performance Summary" target="Performance Summary:" />
		136	</view>
		137	<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="FrontEnd_Acq.pwr" label="Power Report" >
		138	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		139	<toc-item title="Power summary" target="Power summary" />
		140	<toc-item title="Thermal summary" target="Thermal summary" />
		141	</view>
		142	<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="FrontEnd_Acq.bgn" label="Bitgen Report" >
		143	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		144	<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
		145	<toc-item title="Final Summary" target="DRC detected" />
		146	</view>
		147	</viewgroup>
		148	<viewgroup label="Secondary Reports" >
		149	<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
		150	<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/FrontEnd_Acq_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
		151	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		152	</view>
		153	<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/FrontEnd_Acq_translate.nlf" label="Post-Translate Simulation Model Report" >
		154	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		155	</view>
		156	<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
		157	<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FrontEnd_Acq_map.map" label="Map Log File" >
		158	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		159	<toc-item title="Design Information" target="Design Information" />
		160	<toc-item title="Design Summary" target="Design Summary" />
		161	</view>
		162	<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
		163	<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_preroute.twr" label="Post-Map Static Timing Report" >
		164	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		165	<toc-item title="Timing Report Description" target="Device,package,speed:" />
		166	<toc-item title="Informational Messages" target="INFO:" />
		167	<toc-item title="Warning Messages" target="WARNING:" />
		168	<toc-item title="Timing Constraints" target="Timing constraint:" />
		169	<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
		170	<toc-item title="Data Sheet Report" target="Data Sheet report:" />
		171	<toc-item title="Timing Summary" target="Timing summary:" />
		172	<toc-item title="Trace Settings" target="Trace Settings:" />
		173	</view>
		174	<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/FrontEnd_Acq_map.nlf" label="Post-Map Simulation Model Report" />
		175	<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_map.psr" label="Physical Synthesis Report" >
		176	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		177	</view>
		178	<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="FrontEnd_Acq_pad.txt" label="Pad Report" >
		179	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		180	</view>
		181	<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="FrontEnd_Acq.unroutes" label="Unroutes Report" >
		182	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		183	</view>
		184	<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_preroute.tsi" label="Post-Map Constraints Interaction Report" >
		185	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		186	</view>
		187	<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.grf" label="Guide Results Report" />
		188	<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.dly" label="Asynchronous Delay Report" />
		189	<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.clk_rgn" label="Clock Region Report" />
		190	<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.tsi" label="Post-Place and Route Constraints Interaction Report" >
		191	<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
		192	</view>
		193	<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
		194	<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/FrontEnd_Acq_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
		195	<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq_sta.nlf" label="Primetime Netlist Report" >
		196	<toc-item title="Top of Report" target="Release" searchDir="Forward" />
		197	</view>
		198	<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.ibs" label="IBIS Model" >
		199	<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
		200	<toc-item title="Component" target="Component " />
		201	</view>
		202	<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.lck" label="Back-annotate Pin Report" >
		203	<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
		204	<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
		205	</view>
		206	<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="FrontEnd_Acq.lpc" label="Locked Pin Constraints" >
		207	<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
		208	<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
		209	</view>
		210	<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/FrontEnd_Acq_timesim.nlf" label="Post-Fit Simulation Model Report" />
		211	<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
		212	<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
		213	</viewgroup>
		214	</body>
		215	</report-views>

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trunk/firmware/sources/Processing2017/FrontEnd_Acq/joiner_samp.vhd created 10644 +324 0

			@@ -0,0 +1,324
		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 11:35:58 02/20/2017
		6	-- Design Name:
		7	-- Module Name: joiner_samp - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	--library UNISIM;
		30	--use UNISIM.VComponents.all;
		31
		32	entity joiner_samp is
		33	GENERIC(
		34	DBIT_SZ: INTEGER :=3;
		35	BITS_COUNT_SZ: INTEGER :=3;
		36	RESUL_NP_SZ: INTEGER :=40;
		37	SAMPLE_SZ: INTEGER :=24;
		38	SAMPLE_COUNT_SZ: INTEGER := 12;
		39	HEADER_NIB_SZ: INTEGER := 4;
		40	DATA_HEADER_NIB_SZ: INTEGER := 4;
		41	CH_COUNT_SZ: INTEGER :=4
		42	);
		43
		44	PORT(
		45
		46	--Channel number
		47	chn_id_acq: IN STD_LOGIC_VECTOR((CH_COUNT_SZ-1) downto 0);
		48
		49	--Reset del sistema
		50	rst_bar: IN STD_LOGIC;
		51
		52	--Reloj principal
		53	clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n
		54
		55	--Senhales con el microcontrolador
		56	clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del m�dulo de adquisici�n
		57	chn_bits_acq: IN STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del m�dulo de adquisici�n
		58
		59	--Data req
		60	dat_req_ch: IN STD_LOGIC;
		61
		62	--Senhales hacia el sistema
		63	resul_samp: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos
		64	rdy_samp: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria
		65	ack_in: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no
		66
		67	);
		68	end joiner_samp;
		69
		70	architecture Behavioral of joiner_samp is
		71
		72	--Registros para sincronizacion
		73	SIGNAL clk_acq_r : std_logic_vector (2 downto 0) :=(OTHERS=>'1');
		74	SIGNAL chn_bits_acq_bit0 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		75	SIGNAL chn_bits_acq_bit1 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		76	SIGNAL chn_bits_acq_bit2 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		77
		78	--Senhales para deteccion de flancos
		79	SIGNAL clk_acq_rise : std_logic :='0';
		80
		81	--Senhal Interna de dato completo
		82	SIGNAL rdy_mem_aux: std_logic :='0';
		83
		84	--Constantes asociadas al contador de nibbles
		85	SIGNAL dbits_counter : std_logic_vector ((BITS_COUNT_SZ-1) downto 0) :=(OTHERS=>'0');
		86	CONSTANT TOP_COUNT: std_logic_vector((BITS_COUNT_SZ-1) downto 0) :="111";
		87	CONSTANT BASE_COUNT: std_logic_vector((BITS_COUNT_SZ-1) downto 0) :=(OTHERS=>'0');
		88
		89	--Senhales para almacenar resultado a siguiente etapa
		90	SIGNAL resul_mem_internal: std_logic_vector((SAMPLE_SZ-1) downto 0) :=(OTHERS=>'0');
		91	SIGNAL resul_mem_internal_aux: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0');
		92
		93	--Estados de la maquina de presentacion de datos a la RAM y RAM Controller
		94	TYPE data_states IS ( idle,
		95	data_pres, data_proc
		96	);
		97	SIGNAL data_cur_state: data_states := idle;
		98	SIGNAL data_next_state: data_states := idle;
		99
		100	--Estados de la maquina de construccion de paquete
		101	TYPE pack_states IS ( idle,
		102	building
		103	);
		104	SIGNAL pack_cur_state : pack_states := idle;
		105	SIGNAL pack_next_state : pack_states := idle;
		106
		107	SIGNAL nibble_aux: STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0) := (OTHERS => '0');
		108	SIGNAL samp_count: STD_LOGIC_VECTOR((SAMPLE_COUNT_SZ-1) downto 0) := (OTHERS => '0');
		109	CONSTANT TOP_SAMPLES_COUNT: std_logic_vector((SAMPLE_COUNT_SZ-1) downto 0) := "001111101000";
		110	begin
		111
		112	--Etapa de sincronizacion
		113	sync_data: PROCESS(clk_main)
		114	BEGIN
		115	IF(rising_edge(clk_main)) THEN
		116	IF(rst_bar = '0') THEN
		117	chn_bits_acq_bit0 <= (OTHERS=>'0');
		118	chn_bits_acq_bit1 <= (OTHERS=>'0');
		119	chn_bits_acq_bit2 <= (OTHERS=>'0');
		120	ELSE
		121	chn_bits_acq_bit0 <= chn_bits_acq_bit0(0) & chn_bits_acq(0);
		122	chn_bits_acq_bit1 <= chn_bits_acq_bit1(0) & chn_bits_acq(1);
		123	chn_bits_acq_bit2 <= chn_bits_acq_bit2(0) & chn_bits_acq(2);
		124	END IF;
		125	END IF;
		126	END PROCESS;
		127
		128	nibble_aux <= chn_bits_acq_bit2(1) &
		129	chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1);
		130
		131	--Etapa de deteccion de flancos
		132	edge_det: PROCESS(clk_main)
		133	BEGIN
		134	IF(rising_edge(clk_main)) THEN
		135	IF(rst_bar = '0') THEN
		136	clk_acq_r <=(OTHERS =>'1');
		137	clk_acq_rise <= '0';
		138
		139	ELSE
		140	clk_acq_r <= clk_acq_r(1 downto 0) & clk_acq;
		141	IF (clk_acq_r(2 downto 1) = "01") THEN
		142	clk_acq_rise <= '1';
		143	ELSE
		144	clk_acq_rise <= '0';
		145	END IF;
		146
		147	END IF;
		148	END IF;
		149	END PROCESS;
		150
		151	--Etapa de deteccion de cabecera y almacenamiento
		152	cambio_estados: PROCESS(clk_main)
		153	BEGIN
		154	IF (rising_edge(clk_main)) THEN
		155	IF(rst_bar = '0') THEN
		156	pack_cur_state <= idle;
		157	ELSE
		158	pack_cur_state <= pack_next_state;
		159	END IF;
		160	END IF;
		161	END PROCESS;
		162
		163	salidas_estados: PROCESS(pack_cur_state, dbits_counter,clk_acq_rise,dat_req_ch)
		164	BEGIN
		165	CASE pack_cur_state IS
		166	WHEN idle =>
		167	IF(dat_req_ch = '1') THEN
		168	pack_next_state <= building;
		169	ELSE
		170	pack_next_state <= idle;
		171	END IF;
		172	WHEN building =>
		173	IF(clk_acq_rise = '1') THEN
		174	IF (dbits_counter = TOP_COUNT) THEN
		175	pack_next_state <= idle;
		176	ELSE
		177	pack_next_state <= building;
		178	END IF;
		179	ELSE
		180	pack_next_state <= building;
		181	END IF;
		182
		183	WHEN OTHERS =>
		184	pack_next_state <= idle;
		185
		186	END CASE;
		187	END PROCESS;
		188
		189	save_bits: PROCESS(clk_main)
		190	BEGIN
		191	IF(rising_edge(clk_main)) THEN
		192	IF (rst_bar = '0') THEN
		193	dbits_counter <=(OTHERS => '0') ;
		194	resul_mem_internal <=(OTHERS => '0') ;
		195	ELSE
		196	IF (pack_cur_state = building) THEN
		197
		198	IF(dat_req_ch = '1') THEN
		199	dbits_counter <=(OTHERS => '0') ;
		200	ELSIF(clk_acq_rise = '1') THEN
		201	dbits_counter <=std_logic_vector(unsigned(dbits_counter)+1);
		202	CASE dbits_counter IS
		203	WHEN "000" =>
		204	resul_mem_internal(23 downto 21) <= nibble_aux;
		205	WHEN "001" =>
		206	resul_mem_internal(20 downto 18) <= nibble_aux;
		207	WHEN "010" =>
		208	resul_mem_internal(17 downto 15) <= nibble_aux;
		209	WHEN "011" =>
		210	resul_mem_internal(14 downto 12) <= nibble_aux;
		211	WHEN "100" =>
		212	resul_mem_internal(11 downto 9) <= nibble_aux;
		213	WHEN "101" =>
		214	resul_mem_internal(8 downto 6) <= nibble_aux;
		215	WHEN "110"=>
		216	resul_mem_internal(5 downto 3) <= nibble_aux;
		217	WHEN "111"=>
		218	resul_mem_internal(2 downto 0) <= nibble_aux;
		219	dbits_counter <=(OTHERS => '0');
		220	WHEN OTHERS =>
		221	dbits_counter <=(OTHERS => '0');
		222	END CASE;
		223	END IF;
		224	END IF;
		225	END IF;
		226	END IF;
		227	END PROCESS;
		228
		229	resul_mem_internal_aux(39 downto 36) <= chn_id_acq;
		230
		231	guardar_dato: PROCESS(clk_main)
		232	BEGIN
		233	IF (rising_edge(clk_main)) THEN
		234	IF(data_cur_state = idle) THEN
		235	IF(rdy_mem_aux = '1') THEN
		236	resul_mem_internal_aux((RESUL_NP_SZ-5)downto 0) <= --chn_id_acq &
		237	samp_count &
		238	resul_mem_internal;
		239	END IF;
		240	END IF;
		241	END IF;
		242	END PROCESS;
		243
		244	conteo_muestra: PROCESS(clk_main)
		245	BEGIN
		246	IF (rising_edge(clk_main)) THEN
		247	IF(dat_req_ch = '1') THEN
		248	IF(samp_count = TOP_SAMPLES_COUNT) THEN
		249	samp_count <= (OTHERS=>'0');
		250	ELSE
		251	samp_count <= std_logic_vector(unsigned(samp_count)+1) ;
		252	END IF;
		253	END IF;
		254	END IF;
		255	END PROCESS;
		256
		257	output_rdy_mem: PROCESS(clk_main)
		258	BEGIN
		259	IF(rising_edge(clk_main)) THEN
		260	IF (rst_bar = '0') THEN
		261	rdy_mem_aux <= '0';
		262	ELSE
		263	IF((dbits_counter = TOP_COUNT)) THEN
		264	IF((clk_acq_rise = '1')) THEN
		265	rdy_mem_aux <= '1';
		266	END IF;
		267	ELSE
		268	rdy_mem_aux <= '0';
		269	END IF;
		270	END IF;
		271	END IF;
		272	END PROCESS;
		273
		274	cambio_estados_data: PROCESS(clk_main)
		275	BEGIN
		276	IF (rising_edge(clk_main)) THEN
		277	IF(rst_bar = '0') THEN
		278	data_cur_state <= idle;
		279	ELSE
		280	data_cur_state <= data_next_state;
		281	END IF;
		282	END IF;
		283	END PROCESS;
		284
		285	salidas_estados_data: PROCESS(resul_mem_internal_aux,data_cur_state,ack_in,rdy_mem_aux)
		286	BEGIN
		287	CASE data_cur_state IS
		288	WHEN idle =>
		289	rdy_samp <= '0';
		290	resul_samp <= (OTHERS => '0');
		291	IF (rdy_mem_aux = '1') THEN
		292	data_next_state <= data_pres;
		293	ELSE
		294	data_next_state <= idle;
		295	END IF;
		296
		297	WHEN data_pres =>
		298	rdy_samp <= '1';
		299	resul_samp <= resul_mem_internal_aux;
		300	IF (ack_in = '1') THEN
		301	data_next_state <= data_proc;
		302	ELSE
		303	data_next_state <= data_pres;
		304	END IF;
		305
		306	WHEN data_proc =>
		307	rdy_samp <= '1';
		308	resul_samp <= resul_mem_internal_aux;
		309	IF (ack_in = '0') THEN --Si ya est� ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato
		310	data_next_state <= idle;
		311	ELSE
		312	data_next_state <= data_proc;
		313	END IF;
		314
		315	WHEN OTHERS =>
		316	rdy_samp <= '0';
		317	resul_samp <= (OTHERS => '0');
		318	data_next_state <= idle;
		319
		320	END CASE;
		321	END PROCESS;
		322
		323	end Behavioral;
		324

trunk/firmware/sources/Processing2017/FrontEnd_Acq/joiner_samp_1.vhd created 10644 +325 0

			@@ -0,0 +1,325
		1	----------------------------------------------------------------------------------
		2	-- Company:
		3	-- Engineer:
		4	--
		5	-- Create Date: 11:35:58 02/20/2017
		6	-- Design Name:
		7	-- Module Name: joiner_samp - Behavioral
		8	-- Project Name:
		9	-- Target Devices:
		10	-- Tool versions:
		11	-- Description:
		12	--
		13	-- Dependencies:
		14	--
		15	-- Revision:
		16	-- Revision 0.01 - File Created
		17	-- Additional Comments:
		18	--
		19	----------------------------------------------------------------------------------
		20	library IEEE;
		21	use IEEE.STD_LOGIC_1164.ALL;
		22
		23	-- Uncomment the following library declaration if using
		24	-- arithmetic functions with Signed or Unsigned values
		25	use IEEE.NUMERIC_STD.ALL;
		26
		27	-- Uncomment the following library declaration if instantiating
		28	-- any Xilinx primitives in this code.
		29	--library UNISIM;
		30	--use UNISIM.VComponents.all;
		31
		32	entity joiner_samp_1 is
		33	GENERIC(
		34	DBIT_SZ: INTEGER :=3;
		35	BITS_COUNT_SZ: INTEGER :=3;
		36	RESUL_NP_SZ: INTEGER :=40;
		37	SAMPLE_SZ: INTEGER :=24;
		38	SAMPLE_COUNT_SZ: INTEGER := 12;
		39	HEADER_NIB_SZ: INTEGER := 4;
		40	DATA_HEADER_NIB_SZ: INTEGER := 4;
		41	CH_COUNT_SZ: INTEGER :=4
		42	);
		43
		44	PORT(
		45
		46	--Channel number
		47	--chn_id_acq: IN STD_LOGIC_VECTOR((CH_COUNT_SZ-1) downto 0);
		48
		49	--Reset del sistema
		50	rst_bar: IN STD_LOGIC;
		51
		52	--Reloj principal
		53	clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n
		54
		55	--Senhales con el microcontrolador
		56	clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del m�dulo de adquisici�n
		57	chn_bits_acq: IN STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del m�dulo de adquisici�n
		58
		59	--Data req
		60	dat_req_ch: IN STD_LOGIC;
		61
		62	--Senhales hacia el sistema
		63	resul_samp: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos
		64	rdy_samp: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria
		65	ack_in: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no
		66
		67	);
		68	end joiner_samp_1;
		69
		70	architecture Behavioral of joiner_samp_1 is
		71
		72	--Registros para sincronizacion
		73	SIGNAL clk_acq_r : std_logic_vector (2 downto 0) :=(OTHERS=>'1');
		74	SIGNAL chn_bits_acq_bit0 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		75	SIGNAL chn_bits_acq_bit1 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		76	SIGNAL chn_bits_acq_bit2 : std_logic_vector (1 downto 0) :=(OTHERS=>'0');
		77
		78	--Senhales para deteccion de flancos
		79	SIGNAL clk_acq_rise : std_logic :='0';
		80
		81	--Senhal Interna de dato completo
		82	SIGNAL rdy_mem_aux: std_logic :='0';
		83
		84	--Constantes asociadas al contador de nibbles
		85	SIGNAL dbits_counter : std_logic_vector ((BITS_COUNT_SZ-1) downto 0) :=(OTHERS=>'0');
		86	CONSTANT TOP_COUNT: std_logic_vector((BITS_COUNT_SZ-1) downto 0) :="111";
		87	CONSTANT BASE_COUNT: std_logic_vector((BITS_COUNT_SZ-1) downto 0) :=(OTHERS=>'0');
		88
		89	--Senhales para almacenar resultado a siguiente etapa
		90	SIGNAL resul_mem_internal: std_logic_vector((SAMPLE_SZ-1) downto 0) :=(OTHERS=>'0');
		91	SIGNAL resul_mem_internal_aux: std_logic_vector((RESUL_NP_SZ-1) downto 0) :="0001000000000000000000000000000000000000";
		92	CONSTANT chn_id_acq: std_logic_vector((CH_COUNT_SZ-1) downto 0) := "0001";
		93
		94	--Estados de la maquina de presentacion de datos a la RAM y RAM Controller
		95	TYPE data_states IS ( idle,
		96	data_pres, data_proc
		97	);
		98	SIGNAL data_cur_state: data_states := idle;
		99	SIGNAL data_next_state: data_states := idle;
		100
		101	--Estados de la maquina de construccion de paquete
		102	TYPE pack_states IS ( idle,
		103	building
		104	);
		105	SIGNAL pack_cur_state : pack_states := idle;
		106	SIGNAL pack_next_state : pack_states := idle;
		107
		108	SIGNAL nibble_aux: STD_LOGIC_VECTOR((DBIT_SZ-1) downto 0) := (OTHERS => '0');
		109	SIGNAL samp_count: STD_LOGIC_VECTOR((SAMPLE_COUNT_SZ-1) downto 0) := (OTHERS => '0');
		110	CONSTANT TOP_SAMPLES_COUNT: std_logic_vector((SAMPLE_COUNT_SZ-1) downto 0) := "001111101000";
		111	begin
		112
		113	--Etapa de sincronizacion
		114	sync_data: PROCESS(clk_main)
		115	BEGIN
		116	IF(rising_edge(clk_main)) THEN
		117	IF(rst_bar = '0') THEN
		118	chn_bits_acq_bit0 <= (OTHERS=>'0');
		119	chn_bits_acq_bit1 <= (OTHERS=>'0');
		120	chn_bits_acq_bit2 <= (OTHERS=>'0');
		121	ELSE
		122	chn_bits_acq_bit0 <= chn_bits_acq_bit0(0) & chn_bits_acq(0);
		123	chn_bits_acq_bit1 <= chn_bits_acq_bit1(0) & chn_bits_acq(1);
		124	chn_bits_acq_bit2 <= chn_bits_acq_bit2(0) & chn_bits_acq(2);
		125	END IF;
		126	END IF;
		127	END PROCESS;
		128
		129	nibble_aux <= chn_bits_acq_bit2(1) &
		130	chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1);
		131
		132	--Etapa de deteccion de flancos
		133	edge_det: PROCESS(clk_main)
		134	BEGIN
		135	IF(rising_edge(clk_main)) THEN
		136	IF(rst_bar = '0') THEN
		137	clk_acq_r <=(OTHERS =>'1');
		138	clk_acq_rise <= '0';
		139
		140	ELSE
		141	clk_acq_r <= clk_acq_r(1 downto 0) & clk_acq;
		142	IF (clk_acq_r(2 downto 1) = "01") THEN
		143	clk_acq_rise <= '1';
		144	ELSE
		145	clk_acq_rise <= '0';
		146	END IF;
		147
		148	END IF;
		149	END IF;
		150	END PROCESS;
		151
		152	--Etapa de deteccion de cabecera y almacenamiento
		153	cambio_estados: PROCESS(clk_main)
		154	BEGIN
		155	IF (rising_edge(clk_main)) THEN
		156	IF(rst_bar = '0') THEN
		157	pack_cur_state <= idle;
		158	ELSE
		159	pack_cur_state <= pack_next_state;
		160	END IF;
		161	END IF;
		162	END PROCESS;
		163
		164	salidas_estados: PROCESS(pack_cur_state, dbits_counter,clk_acq_rise,dat_req_ch)
		165	BEGIN
		166	CASE pack_cur_state IS
		167	WHEN idle =>
		168	IF(dat_req_ch = '1') THEN
		169	pack_next_state <= building;
		170	ELSE
		171	pack_next_state <= idle;
		172	END IF;
		173	WHEN building =>
		174	IF(clk_acq_rise = '1') THEN
		175	IF (dbits_counter = TOP_COUNT) THEN
		176	pack_next_state <= idle;
		177	ELSE
		178	pack_next_state <= building;
		179	END IF;
		180	ELSE
		181	pack_next_state <= building;
		182	END IF;
		183
		184	WHEN OTHERS =>
		185	pack_next_state <= idle;
		186
		187	END CASE;
		188	END PROCESS;
		189
		190	save_bits: PROCESS(clk_main)
		191	BEGIN
		192	IF(rising_edge(clk_main)) THEN
		193	IF (rst_bar = '0') THEN
		194	dbits_counter <=(OTHERS => '0') ;
		195	resul_mem_internal <=(OTHERS => '0') ;
		196	ELSE
		197	IF (pack_cur_state = building) THEN
		198
		199	IF(dat_req_ch = '1') THEN
		200	dbits_counter <=(OTHERS => '0') ;
		201	ELSIF(clk_acq_rise = '1') THEN
		202	dbits_counter <=std_logic_vector(unsigned(dbits_counter)+1);
		203	CASE dbits_counter IS
		204	WHEN "000" =>
		205	resul_mem_internal(23 downto 21) <= nibble_aux;
		206	WHEN "001" =>
		207	resul_mem_internal(20 downto 18) <= nibble_aux;
		208	WHEN "010" =>
		209	resul_mem_internal(17 downto 15) <= nibble_aux;
		210	WHEN "011" =>
		211	resul_mem_internal(14 downto 12) <= nibble_aux;
		212	WHEN "100" =>
		213	resul_mem_internal(11 downto 9) <= nibble_aux;
		214	WHEN "101" =>
		215	resul_mem_internal(8 downto 6) <= nibble_aux;
		216	WHEN "110"=>
		217	resul_mem_internal(5 downto 3) <= nibble_aux;
		218	WHEN "111"=>
		219	resul_mem_internal(2 downto 0) <= nibble_aux;
		220	dbits_counter <=(OTHERS => '0');
		221	WHEN OTHERS =>
		222	dbits_counter <=(OTHERS => '0');
		223	END CASE;
		224	END IF;
		225	END IF;
		226	END IF;
		227	END IF;
		228	END PROCESS;
		229
		230	resul_mem_internal_aux(39 downto 36) <= chn_id_acq;
		231
		232	guardar_dato: PROCESS(clk_main)
		233	BEGIN
		234	IF (rising_edge(clk_main)) THEN
		235	IF(data_cur_state = idle) THEN
		236	IF(rdy_mem_aux = '1') THEN
		237	resul_mem_internal_aux((RESUL_NP_SZ-5)downto 0) <= --chn_id_acq &
		238	samp_count &
		239	resul_mem_internal;
		240	END IF;
		241	END IF;
		242	END IF;
		243	END PROCESS;
		244
		245	conteo_muestra: PROCESS(clk_main)
		246	BEGIN
		247	IF (rising_edge(clk_main)) THEN
		248	IF(dat_req_ch = '1') THEN
		249	IF(samp_count = TOP_SAMPLES_COUNT) THEN
		250	samp_count <= (OTHERS=>'0');
		251	ELSE
		252	samp_count <= std_logic_vector(unsigned(samp_count)+1) ;
		253	END IF;
		254	END IF;
		255	END IF;
		256	END PROCESS;
		257
		258	output_rdy_mem: PROCESS(clk_main)
		259	BEGIN
		260	IF(rising_edge(clk_main)) THEN
		261	IF (rst_bar = '0') THEN
		262	rdy_mem_aux <= '0';
		263	ELSE
		264	IF((dbits_counter = TOP_COUNT)) THEN
		265	IF((clk_acq_rise = '1')) THEN
		266	rdy_mem_aux <= '1';
		267	END IF;
		268	ELSE
		269	rdy_mem_aux <= '0';
		270	END IF;
		271	END IF;
		272	END IF;
		273	END PROCESS;
		274
		275	cambio_estados_data: PROCESS(clk_main)
		276	BEGIN
		277	IF (rising_edge(clk_main)) THEN
		278	IF(rst_bar = '0') THEN
		279	data_cur_state <= idle;
		280	ELSE
		281	data_cur_state <= data_next_state;
		282	END IF;
		283	END IF;
		284	END PROCESS;
		285
		286	salidas_estados_data: PROCESS(resul_mem_internal_aux,data_cur_state,ack_in,rdy_mem_aux)
		287	BEGIN
		288	CASE data_cur_state IS
		289	WHEN idle =>
		290	rdy_samp <= '0';
		291	resul_samp <= (OTHERS => '0');
		292	IF (rdy_mem_aux = '1') THEN
		293	data_next_state <= data_pres;
		294	ELSE
		295	data_next_state <= idle;
		296	END IF;
		297
		298	WHEN data_pres =>
		299	rdy_samp <= '1';
		300	resul_samp <= resul_mem_internal_aux;
		301	IF (ack_in = '1') THEN
		302	data_next_state <= data_proc;
		303	ELSE
		304	data_next_state <= data_pres;
		305	END IF;
		306
		307	WHEN data_proc =>
		308	rdy_samp <= '1';
		309	resul_samp <= resul_mem_internal_aux;
		310	IF (ack_in = '0') THEN --Si ya est� ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato
		311	data_next_state <= idle;
		312	ELSE
		313	data_next_state <= data_proc;
		314	END IF;
		315
		316	WHEN OTHERS =>
		317	rdy_samp <= '0';
		318	resul_samp <= (OTHERS => '0');
		319	data_next_state <= idle;
		320
		321	END CASE;
		322	END PROCESS;
		323
		324	end Behavioral;
		325

trunk/firmware/sources/Processing2017/FrontEnd_Acq/pepExtractor.prj created 10644 +5 0

			@@ -0,0 +1,5
		1	work "DCM_fwd_int.vhd"
		2	work "Data_Req_gen.vhd"
		3	work "DtoDPRAM.vhd"
		4	work "FrontEnd_Acq.vhd"
		5	work "joiner_samp.vhd"

trunk/firmware/sources/Processing2017/FrontEnd_Acq/tb_FrontEnd_Acq.vhd created 10644 +146 0

			@@ -0,0 +1,146
		1	-- TestBench Template
		2
		3	LIBRARY ieee;
		4	USE ieee.std_logic_1164.ALL;
		5	USE ieee.numeric_std.ALL;
		6
		7	ENTITY testbench IS
		8	GENERIC(
		9	DBIT_SZ: INTEGER := 3;
		10	ADDR_LENGTH: INTEGER := 12;
		11	DATAOUT_LENGTH: INTEGER := 8;
		12	CH_SZ: INTEGER :=5;
		13	NBITS_PERIOD: INTEGER :=18;
		14	NBITS_DUTY: INTEGER :=12;
		15	NBITS_PULSES: INTEGER :=10;
		16	RESUL_NP_SZ: INTEGER :=40;
		17	ID_CH_SZ: INTEGER := 4
		18
		19	);
		20	END testbench;
		21
		22	ARCHITECTURE behavior OF testbench IS
		23
		24	-- Component Declaration
		25	COMPONENT FrontEnd_Acq is
		26	GENERIC(
		27	DBIT_SZ: INTEGER := 3;
		28	ADDR_LENGTH: INTEGER := 12;
		29	DATAOUT_LENGTH: INTEGER := 8;
		30	CH_SZ: INTEGER :=5;
		31	NBITS_PERIOD: INTEGER :=18;
		32	NBITS_DUTY: INTEGER :=12;
		33	NBITS_PULSES: INTEGER :=10;
		34	RESUL_NP_SZ: INTEGER :=40;
		35	ID_CH_SZ: INTEGER := 4
		36
		37	);
		38	PORT(
		39	clk_main: IN std_logic; --Reloj principal de 60MHz
		40	pps: IN std_logic; --Senhal de sincronismo
		41	pck_rdy: OUT std_logic; --Senhal de aviso de paquete de 40 muestras por canal(200total) a la RPi
		42
		43	--Senhales de empaquetadores
		44	data_req_ch1: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		45	data_ch1: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		46	clk_acq_ch1: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		47
		48	data_req_ch2: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		49	data_ch2: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		50	clk_acq_ch2: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		51
		52	data_req_ch3: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		53	data_ch3: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		54	clk_acq_ch3: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		55
		56	data_req_ch4: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		57	data_ch4: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		58	clk_acq_ch4: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		59
		60	data_req_ch5: OUT std_logic; --Senhal de solicitud de datos al uc-ADC
		61	data_ch5: IN std_logic_vector((DBIT_SZ-1)downto 0); --Bits de datos desde el uC
		62	clk_acq_ch5: IN std_logic; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		63
		64	--DPRAM senhales de control, direccion y data
		65	--Direccion de escritura
		66	addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); --Direccion puerto A a escribir en DPRAM
		67	dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0); --Datopuerto A a escribir en DPRAM
		68	enA: OUT std_logic --Habilitacion de escritura del puerto A
		69	);
		70	end COMPONENT;
		71
		72	SIGNAL clk_main: std_logic := '0'; --Reloj principal de 60MHz
		73	SIGNAL pps: std_logic := '0'; --Senhal de sincronismo
		74	SIGNAL data_ch1: std_logic_vector((DBIT_SZ-1)downto 0) :=(OTHERS =>'0'); --Bits de datos desde el uC
		75	SIGNAL clk_acq_ch1: std_logic := '0'; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		76	SIGNAL data_ch2: std_logic_vector((DBIT_SZ-1)downto 0) :=(OTHERS =>'0'); --Bits de datos desde el uC
		77	SIGNAL clk_acq_ch2: std_logic := '0'; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		78	SIGNAL data_ch3: std_logic_vector((DBIT_SZ-1)downto 0) :=(OTHERS =>'0'); --Bits de datos desde el uC
		79	SIGNAL clk_acq_ch3: std_logic := '0'; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		80	SIGNAL data_ch4: std_logic_vector((DBIT_SZ-1)downto 0) :=(OTHERS =>'0'); --Bits de datos desde el uC
		81	SIGNAL clk_acq_ch4: std_logic := '0'; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		82	SIGNAL data_ch5: std_logic_vector((DBIT_SZ-1)downto 0) :=(OTHERS =>'0'); --Bits de datos desde el uC
		83	SIGNAL clk_acq_ch5: std_logic := '0'; --Senhal de aviso por flancos(tipo SPI) de datos a leer
		84
		85	--outputs
		86	SIGNAL pck_rdy: std_logic; --Senhal de aviso de paquete de 40 muestras por canal(200total) a la RPi
		87	SIGNAL data_req_ch1: std_logic; --Senhal de solicitud de datos al uc-ADC
		88	SIGNAL data_req_ch2: std_logic; --Senhal de solicitud de datos al uc-ADC
		89	SIGNAL data_req_ch3: std_logic; --Senhal de solicitud de datos al uc-ADC
		90	SIGNAL data_req_ch4: std_logic; --Senhal de solicitud de datos al uc-ADC
		91	SIGNAL data_req_ch5: std_logic; --Senhal de solicitud de datos al uc-ADC
		92	SIGNAL addrA: std_logic_vector((ADDR_LENGTH-1) downto 0); --Direccion puerto A a escribir en DPRAM
		93	SIGNAL dataA: std_logic_vector((DATAOUT_LENGTH-1) downto 0); --Datopuerto A a escribir en DPRAM
		94	SIGNAL enA: std_logic; --Habilitacion de escritura del puerto A
		95
		96	constant clk_main_period : time := 16.667 ns;
		97
		98	BEGIN
		99
		100	-- Component Instantiation
		101	uut: FrontEnd_Acq PORT MAP(
		102	clk_main => clk_main,
		103	pps => pps,
		104	pck_rdy => pck_rdy,
		105	data_req_ch1 => data_req_ch1,
		106	data_ch1 => data_ch1,
		107	clk_acq_ch1 => clk_acq_ch1,
		108	data_req_ch2 => data_req_ch2,
		109	data_ch2 => data_ch2,
		110	clk_acq_ch2 => clk_acq_ch2,
		111	data_req_ch3 => data_req_ch3,
		112	data_ch3 => data_ch3,
		113	clk_acq_ch3 => clk_acq_ch3,
		114	data_req_ch4 => data_req_ch4 ,
		115	data_ch4 => data_ch4,
		116	clk_acq_ch4 => clk_acq_ch4,
		117	data_req_ch5 => data_req_ch5,
		118	data_ch5 => data_ch5,
		119	clk_acq_ch5 => clk_acq_ch5,
		120	addrA => addrA,
		121	dataA => dataA,
		122	enA => enA
		123	);
		124
		125	-- Clock process definitions
		126	clk_main_process :process
		127	begin
		128	clk_main <= '0';
		129	wait for clk_main_period/2;
		130	clk_main <= '1';
		131	wait for clk_main_period/2;
		132	end process;
		133
		134	-- Test Bench Statements
		135	tb : PROCESS
		136	BEGIN
		137
		138	wait for 100 ns; -- wait until global set/reset completes
		139
		140	-- Add user defined stimulus here
		141
		142	wait; -- will wait forever
		143	END PROCESS tb;
		144	-- End Test Bench
		145
		146	END;

trunk/firmware/sources/Processing2017/FrontEnd_Acq/testbench_stx_beh.prj created 10644 +6 0

			@@ -0,0 +1,6
		1	vhdl isim_temp "joiner_samp.vhd"
		2	vhdl isim_temp "DtoDPRAM.vhd"
		3	vhdl isim_temp "DCM_fwd_int.vhd"
		4	vhdl isim_temp "Data_Req_gen.vhd"
		5	vhdl isim_temp "FrontEnd_Acq.vhd"
		6	vhdl isim_temp "tb_FrontEnd_Acq.vhd"

trunk/firmware/sources/Processing2017/FrontEnd_Acq/webtalk_pn.xml created 10644 +43 0

			@@ -0,0 +1,43
		1	<?xml version="1.0" encoding="UTF-8" ?>
		2	<document>
		3	<!--The data in this file is primarily intended for consumption by Xilinx tools.
		4	The structure and the elements are likely to change over the next few releases.
		5	This means code written to parse this file will need to be revisited each subsequent release.-->
		6	<application name="pn" timeStamp="Fri Feb 24 15:34:46 2017">
		7	<section name="Project Information" visible="false">
		8	<property name="ProjectID" value="38F2FF6F00714A1EAD1B63342807D3E9" type="project"/>
		9	<property name="ProjectIteration" value="0" type="project"/>
		10	<property name="ProjectFile" value="C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xise" type="project"/>
		11	<property name="ProjectCreationTimestamp" value="2017-02-24T09:09:37" type="project"/>
		12	</section>
		13	<section name="Project Statistics" visible="true">
		14	<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
		15	<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
		16	<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
		17	<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
		18	<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
		19	<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
		20	<property name="PROP_SelectedInstanceHierarchicalPath" value="/testbench" type="process"/>
		21	<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
		22	<property name="PROP_SynthTopFile" value="changed" type="process"/>
		23	<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
		24	<property name="PROP_UseSmartGuide" value="false" type="design"/>
		25	<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
		26	<property name="PROP_intProjectCreationTimestamp" value="2017-02-24T09:09:37" type="design"/>
		27	<property name="PROP_intWbtProjectID" value="38F2FF6F00714A1EAD1B63342807D3E9" type="design"/>
		28	<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
		29	<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
		30	<property name="PROP_selectedSimRootSourceNode_behav" value="work.testbench" type="process"/>
		31	<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
		32	<property name="PROP_AutoTop" value="true" type="design"/>
		33	<property name="PROP_DevFamily" value="Spartan6" type="design"/>
		34	<property name="PROP_DevDevice" value="xc6slx9" type="design"/>
		35	<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
		36	<property name="PROP_DevPackage" value="tqg144" type="design"/>
		37	<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
		38	<property name="PROP_DevSpeed" value="-3" type="design"/>
		39	<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
		40	<property name="FILE_VHDL" value="6" type="source"/>
		41	</section>
		42	</application>
		43	</document>

trunk/firmware/sources/Processing2017/FrontEnd_Acq/xilinxsim.ini created 10644 +1 0

			@@ -0,0 +1,1
		1	isim_temp=isim/temp

trunk/firmware/sources/Processing2017/FrontEnd_Acq/xst/work/work.vdbl created 10644 0 0

NO CONTENT: new file 10644

trunk/firmware/sources/Processing2017/FrontEnd_Acq/xst/work/work.vdbx created 10644 0 0

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