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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 17:23:06 02/16/2016
6 -- Design Name:
7 -- Module Name: DCM_fwd_int - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 library UNISIM;
30 use UNISIM.VComponents.all;
31
32 entity DCM_fwd_int is
33 PORT(
34 clk_main_io: IN std_logic;
35 c_200MHz_in: OUT std_logic
36 );
37 end DCM_fwd_int;
38
39 architecture Behavioral of DCM_fwd_int is
40 SIGNAL clk_main: std_logic;
41 SIGNAL c_16MHz: std_logic;
42
43 SIGNAL clk_fb_aux: std_logic;
44 SIGNAL clk_fb_aux_200MHz: std_logic;
45
46 SIGNAL c_16MHz_inv: std_logic;
47
48 begin
49
50
51
52 DCM_SP_inst_int : DCM_SP
53 generic map (
54 CLKDV_DIVIDE => 2.0, -- CLKDV divide value
55 -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
56 CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
57 CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
58 CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
59 CLKIN_PERIOD => 16.667, -- Input clock period specified in nS
60 CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
61 CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
62 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
63 DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
64 DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
65 DSS_MODE => "NONE", -- Unsupported - Do not change value
66 DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
67 FACTORY_JF => X"c080", -- Unsupported - Do not change value
68 PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
69 STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
70 )
71 port map (
72 CLK0 => clk_fb_aux_200MHz, -- 1-bit output: 0 degree clock output
73 CLK180 => open, -- 1-bit output: 180 degree clock output
74 CLK270 => open, -- 1-bit output: 270 degree clock output
75 CLK2X => open, -- 1-bit output: 2X clock frequency clock output
76 CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
77 CLK90 => open, -- 1-bit output: 90 degree clock output
78 CLKDV => open, -- 1-bit output: Divided clock output
79 CLKFX => c_200MHz_in, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
80 CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
81 LOCKED => open, -- 1-bit output: DCM_SP Lock Output
82 PSDONE => open, -- 1-bit output: Phase shift done output
83 STATUS => open, -- 8-bit output: DCM_SP status output
84 CLKFB => clk_fb_aux_200MHz, -- 1-bit input: Clock feedback input
85 CLKIN => clk_main_io, -- 1-bit input: Clock input
86 DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
87 PSCLK => '1', -- 1-bit input: Phase shift clock input
88 PSEN => '0', -- 1-bit input: Phase shift enable
89 PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
90 RST => '0' -- 1-bit input: Active high reset input
91 );
92
93 end Behavioral;
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:47:34 02/08/2017
6 -- Design Name:
7 -- Module Name: Data_Req_gen - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity Data_Req_gen is
33 GENERIC (
34 --CLOCKS_COUNT_1KSPS: INTEGER :=240000; --For 240 000
35 --CYCLES_COUNT_DUTY_1KSPS: INTEGER :=2400; --For 2400
36 --PULSES_COUNT_1KSPS: INTEGER :=1000; --For 1 000
37
38 NBITS_PERIOD: INTEGER :=18;
39 NBITS_DUTY: INTEGER :=12;
40 NBITS_PULSES: INTEGER :=10
41 );
42 PORT(
43 c_200MHz_in : IN std_logic;
44 reset_int : IN std_logic;
45 pps : IN std_logic;
46 data_req : OUT std_logic
47 );
48 end Data_Req_gen;
49
50 architecture Behavioral of Data_Req_gen is
51 --Constantes
52 CONSTANT LIM_COUNT_PERIOD : std_logic_vector((NBITS_PERIOD-1) downto 0) := "111010100100000000"; --240000
53 --CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_DUTY-1) downto 0) := "100101100000"; --2400
54 CONSTANT LIM_COUNT_DUTY : std_logic_vector((NBITS_PERIOD-1) downto 0) := "011101010011000000";
55 CONSTANT LIM_COUNT_PULSES : std_logic_vector((NBITS_PULSES-1) downto 0) := "1111101001"; --1000
56 --CONSTANT LIM_COUNT_PULSES : std_logic_vector((2-1) downto 0) := "11";
57 --Contadores de ciclos de reloj(count_clock) y pulsos generados(count_cycle)
58 SIGNAL count_clock : std_logic_vector((NBITS_PERIOD-1) downto 0) :="000000000000000000"; --"00 0000 0000 0000 0000"
59 SIGNAL count_pulses : std_logic_vector(9 downto 0) :="0000000000"; --"00 0000 0000"
60 --SIGNAL count_pulses : std_logic_vector(1 downto 0) :=(OTHERS =>'0'); --"00"
61 --Registro para deteccion de flanco
62 SIGNAL pps_r: std_logic_vector(1 downto 0) :="00";
63 SIGNAL pps_rising : std_logic := '0';
64 SIGNAL data_req_s: std_logic :='0';
65
66 begin
67
68 --Deteccion de flanco de pps
69 pps_bloco: PROCESS(c_200MHz_in)
70 BEGIN
71 IF (rising_edge(c_200MHz_in)) THEN
72 IF(reset_int = '0') THEN
73 pps_r <= (OTHERS=>'0');
74 ELSE
75 pps_r <= pps_r(0) & pps;
76 IF(pps_r(1 downto 0) = "01") THEN
77 pps_rising <= '1';
78 ELSE
79 pps_rising <= '0';
80 END IF;
81 END IF;
82 END IF;
83 END PROCESS;
84
85
86 out_generator: PROCESS(c_200MHz_in)
87 BEGIN
88 IF(rising_edge(c_200MHz_in)) THEN
89 IF(pps_rising = '1') THEN
90 data_req_s <= '1';
91 count_clock <= (OTHERS=>'0');
92 count_pulses <= "0000000001";
93 ELSE
94 IF(count_pulses = LIM_COUNT_PULSES) THEN
95 data_req_s<= '0';
96 ELSE
97 IF(count_clock = LIM_COUNT_PERIOD) THEN
98 --data_req<= '1';
99 count_clock <= (OTHERS=>'0');
100 count_pulses <= std_logic_vector(unsigned(count_pulses)+1);
101 ELSIF(count_clock = LIM_COUNT_DUTY) THEN
102 data_req_s<= '0';
103 count_clock <= std_logic_vector(unsigned(count_clock)+1);
104 ELSIF(count_clock = "000000000000000000" AND count_pulses /= "00") THEN
105 data_req_s<= '1';
106 count_clock <= std_logic_vector(unsigned(count_clock)+1);
107 ELSE
108 count_clock <= std_logic_vector(unsigned(count_clock)+1);
109 END IF;
110 END IF;
111 END IF;
112 END IF;
113 END PROCESS;
114
115 data_req <= data_req_s;
116 end Behavioral; No newline at end of file
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 16:24:04 02/21/2017
6 -- Design Name:
7 -- Module Name: DtoDPRAM - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity DtoDPRAM is
33 GENERIC(
34 ADDR_LENGTH: INTEGER := 12;
35 DATAOUT_LENGTH: INTEGER := 8;
36 DATAIN_LENGTH: INTEGER := 40;
37 CHAN_NUM: INTEGER := 5;
38 COUNT_BYTE_SZ: INTEGER := 3;
39 COUNT_PACK_SZ: INTEGER := 6
40
41 );
42
43 PORT(
44 --Reset general
45 rst_bar: IN std_logic;
46
47 --Reset general
48 data_req: IN std_logic;
49
50 --Entrada de reloj principal
51 clk_main: IN std_logic;
52
53 --Entradas para indicar dato preparado por leer
54 --Desde los nibble to packets
55 ch_rdy_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
56
57 --Senhal para que indica que termino con una peticion
58 --Hacia los nibble to packets
59 ch_ack_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
60
61 --Data IN
62 datach1: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
63 datach2: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
64 datach3: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
65 datach4: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
66 datach5: IN std_logic_vector((DATAIN_LENGTH-1) downto 0);
67
68 --DPRAM senhales de control, direccion y data
69 --Direccion de escritura/lectura
70 addrA: OUT std_logic_vector((ADDR_LENGTH-1) downto 0);
71 dataA: OUT std_logic_vector((DATAOUT_LENGTH-1) downto 0);
72 enA: OUT std_logic;
73 --Aviso de Paquete de 40 muestras solicitadas a los 5 canales
74 rpi_req: OUT std_logic
75
76 );
77 end DtoDPRAM;
78
79 architecture Behavioral of DtoDPRAM is
80 SIGNAL datach1_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
81 SIGNAL datach2_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
82 SIGNAL datach3_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
83 SIGNAL datach4_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
84 SIGNAL datach5_aux: std_logic_vector((DATAOUT_LENGTH-1) downto 0) := (OTHERS=>'0');
85
86 --Estados del controlador de memoria
87 --Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria
88 --espera de pedido y estados para proceder a una lectura
89 TYPE ram_cont_states IS (idle,
90
91 ------------------------------------------
92 pre_ch1, wr_ch1, end_wrt_ch_1,
93 ------------------------------------------
94 pre_ch2, wr_ch2, end_wrt_ch_2,
95 ------------------------------------------
96 pre_ch3, wr_ch3, end_wrt_ch_3,
97 ------------------------------------------
98 pre_ch4, wr_ch4, end_wrt_ch_4,
99 ------------------------------------------
100 pre_ch5, wr_ch5, end_wrt_ch_5
101
102 );
103
104 SIGNAL ram_contr_cur_state: ram_cont_states := idle;
105 SIGNAL ram_contr_next_state: ram_cont_states := idle;
106
107 ----------------------------------
108 --Estados de la atencion a ready's
109 TYPE chn_cont_states IS ( idle,
110 checking_ch1, attending_ch1,
111 checking_ch2, attending_ch2,
112 checking_ch3, attending_ch3,
113 checking_ch4, attending_ch4,
114 checking_ch5, attending_ch5
115 );
116
117 SIGNAL ch_cont_cur_state: chn_cont_states := idle;
118 SIGNAL ch_cont_next_state: chn_cont_states := idle;
119
120 SIGNAL count_ch_byte: std_logic_vector((COUNT_BYTE_SZ-1) downto 0) := (OTHERS=>'0');
121
122 --Direcciones base por canal
123 CONSTANT BASE_ADDR_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0');
124 CONSTANT BASE_ADDR_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000011001000"; --200
125 CONSTANT BASE_ADDR_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "000110010000"; --400
126 CONSTANT BASE_ADDR_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001001011000"; --600
127 CONSTANT BASE_ADDR_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "001100100000"; --800
128
129 CONSTANT BASE_BUFFER_2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "010000000000"; --1024
130
131 SIGNAL sel_buf: std_logic := '0';
132 SIGNAL count_pack: std_logic_vector((COUNT_PACK_SZ-1) downto 0) := (OTHERS => '0');
133 begin
134
135 ---------------------
136 --Estados para atencion de canales
137 ch_cont_cambio_estados: PROCESS(clk_main)
138 BEGIN
139 IF (rising_edge(clk_main)) THEN
140 IF(rst_bar = '0') THEN
141 ch_cont_cur_state <= idle;
142 ELSE
143 ch_cont_cur_state <= ch_cont_next_state;
144 END IF;
145 END IF;
146 END PROCESS;
147
148 ch_salidas_estados: PROCESS(ch_cont_cur_state,
149 ch_rdy_vector,
150 ram_contr_cur_state
151 )
152 BEGIN
153
154 CASE ch_cont_cur_state IS
155 WHEN idle =>
156 ch_cont_next_state <= checking_ch1;
157
158 WHEN checking_ch1 =>
159 IF(ch_rdy_vector(0) = '1') THEN
160 ch_cont_next_state <= attending_ch1;
161 ELSE
162 ch_cont_next_state <= checking_ch2;
163 END IF;
164
165 WHEN attending_ch1 =>
166 IF(ram_contr_cur_state = end_wrt_ch_1) THEN
167 ch_cont_next_state <= checking_ch2;
168 ELSE
169 ch_cont_next_state <= attending_ch1;
170 END IF;
171
172 WHEN checking_ch2 =>
173 IF(ch_rdy_vector(1) = '1') THEN
174 ch_cont_next_state <= attending_ch2;
175 ELSE
176 ch_cont_next_state <= checking_ch3;
177 END IF;
178
179 WHEN attending_ch2 =>
180 IF(ram_contr_cur_state = end_wrt_ch_2) THEN
181 ch_cont_next_state <= checking_ch3;
182 ELSE
183 ch_cont_next_state <= attending_ch2;
184 END IF;
185
186 WHEN checking_ch3 =>
187 IF(ch_rdy_vector(2) = '1') THEN
188 ch_cont_next_state <= attending_ch3;
189 ELSE
190 ch_cont_next_state <= checking_ch4;
191 END IF;
192
193 WHEN attending_ch3 =>
194 IF(ram_contr_cur_state = end_wrt_ch_3) THEN
195 ch_cont_next_state <= checking_ch4;
196 ELSE
197 ch_cont_next_state <= attending_ch3;
198 END IF;
199
200 WHEN checking_ch4 =>
201 IF(ch_rdy_vector(3) = '1') THEN
202 ch_cont_next_state <= attending_ch4;
203 ELSE
204 ch_cont_next_state <= checking_ch5;
205 END IF;
206
207 WHEN attending_ch4 =>
208 IF(ram_contr_cur_state = end_wrt_ch_4) THEN
209 ch_cont_next_state <= checking_ch5;
210 ELSE
211 ch_cont_next_state <= attending_ch4;
212 END IF;
213
214 WHEN checking_ch5 =>
215 IF(ch_rdy_vector(4) = '1') THEN
216 ch_cont_next_state <= attending_ch5;
217 ELSE
218 ch_cont_next_state <= checking_ch1;
219 END IF;
220
221 WHEN attending_ch5 =>
222 IF(ram_contr_cur_state = end_wrt_ch_5) THEN
223 ch_cont_next_state <= checking_ch1;
224 ELSE
225 ch_cont_next_state <= attending_ch5;
226 END IF;
227
228 WHEN OTHERS =>
229
230 ch_cont_next_state <= idle;
231
232 END CASE;
233 END PROCESS;
234
235 --------------------------------------------------
236 --Estados de m�quina principal para control de RAM
237
238 ctrl_cambio_estados: PROCESS(clk_main)
239 BEGIN
240 IF (rising_edge(clk_main)) THEN
241 IF(rst_bar = '0') THEN
242 ram_contr_cur_state <= idle;
243 ELSE
244 ram_contr_cur_state <= ram_contr_next_state;
245 END IF;
246 END IF;
247 END PROCESS;
248
249 --Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set s�.
250 ctrl_salidas_estados: PROCESS(ram_contr_cur_state, ch_cont_cur_state,
251 count_pack, count_ch_byte, sel_buf,
252 datach1_aux, datach2_aux, datach3_aux, datach4_aux, datach5_aux
253 )
254 BEGIN
255 CASE ram_contr_cur_state IS
256 WHEN idle =>
257 enA <= '0';
258 dataA <= (OTHERS=>'0');
259 addrA <= (OTHERS=>'0');
260 ch_ack_vector <= (OTHERS=>'0');
261 IF (ch_cont_cur_state=attending_ch1) THEN
262 ram_contr_next_state <= pre_ch1;
263 ELSIF (ch_cont_cur_state=attending_ch2) THEN
264 ram_contr_next_state <= pre_ch2;
265 ELSIF (ch_cont_cur_state=attending_ch3) THEN
266 ram_contr_next_state <= pre_ch3;
267 ELSIF (ch_cont_cur_state=attending_ch4) THEN
268 ram_contr_next_state <= pre_ch4;
269 ELSIF (ch_cont_cur_state=attending_ch5) THEN
270 ram_contr_next_state <= pre_ch5;
271 ELSE
272 ram_contr_next_state <= idle;
273 END IF;
274
275 WHEN pre_ch1 =>
276 enA <= '0';
277 dataA <= datach1_aux;
278 ch_ack_vector <= "00000";
279 IF ( sel_buf = '1' ) THEN
280 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
281 ELSE
282 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
283 END IF;
284 ram_contr_next_state <= wr_ch1;
285
286 WHEN wr_ch1 =>
287 enA <= '1';
288 dataA <= datach1_aux;
289 ch_ack_vector <= "00000";
290 IF ( sel_buf = '1' ) THEN
291 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
292 ELSE
293 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
294 END IF;
295 ram_contr_next_state <= end_wrt_ch_1;
296
297 WHEN end_wrt_ch_1 =>
298 enA <= '0';
299 dataA <= datach1_aux;
300 ch_ack_vector <= "00001";
301 IF ( sel_buf = '1' ) THEN
302 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
303 ELSE
304 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH1) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
305 END IF;
306 IF (count_ch_byte = "100") THEN
307 ram_contr_next_state <= idle;
308 ELSE
309 ram_contr_next_state <= pre_ch1;
310 END IF;
311
312 ---------------------------------------
313
314 WHEN pre_ch2 =>
315 enA <= '0';
316 dataA <= datach2_aux;
317 ch_ack_vector <= "00000";
318 IF ( sel_buf = '1' ) THEN
319 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
320 ELSE
321 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
322 END IF;
323 ram_contr_next_state <= wr_ch2;
324
325 WHEN wr_ch2 =>
326 enA <= '1';
327 dataA <= datach2_aux;
328 ch_ack_vector <= "00000";
329 IF ( sel_buf = '1' ) THEN
330 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
331 ELSE
332 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
333 END IF;
334 ram_contr_next_state <= end_wrt_ch_2;
335
336 WHEN end_wrt_ch_2 =>
337 enA <= '0';
338 dataA <= datach2_aux;
339 ch_ack_vector <= "00010";
340 IF ( sel_buf = '1' ) THEN
341 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
342 ELSE
343 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
344 END IF;
345 IF (count_ch_byte = "100") THEN
346 ram_contr_next_state <= idle;
347 ELSE
348 ram_contr_next_state <= pre_ch2;
349 END IF;
350
351 ------------------------------
352
353 WHEN pre_ch3 =>
354 enA <= '0';
355 dataA <= datach3_aux;
356 ch_ack_vector <= "00000";
357 IF ( sel_buf = '1' ) THEN
358 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
359 ELSE
360 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
361 END IF;
362 ram_contr_next_state <= wr_ch3;
363
364 WHEN wr_ch3 =>
365 enA <= '1';
366 dataA <= datach3_aux;
367 ch_ack_vector <= "00000";
368 IF ( sel_buf = '1' ) THEN
369 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
370 ELSE
371 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
372 END IF;
373 ram_contr_next_state <= end_wrt_ch_3;
374
375 WHEN end_wrt_ch_3 =>
376 enA <= '0';
377 dataA <= datach3_aux;
378 ch_ack_vector <= "00100";
379 IF ( sel_buf = '1' ) THEN
380 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
381 ELSE
382 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH3) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
383 END IF;
384 IF (count_ch_byte = "100") THEN
385 ram_contr_next_state <= idle;
386 ELSE
387 ram_contr_next_state <= pre_ch3;
388 END IF;
389
390 --------------------------------------------------
391
392 WHEN pre_ch4 =>
393 enA <= '0';
394 dataA <= datach4_aux;
395 ch_ack_vector <= "00000";
396 IF ( sel_buf = '1' ) THEN
397 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
398 ELSE
399 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
400 END IF;
401 ram_contr_next_state <= wr_ch4;
402
403 WHEN wr_ch4 =>
404 enA <= '1';
405 dataA <= datach4_aux;
406 ch_ack_vector <= "00000";
407 IF ( sel_buf = '1' ) THEN
408 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
409 ELSE
410 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
411 END IF;
412 ram_contr_next_state <= end_wrt_ch_4;
413
414 WHEN end_wrt_ch_4 =>
415 enA <= '0';
416 dataA <= datach4_aux;
417 ch_ack_vector <= "01000";
418 IF ( sel_buf = '1' ) THEN
419 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
420 ELSE
421 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH4) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
422 END IF;
423 IF (count_ch_byte = "100") THEN
424 ram_contr_next_state <= idle;
425 ELSE
426 ram_contr_next_state <= pre_ch4;
427 END IF;
428
429 ------------------------------------------
430
431 WHEN pre_ch5 =>
432 enA <= '0';
433 dataA <= datach5_aux;
434 ch_ack_vector <= "00000";
435 IF ( sel_buf = '1' ) THEN
436 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
437 ELSE
438 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
439 END IF;
440 ram_contr_next_state <= wr_ch5;
441
442 WHEN wr_ch5 =>
443 enA <= '1';
444 dataA <= datach5_aux;
445 ch_ack_vector <= "00000";
446 IF ( sel_buf = '1' ) THEN
447 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
448 ELSE
449 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
450 END IF;
451 ram_contr_next_state <= end_wrt_ch_5;
452
453 WHEN end_wrt_ch_5 =>
454 enA <= '0';
455 dataA <= datach5_aux;
456 ch_ack_vector <= "10000";
457 IF ( sel_buf = '1' ) THEN
458 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(BASE_BUFFER_2) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
459 ELSE
460 addrA <= std_logic_vector(unsigned(BASE_ADDR_CH5) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_pack) + unsigned(count_ch_byte));
461 END IF;
462 IF (count_ch_byte = "100") THEN
463 ram_contr_next_state <= idle;
464 ELSE
465 ram_contr_next_state <= pre_ch5;
466 END IF;
467
468
469 WHEN OTHERS =>
470
471 enA <= '0';
472 dataA <= (OTHERS=>'0');
473 addrA <= (OTHERS=>'0');
474 ch_ack_vector <= (OTHERS=>'0');
475 ram_contr_next_state <= idle;
476
477 END CASE;
478 END PROCESS;
479
480 --Contador de paquetes
481 wr_bytes_dpram: PROCESS(clk_main)
482 BEGIN
483 IF(rising_edge(clk_main)) THEN
484 IF (rst_bar = '0') THEN
485 --count_req <= (OTHERS => '0');
486 count_pack <= (OTHERS => '1');
487 ELSE
488 --IF (data_req = '1') THEN
489 -- count_req <= std_logic_vector(unsigned(count_req) + 1);
490 --END IF;
491
492 IF (data_req = '1') THEN
493 IF (count_pack = "100111") THEN
494 count_pack <= (OTHERS => '0');
495 sel_buf <= NOT(sel_buf);
496 rpi_req <= '1';
497 ELSE
498 count_pack <= std_logic_vector(unsigned(count_pack) + 1);
499 rpi_req <= '0';
500 END IF;
501 ELSE
502 rpi_req <= '0';
503 END IF;
504
505 END IF;
506 END IF;
507 END PROCESS;
508
509
510 --Contador de bytes
511 count_ch_bytes: PROCESS(clk_main)
512 BEGIN
513 IF(rising_edge(clk_main)) THEN
514 IF (rst_bar = '0') THEN
515 count_ch_byte <= (OTHERS => '0');
516 ELSE
517 IF (ram_contr_cur_state = idle) THEN
518 count_ch_byte <= (OTHERS => '0');
519 ELSE
520 IF (ram_contr_cur_state = end_wrt_ch_1 OR
521 ram_contr_cur_state = end_wrt_ch_2 OR
522 ram_contr_cur_state = end_wrt_ch_3 OR
523 ram_contr_cur_state = end_wrt_ch_4 OR
524 ram_contr_cur_state = end_wrt_ch_5
525 ) THEN
526 count_ch_byte <= std_logic_vector(unsigned(count_ch_byte) + 1);
527 END IF;
528 END IF;
529 END IF;
530 END IF;
531 END PROCESS;
532
533 -----------------------------------------
534 datach1_bytes: PROCESS(clk_main)
535 BEGIN
536 IF (rising_edge(clk_main))THEN
537 IF (rst_bar = '0') THEN
538 datach1_aux <= (OTHERS =>'0');
539 ELSE
540 CASE count_ch_byte IS
541 WHEN "000" =>
542 datach1_aux <= datach1(39 downto 32);
543 WHEN "001" =>
544 datach1_aux <= datach1(31 downto 24);
545 WHEN "010" =>
546 datach1_aux <= datach1(23 downto 16);
547 WHEN "011" =>
548 datach1_aux <= datach1(15 downto 8);
549 WHEN "100" =>
550 datach1_aux <= datach1(7 downto 0);
551 WHEN OTHERS =>
552 datach1_aux <= (OTHERS =>'0');
553 END CASE;
554 END IF;
555 END IF;
556 END PROCESS;
557
558 datach2_bytes: PROCESS(clk_main)
559 BEGIN
560 IF (rising_edge(clk_main))THEN
561 IF (rst_bar = '0') THEN
562 datach2_aux <= (OTHERS =>'0');
563 ELSE
564 CASE count_ch_byte IS
565 WHEN "000" =>
566 datach2_aux <= datach2(39 downto 32);
567 WHEN "001" =>
568 datach2_aux <= datach2(31 downto 24);
569 WHEN "010" =>
570 datach2_aux <= datach2(23 downto 16);
571 WHEN "011" =>
572 datach2_aux <= datach2(15 downto 8);
573 WHEN "100" =>
574 datach2_aux <= datach2(7 downto 0);
575 WHEN OTHERS =>
576 datach2_aux <= (OTHERS =>'0');
577 END CASE;
578 END IF;
579 END IF;
580 END PROCESS;
581
582 datach3_bytes: PROCESS(clk_main)
583 BEGIN
584 IF (rising_edge(clk_main))THEN
585 IF (rst_bar = '0') THEN
586 datach3_aux <= (OTHERS =>'0');
587 ELSE
588 CASE count_ch_byte IS
589 WHEN "000" =>
590 datach3_aux <= datach3(39 downto 32);
591 WHEN "001" =>
592 datach3_aux <= datach3(31 downto 24);
593 WHEN "010" =>
594 datach3_aux <= datach3(23 downto 16);
595 WHEN "011" =>
596 datach3_aux <= datach3(15 downto 8);
597 WHEN "100" =>
598 datach3_aux <= datach3(7 downto 0);
599 WHEN OTHERS =>
600 datach3_aux <= (OTHERS =>'0');
601 END CASE;
602 END IF;
603 END IF;
604 END PROCESS;
605
606 datach4_bytes: PROCESS(clk_main)
607 BEGIN
608 IF (rising_edge(clk_main))THEN
609 IF (rst_bar = '0') THEN
610 datach4_aux <= (OTHERS =>'0');
611 ELSE
612 CASE count_ch_byte IS
613 WHEN "000" =>
614 datach4_aux <= datach4(39 downto 32);
615 WHEN "001" =>
616 datach4_aux <= datach4(31 downto 24);
617 WHEN "010" =>
618 datach4_aux <= datach4(23 downto 16);
619 WHEN "011" =>
620 datach4_aux <= datach4(15 downto 8);
621 WHEN "100" =>
622 datach4_aux <= datach4(7 downto 0);
623 WHEN OTHERS =>
624 datach4_aux <= (OTHERS =>'0');
625 END CASE;
626 END IF;
627 END IF;
628 END PROCESS;
629
630 datach5_bytes: PROCESS(clk_main)
631 BEGIN
632 IF (rising_edge(clk_main))THEN
633 IF (rst_bar = '0') THEN
634 datach5_aux <= (OTHERS =>'0');
635 ELSE
636 CASE count_ch_byte IS
637 WHEN "000" =>
638 datach5_aux <= datach5(39 downto 32);
639 WHEN "001" =>
640 datach5_aux <= datach5(31 downto 24);
641 WHEN "010" =>
642 datach5_aux <= datach5(23 downto 16);
643 WHEN "011" =>
644 datach5_aux <= datach5(15 downto 8);
645 WHEN "100" =>
646 datach5_aux <= datach5(7 downto 0);
647 WHEN OTHERS =>
648 datach5_aux <= (OTHERS =>'0');
649 END CASE;
650 END IF;
651 END IF;
652 END PROCESS;
653
654
655 end Behavioral;
656
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@@ -0,0 +1,13
1 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
2 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
3 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
4 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
5 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
6 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
7 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
8 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
9 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
10 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
11 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
12 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
13 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/FrontEnd_Acq/FrontEnd_Acq.syr"
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@@ -0,0 +1,118
1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2 <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4 <!-- -->
5
6 <!-- For tool use only. Do not edit. -->
7
8 <!-- -->
9
10 <!-- ProjectNavigator created generated project file. -->
11
12 <!-- For use in tracking generated file and other information -->
13
14 <!-- allowing preservation of process status. -->
15
16 <!-- -->
17
18 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
19
20 <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21
22 <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="FrontEnd_Acq.xise"/>
23
24 <files xmlns="http://www.xilinx.com/XMLSchema">
25 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="FrontEnd_Acq.cmd_log"/>
26 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="FrontEnd_Acq.lso"/>
27 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="FrontEnd_Acq.ngc"/>
28 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="FrontEnd_Acq.ngr"/>
29 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="FrontEnd_Acq.prj"/>
30 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="FrontEnd_Acq.stx"/>
31 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="FrontEnd_Acq.syr"/>
32 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="FrontEnd_Acq.xst"/>
33 <file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_envsettings.html"/>
34 <file xil_pn:fileType="FILE_HTML" xil_pn:name="FrontEnd_Acq_summary.html"/>
35 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="FrontEnd_Acq_xst.xrpt"/>
36 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
37 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
38 <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="testbench_stx_beh.prj"/>
39 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
40 <file xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
41 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
42 </files>
43
44 <transforms xmlns="http://www.xilinx.com/XMLSchema">
45 <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1487967396">
46 <status xil_pn:value="SuccessfullyRun"/>
47 <status xil_pn:value="ReadyToRun"/>
48 </transform>
49 <transform xil_pn:end_ts="1487969891" xil_pn:in_ck="3689099153043928551" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1487969891">
50 <status xil_pn:value="SuccessfullyRun"/>
51 <status xil_pn:value="ReadyToRun"/>
52 <outfile xil_pn:name="DCM_fwd_int.vhd"/>
53 <outfile xil_pn:name="Data_Req_gen.vhd"/>
54 <outfile xil_pn:name="DtoDPRAM.vhd"/>
55 <outfile xil_pn:name="FrontEnd_Acq.vhd"/>
56 <outfile xil_pn:name="joiner_samp.vhd"/>
57 <outfile xil_pn:name="tb_FrontEnd_Acq.vhd"/>
58 </transform>
59 <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-9044832904953873877" xil_pn:start_ts="1487967396">
60 <status xil_pn:value="SuccessfullyRun"/>
61 <status xil_pn:value="ReadyToRun"/>
62 <status xil_pn:value="OutOfDateForProperties"/>
63 </transform>
64 <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-2793873426928892759" xil_pn:start_ts="1487967396">
65 <status xil_pn:value="SuccessfullyRun"/>
66 <status xil_pn:value="ReadyToRun"/>
67 <status xil_pn:value="OutOfDateForProperties"/>
68 </transform>
69 <transform xil_pn:end_ts="1487967396" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487967396">
70 <status xil_pn:value="SuccessfullyRun"/>
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72 </transform>
73 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1487953541">
74 <status xil_pn:value="SuccessfullyRun"/>
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76 </transform>
77 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-3768900233016590667" xil_pn:start_ts="1487953541">
78 <status xil_pn:value="SuccessfullyRun"/>
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80 </transform>
81 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="8806113302358300741" xil_pn:start_ts="1487953541">
82 <status xil_pn:value="SuccessfullyRun"/>
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86 <status xil_pn:value="SuccessfullyRun"/>
87 <status xil_pn:value="ReadyToRun"/>
88 </transform>
89 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="7509621194074287415" xil_pn:start_ts="1487953541">
90 <status xil_pn:value="SuccessfullyRun"/>
91 <status xil_pn:value="ReadyToRun"/>
92 </transform>
93 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1487953541">
94 <status xil_pn:value="SuccessfullyRun"/>
95 <status xil_pn:value="ReadyToRun"/>
96 </transform>
97 <transform xil_pn:end_ts="1487953541" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="3361842800594627215" xil_pn:start_ts="1487953541">
98 <status xil_pn:value="SuccessfullyRun"/>
99 <status xil_pn:value="ReadyToRun"/>
100 </transform>
101 <transform xil_pn:end_ts="1487968498" xil_pn:in_ck="-1660920062075515250" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="2407589981579732958" xil_pn:start_ts="1487968485">
102 <status xil_pn:value="SuccessfullyRun"/>
103 <status xil_pn:value="ReadyToRun"/>
104 <outfile xil_pn:name="FrontEnd_Acq.lso"/>
105 <outfile xil_pn:name="FrontEnd_Acq.ngc"/>
106 <outfile xil_pn:name="FrontEnd_Acq.ngr"/>
107 <outfile xil_pn:name="FrontEnd_Acq.prj"/>
108 <outfile xil_pn:name="FrontEnd_Acq.stx"/>
109 <outfile xil_pn:name="FrontEnd_Acq.syr"/>
110 <outfile xil_pn:name="FrontEnd_Acq.xst"/>
111 <outfile xil_pn:name="FrontEnd_Acq_xst.xrpt"/>
112 <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
113 <outfile xil_pn:name="webtalk_pn.xml"/>
114 <outfile xil_pn:name="xst"/>
115 </transform>
116 </transforms>
117
118 </generated_project>
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@@ -0,0 +1,1
1 work
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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