##// END OF EJS Templates
jro_hard » gen_acq
RSS
Versiones de pruebas de integracion OK
lgonzales -
r223:224
parent child
Show More

The requested changes are too big and content was truncated. Show full diff

Show file before | Show file after | Hide comments
@@ -0,0 +1,20
1 
2 Microsoft Visual Studio Solution File, Format Version 11.00
3 # Atmel Studio Solution File, Format Version 11.00
4 Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_v01", "ADCSPI_v01\ADCSPI_v01.cproj", "{7024C456-574A-4FD1-BAA2-1F09B3D11566}"
5 EndProject
6 Global
7 GlobalSection(SolutionConfigurationPlatforms) = preSolution
8 Debug|AVR = Debug|AVR
9 Release|AVR = Release|AVR
10 EndGlobalSection
11 GlobalSection(ProjectConfigurationPlatforms) = postSolution
12 {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Debug|AVR.ActiveCfg = Debug|AVR
13 {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Debug|AVR.Build.0 = Debug|AVR
14 {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Release|AVR.ActiveCfg = Release|AVR
15 {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Release|AVR.Build.0 = Release|AVR
16 EndGlobalSection
17 GlobalSection(SolutionProperties) = preSolution
18 HideSolutionNode = FALSE
19 EndGlobalSection
20 EndGlobal
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
Show file before | Show file after | Hide comments
@@ -0,0 +1,147
1 <?xml version="1.0" encoding="utf-8"?>
2 <Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
3 <PropertyGroup>
4 <SchemaVersion>2.0</SchemaVersion>
5 <ProjectVersion>6.2</ProjectVersion>
6 <ToolchainName>com.Atmel.AVRGCC8.C</ToolchainName>
7 <ProjectGuid>{7024c456-574a-4fd1-baa2-1f09b3d11566}</ProjectGuid>
8 <avrdevice>ATxmega32D4</avrdevice>
9 <avrdeviceseries>none</avrdeviceseries>
10 <OutputType>Executable</OutputType>
11 <Language>C</Language>
12 <OutputFileName>$(MSBuildProjectName)</OutputFileName>
13 <OutputFileExtension>.elf</OutputFileExtension>
14 <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory>
15 <AssemblyName>ADCSPI_v01</AssemblyName>
16 <Name>ADCSPI_v01</Name>
17 <RootNamespace>ADCSPI_v01</RootNamespace>
18 <ToolchainFlavour>Native</ToolchainFlavour>
19 <KeepTimersRunning>true</KeepTimersRunning>
20 <OverrideVtor>false</OverrideVtor>
21 <CacheFlash>true</CacheFlash>
22 <ProgFlashFromRam>true</ProgFlashFromRam>
23 <RamSnippetAddress>0x20000000</RamSnippetAddress>
24 <UncachedRange />
25 <preserveEEPROM>true</preserveEEPROM>
26 <OverrideVtorValue>exception_table</OverrideVtorValue>
27 <BootSegment>2</BootSegment>
28 <eraseonlaunchrule>0</eraseonlaunchrule>
29 <AsfFrameworkConfig>
30 <framework-data xmlns="">
31 <options />
32 <configurations />
33 <files />
34 <documentation help="" />
35 <offline-documentation help="" />
36 <dependencies>
37 <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.28.1" />
38 </dependencies>
39 </framework-data>
40 </AsfFrameworkConfig>
41 <avrtool>com.atmel.avrdbg.tool.atmelice</avrtool>
42 <avrtoolinterface>PDI</avrtoolinterface>
43 <com_atmel_avrdbg_tool_atmelice>
44 <ToolOptions>
45 <InterfaceProperties>
46 <PdiClock>4000000</PdiClock>
47 </InterfaceProperties>
48 <InterfaceName>PDI</InterfaceName>
49 </ToolOptions>
50 <ToolType>com.atmel.avrdbg.tool.atmelice</ToolType>
51 <ToolNumber>J41800030896</ToolNumber>
52 <ToolName>Atmel-ICE</ToolName>
53 </com_atmel_avrdbg_tool_atmelice>
54 </PropertyGroup>
55 <PropertyGroup Condition=" '$(Configuration)' == 'Release' ">
56 <ToolchainSettings>
57 <AvrGcc>
58 <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex>
59 <avrgcc.common.outputfiles.lss>True</avrgcc.common.outputfiles.lss>
60 <avrgcc.common.outputfiles.eep>True</avrgcc.common.outputfiles.eep>
61 <avrgcc.common.outputfiles.srec>True</avrgcc.common.outputfiles.srec>
62 <avrgcc.common.outputfiles.usersignatures>False</avrgcc.common.outputfiles.usersignatures>
63 <avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>
64 <avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>
65 <avrgcc.compiler.symbols.DefSymbols>
66 <ListValues>
67 <Value>NDEBUG</Value>
68 </ListValues>
69 </avrgcc.compiler.symbols.DefSymbols>
70 <avrgcc.compiler.optimization.level>Optimize for size (-Os)</avrgcc.compiler.optimization.level>
71 <avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers>
72 <avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum>
73 <avrgcc.compiler.warnings.AllWarnings>True</avrgcc.compiler.warnings.AllWarnings>
74 <avrgcc.linker.libraries.Libraries>
75 <ListValues>
76 <Value>libm</Value>
77 </ListValues>
78 </avrgcc.linker.libraries.Libraries>
79 </AvrGcc>
80 </ToolchainSettings>
81 </PropertyGroup>
82 <PropertyGroup Condition=" '$(Configuration)' == 'Debug' ">
83 <ToolchainSettings>
84 <AvrGcc>
85 <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex>
86 <avrgcc.common.outputfiles.lss>True</avrgcc.common.outputfiles.lss>
87 <avrgcc.common.outputfiles.eep>True</avrgcc.common.outputfiles.eep>
88 <avrgcc.common.outputfiles.srec>True</avrgcc.common.outputfiles.srec>
89 <avrgcc.common.outputfiles.usersignatures>False</avrgcc.common.outputfiles.usersignatures>
90 <avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>
91 <avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>
92 <avrgcc.compiler.symbols.DefSymbols>
93 <ListValues>
94 <Value>DEBUG</Value>
95 </ListValues>
96 </avrgcc.compiler.symbols.DefSymbols>
97 <avrgcc.compiler.optimization.level>Optimize (-O1)</avrgcc.compiler.optimization.level>
98 <avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers>
99 <avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum>
100 <avrgcc.compiler.optimization.DebugLevel>Default (-g2)</avrgcc.compiler.optimization.DebugLevel>
101 <avrgcc.compiler.warnings.AllWarnings>True</avrgcc.compiler.warnings.AllWarnings>
102 <avrgcc.linker.libraries.Libraries>
103 <ListValues>
104 <Value>libm</Value>
105 </ListValues>
106 </avrgcc.linker.libraries.Libraries>
107 <avrgcc.assembler.debugging.DebugLevel>Default (-Wa,-g)</avrgcc.assembler.debugging.DebugLevel>
108 </AvrGcc>
109 </ToolchainSettings>
110 </PropertyGroup>
111 <ItemGroup>
112 <Compile Include="ADC_7176_2.c">
113 <SubType>compile</SubType>
114 </Compile>
115 <Compile Include="ADC_7176_2.h">
116 <SubType>compile</SubType>
117 </Compile>
118 <Compile Include="commSPI_ADC.h">
119 <SubType>compile</SubType>
120 </Compile>
121 <Compile Include="main.c">
122 <SubType>compile</SubType>
123 </Compile>
124 <Compile Include="commSPI_ADC.c">
125 <SubType>compile</SubType>
126 </Compile>
127 <Compile Include="fpga_port.c">
128 <SubType>compile</SubType>
129 </Compile>
130 <Compile Include="fpga_port.h">
131 <SubType>compile</SubType>
132 </Compile>
133 <Compile Include="Ports.c">
134 <SubType>compile</SubType>
135 </Compile>
136 <Compile Include="Ports.h">
137 <SubType>compile</SubType>
138 </Compile>
139 <Compile Include="sys_clock.c">
140 <SubType>compile</SubType>
141 </Compile>
142 <Compile Include="sys_clock.h">
143 <SubType>compile</SubType>
144 </Compile>
145 </ItemGroup>
146 <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" />
147 </Project> No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,257
1 /*
2 * ADC_7176_2.c
3 *
4 * Created: 26/04/16 11:46:48
5 * Author: Francisco
6 */
7
8 /*!
9 * \fn test_adc
10 * \brief Lectura de ID del adc
11 *
12 * Lectura esperada: 0x0C94
13 *
14 * Esta funci�n tiene como fin probar la comunicaci�n on el ADC
15 *
16 #define ADC_WENbar_bm (1<<7)
17 #define ADC_RWbar_bm (1<<6)
18 #define ADC_ADDR_READ_ID 0x07
19 * \
20 */
21
22 #define F_CPU 32000000UL
23 #include <avr/io.h>
24 #include "ADC_7176_2.h"
25 #include <util/delay.h>
26
27 inline uint16_t test_adc(void){
28 uint16_t aux;
29 PORTSPI.OUTCLR = SPI_SS_bm;
30 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
31 aux = adcport_tranceiv(0);
32 aux = (aux << 8) | adcport_tranceiv(0);
33 PORTSPI.OUTSET = SPI_SS_bm;
34 return aux;
35 }
36
37 inline void test_adc_2(uint8_t* dato){
38 PORTSPI.OUTCLR = SPI_SS_bm;
39 adcport_read_data(dato,ADC_DATASZ);
40 PORTSPI.OUTSET = SPI_SS_bm;
41 }
42
43 inline uint16_t test_adc_3(void){
44 uint16_t aux;
45 PORTSPI.OUTCLR = SPI_SS_bm;
46 adcport_tranceiv((ADC_FILTCON0|ADC_RWbar_bm)&(~ADC_WENbar_bm));
47 aux = adcport_tranceiv(0);
48 aux = (aux << 8) | adcport_tranceiv(0);
49 PORTSPI.OUTSET = SPI_SS_bm;
50 return aux;
51 }
52
53 /*!
54 * \fn adcport_tranceiv
55 * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y
56 * el microcontrolador.
57 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
58 * transmision genera clock en el pin "sclk"
59 * \param El dato a transmitir
60 * \return El dato leido del ADC
61 */
62 inline uint8_t adcport_tranceiv(uint8_t data){
63 //
64 SPIC.DATA = data;
65
66 //Wait until transmission complete
67 while( !(SPIC.STATUS & SPI_IF_bm));
68
69 // Return received data
70
71 return SPIC.DATA;
72 }
73
74 /*!
75 * \fn adcport_readdata
76 * \brief Realiza la lectura de datos en modo de conversi�n continua
77 * el microcontrolador.
78 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
79 * transmision genera clock en el pin "sclk"
80 * \param La direcci�n del puntero a dato
81 * \return Ninguno s�lo se llena el puntero al dato
82 */
83 inline void adcport_read_data(uint8_t* dato,int j)
84 {
85
86 //Env�o del comando de lectura de datos 0x44
87 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
88
89 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
90
91 // Save received data
92 for(int i=0; i<j ; i++)
93 dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1)
94 //Si se desease almacenar el dato de byte menos significativo a m�s signficativo: dato[j-i-1] = adcport_tranceiv(0);
95 }
96
97 inline void adcport_read_data_contread(uint8_t* dato,int j)
98 {
99
100 //Env�o del comando de lectura de datos 0x44
101 //adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
102
103 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
104
105 // Save received data
106 for(int i=0; i<j ; i++)
107 dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1)
108 //Si se desease almacenar el dato de byte menos significativo a m�s signficativo: dato[j-i-1] = adcport_tranceiv(0);
109 }
110
111 inline void adcport_read_data_synconv(uint8_t* dato,int j)
112 {
113
114 //Env�o del comando de lectura de datos 0x44
115 adcport_tranceiv((ADC_MODREG)&(~ADC_WENbar_bm)&(~ADC_RWbar_bm));
116 adcport_tranceiv((ADC_REFEN_bm<<ADC_REFOUT_bp)|(ADC_SINGLECONV_EN_bm<<ADC_SYNCYC_bp)); //0b10000000
117 adcport_tranceiv(ADC_SINGLECONV<<ADC_MODECONV_bp); //0b00010000
118
119 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
120
121 // Save received data
122 for(int i=0; i<j ; i++)
123 dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1)
124 //Si se desease almacenar el dato de byte menos significativo a m�s signficativo: dato[j-i-1] = adcport_tranceiv(0);
125 }
126
127 void config_adc(void)
128 {
129 PORTSPI.OUTCLR = SPI_SS_bm;
130 adcport_write_reset();
131 PORTSPI.OUTSET = SPI_SS_bm;
132
133 _delay_us(300);
134
135 PORTSPI.OUTCLR = SPI_SS_bm;
136 adcport_write_adcmode();
137 //PORTSPI.OUTSET = SPI_SS_bm;
138
139 //PORTSPI.OUTCLR = SPI_SS_bm;
140 adcport_write_interfmode();
141 //PORTSPI.OUTSET = SPI_SS_bm;
142
143 //PORTSPI.OUTCLR = SPI_SS_bm;
144 adcport_write_filtcon0();
145 //PORTSPI.OUTSET = SPI_SS_bm;
146
147 //PORTSPI.OUTCLR = SPI_SS_bm;
148 adcport_write_setupcon0();
149 //PORTSPI.OUTSET = SPI_SS_bm;
150
151 //PORTSPI.OUTCLR = SPI_SS_bm;
152 adcport_write_chmapreg0();
153 //PORTSPI.OUTSET = SPI_SS_bm;
154
155 //PORTSPI.OUTCLR = SPI_SS_bm;
156 adcport_write_chmapreg1();
157 //PORTSPI.OUTSET = SPI_SS_bm;
158
159 //PORTSPI.OUTCLR = SPI_SS_bm;
160 adcport_write_chmapreg2();
161 //PORTSPI.OUTSET = SPI_SS_bm;
162
163 //PORTSPI.OUTCLR = SPI_SS_bm;
164 adcport_write_chmapreg3();
165 PORTSPI.OUTSET = SPI_SS_bm;
166
167 }
168
169 void adcport_write_adcmode(void)
170 {
171 adcport_tranceiv((ADC_MODREG) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
172 adcport_tranceiv((ADC_REFEN_bm<<ADC_REFOUT_bp)|(ADC_SINGLECONV_NEN_bm<<ADC_SYNCYC_bp));
173 adcport_tranceiv(ADC_CONTCONV<<ADC_MODECONV_bp);
174 }
175
176 void adcport_write_adcmode_2(void)
177 {
178 PORTSPI.OUTCLR = SPI_SS_bm;
179 adcport_tranceiv((ADC_MODREG) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
180 adcport_tranceiv((ADC_REFEN_bm<<ADC_REFOUT_bp)|(ADC_SINGLECONV_EN_bm<<ADC_SYNCYC_bp));
181 adcport_tranceiv(ADC_CONTCONV<<ADC_MODECONV_bp);
182 PORTSPI.OUTSET = SPI_SS_bm;
183 }
184
185 void adcport_write_filtcon0(void)
186 {
187 adcport_tranceiv((ADC_FILTCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
188 adcport_tranceiv(0);
189 adcport_tranceiv((ADC_SINC5SINC1<<ADC_FILT0_ORDER0_bp)|(ADC_50000S<<ADC_FILT0_ODR0_bp));
190 }
191
192 inline uint16_t adcport_read_filtcon0(void)
193 {
194
195 uint16_t aux;
196 //PORTSPI.OUTCLR = SPI_SS_bm;
197 adcport_tranceiv((ADC_FILTCON0|ADC_RWbar_bm)&(~ADC_WENbar_bm));
198 //adcport_tranceiv(0xFF);
199 aux = adcport_tranceiv(0);
200 aux = (aux << 8) | adcport_tranceiv(0);
201 //PORTSPI.OUTSET = SPI_SS_bm;
202 return aux;
203 }
204
205 void adcport_write_interfmode(void)
206 {
207 adcport_tranceiv((ADC_INTERFMODE_REG) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
208 adcport_tranceiv(ADC_IOSTRENGTH_NE<<ADC_IOSTRENGTH_bp);
209 adcport_tranceiv((ADC_CONTREAD_NE<<ADC_CONTREAD_bp)|(ADC_24b<<ADC_WL16_bp));
210 }
211
212 void adcport_write_chmapreg0(void)
213 {
214 adcport_tranceiv((ADC_CHMAPREG0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
215 adcport_tranceiv((ADC_CHMAPEN_E<<ADC_CHMAPEN_bp)|(ADC_SET0_bm<<ADC_CHSETSEL_bp)|(ADC_AINPOSUB1_bm<<ADC_AINPOSUB_bp));
216 adcport_tranceiv((ADC_AINPOSLB1_bm<<ADC_AINPOSLB_bp)|(ADC_AINEG0_bm<<ADC_AINNEG_bp));
217 }
218
219 void adcport_write_chmapreg1(void)
220 {
221 adcport_tranceiv((ADC_CHMAPREG1) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
222 adcport_tranceiv((ADC_CHMAPEN_NE<<ADC_CHMAPEN_bp)|(ADC_SET0_bm<<ADC_CHSETSEL_bp)|(ADC_AINPOSUB0_bm<<ADC_AINPOSUB_bp));
223 adcport_tranceiv((ADC_AINPOSLB0_bm<<ADC_AINPOSLB_bp)|(ADC_AINEG1_bm<<ADC_AINNEG_bp));
224 }
225
226 void adcport_write_chmapreg2(void)
227 {
228 adcport_tranceiv((ADC_CHMAPREG2) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
229 adcport_tranceiv((ADC_CHMAPEN_NE<<ADC_CHMAPEN_bp)|(ADC_SET0_bm<<ADC_CHSETSEL_bp)|(ADC_AINPOSUB0_bm<<ADC_AINPOSUB_bp));
230 adcport_tranceiv((ADC_AINPOSLB0_bm<<ADC_AINPOSLB_bp)|(ADC_AINEG1_bm<<ADC_AINNEG_bp));
231 }
232
233 void adcport_write_chmapreg3(void)
234 {
235 adcport_tranceiv((ADC_CHMAPREG3) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
236 adcport_tranceiv((ADC_CHMAPEN_NE<<ADC_CHMAPEN_bp)|(ADC_SET0_bm<<ADC_CHSETSEL_bp)|(ADC_AINPOSUB0_bm<<ADC_AINPOSUB_bp));
237 adcport_tranceiv((ADC_AINPOSLB0_bm<<ADC_AINPOSLB_bp)|(ADC_AINEG1_bm<<ADC_AINNEG_bp));
238 }
239
240 void adcport_write_setupcon0(void)
241 {
242 adcport_tranceiv((ADC_SETUPCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
243 adcport_tranceiv((ADC_OFFSETBIP_bm<<ADC_BI_UNIPOLAR_bp));
244 adcport_tranceiv((ADC_INT25V_bm<<ADC_REFSEL_bp));
245 }
246
247 void adcport_write_reset(void)
248 {
249 adcport_tranceiv(0xFF);
250 adcport_tranceiv(0xFF);
251 adcport_tranceiv(0xFF);
252 adcport_tranceiv(0xFF);
253 adcport_tranceiv(0xFF);
254 adcport_tranceiv(0xFF);
255 adcport_tranceiv(0xFF);
256 adcport_tranceiv(0xFF);
257 } No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,147
1 /*
2 * ADC_7176_2.h
3 *
4 * Created: 26/04/16 11:47:27
5 * Author: Francisco
6 */
7
8
9
10 #ifndef ADC_7176_2_H_
11 #define ADC_7176_2_H_
12
13 #define F_CPU 32000000UL
14 #include <avr/io.h>
15 #include "Ports.h"
16 #include "commSPI_ADC.h"
17
18 //ID esperada
19 //tama�o 16 bits
20 //Valor 0x0C94
21 #define ADC_VALFIL0 0x0013
22 //#define ADC_VALFIL0 0x8000
23 #define ADC_ID 0x0C94
24 #define ADC_RD 0x04
25
26 #define ADC_MODREG 0x01
27 #define ADC_DATREG 0x04
28 #define ADC_FILTCON0 0x28
29 #define ADC_INTERFMODE_REG 0x02
30
31 #define ADC_ADDR_READ_ID (0x07)
32 #define ADC_CHMAPREG0 0x10
33 #define ADC_CHMAPREG1 0x11
34 #define ADC_CHMAPREG2 0x12
35 #define ADC_CHMAPREG3 0x13
36 #define ADC_SETUPCON0 0x20
37
38 #define ADC_DATASZ 3 //Numero de bytes
39
40 //Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n
41 #define ADC_WENbar_bm 0b10000000
42 #define ADC_RWbar_bm 0b01000000
43 #define ADC_FILT0_ORDER0_bp 5
44 #define ADC_FILT0_ODR0_bp 0
45
46 #define ADC_CONTREAD_bp 7
47 #define ADC_WL16_bp 0
48 #define ADC_IOSTRENGTH_bp 3
49 #define ADC_IOSTRENGTH_E 0b1
50 #define ADC_IOSTRENGTH_NE 0b0
51
52 #define ADC_SYNCYC_bp 5
53 #define ADC_REFOUT_bp 7
54 #define ADC_MODECONV_bp 4
55 #define ADC_SINGLECONV 0b001
56 #define ADC_CONTCONV 0b000
57
58 #define ADC_SINC5SINC1 0b00
59 #define ADC_CONTREAD_E 0b1
60 #define ADC_CONTREAD_NE 0b0
61
62 #define ADC_REFEN_bm 0b1
63 #define ADC_REFNEN_bm 0b0
64
65 #define ADC_SINGLECONV_EN_bm 0b1
66 #define ADC_SINGLECONV_NEN_bm 0b0
67
68 #define ADC_CHMAPEN_bp 7
69 #define ADC_CHMAPEN_E 1
70 #define ADC_CHMAPEN_NE 0
71
72
73 #define ADC_CHSETSEL_bp 4
74 #define ADC_SET0_bm 0b000
75
76 #define ADC_AINPOSUB_bp 0
77 #define ADC_AINPOSLB_bp 5
78 #define ADC_AINNEG_bp 0
79
80 #define ADC_AINPOSUB0_bm 0b00
81 #define ADC_AINPOSLB0_bm 0b000
82 #define ADC_AINEG1_bm 0b00001
83
84 #define ADC_AINPOSUB1_bm 0b00
85 #define ADC_AINPOSLB1_bm 0b001
86 #define ADC_AINEG0_bm 0b00000
87
88
89 #define ADC_BI_UNIPOLAR_bp 4
90 #define ADC_OFFSETBIP_bm 0b1
91 #define ADC_REFSEL_bp 4
92 #define ADC_INT25V_bm 0b10
93
94
95
96
97 #define ADC_250000S 0b00000
98 #define ADC_125000S 0b00001
99 #define ADC_62500S 0b00010
100 #define ADC_50000S 0b00011
101 #define ADC_31250S 0b00100
102 #define ADC_25000S 0b00101
103 #define ADC_15625S 0b00110
104 #define ADC_10000S 0b00111
105 #define ADC_5000S 0b01000
106 #define ADC_2500S 0b01001
107 #define ADC_1000S 0b01010
108 #define ADC_500S 0b01011
109 #define ADC_3975S 0b01100
110 #define ADC_200S 0b01101
111 #define ADC_100S 0b01110
112 #define ADC_5994S 0b01111
113 #define ADC_4996S 0b10000
114 #define ADC_20S 0b10001
115 #define ADC_166S 0b10010
116 #define ADC_10S 0b10011
117 #define ADC_5S 0b10100
118
119 #define ADC_24b 0b0
120 #define ADC_16b 0b1
121
122 uint8_t adcport_tranceiv(uint8_t data);
123 void adcport_read_data(uint8_t* dato,int j);
124
125 uint16_t adcport_read_filtcon0(void);
126
127 void adcport_write_filtcon0(void);
128 void adcport_write_interfmode(void);
129 void adcport_write_adcmode(void);
130 void adcport_write_reset(void);
131 void adcport_write_chmapreg0(void);
132 void adcport_write_chmapreg1(void);
133 void adcport_write_chmapreg2(void);
134 void adcport_write_chmapreg3(void);
135 void adcport_write_setupcon0(void);
136 void adcport_write_adcmode_2(void);
137 void adcport_read_data_synconv(uint8_t* dato,int j);
138 void adcport_read_data_contread(uint8_t* dato,int j);
139
140
141 uint16_t test_adc(void);
142 void test_adc_2(uint8_t* dato);
143 uint16_t test_adc_3(void);
144
145 void config_adc(void);
146
147 #endif /* ADC_7176_2_H_ */ No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,1
1 :00000001FF
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
Show file before | Show file after | Hide comments
@@ -0,0 +1,143
1 :100000000C94B6000C94C8000C94AC020C94C8007C
2 :100010000C94C8000C94C8000C94C8000C94C80040
3 :100020000C94C8000C94C8000C94C8000C94C80030
4 :100030000C94C8000C94C8000C94C8000C94C80020
5 :100040000C94C8000C94C8000C94C8000C94C80010
6 :100050000C94C8000C94C8000C94C8000C94C80000
7 :100060000C94C8000C94C8000C94C8000C94C800F0
8 :100070000C94C8000C94C8000C94C8000C94C800E0
9 :100080000C94C8000C94C8000C94C8000C94630233
10 :100090000C94C8000C94C8000C94C8000C94C800C0
11 :1000A0000C94C8000C94C8000C94C8000C94C800B0
12 :1000B0000C94C8000C94C8000C94C8000C94C800A0
13 :1000C0000C94C8000C94C8000C94C8000C94C80090
14 :1000D0000C94C8000C94C8000C94C8000C94C80080
15 :1000E0000C94C8000C94C8000C94C8000C94C80070
16 :1000F0000C94C8000C94C8000C94C8000C94C80060
17 :100100000C942F020C94C8000C94C8000C94C800E6
18 :100110000C94C8000C94C8000C94C8000C94C8003F
19 :100120000C94C8000C94C8000C94C8000C94C8002F
20 :100130000C94C8000C94C8000C94C8000C94C8001F
21 :100140000C94C8000C94C8000C94C8000C94C8000F
22 :100150000C94C8000C94C8000C94C8000C94C800FF
23 :100160000C94C8000C94C8000C94C80011241FBE45
24 :10017000CFEFCDBFDFE2DEBF20E2A0E0B0E201C002
25 :100180001D92A230B207E1F70E941E020C9468048F
26 :100190000C94000024E4E0ECF8E023832281222385
27 :1001A000ECF7E0ECF8E023811616170664F4DC01A6
28 :1001B000860F971F138222812223ECF723812D9330
29 :1001C000A817B907B9F7089581E0E0ECF8E0838358
30 :1001D00082818823ECF7E0ECF8E0838180E8838378
31 :1001E00082818823ECF7E0ECF8E08381138282813E
32 :1001F0008823ECF7E0ECF8E08381089588E2E0ECF6
33 :10020000F8E0838382818823ECF7E0ECF8E08381D7
34 :10021000138282818823ECF7E0ECF8E0838183E0AD
35 :10022000838382818823ECF7E0ECF8E083810895F2
36 :1002300082E0E0ECF8E0838382818823ECF7E0EC55
37 :10024000F8E08381138282818823ECF7E0ECF8E008
38 :100250008381138282818823ECF7E0ECF8E08381CC
39 :10026000089580E1E0ECF8E0838382818823ECF755
40 :10027000E0ECF8E0838180E8838382818823ECF7D7
41 :10028000E0ECF8E0838180E2838382818823ECF7CD
42 :10029000E0ECF8E08381089581E1E0ECF8E083830D
43 :1002A00082818823ECF7E0ECF8E08381138282817D
44 :1002B0008823ECF7E0ECF8E0838181E0838382819E
45 :1002C0008823ECF7E0ECF8E08381089582E1E0EC2C
46 :1002D000F8E0838382818823ECF7E0ECF8E0838107
47 :1002E000138282818823ECF7E0ECF8E0838181E0DF
48 :1002F000838382818823ECF7E0ECF8E08381089522
49 :1003000083E1E0ECF8E0838382818823ECF7E0EC82
50 :10031000F8E08381138282818823ECF7E0ECF8E037
51 :10032000838181E0838382818823ECF7E0ECF8E02D
52 :100330008381089580E2E0ECF8E083838281882362
53 :10034000ECF7E0ECF8E0838180E18383828188230D
54 :10035000ECF7E0ECF8E0838180E2838382818823FC
55 :10036000ECF7E0ECF8E0838108958FEFE0ECF8E043
56 :10037000838382818823ECF7E0ECF8E083818FEFC0
57 :10038000838382818823ECF7E0ECF8E083818FEFB0
58 :10039000838382818823ECF7E0ECF8E083818FEFA0
59 :1003A000838382818823ECF7E0ECF8E083818FEF90
60 :1003B000838382818823ECF7E0ECF8E083818FEF80
61 :1003C000838382818823ECF7E0ECF8E083818FEF70
62 :1003D000838382818823ECF7E0ECF8E083818FEF60
63 :1003E000838382818823ECF7E0ECF8E08381089531
64 :1003F0001F93CF93DF93C0E4D6E010E11E830E94E9
65 :10040000B5011D838FE599E00197F1F700C0000069
66 :100410001E830E94E4000E9418010E94FE000E94B8
67 :100420009A010E9431010E944C010E9466010E94C3
68 :1004300080011D83DF91CF911F9108950E94CF030A
69 :100440000E9449040E94E4020E94E8020E94F8010E
70 :1004500084E0E0EAF0E082830E941B03FFCF1F925A
71 :100460000F920FB60F9211248F939F93EF93FF93E8
72 :10047000E0E6F6E0808581FF11C081E0E0E4F6E08F
73 :10048000848792E0E0E2F6E09487E0EAF0E092818F
74 :1004900092609283E0E0F6E085830CC0E0EAF0E051
75 :1004A00082818D7F828382818E7F828381E0E0E002
76 :1004B000F6E08683FF91EF919F918F910F900FBE91
77 :1004C0000F901F9018951F920F920FB60F92112444
78 :1004D0008F93EF93FF93E0EAF0E082818E7F828337
79 :1004E000E0E4F6E081E084878487000000000000FB
80 :1004F00000001092002010920120E0EAF0E08281DA
81 :1005000081608283E0E4F6E081E0848780E1858396
82 :10051000000084E0E0E6F6E08583000000000000D3
83 :1005200000000000000000000000000000000000CB
84 :100530000000000080E1E0E4F6E086838AE68A9528
85 :10054000F1F700C081E08487FF91EF918F910F90C8
86 :100550000FBE0F901F9018951F920F920FB60F921B
87 :1005600011242F933F934F935F936F937F938F93B8
88 :100570009F93AF93BF93EF93FF938091002090914F
89 :10058000012080329E445CF40E94B90380910020D7
90 :10059000909101200196809300209093012081E0AA
91 :1005A000E0E4F6E08487FF91EF91BF91AF919F91D6
92 :1005B0008F917F916F915F914F913F912F910F900C
93 :1005C0000FBE0F901F9018958CED8093C008089572
94 :1005D000CF93DF93E0E6F6E0118A92E0928320E188
95 :1005E000228B84E081838683A0E2B6E012968C930E
96 :1005F000129752962C935297C0E0D6E021E02983BF
97 :100600002E8321852360218792879189987F918B02
98 :100610009185937F986019969C9319971B968C935C
99 :100620001B9752968C915297887F816052968C933B
100 :10063000DF91CF91089578940895000000000000A4
101 :1006400000000000000000000000000000000000AA
102 :10065000000000000000000000000000000000009A
103 :10066000000084E0E0E6F6E0858300000000000082
104 :10067000000000000000000000000000000000007A
105 :10068000000000000000000000000000000000006A
106 :1006900000008683868188E48483000000000000D7
107 :1006A000000000000000000000000000000000004A
108 :1006B000000000000000000000000000000000003A
109 :1006C000000084E0858300000000000000000000BE
110 :1006D000000000000000000000000000000000001A
111 :1006E0000000000000000000000000000000868301
112 :1006F000868180E684830000000000000000000086
113 :1007000000000000000000000000000000000000E9
114 :10071000000000000000000000000000000084E075
115 :1007200085830000000000000000000000000000C1
116 :1007300000000000000000000000000000000000B9
117 :1007400000000000000008950F931F93CF93DF93E4
118 :100750008C01C0E0D0E0F80181918F010E941D035F
119 :100760002196C330D105B9F7DF91CF911F910F9139
120 :100770000895CF93DF9300D01F92CDB7DEB763E02B
121 :1007800070E0CE0101960E94CA00CE0101960E943F
122 :10079000A4032396CDBFDEBFDF91CF910895E0E0A3
123 :1007A000F6E088E1878B868B858B848B838B828BAD
124 :1007B000818B9EEF928398E3908B91E09683918357
125 :1007C000E0E2F6E0838B828B818B808B2FE02283AB
126 :1007D000E0E4F6E0868B838B828B818B808B9FE4B9
127 :1007E0009283158A178A148A90EB918390E99583F6
128 :1007F00090E29683A0E6B6E094E011969C93119760
129 :1008000016969C93169757968C93579750968C9361
130 :10081000509793E812969C93129790E151969C936F
131 :10082000519756961C92569755961C9255975496EA
132 :100830001C92549753961C92539738E711963C9309
133 :10084000119716963C93A0E8B6E053968C93539775
134 :1008500052968C93529751968C93519750968C93B5
135 :10086000509712962C93A0EEB7E051969C93519717
136 :1008700093E012969C93129750968C9380E4828713
137 :1008800081858C7F816081878689887F8260868B65
138 :10089000089510924100E0E5F0E080818660808359
139 :1008A000818182FFFDCFE0E5F0E0818181FFFDCF16
140 :1008B00081E080936000E0E5F0E096819D7F968383
141 :1008C00098ED94BF8093400080818E7F808308954F
142 :0408D000F894FFCFCA
143 :00000001FF
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (1825 lines changed) Show them Hide them
@@ -0,0 +1,1825
1
2 ADCSPI_v01.elf: file format elf32-avr
3
4 Sections:
5 Idx Name Size VMA LMA File off Algn
6 0 .text 000008d4 00000000 00000000 00000074 2**1
7 CONTENTS, ALLOC, LOAD, READONLY, CODE
8 1 .bss 00000002 00802000 00802000 00000948 2**0
9 ALLOC
10 2 .comment 00000030 00000000 00000000 00000948 2**0
11 CONTENTS, READONLY
12 3 .debug_aranges 00000198 00000000 00000000 00000978 2**0
13 CONTENTS, READONLY, DEBUGGING
14 4 .debug_info 00001a04 00000000 00000000 00000b10 2**0
15 CONTENTS, READONLY, DEBUGGING
16 5 .debug_abbrev 00000726 00000000 00000000 00002514 2**0
17 CONTENTS, READONLY, DEBUGGING
18 6 .debug_line 00000c70 00000000 00000000 00002c3a 2**0
19 CONTENTS, READONLY, DEBUGGING
20 7 .debug_frame 0000034c 00000000 00000000 000038ac 2**2
21 CONTENTS, READONLY, DEBUGGING
22 8 .debug_str 000008ad 00000000 00000000 00003bf8 2**0
23 CONTENTS, READONLY, DEBUGGING
24 9 .debug_loc 00000564 00000000 00000000 000044a5 2**0
25 CONTENTS, READONLY, DEBUGGING
26 10 .debug_ranges 00000138 00000000 00000000 00004a09 2**0
27 CONTENTS, READONLY, DEBUGGING
28
29 Disassembly of section .text:
30
31 00000000 <__vectors>:
32 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end>
33 4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
34 8: 0c 94 ac 02 jmp 0x558 ; 0x558 <__vector_2>
35 c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
36 10: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
37 14: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
38 18: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
39 1c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
40 20: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
41 24: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
42 28: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
43 2c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
44 30: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
45 34: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
46 38: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
47 3c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
48 40: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
49 44: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
50 48: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
51 4c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
52 50: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
53 54: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
54 58: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
55 5c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
56 60: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
57 64: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
58 68: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
59 6c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
60 70: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
61 74: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
62 78: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
63 7c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
64 80: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
65 84: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
66 88: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
67 8c: 0c 94 63 02 jmp 0x4c6 ; 0x4c6 <__vector_35>
68 90: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
69 94: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
70 98: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
71 9c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
72 a0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
73 a4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
74 a8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
75 ac: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
76 b0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
77 b4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
78 b8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
79 bc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
80 c0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
81 c4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
82 c8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
83 cc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
84 d0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
85 d4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
86 d8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
87 dc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
88 e0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
89 e4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
90 e8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
91 ec: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
92 f0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
93 f4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
94 f8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
95 fc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
96 100: 0c 94 2f 02 jmp 0x45e ; 0x45e <__vector_64>
97 104: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
98 108: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
99 10c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
100 110: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
101 114: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
102 118: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
103 11c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
104 120: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
105 124: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
106 128: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
107 12c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
108 130: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
109 134: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
110 138: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
111 13c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
112 140: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
113 144: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
114 148: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
115 14c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
116 150: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
117 154: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
118 158: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
119 15c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
120 160: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
121 164: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
122 168: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt>
123
124 0000016c <__ctors_end>:
125 16c: 11 24 eor r1, r1
126 16e: 1f be out 0x3f, r1 ; 63
127 170: cf ef ldi r28, 0xFF ; 255
128 172: cd bf out 0x3d, r28 ; 61
129 174: df e2 ldi r29, 0x2F ; 47
130 176: de bf out 0x3e, r29 ; 62
131
132 00000178 <__do_clear_bss>:
133 178: 20 e2 ldi r18, 0x20 ; 32
134 17a: a0 e0 ldi r26, 0x00 ; 0
135 17c: b0 e2 ldi r27, 0x20 ; 32
136 17e: 01 c0 rjmp .+2 ; 0x182 <.do_clear_bss_start>
137
138 00000180 <.do_clear_bss_loop>:
139 180: 1d 92 st X+, r1
140
141 00000182 <.do_clear_bss_start>:
142 182: a2 30 cpi r26, 0x02 ; 2
143 184: b2 07 cpc r27, r18
144 186: e1 f7 brne .-8 ; 0x180 <.do_clear_bss_loop>
145 188: 0e 94 1e 02 call 0x43c ; 0x43c <main>
146 18c: 0c 94 68 04 jmp 0x8d0 ; 0x8d0 <_exit>
147
148 00000190 <__bad_interrupt>:
149 190: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
150
151 00000194 <adcport_read_data>:
152 * \param El dato a transmitir
153 * \return El dato leido del ADC
154 */
155 inline uint8_t adcport_tranceiv(uint8_t data){
156 //
157 SPIC.DATA = data;
158 194: 24 e4 ldi r18, 0x44 ; 68
159 196: e0 ec ldi r30, 0xC0 ; 192
160 198: f8 e0 ldi r31, 0x08 ; 8
161 19a: 23 83 std Z+3, r18 ; 0x03
162
163 //Wait until transmission complete
164 while( !(SPIC.STATUS & SPI_IF_bm));
165 19c: 22 81 ldd r18, Z+2 ; 0x02
166 19e: 22 23 and r18, r18
167 1a0: ec f7 brge .-6 ; 0x19c <adcport_read_data+0x8>
168
169 // Return received data
170
171 return SPIC.DATA;
172 1a2: e0 ec ldi r30, 0xC0 ; 192
173 1a4: f8 e0 ldi r31, 0x08 ; 8
174 1a6: 23 81 ldd r18, Z+3 ; 0x03
175 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
176
177 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
178
179 // Save received data
180 for(int i=0; i<j ; i++)
181 1a8: 16 16 cp r1, r22
182 1aa: 17 06 cpc r1, r23
183 1ac: 64 f4 brge .+24 ; 0x1c6 <adcport_read_data+0x32>
184 1ae: dc 01 movw r26, r24
185 1b0: 86 0f add r24, r22
186 1b2: 97 1f adc r25, r23
187 * \param El dato a transmitir
188 * \return El dato leido del ADC
189 */
190 inline uint8_t adcport_tranceiv(uint8_t data){
191 //
192 SPIC.DATA = data;
193 1b4: 13 82 std Z+3, r1 ; 0x03
194
195 //Wait until transmission complete
196 while( !(SPIC.STATUS & SPI_IF_bm));
197 1b6: 22 81 ldd r18, Z+2 ; 0x02
198 1b8: 22 23 and r18, r18
199 1ba: ec f7 brge .-6 ; 0x1b6 <adcport_read_data+0x22>
200
201 // Return received data
202
203 return SPIC.DATA;
204 1bc: 23 81 ldd r18, Z+3 ; 0x03
205
206 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
207
208 // Save received data
209 for(int i=0; i<j ; i++)
210 dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1)
211 1be: 2d 93 st X+, r18
212 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
213
214 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
215
216 // Save received data
217 for(int i=0; i<j ; i++)
218 1c0: a8 17 cp r26, r24
219 1c2: b9 07 cpc r27, r25
220 1c4: b9 f7 brne .-18 ; 0x1b4 <adcport_read_data+0x20>
221 1c6: 08 95 ret
222
223 000001c8 <adcport_write_adcmode>:
224 * \param El dato a transmitir
225 * \return El dato leido del ADC
226 */
227 inline uint8_t adcport_tranceiv(uint8_t data){
228 //
229 SPIC.DATA = data;
230 1c8: 81 e0 ldi r24, 0x01 ; 1
231 1ca: e0 ec ldi r30, 0xC0 ; 192
232 1cc: f8 e0 ldi r31, 0x08 ; 8
233 1ce: 83 83 std Z+3, r24 ; 0x03
234
235 //Wait until transmission complete
236 while( !(SPIC.STATUS & SPI_IF_bm));
237 1d0: 82 81 ldd r24, Z+2 ; 0x02
238 1d2: 88 23 and r24, r24
239 1d4: ec f7 brge .-6 ; 0x1d0 <adcport_write_adcmode+0x8>
240
241 // Return received data
242
243 return SPIC.DATA;
244 1d6: e0 ec ldi r30, 0xC0 ; 192
245 1d8: f8 e0 ldi r31, 0x08 ; 8
246 1da: 83 81 ldd r24, Z+3 ; 0x03
247 * \param El dato a transmitir
248 * \return El dato leido del ADC
249 */
250 inline uint8_t adcport_tranceiv(uint8_t data){
251 //
252 SPIC.DATA = data;
253 1dc: 80 e8 ldi r24, 0x80 ; 128
254 1de: 83 83 std Z+3, r24 ; 0x03
255
256 //Wait until transmission complete
257 while( !(SPIC.STATUS & SPI_IF_bm));
258 1e0: 82 81 ldd r24, Z+2 ; 0x02
259 1e2: 88 23 and r24, r24
260 1e4: ec f7 brge .-6 ; 0x1e0 <adcport_write_adcmode+0x18>
261
262 // Return received data
263
264 return SPIC.DATA;
265 1e6: e0 ec ldi r30, 0xC0 ; 192
266 1e8: f8 e0 ldi r31, 0x08 ; 8
267 1ea: 83 81 ldd r24, Z+3 ; 0x03
268 * \param El dato a transmitir
269 * \return El dato leido del ADC
270 */
271 inline uint8_t adcport_tranceiv(uint8_t data){
272 //
273 SPIC.DATA = data;
274 1ec: 13 82 std Z+3, r1 ; 0x03
275
276 //Wait until transmission complete
277 while( !(SPIC.STATUS & SPI_IF_bm));
278 1ee: 82 81 ldd r24, Z+2 ; 0x02
279 1f0: 88 23 and r24, r24
280 1f2: ec f7 brge .-6 ; 0x1ee <adcport_write_adcmode+0x26>
281
282 // Return received data
283
284 return SPIC.DATA;
285 1f4: e0 ec ldi r30, 0xC0 ; 192
286 1f6: f8 e0 ldi r31, 0x08 ; 8
287 1f8: 83 81 ldd r24, Z+3 ; 0x03
288 1fa: 08 95 ret
289
290 000001fc <adcport_write_filtcon0>:
291 * \param El dato a transmitir
292 * \return El dato leido del ADC
293 */
294 inline uint8_t adcport_tranceiv(uint8_t data){
295 //
296 SPIC.DATA = data;
297 1fc: 88 e2 ldi r24, 0x28 ; 40
298 1fe: e0 ec ldi r30, 0xC0 ; 192
299 200: f8 e0 ldi r31, 0x08 ; 8
300 202: 83 83 std Z+3, r24 ; 0x03
301
302 //Wait until transmission complete
303 while( !(SPIC.STATUS & SPI_IF_bm));
304 204: 82 81 ldd r24, Z+2 ; 0x02
305 206: 88 23 and r24, r24
306 208: ec f7 brge .-6 ; 0x204 <adcport_write_filtcon0+0x8>
307
308 // Return received data
309
310 return SPIC.DATA;
311 20a: e0 ec ldi r30, 0xC0 ; 192
312 20c: f8 e0 ldi r31, 0x08 ; 8
313 20e: 83 81 ldd r24, Z+3 ; 0x03
314 * \param El dato a transmitir
315 * \return El dato leido del ADC
316 */
317 inline uint8_t adcport_tranceiv(uint8_t data){
318 //
319 SPIC.DATA = data;
320 210: 13 82 std Z+3, r1 ; 0x03
321
322 //Wait until transmission complete
323 while( !(SPIC.STATUS & SPI_IF_bm));
324 212: 82 81 ldd r24, Z+2 ; 0x02
325 214: 88 23 and r24, r24
326 216: ec f7 brge .-6 ; 0x212 <adcport_write_filtcon0+0x16>
327
328 // Return received data
329
330 return SPIC.DATA;
331 218: e0 ec ldi r30, 0xC0 ; 192
332 21a: f8 e0 ldi r31, 0x08 ; 8
333 21c: 83 81 ldd r24, Z+3 ; 0x03
334 * \param El dato a transmitir
335 * \return El dato leido del ADC
336 */
337 inline uint8_t adcport_tranceiv(uint8_t data){
338 //
339 SPIC.DATA = data;
340 21e: 83 e0 ldi r24, 0x03 ; 3
341 220: 83 83 std Z+3, r24 ; 0x03
342
343 //Wait until transmission complete
344 while( !(SPIC.STATUS & SPI_IF_bm));
345 222: 82 81 ldd r24, Z+2 ; 0x02
346 224: 88 23 and r24, r24
347 226: ec f7 brge .-6 ; 0x222 <adcport_write_filtcon0+0x26>
348
349 // Return received data
350
351 return SPIC.DATA;
352 228: e0 ec ldi r30, 0xC0 ; 192
353 22a: f8 e0 ldi r31, 0x08 ; 8
354 22c: 83 81 ldd r24, Z+3 ; 0x03
355 22e: 08 95 ret
356
357 00000230 <adcport_write_interfmode>:
358 * \param El dato a transmitir
359 * \return El dato leido del ADC
360 */
361 inline uint8_t adcport_tranceiv(uint8_t data){
362 //
363 SPIC.DATA = data;
364 230: 82 e0 ldi r24, 0x02 ; 2
365 232: e0 ec ldi r30, 0xC0 ; 192
366 234: f8 e0 ldi r31, 0x08 ; 8
367 236: 83 83 std Z+3, r24 ; 0x03
368
369 //Wait until transmission complete
370 while( !(SPIC.STATUS & SPI_IF_bm));
371 238: 82 81 ldd r24, Z+2 ; 0x02
372 23a: 88 23 and r24, r24
373 23c: ec f7 brge .-6 ; 0x238 <adcport_write_interfmode+0x8>
374
375 // Return received data
376
377 return SPIC.DATA;
378 23e: e0 ec ldi r30, 0xC0 ; 192
379 240: f8 e0 ldi r31, 0x08 ; 8
380 242: 83 81 ldd r24, Z+3 ; 0x03
381 * \param El dato a transmitir
382 * \return El dato leido del ADC
383 */
384 inline uint8_t adcport_tranceiv(uint8_t data){
385 //
386 SPIC.DATA = data;
387 244: 13 82 std Z+3, r1 ; 0x03
388
389 //Wait until transmission complete
390 while( !(SPIC.STATUS & SPI_IF_bm));
391 246: 82 81 ldd r24, Z+2 ; 0x02
392 248: 88 23 and r24, r24
393 24a: ec f7 brge .-6 ; 0x246 <adcport_write_interfmode+0x16>
394
395 // Return received data
396
397 return SPIC.DATA;
398 24c: e0 ec ldi r30, 0xC0 ; 192
399 24e: f8 e0 ldi r31, 0x08 ; 8
400 250: 83 81 ldd r24, Z+3 ; 0x03
401 * \param El dato a transmitir
402 * \return El dato leido del ADC
403 */
404 inline uint8_t adcport_tranceiv(uint8_t data){
405 //
406 SPIC.DATA = data;
407 252: 13 82 std Z+3, r1 ; 0x03
408
409 //Wait until transmission complete
410 while( !(SPIC.STATUS & SPI_IF_bm));
411 254: 82 81 ldd r24, Z+2 ; 0x02
412 256: 88 23 and r24, r24
413 258: ec f7 brge .-6 ; 0x254 <adcport_write_interfmode+0x24>
414
415 // Return received data
416
417 return SPIC.DATA;
418 25a: e0 ec ldi r30, 0xC0 ; 192
419 25c: f8 e0 ldi r31, 0x08 ; 8
420 25e: 83 81 ldd r24, Z+3 ; 0x03
421 260: 08 95 ret
422
423 00000262 <adcport_write_chmapreg0>:
424 * \param El dato a transmitir
425 * \return El dato leido del ADC
426 */
427 inline uint8_t adcport_tranceiv(uint8_t data){
428 //
429 SPIC.DATA = data;
430 262: 80 e1 ldi r24, 0x10 ; 16
431 264: e0 ec ldi r30, 0xC0 ; 192
432 266: f8 e0 ldi r31, 0x08 ; 8
433 268: 83 83 std Z+3, r24 ; 0x03
434
435 //Wait until transmission complete
436 while( !(SPIC.STATUS & SPI_IF_bm));
437 26a: 82 81 ldd r24, Z+2 ; 0x02
438 26c: 88 23 and r24, r24
439 26e: ec f7 brge .-6 ; 0x26a <adcport_write_chmapreg0+0x8>
440
441 // Return received data
442
443 return SPIC.DATA;
444 270: e0 ec ldi r30, 0xC0 ; 192
445 272: f8 e0 ldi r31, 0x08 ; 8
446 274: 83 81 ldd r24, Z+3 ; 0x03
447 * \param El dato a transmitir
448 * \return El dato leido del ADC
449 */
450 inline uint8_t adcport_tranceiv(uint8_t data){
451 //
452 SPIC.DATA = data;
453 276: 80 e8 ldi r24, 0x80 ; 128
454 278: 83 83 std Z+3, r24 ; 0x03
455
456 //Wait until transmission complete
457 while( !(SPIC.STATUS & SPI_IF_bm));
458 27a: 82 81 ldd r24, Z+2 ; 0x02
459 27c: 88 23 and r24, r24
460 27e: ec f7 brge .-6 ; 0x27a <adcport_write_chmapreg0+0x18>
461
462 // Return received data
463
464 return SPIC.DATA;
465 280: e0 ec ldi r30, 0xC0 ; 192
466 282: f8 e0 ldi r31, 0x08 ; 8
467 284: 83 81 ldd r24, Z+3 ; 0x03
468 * \param El dato a transmitir
469 * \return El dato leido del ADC
470 */
471 inline uint8_t adcport_tranceiv(uint8_t data){
472 //
473 SPIC.DATA = data;
474 286: 80 e2 ldi r24, 0x20 ; 32
475 288: 83 83 std Z+3, r24 ; 0x03
476
477 //Wait until transmission complete
478 while( !(SPIC.STATUS & SPI_IF_bm));
479 28a: 82 81 ldd r24, Z+2 ; 0x02
480 28c: 88 23 and r24, r24
481 28e: ec f7 brge .-6 ; 0x28a <adcport_write_chmapreg0+0x28>
482
483 // Return received data
484
485 return SPIC.DATA;
486 290: e0 ec ldi r30, 0xC0 ; 192
487 292: f8 e0 ldi r31, 0x08 ; 8
488 294: 83 81 ldd r24, Z+3 ; 0x03
489 296: 08 95 ret
490
491 00000298 <adcport_write_chmapreg1>:
492 * \param El dato a transmitir
493 * \return El dato leido del ADC
494 */
495 inline uint8_t adcport_tranceiv(uint8_t data){
496 //
497 SPIC.DATA = data;
498 298: 81 e1 ldi r24, 0x11 ; 17
499 29a: e0 ec ldi r30, 0xC0 ; 192
500 29c: f8 e0 ldi r31, 0x08 ; 8
501 29e: 83 83 std Z+3, r24 ; 0x03
502
503 //Wait until transmission complete
504 while( !(SPIC.STATUS & SPI_IF_bm));
505 2a0: 82 81 ldd r24, Z+2 ; 0x02
506 2a2: 88 23 and r24, r24
507 2a4: ec f7 brge .-6 ; 0x2a0 <adcport_write_chmapreg1+0x8>
508
509 // Return received data
510
511 return SPIC.DATA;
512 2a6: e0 ec ldi r30, 0xC0 ; 192
513 2a8: f8 e0 ldi r31, 0x08 ; 8
514 2aa: 83 81 ldd r24, Z+3 ; 0x03
515 * \param El dato a transmitir
516 * \return El dato leido del ADC
517 */
518 inline uint8_t adcport_tranceiv(uint8_t data){
519 //
520 SPIC.DATA = data;
521 2ac: 13 82 std Z+3, r1 ; 0x03
522
523 //Wait until transmission complete
524 while( !(SPIC.STATUS & SPI_IF_bm));
525 2ae: 82 81 ldd r24, Z+2 ; 0x02
526 2b0: 88 23 and r24, r24
527 2b2: ec f7 brge .-6 ; 0x2ae <adcport_write_chmapreg1+0x16>
528
529 // Return received data
530
531 return SPIC.DATA;
532 2b4: e0 ec ldi r30, 0xC0 ; 192
533 2b6: f8 e0 ldi r31, 0x08 ; 8
534 2b8: 83 81 ldd r24, Z+3 ; 0x03
535 * \param El dato a transmitir
536 * \return El dato leido del ADC
537 */
538 inline uint8_t adcport_tranceiv(uint8_t data){
539 //
540 SPIC.DATA = data;
541 2ba: 81 e0 ldi r24, 0x01 ; 1
542 2bc: 83 83 std Z+3, r24 ; 0x03
543
544 //Wait until transmission complete
545 while( !(SPIC.STATUS & SPI_IF_bm));
546 2be: 82 81 ldd r24, Z+2 ; 0x02
547 2c0: 88 23 and r24, r24
548 2c2: ec f7 brge .-6 ; 0x2be <adcport_write_chmapreg1+0x26>
549
550 // Return received data
551
552 return SPIC.DATA;
553 2c4: e0 ec ldi r30, 0xC0 ; 192
554 2c6: f8 e0 ldi r31, 0x08 ; 8
555 2c8: 83 81 ldd r24, Z+3 ; 0x03
556 2ca: 08 95 ret
557
558 000002cc <adcport_write_chmapreg2>:
559 * \param El dato a transmitir
560 * \return El dato leido del ADC
561 */
562 inline uint8_t adcport_tranceiv(uint8_t data){
563 //
564 SPIC.DATA = data;
565 2cc: 82 e1 ldi r24, 0x12 ; 18
566 2ce: e0 ec ldi r30, 0xC0 ; 192
567 2d0: f8 e0 ldi r31, 0x08 ; 8
568 2d2: 83 83 std Z+3, r24 ; 0x03
569
570 //Wait until transmission complete
571 while( !(SPIC.STATUS & SPI_IF_bm));
572 2d4: 82 81 ldd r24, Z+2 ; 0x02
573 2d6: 88 23 and r24, r24
574 2d8: ec f7 brge .-6 ; 0x2d4 <adcport_write_chmapreg2+0x8>
575
576 // Return received data
577
578 return SPIC.DATA;
579 2da: e0 ec ldi r30, 0xC0 ; 192
580 2dc: f8 e0 ldi r31, 0x08 ; 8
581 2de: 83 81 ldd r24, Z+3 ; 0x03
582 * \param El dato a transmitir
583 * \return El dato leido del ADC
584 */
585 inline uint8_t adcport_tranceiv(uint8_t data){
586 //
587 SPIC.DATA = data;
588 2e0: 13 82 std Z+3, r1 ; 0x03
589
590 //Wait until transmission complete
591 while( !(SPIC.STATUS & SPI_IF_bm));
592 2e2: 82 81 ldd r24, Z+2 ; 0x02
593 2e4: 88 23 and r24, r24
594 2e6: ec f7 brge .-6 ; 0x2e2 <adcport_write_chmapreg2+0x16>
595
596 // Return received data
597
598 return SPIC.DATA;
599 2e8: e0 ec ldi r30, 0xC0 ; 192
600 2ea: f8 e0 ldi r31, 0x08 ; 8
601 2ec: 83 81 ldd r24, Z+3 ; 0x03
602 * \param El dato a transmitir
603 * \return El dato leido del ADC
604 */
605 inline uint8_t adcport_tranceiv(uint8_t data){
606 //
607 SPIC.DATA = data;
608 2ee: 81 e0 ldi r24, 0x01 ; 1
609 2f0: 83 83 std Z+3, r24 ; 0x03
610
611 //Wait until transmission complete
612 while( !(SPIC.STATUS & SPI_IF_bm));
613 2f2: 82 81 ldd r24, Z+2 ; 0x02
614 2f4: 88 23 and r24, r24
615 2f6: ec f7 brge .-6 ; 0x2f2 <adcport_write_chmapreg2+0x26>
616
617 // Return received data
618
619 return SPIC.DATA;
620 2f8: e0 ec ldi r30, 0xC0 ; 192
621 2fa: f8 e0 ldi r31, 0x08 ; 8
622 2fc: 83 81 ldd r24, Z+3 ; 0x03
623 2fe: 08 95 ret
624
625 00000300 <adcport_write_chmapreg3>:
626 * \param El dato a transmitir
627 * \return El dato leido del ADC
628 */
629 inline uint8_t adcport_tranceiv(uint8_t data){
630 //
631 SPIC.DATA = data;
632 300: 83 e1 ldi r24, 0x13 ; 19
633 302: e0 ec ldi r30, 0xC0 ; 192
634 304: f8 e0 ldi r31, 0x08 ; 8
635 306: 83 83 std Z+3, r24 ; 0x03
636
637 //Wait until transmission complete
638 while( !(SPIC.STATUS & SPI_IF_bm));
639 308: 82 81 ldd r24, Z+2 ; 0x02
640 30a: 88 23 and r24, r24
641 30c: ec f7 brge .-6 ; 0x308 <adcport_write_chmapreg3+0x8>
642
643 // Return received data
644
645 return SPIC.DATA;
646 30e: e0 ec ldi r30, 0xC0 ; 192
647 310: f8 e0 ldi r31, 0x08 ; 8
648 312: 83 81 ldd r24, Z+3 ; 0x03
649 * \param El dato a transmitir
650 * \return El dato leido del ADC
651 */
652 inline uint8_t adcport_tranceiv(uint8_t data){
653 //
654 SPIC.DATA = data;
655 314: 13 82 std Z+3, r1 ; 0x03
656
657 //Wait until transmission complete
658 while( !(SPIC.STATUS & SPI_IF_bm));
659 316: 82 81 ldd r24, Z+2 ; 0x02
660 318: 88 23 and r24, r24
661 31a: ec f7 brge .-6 ; 0x316 <adcport_write_chmapreg3+0x16>
662
663 // Return received data
664
665 return SPIC.DATA;
666 31c: e0 ec ldi r30, 0xC0 ; 192
667 31e: f8 e0 ldi r31, 0x08 ; 8
668 320: 83 81 ldd r24, Z+3 ; 0x03
669 * \param El dato a transmitir
670 * \return El dato leido del ADC
671 */
672 inline uint8_t adcport_tranceiv(uint8_t data){
673 //
674 SPIC.DATA = data;
675 322: 81 e0 ldi r24, 0x01 ; 1
676 324: 83 83 std Z+3, r24 ; 0x03
677
678 //Wait until transmission complete
679 while( !(SPIC.STATUS & SPI_IF_bm));
680 326: 82 81 ldd r24, Z+2 ; 0x02
681 328: 88 23 and r24, r24
682 32a: ec f7 brge .-6 ; 0x326 <adcport_write_chmapreg3+0x26>
683
684 // Return received data
685
686 return SPIC.DATA;
687 32c: e0 ec ldi r30, 0xC0 ; 192
688 32e: f8 e0 ldi r31, 0x08 ; 8
689 330: 83 81 ldd r24, Z+3 ; 0x03
690 332: 08 95 ret
691
692 00000334 <adcport_write_setupcon0>:
693 * \param El dato a transmitir
694 * \return El dato leido del ADC
695 */
696 inline uint8_t adcport_tranceiv(uint8_t data){
697 //
698 SPIC.DATA = data;
699 334: 80 e2 ldi r24, 0x20 ; 32
700 336: e0 ec ldi r30, 0xC0 ; 192
701 338: f8 e0 ldi r31, 0x08 ; 8
702 33a: 83 83 std Z+3, r24 ; 0x03
703
704 //Wait until transmission complete
705 while( !(SPIC.STATUS & SPI_IF_bm));
706 33c: 82 81 ldd r24, Z+2 ; 0x02
707 33e: 88 23 and r24, r24
708 340: ec f7 brge .-6 ; 0x33c <adcport_write_setupcon0+0x8>
709
710 // Return received data
711
712 return SPIC.DATA;
713 342: e0 ec ldi r30, 0xC0 ; 192
714 344: f8 e0 ldi r31, 0x08 ; 8
715 346: 83 81 ldd r24, Z+3 ; 0x03
716 * \param El dato a transmitir
717 * \return El dato leido del ADC
718 */
719 inline uint8_t adcport_tranceiv(uint8_t data){
720 //
721 SPIC.DATA = data;
722 348: 80 e1 ldi r24, 0x10 ; 16
723 34a: 83 83 std Z+3, r24 ; 0x03
724
725 //Wait until transmission complete
726 while( !(SPIC.STATUS & SPI_IF_bm));
727 34c: 82 81 ldd r24, Z+2 ; 0x02
728 34e: 88 23 and r24, r24
729 350: ec f7 brge .-6 ; 0x34c <adcport_write_setupcon0+0x18>
730
731 // Return received data
732
733 return SPIC.DATA;
734 352: e0 ec ldi r30, 0xC0 ; 192
735 354: f8 e0 ldi r31, 0x08 ; 8
736 356: 83 81 ldd r24, Z+3 ; 0x03
737 * \param El dato a transmitir
738 * \return El dato leido del ADC
739 */
740 inline uint8_t adcport_tranceiv(uint8_t data){
741 //
742 SPIC.DATA = data;
743 358: 80 e2 ldi r24, 0x20 ; 32
744 35a: 83 83 std Z+3, r24 ; 0x03
745
746 //Wait until transmission complete
747 while( !(SPIC.STATUS & SPI_IF_bm));
748 35c: 82 81 ldd r24, Z+2 ; 0x02
749 35e: 88 23 and r24, r24
750 360: ec f7 brge .-6 ; 0x35c <adcport_write_setupcon0+0x28>
751
752 // Return received data
753
754 return SPIC.DATA;
755 362: e0 ec ldi r30, 0xC0 ; 192
756 364: f8 e0 ldi r31, 0x08 ; 8
757 366: 83 81 ldd r24, Z+3 ; 0x03
758 368: 08 95 ret
759
760 0000036a <adcport_write_reset>:
761 * \param El dato a transmitir
762 * \return El dato leido del ADC
763 */
764 inline uint8_t adcport_tranceiv(uint8_t data){
765 //
766 SPIC.DATA = data;
767 36a: 8f ef ldi r24, 0xFF ; 255
768 36c: e0 ec ldi r30, 0xC0 ; 192
769 36e: f8 e0 ldi r31, 0x08 ; 8
770 370: 83 83 std Z+3, r24 ; 0x03
771
772 //Wait until transmission complete
773 while( !(SPIC.STATUS & SPI_IF_bm));
774 372: 82 81 ldd r24, Z+2 ; 0x02
775 374: 88 23 and r24, r24
776 376: ec f7 brge .-6 ; 0x372 <adcport_write_reset+0x8>
777
778 // Return received data
779
780 return SPIC.DATA;
781 378: e0 ec ldi r30, 0xC0 ; 192
782 37a: f8 e0 ldi r31, 0x08 ; 8
783 37c: 83 81 ldd r24, Z+3 ; 0x03
784 * \param El dato a transmitir
785 * \return El dato leido del ADC
786 */
787 inline uint8_t adcport_tranceiv(uint8_t data){
788 //
789 SPIC.DATA = data;
790 37e: 8f ef ldi r24, 0xFF ; 255
791 380: 83 83 std Z+3, r24 ; 0x03
792
793 //Wait until transmission complete
794 while( !(SPIC.STATUS & SPI_IF_bm));
795 382: 82 81 ldd r24, Z+2 ; 0x02
796 384: 88 23 and r24, r24
797 386: ec f7 brge .-6 ; 0x382 <adcport_write_reset+0x18>
798
799 // Return received data
800
801 return SPIC.DATA;
802 388: e0 ec ldi r30, 0xC0 ; 192
803 38a: f8 e0 ldi r31, 0x08 ; 8
804 38c: 83 81 ldd r24, Z+3 ; 0x03
805 * \param El dato a transmitir
806 * \return El dato leido del ADC
807 */
808 inline uint8_t adcport_tranceiv(uint8_t data){
809 //
810 SPIC.DATA = data;
811 38e: 8f ef ldi r24, 0xFF ; 255
812 390: 83 83 std Z+3, r24 ; 0x03
813
814 //Wait until transmission complete
815 while( !(SPIC.STATUS & SPI_IF_bm));
816 392: 82 81 ldd r24, Z+2 ; 0x02
817 394: 88 23 and r24, r24
818 396: ec f7 brge .-6 ; 0x392 <adcport_write_reset+0x28>
819
820 // Return received data
821
822 return SPIC.DATA;
823 398: e0 ec ldi r30, 0xC0 ; 192
824 39a: f8 e0 ldi r31, 0x08 ; 8
825 39c: 83 81 ldd r24, Z+3 ; 0x03
826 * \param El dato a transmitir
827 * \return El dato leido del ADC
828 */
829 inline uint8_t adcport_tranceiv(uint8_t data){
830 //
831 SPIC.DATA = data;
832 39e: 8f ef ldi r24, 0xFF ; 255
833 3a0: 83 83 std Z+3, r24 ; 0x03
834
835 //Wait until transmission complete
836 while( !(SPIC.STATUS & SPI_IF_bm));
837 3a2: 82 81 ldd r24, Z+2 ; 0x02
838 3a4: 88 23 and r24, r24
839 3a6: ec f7 brge .-6 ; 0x3a2 <adcport_write_reset+0x38>
840
841 // Return received data
842
843 return SPIC.DATA;
844 3a8: e0 ec ldi r30, 0xC0 ; 192
845 3aa: f8 e0 ldi r31, 0x08 ; 8
846 3ac: 83 81 ldd r24, Z+3 ; 0x03
847 * \param El dato a transmitir
848 * \return El dato leido del ADC
849 */
850 inline uint8_t adcport_tranceiv(uint8_t data){
851 //
852 SPIC.DATA = data;
853 3ae: 8f ef ldi r24, 0xFF ; 255
854 3b0: 83 83 std Z+3, r24 ; 0x03
855
856 //Wait until transmission complete
857 while( !(SPIC.STATUS & SPI_IF_bm));
858 3b2: 82 81 ldd r24, Z+2 ; 0x02
859 3b4: 88 23 and r24, r24
860 3b6: ec f7 brge .-6 ; 0x3b2 <adcport_write_reset+0x48>
861
862 // Return received data
863
864 return SPIC.DATA;
865 3b8: e0 ec ldi r30, 0xC0 ; 192
866 3ba: f8 e0 ldi r31, 0x08 ; 8
867 3bc: 83 81 ldd r24, Z+3 ; 0x03
868 * \param El dato a transmitir
869 * \return El dato leido del ADC
870 */
871 inline uint8_t adcport_tranceiv(uint8_t data){
872 //
873 SPIC.DATA = data;
874 3be: 8f ef ldi r24, 0xFF ; 255
875 3c0: 83 83 std Z+3, r24 ; 0x03
876
877 //Wait until transmission complete
878 while( !(SPIC.STATUS & SPI_IF_bm));
879 3c2: 82 81 ldd r24, Z+2 ; 0x02
880 3c4: 88 23 and r24, r24
881 3c6: ec f7 brge .-6 ; 0x3c2 <adcport_write_reset+0x58>
882
883 // Return received data
884
885 return SPIC.DATA;
886 3c8: e0 ec ldi r30, 0xC0 ; 192
887 3ca: f8 e0 ldi r31, 0x08 ; 8
888 3cc: 83 81 ldd r24, Z+3 ; 0x03
889 * \param El dato a transmitir
890 * \return El dato leido del ADC
891 */
892 inline uint8_t adcport_tranceiv(uint8_t data){
893 //
894 SPIC.DATA = data;
895 3ce: 8f ef ldi r24, 0xFF ; 255
896 3d0: 83 83 std Z+3, r24 ; 0x03
897
898 //Wait until transmission complete
899 while( !(SPIC.STATUS & SPI_IF_bm));
900 3d2: 82 81 ldd r24, Z+2 ; 0x02
901 3d4: 88 23 and r24, r24
902 3d6: ec f7 brge .-6 ; 0x3d2 <adcport_write_reset+0x68>
903
904 // Return received data
905
906 return SPIC.DATA;
907 3d8: e0 ec ldi r30, 0xC0 ; 192
908 3da: f8 e0 ldi r31, 0x08 ; 8
909 3dc: 83 81 ldd r24, Z+3 ; 0x03
910 * \param El dato a transmitir
911 * \return El dato leido del ADC
912 */
913 inline uint8_t adcport_tranceiv(uint8_t data){
914 //
915 SPIC.DATA = data;
916 3de: 8f ef ldi r24, 0xFF ; 255
917 3e0: 83 83 std Z+3, r24 ; 0x03
918
919 //Wait until transmission complete
920 while( !(SPIC.STATUS & SPI_IF_bm));
921 3e2: 82 81 ldd r24, Z+2 ; 0x02
922 3e4: 88 23 and r24, r24
923 3e6: ec f7 brge .-6 ; 0x3e2 <adcport_write_reset+0x78>
924
925 // Return received data
926
927 return SPIC.DATA;
928 3e8: e0 ec ldi r30, 0xC0 ; 192
929 3ea: f8 e0 ldi r31, 0x08 ; 8
930 3ec: 83 81 ldd r24, Z+3 ; 0x03
931 3ee: 08 95 ret
932
933 000003f0 <config_adc>:
934 dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1)
935 //Si se desease almacenar el dato de byte menos significativo a m�s signficativo: dato[j-i-1] = adcport_tranceiv(0);
936 }
937
938 void config_adc(void)
939 {
940 3f0: 1f 93 push r17
941 3f2: cf 93 push r28
942 3f4: df 93 push r29
943 PORTSPI.OUTCLR = SPI_SS_bm;
944 3f6: c0 e4 ldi r28, 0x40 ; 64
945 3f8: d6 e0 ldi r29, 0x06 ; 6
946 3fa: 10 e1 ldi r17, 0x10 ; 16
947 3fc: 1e 83 std Y+6, r17 ; 0x06
948 adcport_write_reset();
949 3fe: 0e 94 b5 01 call 0x36a ; 0x36a <adcport_write_reset>
950 PORTSPI.OUTSET = SPI_SS_bm;
951 402: 1d 83 std Y+5, r17 ; 0x05
952 #else
953 //round up by default
954 __ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
955 #endif
956
957 __builtin_avr_delay_cycles(__ticks_dc);
958 404: 8f e5 ldi r24, 0x5F ; 95
959 406: 99 e0 ldi r25, 0x09 ; 9
960 408: 01 97 sbiw r24, 0x01 ; 1
961 40a: f1 f7 brne .-4 ; 0x408 <config_adc+0x18>
962 40c: 00 c0 rjmp .+0 ; 0x40e <config_adc+0x1e>
963 40e: 00 00 nop
964
965 _delay_us(300);
966
967 PORTSPI.OUTCLR = SPI_SS_bm;
968 410: 1e 83 std Y+6, r17 ; 0x06
969 adcport_write_adcmode();
970 412: 0e 94 e4 00 call 0x1c8 ; 0x1c8 <adcport_write_adcmode>
971 //PORTSPI.OUTSET = SPI_SS_bm;
972
973 //PORTSPI.OUTCLR = SPI_SS_bm;
974 adcport_write_interfmode();
975 416: 0e 94 18 01 call 0x230 ; 0x230 <adcport_write_interfmode>
976 //PORTSPI.OUTSET = SPI_SS_bm;
977
978 //PORTSPI.OUTCLR = SPI_SS_bm;
979 adcport_write_filtcon0();
980 41a: 0e 94 fe 00 call 0x1fc ; 0x1fc <adcport_write_filtcon0>
981 //PORTSPI.OUTSET = SPI_SS_bm;
982
983 //PORTSPI.OUTCLR = SPI_SS_bm;
984 adcport_write_setupcon0();
985 41e: 0e 94 9a 01 call 0x334 ; 0x334 <adcport_write_setupcon0>
986 //PORTSPI.OUTSET = SPI_SS_bm;
987
988 //PORTSPI.OUTCLR = SPI_SS_bm;
989 adcport_write_chmapreg0();
990 422: 0e 94 31 01 call 0x262 ; 0x262 <adcport_write_chmapreg0>
991 //PORTSPI.OUTSET = SPI_SS_bm;
992
993 //PORTSPI.OUTCLR = SPI_SS_bm;
994 adcport_write_chmapreg1();
995 426: 0e 94 4c 01 call 0x298 ; 0x298 <adcport_write_chmapreg1>
996 //PORTSPI.OUTSET = SPI_SS_bm;
997
998 //PORTSPI.OUTCLR = SPI_SS_bm;
999 adcport_write_chmapreg2();
1000 42a: 0e 94 66 01 call 0x2cc ; 0x2cc <adcport_write_chmapreg2>
1001 //PORTSPI.OUTSET = SPI_SS_bm;
1002
1003 //PORTSPI.OUTCLR = SPI_SS_bm;
1004 adcport_write_chmapreg3();
1005 42e: 0e 94 80 01 call 0x300 ; 0x300 <adcport_write_chmapreg3>
1006 PORTSPI.OUTSET = SPI_SS_bm;
1007 432: 1d 83 std Y+5, r17 ; 0x05
1008
1009 }
1010 434: df 91 pop r29
1011 436: cf 91 pop r28
1012 438: 1f 91 pop r17
1013 43a: 08 95 ret
1014
1015 0000043c <main>:
1016
1017 int aux = 0;
1018 int main(void)
1019 {
1020 //uint8_t datos_adc[3];
1021 config_puertos();
1022 43c: 0e 94 cf 03 call 0x79e ; 0x79e <config_puertos>
1023 config_sysclock();
1024 440: 0e 94 49 04 call 0x892 ; 0x892 <config_sysclock>
1025 config_spiparm();
1026 444: 0e 94 e4 02 call 0x5c8 ; 0x5c8 <config_spiparm>
1027 config_fpgaport();
1028 448: 0e 94 e8 02 call 0x5d0 ; 0x5d0 <config_fpgaport>
1029 config_adc();
1030 44c: 0e 94 f8 01 call 0x3f0 ; 0x3f0 <config_adc>
1031 //datos_adc[0] = 0x00;
1032 //datos_adc[1] = 0x00;
1033 //datos_adc[2] = 0x00;
1034 //PORTD.OUTSET = PIN5_bm;
1035
1036 PMIC.CTRL = hab_prioridad_alta;
1037 450: 84 e0 ldi r24, 0x04 ; 4
1038 452: e0 ea ldi r30, 0xA0 ; 160
1039 454: f0 e0 ldi r31, 0x00 ; 0
1040 456: 82 83 std Z+2, r24 ; 0x02
1041 habilitar_interrupciones_globales();
1042 458: 0e 94 1b 03 call 0x636 ; 0x636 <habilitar_interrupciones_globales>
1043 45c: ff cf rjmp .-2 ; 0x45c <main+0x20>
1044
1045 0000045e <__vector_64>:
1046 return 0;
1047 }
1048
1049
1050 ISR(INT_LOCK_FPGA)
1051 {
1052 45e: 1f 92 push r1
1053 460: 0f 92 push r0
1054 462: 0f b6 in r0, 0x3f ; 63
1055 464: 0f 92 push r0
1056 466: 11 24 eor r1, r1
1057 468: 8f 93 push r24
1058 46a: 9f 93 push r25
1059 46c: ef 93 push r30
1060 46e: ff 93 push r31
1061 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
1062 470: e0 e6 ldi r30, 0x60 ; 96
1063 472: f6 e0 ldi r31, 0x06 ; 6
1064 474: 80 85 ldd r24, Z+8 ; 0x08
1065 476: 81 ff sbrs r24, 1
1066 478: 11 c0 rjmp .+34 ; 0x49c <__vector_64+0x3e>
1067 {
1068 PORTSPI.SPI_INTFLAGS =0b00000001;
1069 47a: 81 e0 ldi r24, 0x01 ; 1
1070 47c: e0 e4 ldi r30, 0x40 ; 64
1071 47e: f6 e0 ldi r31, 0x06 ; 6
1072 480: 84 87 std Z+12, r24 ; 0x0c
1073 PORT_PPS.PPS_FPGA_INTFLAGS =0b00000010;
1074 482: 92 e0 ldi r25, 0x02 ; 2
1075 484: e0 e2 ldi r30, 0x20 ; 32
1076 486: f6 e0 ldi r31, 0x06 ; 6
1077 488: 94 87 std Z+12, r25 ; 0x0c
1078 PMIC.CTRL |= hab_prioridad_media;
1079 48a: e0 ea ldi r30, 0xA0 ; 160
1080 48c: f0 e0 ldi r31, 0x00 ; 0
1081 48e: 92 81 ldd r25, Z+2 ; 0x02
1082 490: 92 60 ori r25, 0x02 ; 2
1083 492: 92 83 std Z+2, r25 ; 0x02
1084 PORT_LOCKOUT.OUTSET = LOCK_OUT;
1085 494: e0 e0 ldi r30, 0x00 ; 0
1086 496: f6 e0 ldi r31, 0x06 ; 6
1087 498: 85 83 std Z+5, r24 ; 0x05
1088 49a: 0c c0 rjmp .+24 ; 0x4b4 <__vector_64+0x56>
1089 //PORTD.OUTSET = PIN4_bm;
1090 }
1091 else
1092 {
1093 PMIC.CTRL &= ~hab_prioridad_media;
1094 49c: e0 ea ldi r30, 0xA0 ; 160
1095 49e: f0 e0 ldi r31, 0x00 ; 0
1096 4a0: 82 81 ldd r24, Z+2 ; 0x02
1097 4a2: 8d 7f andi r24, 0xFD ; 253
1098 4a4: 82 83 std Z+2, r24 ; 0x02
1099 PMIC.CTRL &= ~hab_prioridad_baja;
1100 4a6: 82 81 ldd r24, Z+2 ; 0x02
1101 4a8: 8e 7f andi r24, 0xFE ; 254
1102 4aa: 82 83 std Z+2, r24 ; 0x02
1103 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
1104 4ac: 81 e0 ldi r24, 0x01 ; 1
1105 4ae: e0 e0 ldi r30, 0x00 ; 0
1106 4b0: f6 e0 ldi r31, 0x06 ; 6
1107 4b2: 86 83 std Z+6, r24 ; 0x06
1108 //PORTSPI.OUTSET = SPI_SS_bm;
1109 //PORTD.OUTCLR = PIN4_bm;
1110 }
1111 }
1112 4b4: ff 91 pop r31
1113 4b6: ef 91 pop r30
1114 4b8: 9f 91 pop r25
1115 4ba: 8f 91 pop r24
1116 4bc: 0f 90 pop r0
1117 4be: 0f be out 0x3f, r0 ; 63
1118 4c0: 0f 90 pop r0
1119 4c2: 1f 90 pop r1
1120 4c4: 18 95 reti
1121
1122 000004c6 <__vector_35>:
1123 //Habilito interrupciones de prioridad baja
1124 //Selecciono el chip del ADC para iniciar comunicaci�n.
1125 //Al iniciar esta comunicaci�n se indicar� al ADC que use el RDYbar
1126 //Esta ser� nuestra interrupci�n para lectura del ADC y env�o de dato a la FPGA
1127 ISR(INT_PPS)
1128 {
1129 4c6: 1f 92 push r1
1130 4c8: 0f 92 push r0
1131 4ca: 0f b6 in r0, 0x3f ; 63
1132 4cc: 0f 92 push r0
1133 4ce: 11 24 eor r1, r1
1134 4d0: 8f 93 push r24
1135 4d2: ef 93 push r30
1136 4d4: ff 93 push r31
1137 PMIC.CTRL &= ~hab_prioridad_baja;
1138 4d6: e0 ea ldi r30, 0xA0 ; 160
1139 4d8: f0 e0 ldi r31, 0x00 ; 0
1140 4da: 82 81 ldd r24, Z+2 ; 0x02
1141 4dc: 8e 7f andi r24, 0xFE ; 254
1142 4de: 82 83 std Z+2, r24 ; 0x02
1143 PORTSPI.SPI_INTFLAGS =0b00000001;
1144 4e0: e0 e4 ldi r30, 0x40 ; 64
1145 4e2: f6 e0 ldi r31, 0x06 ; 6
1146 4e4: 81 e0 ldi r24, 0x01 ; 1
1147 4e6: 84 87 std Z+12, r24 ; 0x0c
1148 PORTSPI.SPI_INTFLAGS =0b00000001;
1149 4e8: 84 87 std Z+12, r24 ; 0x0c
1150 ...
1151 asm("nop");
1152 asm("nop");
1153 asm("nop");
1154 asm("nop");
1155 aux = 0;
1156 4f2: 10 92 00 20 sts 0x2000, r1
1157 4f6: 10 92 01 20 sts 0x2001, r1
1158 //if(aux==0)
1159 PMIC.CTRL |= hab_prioridad_baja;
1160 4fa: e0 ea ldi r30, 0xA0 ; 160
1161 4fc: f0 e0 ldi r31, 0x00 ; 0
1162 4fe: 82 81 ldd r24, Z+2 ; 0x02
1163 500: 81 60 ori r24, 0x01 ; 1
1164 502: 82 83 std Z+2, r24 ; 0x02
1165 PORTSPI.SPI_INTFLAGS =0b00000001;
1166 504: e0 e4 ldi r30, 0x40 ; 64
1167 506: f6 e0 ldi r31, 0x06 ; 6
1168 508: 81 e0 ldi r24, 0x01 ; 1
1169 50a: 84 87 std Z+12, r24 ; 0x0c
1170 PORTSPI.OUTSET = SPI_SS_bm;
1171 50c: 80 e1 ldi r24, 0x10 ; 16
1172 50e: 85 83 std Z+5, r24 ; 0x05
1173 asm("nop");
1174 510: 00 00 nop
1175 PORT_FPGA.OUTSET = CLK_FPGA;
1176 512: 84 e0 ldi r24, 0x04 ; 4
1177 514: e0 e6 ldi r30, 0x60 ; 96
1178 516: f6 e0 ldi r31, 0x06 ; 6
1179 518: 85 83 std Z+5, r24 ; 0x05
1180 ...
1181 asm("nop");
1182 asm("nop");
1183 asm("nop");
1184 asm("nop");
1185 asm("nop");
1186 asm("nop");
1187 532: 00 00 nop
1188 PORTSPI.OUTCLR = SPI_SS_bm;
1189 534: 80 e1 ldi r24, 0x10 ; 16
1190 536: e0 e4 ldi r30, 0x40 ; 64
1191 538: f6 e0 ldi r31, 0x06 ; 6
1192 53a: 86 83 std Z+6, r24 ; 0x06
1193 53c: 8a e6 ldi r24, 0x6A ; 106
1194 53e: 8a 95 dec r24
1195 540: f1 f7 brne .-4 ; 0x53e <__vector_35+0x78>
1196 542: 00 c0 rjmp .+0 ; 0x544 <__vector_35+0x7e>
1197
1198 _delay_us(10);
1199 PORTSPI.SPI_INTFLAGS =0b00000001;
1200 544: 81 e0 ldi r24, 0x01 ; 1
1201 546: 84 87 std Z+12, r24 ; 0x0c
1202 //envio_datos_fpga();
1203 //PORTSPI.OUTSET = SPI_SS_bm;
1204
1205 }
1206 548: ff 91 pop r31
1207 54a: ef 91 pop r30
1208 54c: 8f 91 pop r24
1209 54e: 0f 90 pop r0
1210 550: 0f be out 0x3f, r0 ; 63
1211 552: 0f 90 pop r0
1212 554: 1f 90 pop r1
1213 556: 18 95 reti
1214
1215 00000558 <__vector_2>:
1216
1217 ISR(INT_RDY)
1218 {
1219 558: 1f 92 push r1
1220 55a: 0f 92 push r0
1221 55c: 0f b6 in r0, 0x3f ; 63
1222 55e: 0f 92 push r0
1223 560: 11 24 eor r1, r1
1224 562: 2f 93 push r18
1225 564: 3f 93 push r19
1226 566: 4f 93 push r20
1227 568: 5f 93 push r21
1228 56a: 6f 93 push r22
1229 56c: 7f 93 push r23
1230 56e: 8f 93 push r24
1231 570: 9f 93 push r25
1232 572: af 93 push r26
1233 574: bf 93 push r27
1234 576: ef 93 push r30
1235 578: ff 93 push r31
1236 //PMIC.CTRL &= ~hab_prioridad_media;
1237 //PMIC.CTRL &= ~hab_prioridad_alta;
1238 if(aux < 20000){
1239 57a: 80 91 00 20 lds r24, 0x2000
1240 57e: 90 91 01 20 lds r25, 0x2001
1241 582: 80 32 cpi r24, 0x20 ; 32
1242 584: 9e 44 sbci r25, 0x4E ; 78
1243 586: 5c f4 brge .+22 ; 0x59e <__vector_2+0x46>
1244 envio_datos_fpga();
1245 588: 0e 94 b9 03 call 0x772 ; 0x772 <envio_datos_fpga>
1246 aux = aux+1;
1247 58c: 80 91 00 20 lds r24, 0x2000
1248 590: 90 91 01 20 lds r25, 0x2001
1249 594: 01 96 adiw r24, 0x01 ; 1
1250 596: 80 93 00 20 sts 0x2000, r24
1251 59a: 90 93 01 20 sts 0x2001, r25
1252 }
1253 //PORTSPI.OUTCLR = SPI_SS_bm;
1254 //adcport_read_filtcon0();
1255 //PMIC.CTRL |= hab_prioridad_media;
1256 //PMIC.CTRL |= hab_prioridad_alta;
1257 PORTSPI.SPI_INTFLAGS =0b00000001;
1258 59e: 81 e0 ldi r24, 0x01 ; 1
1259 5a0: e0 e4 ldi r30, 0x40 ; 64
1260 5a2: f6 e0 ldi r31, 0x06 ; 6
1261 5a4: 84 87 std Z+12, r24 ; 0x0c
1262 }
1263 5a6: ff 91 pop r31
1264 5a8: ef 91 pop r30
1265 5aa: bf 91 pop r27
1266 5ac: af 91 pop r26
1267 5ae: 9f 91 pop r25
1268 5b0: 8f 91 pop r24
1269 5b2: 7f 91 pop r23
1270 5b4: 6f 91 pop r22
1271 5b6: 5f 91 pop r21
1272 5b8: 4f 91 pop r20
1273 5ba: 3f 91 pop r19
1274 5bc: 2f 91 pop r18
1275 5be: 0f 90 pop r0
1276 5c0: 0f be out 0x3f, r0 ; 63
1277 5c2: 0f 90 pop r0
1278 5c4: 1f 90 pop r1
1279 5c6: 18 95 reti
1280
1281 000005c8 <config_spiparm>:
1282 inline void config_spiparm(void){
1283 // Preescaler: clkper/2 = f_cpu/2.
1284 // Master
1285 // Mode 3: CPOL=1,CPHA=1
1286 // MSB --- LSB
1287 SPIC.CTRL = (SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE1_bm | SPI_MODE0_bm | SPI_CLK2X_bm);//SPI_PRESCALER1_bm | SPI_CLK2X_bm);
1288 5c8: 8c ed ldi r24, 0xDC ; 220
1289 5ca: 80 93 c0 08 sts 0x08C0, r24
1290 5ce: 08 95 ret
1291
1292 000005d0 <config_fpgaport>:
1293 #include <util/delay.h>
1294
1295 #include "fpga_port.h"
1296
1297 inline void config_fpgaport()
1298 {
1299 5d0: cf 93 push r28
1300 5d2: df 93 push r29
1301 //Configuracion pines del puerto D: PD6-PA1
1302 //Pines de entrada CLK_FPGA, LOCK_FPGA
1303 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
1304
1305 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc;
1306 5d4: e0 e6 ldi r30, 0x60 ; 96
1307 5d6: f6 e0 ldi r31, 0x06 ; 6
1308 5d8: 11 8a std Z+17, r1 ; 0x11
1309 PORT_FPGA.DIRCLR = LOCK_FPGA;
1310 5da: 92 e0 ldi r25, 0x02 ; 2
1311 5dc: 92 83 std Z+2, r25 ; 0x02
1312
1313 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
1314 5de: 20 e1 ldi r18, 0x10 ; 16
1315 5e0: 22 8b std Z+18, r18 ; 0x12
1316 PORT_FPGA.DIRSET = CLK_FPGA;
1317 5e2: 84 e0 ldi r24, 0x04 ; 4
1318 5e4: 81 83 std Z+1, r24 ; 0x01
1319 PORT_FPGA.OUTCLR = CLK_FPGA;
1320 5e6: 86 83 std Z+6, r24 ; 0x06
1321 //PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
1322
1323 //Configuracion pines del puerto B: PPS
1324 //Pines de entrada PPS_FPGA
1325 //Pines de entrada en pulldown
1326 PORT_PPS.DIRCLR = PPS_FPGA;
1327 5e8: a0 e2 ldi r26, 0x20 ; 32
1328 5ea: b6 e0 ldi r27, 0x06 ; 6
1329 5ec: 12 96 adiw r26, 0x02 ; 2
1330 5ee: 8c 93 st X, r24
1331 5f0: 12 97 sbiw r26, 0x02 ; 2
1332 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
1333 5f2: 52 96 adiw r26, 0x12 ; 18
1334 5f4: 2c 93 st X, r18
1335 5f6: 52 97 sbiw r26, 0x12 ; 18
1336
1337 //Configuracion pines del puerto A: LOCKOUT
1338 //Pines de salida LOCK_OUT
1339 //Pines de salida en baja
1340 PORT_LOCKOUT.DIRSET = LOCK_OUT;
1341 5f8: c0 e0 ldi r28, 0x00 ; 0
1342 5fa: d6 e0 ldi r29, 0x06 ; 6
1343 5fc: 21 e0 ldi r18, 0x01 ; 1
1344 5fe: 29 83 std Y+1, r18 ; 0x01
1345 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
1346 600: 2e 83 std Y+6, r18 ; 0x06
1347
1348
1349
1350 //Configuracion de interrupciones de LOCK_FPGA
1351
1352 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
1353 602: 21 85 ldd r18, Z+9 ; 0x09
1354 604: 23 60 ori r18, 0x03 ; 3
1355 606: 21 87 std Z+9, r18 ; 0x09
1356 PORT_FPGA.INT0MASK = LOCK_FPGA;
1357 608: 92 87 std Z+10, r25 ; 0x0a
1358 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
1359 60a: 91 89 ldd r25, Z+17 ; 0x11
1360 60c: 98 7f andi r25, 0xF8 ; 248
1361 60e: 91 8b std Z+17, r25 ; 0x11
1362 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
1363 //PORT_FPGA.INT1MASK = CLK_FPGA;
1364 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
1365
1366 //Configuracion de interrupciones de PPS
1367 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
1368 610: 91 85 ldd r25, Z+9 ; 0x09
1369 612: 93 7f andi r25, 0xF3 ; 243
1370 614: 98 60 ori r25, 0x08 ; 8
1371 616: 19 96 adiw r26, 0x09 ; 9
1372 618: 9c 93 st X, r25
1373 61a: 19 97 sbiw r26, 0x09 ; 9
1374 PORT_PPS.INT1MASK = PPS_FPGA;
1375 61c: 1b 96 adiw r26, 0x0b ; 11
1376 61e: 8c 93 st X, r24
1377 620: 1b 97 sbiw r26, 0x0b ; 11
1378 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
1379 622: 52 96 adiw r26, 0x12 ; 18
1380 624: 8c 91 ld r24, X
1381 626: 52 97 sbiw r26, 0x12 ; 18
1382 628: 88 7f andi r24, 0xF8 ; 248
1383 62a: 81 60 ori r24, 0x01 ; 1
1384 62c: 52 96 adiw r26, 0x12 ; 18
1385 62e: 8c 93 st X, r24
1386 }
1387 630: df 91 pop r29
1388 632: cf 91 pop r28
1389 634: 08 95 ret
1390
1391 00000636 <habilitar_interrupciones_globales>:
1392 PMIC.CTRL |= level_mask;
1393 }
1394
1395 void habilitar_interrupciones_globales( void )
1396 {
1397 sei();
1398 636: 78 94 sei
1399 638: 08 95 ret
1400
1401 0000063a <envio_nibble>:
1402 ...
1403 asm("nop");
1404 asm("nop");
1405 asm("nop");
1406 asm("nop");
1407 asm("nop");
1408 PORT_FPGA.OUTSET = CLK_FPGA;
1409 662: 84 e0 ldi r24, 0x04 ; 4
1410 664: e0 e6 ldi r30, 0x60 ; 96
1411 666: f6 e0 ldi r31, 0x06 ; 6
1412 668: 85 83 std Z+5, r24 ; 0x05
1413 ...
1414 asm("nop");
1415 asm("nop");
1416 asm("nop");
1417 asm("nop");
1418 asm("nop");
1419 PORT_FPGA.OUTCLR = CLK_FPGA;
1420 692: 86 83 std Z+6, r24 ; 0x06
1421 //_delay_ms(100);
1422 temp_regin = PORT_FPGA.OUTCLR;
1423 694: 86 81 ldd r24, Z+6 ; 0x06
1424 temp_dato = fpga_dato & nibble_alto_bm;
1425 //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato >> fpga_salidas_nibblealto_bp);
1426 PORT_FPGA.OUT = (0b01001000);
1427 696: 88 e4 ldi r24, 0x48 ; 72
1428 698: 84 83 std Z+4, r24 ; 0x04
1429 ...
1430 asm("nop");
1431 asm("nop");
1432 asm("nop");
1433 asm("nop");
1434 asm("nop");
1435 PORT_FPGA.OUTSET = CLK_FPGA;
1436 6c2: 84 e0 ldi r24, 0x04 ; 4
1437 6c4: 85 83 std Z+5, r24 ; 0x05
1438 ...
1439 asm("nop");
1440 asm("nop");
1441 asm("nop");
1442 //_delay_ms(200);
1443 //Nibble inferior 3 a 0
1444 PORT_FPGA.OUTCLR = CLK_FPGA;
1445 6ee: 86 83 std Z+6, r24 ; 0x06
1446 temp_regin = PORT_FPGA.OUTCLR;
1447 6f0: 86 81 ldd r24, Z+6 ; 0x06
1448 temp_dato = fpga_dato & nibble_bajo_bm;
1449 //_delay_ms(100);
1450 //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato << fpga_salidas_nibblebajo_bp);
1451 PORT_FPGA.OUT = (0b01100000);
1452 6f2: 80 e6 ldi r24, 0x60 ; 96
1453 6f4: 84 83 std Z+4, r24 ; 0x04
1454 ...
1455 asm("nop");
1456 asm("nop");
1457 asm("nop");
1458 asm("nop");
1459 asm("nop");
1460 PORT_FPGA.OUTSET = CLK_FPGA;
1461 71e: 84 e0 ldi r24, 0x04 ; 4
1462 720: 85 83 std Z+5, r24 ; 0x05
1463 ...
1464 asm("nop");
1465 asm("nop");
1466 asm("nop");
1467 asm("nop");
1468 asm("nop");
1469 asm("nop");
1470 746: 08 95 ret
1471
1472 00000748 <envio_dato_adc>:
1473 //envio_dato_adc(aux_dato);
1474 envio_dato_adc(fpga_dato);
1475 }
1476
1477 void envio_dato_adc(uint8_t* dato_adc)
1478 {
1479 748: 0f 93 push r16
1480 74a: 1f 93 push r17
1481 74c: cf 93 push r28
1482 74e: df 93 push r29
1483 750: 8c 01 movw r16, r24
1484 //dato_adc[1] = 0b11111110;
1485 //dato_adc[0] = 0b11111110;
1486 //dato_adc[2] = 0b11111110;
1487 //dato_adc[1] = 0b11111111;
1488 //dato_adc[0] = 0b11111110;
1489 for(int i=0; i<ADC_DATASZ ; i++)
1490 752: c0 e0 ldi r28, 0x00 ; 0
1491 754: d0 e0 ldi r29, 0x00 ; 0
1492 envio_nibble(dato_adc[i]);
1493 756: f8 01 movw r30, r16
1494 758: 81 91 ld r24, Z+
1495 75a: 8f 01 movw r16, r30
1496 75c: 0e 94 1d 03 call 0x63a ; 0x63a <envio_nibble>
1497 //dato_adc[1] = 0b11111110;
1498 //dato_adc[0] = 0b11111110;
1499 //dato_adc[2] = 0b11111110;
1500 //dato_adc[1] = 0b11111111;
1501 //dato_adc[0] = 0b11111110;
1502 for(int i=0; i<ADC_DATASZ ; i++)
1503 760: 21 96 adiw r28, 0x01 ; 1
1504 762: c3 30 cpi r28, 0x03 ; 3
1505 764: d1 05 cpc r29, r1
1506 766: b9 f7 brne .-18 ; 0x756 <envio_dato_adc+0xe>
1507 envio_nibble(dato_adc[i]);
1508
1509 //envio_nibble(dato_adc[0]);
1510 }
1511 768: df 91 pop r29
1512 76a: cf 91 pop r28
1513 76c: 1f 91 pop r17
1514 76e: 0f 91 pop r16
1515 770: 08 95 ret
1516
1517 00000772 <envio_datos_fpga>:
1518 asm("nop");
1519 //_delay_ms(200);
1520 }
1521
1522 void envio_datos_fpga(void)
1523 {
1524 772: cf 93 push r28
1525 774: df 93 push r29
1526 776: 00 d0 rcall .+0 ; 0x778 <envio_datos_fpga+0x6>
1527 778: 1f 92 push r1
1528 77a: cd b7 in r28, 0x3d ; 61
1529 77c: de b7 in r29, 0x3e ; 62
1530 uint8_t fpga_dato[ADC_DATASZ] ;
1531 //uint8_t aux_dato[ADC_DATASZ] ;
1532
1533 adcport_read_data(fpga_dato,ADC_DATASZ);
1534 77e: 63 e0 ldi r22, 0x03 ; 3
1535 780: 70 e0 ldi r23, 0x00 ; 0
1536 782: ce 01 movw r24, r28
1537 784: 01 96 adiw r24, 0x01 ; 1
1538 786: 0e 94 ca 00 call 0x194 ; 0x194 <adcport_read_data>
1539 //aux_dato[1] = fpga_dato[1];
1540 //aux_dato[2] = fpga_dato[2];
1541 //adcport_read_data(fpga_dato,ADC_DATASZ);
1542
1543 //envio_dato_adc(aux_dato);
1544 envio_dato_adc(fpga_dato);
1545 78a: ce 01 movw r24, r28
1546 78c: 01 96 adiw r24, 0x01 ; 1
1547 78e: 0e 94 a4 03 call 0x748 ; 0x748 <envio_dato_adc>
1548 }
1549 792: 23 96 adiw r28, 0x03 ; 3
1550 794: cd bf out 0x3d, r28 ; 61
1551 796: de bf out 0x3e, r29 ; 62
1552 798: df 91 pop r29
1553 79a: cf 91 pop r28
1554 79c: 08 95 ret
1555
1556 0000079e <config_puertos>:
1557 #include "commSPI_ADC.h"
1558
1559 inline void config_puertos(void){
1560 //Configuracion pines del puerto A: PA7-PA0
1561 //Pines de entrada y totem_pullup
1562 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
1563 79e: e0 e0 ldi r30, 0x00 ; 0
1564 7a0: f6 e0 ldi r31, 0x06 ; 6
1565 7a2: 88 e1 ldi r24, 0x18 ; 24
1566 7a4: 87 8b std Z+23, r24 ; 0x17
1567 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
1568 7a6: 86 8b std Z+22, r24 ; 0x16
1569 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
1570 7a8: 85 8b std Z+21, r24 ; 0x15
1571 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
1572 7aa: 84 8b std Z+20, r24 ; 0x14
1573 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
1574 7ac: 83 8b std Z+19, r24 ; 0x13
1575 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
1576 7ae: 82 8b std Z+18, r24 ; 0x12
1577 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
1578 7b0: 81 8b std Z+17, r24 ; 0x11
1579 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
1580 7b2: 9e ef ldi r25, 0xFE ; 254
1581 7b4: 92 83 std Z+2, r25 ; 0x02
1582 //Pin de salida A0
1583 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
1584 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
1585 //Valor por defecto salida: PA0 = low
1586
1587 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
1588 7b6: 98 e3 ldi r25, 0x38 ; 56
1589 7b8: 90 8b std Z+16, r25 ; 0x10
1590 PORTA.OUTCLR = PIN0_bm;
1591 7ba: 91 e0 ldi r25, 0x01 ; 1
1592 7bc: 96 83 std Z+6, r25 ; 0x06
1593 PORTA.DIRSET = PIN0_bm;
1594 7be: 91 83 std Z+1, r25 ; 0x01
1595
1596 //Configuracion pines del puerto B: PB3-PB0
1597 //Pines de entrada y totem_pullup
1598 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
1599 7c0: e0 e2 ldi r30, 0x20 ; 32
1600 7c2: f6 e0 ldi r31, 0x06 ; 6
1601 7c4: 83 8b std Z+19, r24 ; 0x13
1602 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
1603 7c6: 82 8b std Z+18, r24 ; 0x12
1604 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
1605 7c8: 81 8b std Z+17, r24 ; 0x11
1606 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
1607 7ca: 80 8b std Z+16, r24 ; 0x10
1608 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
1609 7cc: 2f e0 ldi r18, 0x0F ; 15
1610 7ce: 22 83 std Z+2, r18 ; 0x02
1611
1612 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
1613 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
1614 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
1615 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
1616 7d0: e0 e4 ldi r30, 0x40 ; 64
1617 7d2: f6 e0 ldi r31, 0x06 ; 6
1618 7d4: 86 8b std Z+22, r24 ; 0x16
1619 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
1620 7d6: 83 8b std Z+19, r24 ; 0x13
1621 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
1622 7d8: 82 8b std Z+18, r24 ; 0x12
1623 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
1624 7da: 81 8b std Z+17, r24 ; 0x11
1625 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
1626 7dc: 80 8b std Z+16, r24 ; 0x10
1627 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
1628 7de: 9f e4 ldi r25, 0x4F ; 79
1629 7e0: 92 83 std Z+2, r25 ; 0x02
1630
1631 //Pines de salida wiredand-pull
1632 //Valor por defecto salida: PC4,PC7 = low
1633 //Valor por defecto salida: PC5 = set
1634
1635 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
1636 7e2: 15 8a std Z+21, r1 ; 0x15
1637 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
1638 7e4: 17 8a std Z+23, r1 ; 0x17
1639 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
1640 7e6: 14 8a std Z+20, r1 ; 0x14
1641 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
1642 7e8: 90 eb ldi r25, 0xB0 ; 176
1643 7ea: 91 83 std Z+1, r25 ; 0x01
1644 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
1645 7ec: 90 e9 ldi r25, 0x90 ; 144
1646 7ee: 95 83 std Z+5, r25 ; 0x05
1647 PORTSPI.OUTCLR = SPI_MOSI_bm;
1648 7f0: 90 e2 ldi r25, 0x20 ; 32
1649 7f2: 96 83 std Z+6, r25 ; 0x06
1650 //Configuracion pines del puerto D: PD7-PD0
1651 //Pines de entrada y totem_pullup: PIN7 y PIN0
1652 //NOTA
1653 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
1654 //NOTA FIN
1655 PORTD.DIRSET = PIN2_bm;
1656 7f4: a0 e6 ldi r26, 0x60 ; 96
1657 7f6: b6 e0 ldi r27, 0x06 ; 6
1658 7f8: 94 e0 ldi r25, 0x04 ; 4
1659 7fa: 11 96 adiw r26, 0x01 ; 1
1660 7fc: 9c 93 st X, r25
1661 7fe: 11 97 sbiw r26, 0x01 ; 1
1662 PORTD.OUTCLR = PIN2_bm;
1663 800: 16 96 adiw r26, 0x06 ; 6
1664 802: 9c 93 st X, r25
1665 804: 16 97 sbiw r26, 0x06 ; 6
1666
1667
1668 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
1669 806: 57 96 adiw r26, 0x17 ; 23
1670 808: 8c 93 st X, r24
1671 80a: 57 97 sbiw r26, 0x17 ; 23
1672 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
1673 80c: 50 96 adiw r26, 0x10 ; 16
1674 80e: 8c 93 st X, r24
1675 810: 50 97 sbiw r26, 0x10 ; 16
1676 PORTD.DIRCLR = PIN7_bm | PIN1_bm| PIN0_bm;
1677 812: 93 e8 ldi r25, 0x83 ; 131
1678 814: 12 96 adiw r26, 0x02 ; 2
1679 816: 9c 93 st X, r25
1680 818: 12 97 sbiw r26, 0x02 ; 2
1681 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
1682 //PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
1683
1684 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
1685 81a: 90 e1 ldi r25, 0x10 ; 16
1686 81c: 51 96 adiw r26, 0x11 ; 17
1687 81e: 9c 93 st X, r25
1688 820: 51 97 sbiw r26, 0x11 ; 17
1689 //Pines de salida tipo wired-and-pull
1690 //Valor por defecto PD6, PD5, PD4, PD3 = low
1691
1692 PORTD.PIN6CTRL = PORT_OPC_TOTEM_gc;
1693 822: 56 96 adiw r26, 0x16 ; 22
1694 824: 1c 92 st X, r1
1695 826: 56 97 sbiw r26, 0x16 ; 22
1696 PORTD.PIN5CTRL = PORT_OPC_TOTEM_gc;
1697 828: 55 96 adiw r26, 0x15 ; 21
1698 82a: 1c 92 st X, r1
1699 82c: 55 97 sbiw r26, 0x15 ; 21
1700 PORTD.PIN4CTRL = PORT_OPC_TOTEM_gc;
1701 82e: 54 96 adiw r26, 0x14 ; 20
1702 830: 1c 92 st X, r1
1703 832: 54 97 sbiw r26, 0x14 ; 20
1704 PORTD.PIN3CTRL = PORT_OPC_TOTEM_gc;
1705 834: 53 96 adiw r26, 0x13 ; 19
1706 836: 1c 92 st X, r1
1707 838: 53 97 sbiw r26, 0x13 ; 19
1708 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
1709 83a: 38 e7 ldi r19, 0x78 ; 120
1710 83c: 11 96 adiw r26, 0x01 ; 1
1711 83e: 3c 93 st X, r19
1712 840: 11 97 sbiw r26, 0x01 ; 1
1713 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
1714 842: 16 96 adiw r26, 0x06 ; 6
1715 844: 3c 93 st X, r19
1716
1717 //Configuracion pines del puerto E: PE3-PE0
1718 //Pines de entrada y totem_pullup: PIN3 - PIN0
1719
1720 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
1721 846: a0 e8 ldi r26, 0x80 ; 128
1722 848: b6 e0 ldi r27, 0x06 ; 6
1723 84a: 53 96 adiw r26, 0x13 ; 19
1724 84c: 8c 93 st X, r24
1725 84e: 53 97 sbiw r26, 0x13 ; 19
1726 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
1727 850: 52 96 adiw r26, 0x12 ; 18
1728 852: 8c 93 st X, r24
1729 854: 52 97 sbiw r26, 0x12 ; 18
1730 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
1731 856: 51 96 adiw r26, 0x11 ; 17
1732 858: 8c 93 st X, r24
1733 85a: 51 97 sbiw r26, 0x11 ; 17
1734 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
1735 85c: 50 96 adiw r26, 0x10 ; 16
1736 85e: 8c 93 st X, r24
1737 860: 50 97 sbiw r26, 0x10 ; 16
1738 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
1739 862: 12 96 adiw r26, 0x02 ; 2
1740 864: 2c 93 st X, r18
1741
1742 //Configuracion pines del puerto R: PR1-PR0
1743 //Pines de entrada y totem_pulldown: PIN0
1744 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
1745 866: a0 ee ldi r26, 0xE0 ; 224
1746 868: b7 e0 ldi r27, 0x07 ; 7
1747 86a: 51 96 adiw r26, 0x11 ; 17
1748 86c: 9c 93 st X, r25
1749 86e: 51 97 sbiw r26, 0x11 ; 17
1750 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
1751 870: 93 e0 ldi r25, 0x03 ; 3
1752 872: 12 96 adiw r26, 0x02 ; 2
1753 874: 9c 93 st X, r25
1754 876: 12 97 sbiw r26, 0x02 ; 2
1755 //Pines de entrada y totem_pulldup:PIN1
1756 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
1757 878: 50 96 adiw r26, 0x10 ; 16
1758 87a: 8c 93 st X, r24
1759
1760 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
1761
1762 PORTSPI.INT0MASK = SPI_MISO_bm;
1763 87c: 80 e4 ldi r24, 0x40 ; 64
1764 87e: 82 87 std Z+10, r24 ; 0x0a
1765 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
1766 880: 81 85 ldd r24, Z+9 ; 0x09
1767 882: 8c 7f andi r24, 0xFC ; 252
1768 884: 81 60 ori r24, 0x01 ; 1
1769 886: 81 87 std Z+9, r24 ; 0x09
1770 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
1771 888: 86 89 ldd r24, Z+22 ; 0x16
1772 88a: 88 7f andi r24, 0xF8 ; 248
1773 88c: 82 60 ori r24, 0x02 ; 2
1774 88e: 86 8b std Z+22, r24 ; 0x16
1775 890: 08 95 ret
1776
1777 00000892 <config_sysclock>:
1778 #define F_CPU 32000000UL
1779 #include <avr/io.h>
1780
1781 void config_sysclock(void){
1782
1783 CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1
1784 892: 10 92 41 00 sts 0x0041, r1
1785 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */
1786 896: e0 e5 ldi r30, 0x50 ; 80
1787 898: f0 e0 ldi r31, 0x00 ; 0
1788 89a: 80 81 ld r24, Z
1789 89c: 86 60 ori r24, 0x06 ; 6
1790 89e: 80 83 st Z, r24
1791 while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */
1792 8a0: 81 81 ldd r24, Z+1 ; 0x01
1793 8a2: 82 ff sbrs r24, 2
1794 8a4: fd cf rjmp .-6 ; 0x8a0 <config_sysclock+0xe>
1795 while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */
1796 8a6: e0 e5 ldi r30, 0x50 ; 80
1797 8a8: f0 e0 ldi r31, 0x00 ; 0
1798 8aa: 81 81 ldd r24, Z+1 ; 0x01
1799 8ac: 81 ff sbrs r24, 1
1800 8ae: fd cf rjmp .-6 ; 0x8aa <config_sysclock+0x18>
1801 DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */
1802 8b0: 81 e0 ldi r24, 0x01 ; 1
1803 8b2: 80 93 60 00 sts 0x0060, r24
1804 OSC.DFLLCTRL &= 0xFD; //Habilito calibraci�n interna mediante reloj de 32K
1805 8b6: e0 e5 ldi r30, 0x50 ; 80
1806 8b8: f0 e0 ldi r31, 0x00 ; 0
1807 8ba: 96 81 ldd r25, Z+6 ; 0x06
1808 8bc: 9d 7f andi r25, 0xFD ; 253
1809 8be: 96 83 std Z+6, r25 ; 0x06
1810 CCP = CCP_IOREG_gc; /* Disable register security for clock update */
1811 8c0: 98 ed ldi r25, 0xD8 ; 216
1812 8c2: 94 bf out 0x34, r25 ; 52
1813 CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */
1814 8c4: 80 93 40 00 sts 0x0040, r24
1815 OSC.CTRL &= ~OSC_RC2MEN_bm;
1816 8c8: 80 81 ld r24, Z
1817 8ca: 8e 7f andi r24, 0xFE ; 254
1818 8cc: 80 83 st Z, r24
1819 8ce: 08 95 ret
1820
1821 000008d0 <_exit>:
1822 8d0: f8 94 cli
1823
1824 000008d2 <__stop_program>:
1825 8d2: ff cf rjmp .-2 ; 0x8d2 <__stop_program>
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (639 lines changed) Show them Hide them
@@ -0,0 +1,639
1 Archive member included because of file (symbol)
2
3 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o (exit)
5 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
6 main.o (__do_clear_bss)
7
8 Discarded input sections
9
10 .data 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
11 .bss 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
12 .text 0x00000000 0x0 ADC_7176_2.o
13 .data 0x00000000 0x0 ADC_7176_2.o
14 .bss 0x00000000 0x0 ADC_7176_2.o
15 .text.test_adc
16 0x00000000 0x4a ADC_7176_2.o
17 .text.test_adc_2
18 0x00000000 0x42 ADC_7176_2.o
19 .text.test_adc_3
20 0x00000000 0x4a ADC_7176_2.o
21 .text.adcport_tranceiv
22 0x00000000 0x14 ADC_7176_2.o
23 .text.adcport_read_data_contread
24 0x00000000 0x24 ADC_7176_2.o
25 .text.adcport_read_data_synconv
26 0x00000000 0x54 ADC_7176_2.o
27 .text.adcport_write_adcmode_2
28 0x00000000 0x44 ADC_7176_2.o
29 .text.adcport_read_filtcon0
30 0x00000000 0x3a ADC_7176_2.o
31 .text 0x00000000 0x0 main.o
32 .data 0x00000000 0x0 main.o
33 .bss 0x00000000 0x0 main.o
34 .text 0x00000000 0x0 commSPI_ADC.o
35 .data 0x00000000 0x0 commSPI_ADC.o
36 .bss 0x00000000 0x0 commSPI_ADC.o
37 .text 0x00000000 0x0 fpga_port.o
38 .data 0x00000000 0x0 fpga_port.o
39 .bss 0x00000000 0x0 fpga_port.o
40 .text.habilitar_interrupciones
41 0x00000000 0xc fpga_port.o
42 .text.deshabilitar_interrupciones_globales
43 0x00000000 0x4 fpga_port.o
44 .text 0x00000000 0x0 Ports.o
45 .data 0x00000000 0x0 Ports.o
46 .bss 0x00000000 0x0 Ports.o
47 .text 0x00000000 0x0 sys_clock.o
48 .data 0x00000000 0x0 sys_clock.o
49 .bss 0x00000000 0x0 sys_clock.o
50 .text 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
51 .data 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
52 .bss 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
53 .text.libgcc.mul
54 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
55 .text.libgcc.div
56 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
57 .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
58 .text.libgcc.prologue
59 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
60 .text.libgcc.builtins
61 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
62 .text.libgcc.fmul
63 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
64 .text.libgcc.fixed
65 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
66 .text 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
67 .data 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
68 .bss 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
69 .text.libgcc.mul
70 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
71 .text.libgcc.div
72 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
73 .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
74 .text.libgcc.prologue
75 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
76 .text.libgcc.builtins
77 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
78 .text.libgcc.fmul
79 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
80 .text.libgcc.fixed
81 0x00000000 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
82
83 Memory Configuration
84
85 Name Origin Length Attributes
86 text 0x00000000 0x00100000 xr
87 data 0x00802000 0x0000ffa0 rw !x
88 eeprom 0x00810000 0x00010000 rw !x
89 fuse 0x00820000 0x00000400 rw !x
90 lock 0x00830000 0x00000400 rw !x
91 signature 0x00840000 0x00000400 rw !x
92 user_signatures 0x00850000 0x00000400 rw !x
93 *default* 0x00000000 0xffffffff
94
95 Linker script and memory map
96
97 LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
98 LOAD ADC_7176_2.o
99 LOAD main.o
100 LOAD commSPI_ADC.o
101 LOAD fpga_port.o
102 LOAD Ports.o
103 LOAD sys_clock.o
104 START GROUP
105 LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2\libm.a
106 END GROUP
107 START GROUP
108 LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a
109 LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2\libm.a
110 LOAD c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2\libc.a
111 END GROUP
112
113 .hash
114 *(.hash)
115
116 .dynsym
117 *(.dynsym)
118
119 .dynstr
120 *(.dynstr)
121
122 .gnu.version
123 *(.gnu.version)
124
125 .gnu.version_d
126 *(.gnu.version_d)
127
128 .gnu.version_r
129 *(.gnu.version_r)
130
131 .rel.init
132 *(.rel.init)
133
134 .rela.init
135 *(.rela.init)
136
137 .rel.text
138 *(.rel.text)
139 *(.rel.text.*)
140 *(.rel.gnu.linkonce.t*)
141
142 .rela.text
143 *(.rela.text)
144 *(.rela.text.*)
145 *(.rela.gnu.linkonce.t*)
146
147 .rel.fini
148 *(.rel.fini)
149
150 .rela.fini
151 *(.rela.fini)
152
153 .rel.rodata
154 *(.rel.rodata)
155 *(.rel.rodata.*)
156 *(.rel.gnu.linkonce.r*)
157
158 .rela.rodata
159 *(.rela.rodata)
160 *(.rela.rodata.*)
161 *(.rela.gnu.linkonce.r*)
162
163 .rel.data
164 *(.rel.data)
165 *(.rel.data.*)
166 *(.rel.gnu.linkonce.d*)
167
168 .rela.data
169 *(.rela.data)
170 *(.rela.data.*)
171 *(.rela.gnu.linkonce.d*)
172
173 .rel.ctors
174 *(.rel.ctors)
175
176 .rela.ctors
177 *(.rela.ctors)
178
179 .rel.dtors
180 *(.rel.dtors)
181
182 .rela.dtors
183 *(.rela.dtors)
184
185 .rel.got
186 *(.rel.got)
187
188 .rela.got
189 *(.rela.got)
190
191 .rel.bss
192 *(.rel.bss)
193
194 .rela.bss
195 *(.rela.bss)
196
197 .rel.plt
198 *(.rel.plt)
199
200 .rela.plt
201 *(.rela.plt)
202
203 .text 0x00000000 0x8d4
204 *(.vectors)
205 .vectors 0x00000000 0x16c c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
206 0x00000000 __vector_default
207 0x00000000 __vectors
208 *(.vectors)
209 *(.progmem.gcc*)
210 0x0000016c . = ALIGN (0x2)
211 0x0000016c __trampolines_start = .
212 *(.trampolines)
213 .trampolines 0x0000016c 0x0 linker stubs
214 *(.trampolines*)
215 0x0000016c __trampolines_end = .
216 *(.progmem*)
217 0x0000016c . = ALIGN (0x2)
218 *(.jumptables)
219 *(.jumptables*)
220 *(.lowtext)
221 *(.lowtext*)
222 0x0000016c __ctors_start = .
223 *(.ctors)
224 0x0000016c __ctors_end = .
225 0x0000016c __dtors_start = .
226 *(.dtors)
227 0x0000016c __dtors_end = .
228 SORT(*)(.ctors)
229 SORT(*)(.dtors)
230 *(.init0)
231 .init0 0x0000016c 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
232 0x0000016c __init
233 *(.init0)
234 *(.init1)
235 *(.init1)
236 *(.init2)
237 .init2 0x0000016c 0xc c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
238 *(.init2)
239 *(.init3)
240 *(.init3)
241 *(.init4)
242 .init4 0x00000178 0x10 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_clear_bss.o)
243 0x00000178 __do_clear_bss
244 *(.init4)
245 *(.init5)
246 *(.init5)
247 *(.init6)
248 *(.init6)
249 *(.init7)
250 *(.init7)
251 *(.init8)
252 *(.init8)
253 *(.init9)
254 .init9 0x00000188 0x8 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
255 *(.init9)
256 *(.text)
257 .text 0x00000190 0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/../../../../avr/lib/avrxmega2/crtx32d4.o
258 0x00000190 __vector_38
259 0x00000190 __vector_22
260 0x00000190 __vector_63
261 0x00000190 __vector_28
262 0x00000190 __vector_67
263 0x00000190 __vector_1
264 0x00000190 __vector_32
265 0x00000190 __vector_75
266 0x00000190 __vector_71
267 0x00000190 __vector_34
268 0x00000190 __vector_62
269 0x00000190 __vector_77
270 0x00000190 __vector_24
271 0x00000190 __vector_12
272 0x00000190 __vector_55
273 0x00000190 __vector_69
274 0x00000190 __vector_81
275 0x00000190 __vector_90
276 0x00000190 __vector_46
277 0x00000190 __bad_interrupt
278 0x00000190 __vector_72
279 0x00000190 __vector_6
280 0x00000190 __vector_31
281 0x00000190 __vector_78
282 0x00000190 __vector_74
283 0x00000190 __vector_39
284 0x00000190 __vector_3
285 0x00000190 __vector_23
286 0x00000190 __vector_68
287 0x00000190 __vector_30
288 0x00000190 __vector_73
289 0x00000190 __vector_45
290 0x00000190 __vector_25
291 0x00000190 __vector_61
292 0x00000190 __vector_11
293 0x00000190 __vector_54
294 0x00000190 __vector_13
295 0x00000190 __vector_17
296 0x00000190 __vector_19
297 0x00000190 __vector_56
298 0x00000190 __vector_7
299 0x00000190 __vector_49
300 0x00000190 __vector_41
301 0x00000190 __vector_86
302 0x00000190 __vector_88
303 0x00000190 __vector_43
304 0x00000190 __vector_27
305 0x00000190 __vector_5
306 0x00000190 __vector_33
307 0x00000190 __vector_76
308 0x00000190 __vector_47
309 0x00000190 __vector_52
310 0x00000190 __vector_37
311 0x00000190 __vector_89
312 0x00000190 __vector_4
313 0x00000190 __vector_44
314 0x00000190 __vector_82
315 0x00000190 __vector_51
316 0x00000190 __vector_9
317 0x00000190 __vector_21
318 0x00000190 __vector_15
319 0x00000190 __vector_66
320 0x00000190 __vector_36
321 0x00000190 __vector_79
322 0x00000190 __vector_58
323 0x00000190 __vector_70
324 0x00000190 __vector_83
325 0x00000190 __vector_29
326 0x00000190 __vector_60
327 0x00000190 __vector_40
328 0x00000190 __vector_85
329 0x00000190 __vector_8
330 0x00000190 __vector_26
331 0x00000190 __vector_48
332 0x00000190 __vector_80
333 0x00000190 __vector_14
334 0x00000190 __vector_84
335 0x00000190 __vector_57
336 0x00000190 __vector_53
337 0x00000190 __vector_10
338 0x00000190 __vector_50
339 0x00000190 __vector_16
340 0x00000190 __vector_59
341 0x00000190 __vector_18
342 0x00000190 __vector_20
343 0x00000190 __vector_42
344 0x00000190 __vector_87
345 0x00000190 __vector_65
346 0x00000194 . = ALIGN (0x2)
347 *(.text.*)
348 .text.adcport_read_data
349 0x00000194 0x34 ADC_7176_2.o
350 0x00000194 adcport_read_data
351 .text.adcport_write_adcmode
352 0x000001c8 0x34 ADC_7176_2.o
353 0x000001c8 adcport_write_adcmode
354 .text.adcport_write_filtcon0
355 0x000001fc 0x34 ADC_7176_2.o
356 0x000001fc adcport_write_filtcon0
357 .text.adcport_write_interfmode
358 0x00000230 0x32 ADC_7176_2.o
359 0x00000230 adcport_write_interfmode
360 .text.adcport_write_chmapreg0
361 0x00000262 0x36 ADC_7176_2.o
362 0x00000262 adcport_write_chmapreg0
363 .text.adcport_write_chmapreg1
364 0x00000298 0x34 ADC_7176_2.o
365 0x00000298 adcport_write_chmapreg1
366 .text.adcport_write_chmapreg2
367 0x000002cc 0x34 ADC_7176_2.o
368 0x000002cc adcport_write_chmapreg2
369 .text.adcport_write_chmapreg3
370 0x00000300 0x34 ADC_7176_2.o
371 0x00000300 adcport_write_chmapreg3
372 .text.adcport_write_setupcon0
373 0x00000334 0x36 ADC_7176_2.o
374 0x00000334 adcport_write_setupcon0
375 .text.adcport_write_reset
376 0x0000036a 0x86 ADC_7176_2.o
377 0x0000036a adcport_write_reset
378 .text.config_adc
379 0x000003f0 0x4c ADC_7176_2.o
380 0x000003f0 config_adc
381 .text.main 0x0000043c 0x22 main.o
382 0x0000043c main
383 .text.__vector_64
384 0x0000045e 0x68 main.o
385 0x0000045e __vector_64
386 .text.__vector_35
387 0x000004c6 0x92 main.o
388 0x000004c6 __vector_35
389 .text.__vector_2
390 0x00000558 0x70 main.o
391 0x00000558 __vector_2
392 .text.config_spiparm
393 0x000005c8 0x8 commSPI_ADC.o
394 0x000005c8 config_spiparm
395 .text.config_fpgaport
396 0x000005d0 0x66 fpga_port.o
397 0x000005d0 config_fpgaport
398 .text.habilitar_interrupciones_globales
399 0x00000636 0x4 fpga_port.o
400 0x00000636 habilitar_interrupciones_globales
401 .text.envio_nibble
402 0x0000063a 0x10e fpga_port.o
403 0x0000063a envio_nibble
404 .text.envio_dato_adc
405 0x00000748 0x2a fpga_port.o
406 0x00000748 envio_dato_adc
407 .text.envio_datos_fpga
408 0x00000772 0x2c fpga_port.o
409 0x00000772 envio_datos_fpga
410 .text.config_puertos
411 0x0000079e 0xf4 Ports.o
412 0x0000079e config_puertos
413 .text.config_sysclock
414 0x00000892 0x3e sys_clock.o
415 0x00000892 config_sysclock
416 0x000008d0 . = ALIGN (0x2)
417 *(.fini9)
418 .fini9 0x000008d0 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
419 0x000008d0 _exit
420 0x000008d0 exit
421 *(.fini9)
422 *(.fini8)
423 *(.fini8)
424 *(.fini7)
425 *(.fini7)
426 *(.fini6)
427 *(.fini6)
428 *(.fini5)
429 *(.fini5)
430 *(.fini4)
431 *(.fini4)
432 *(.fini3)
433 *(.fini3)
434 *(.fini2)
435 *(.fini2)
436 *(.fini1)
437 *(.fini1)
438 *(.fini0)
439 .fini0 0x000008d0 0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o)
440 *(.fini0)
441 0x000008d4 _etext = .
442
443 .data 0x00802000 0x0 load address 0x000008d4
444 0x00802000 PROVIDE (__data_start, .)
445 *(.data)
446 *(.data*)
447 *(.rodata)
448 *(.rodata*)
449 *(.gnu.linkonce.d*)
450 0x00802000 . = ALIGN (0x2)
451 0x00802000 _edata = .
452 0x00802000 PROVIDE (__data_end, .)
453
454 .bss 0x00802000 0x2
455 0x00802000 PROVIDE (__bss_start, .)
456 *(.bss)
457 *(.bss*)
458 .bss.aux 0x00802000 0x2 main.o
459 0x00802000 aux
460 *(COMMON)
461 0x00802002 PROVIDE (__bss_end, .)
462 0x000008d4 __data_load_start = LOADADDR (.data)
463 0x000008d4 __data_load_end = (__data_load_start + SIZEOF (.data))
464
465 .noinit 0x00802002 0x0
466 0x00802002 PROVIDE (__noinit_start, .)
467 *(.noinit*)
468 0x00802002 PROVIDE (__noinit_end, .)
469 0x00802002 _end = .
470 0x00802002 PROVIDE (__heap_start, .)
471
472 .eeprom 0x00810000 0x0
473 *(.eeprom*)
474 0x00810000 __eeprom_end = .
475
476 .fuse
477 *(.fuse)
478 *(.lfuse)
479 *(.hfuse)
480 *(.efuse)
481
482 .lock
483 *(.lock*)
484
485 .signature
486 *(.signature*)
487
488 .user_signatures
489 *(.user_signatures*)
490
491 .stab
492 *(.stab)
493
494 .stabstr
495 *(.stabstr)
496
497 .stab.excl
498 *(.stab.excl)
499
500 .stab.exclstr
501 *(.stab.exclstr)
502
503 .stab.index
504 *(.stab.index)
505
506 .stab.indexstr
507 *(.stab.indexstr)
508
509 .comment 0x00000000 0x30
510 *(.comment)
511 .comment 0x00000000 0x30 ADC_7176_2.o
512 0x31 (size before relaxing)
513 .comment 0x00000000 0x31 main.o
514 .comment 0x00000000 0x31 commSPI_ADC.o
515 .comment 0x00000000 0x31 fpga_port.o
516 .comment 0x00000000 0x31 Ports.o
517 .comment 0x00000000 0x31 sys_clock.o
518
519 .note.gnu.build-id
520 *(.note.gnu.build-id)
521
522 .debug
523 *(.debug)
524
525 .line
526 *(.line)
527
528 .debug_srcinfo
529 *(.debug_srcinfo)
530
531 .debug_sfnames
532 *(.debug_sfnames)
533
534 .debug_aranges 0x00000000 0x198
535 *(.debug_aranges)
536 .debug_aranges
537 0x00000000 0xb0 ADC_7176_2.o
538 .debug_aranges
539 0x000000b0 0x38 main.o
540 .debug_aranges
541 0x000000e8 0x20 commSPI_ADC.o
542 .debug_aranges
543 0x00000108 0x50 fpga_port.o
544 .debug_aranges
545 0x00000158 0x20 Ports.o
546 .debug_aranges
547 0x00000178 0x20 sys_clock.o
548
549 .debug_pubnames
550 *(.debug_pubnames)
551
552 .debug_info 0x00000000 0x1a04
553 *(.debug_info .gnu.linkonce.wi.*)
554 .debug_info 0x00000000 0xbc5 ADC_7176_2.o
555 .debug_info 0x00000bc5 0x3d8 main.o
556 .debug_info 0x00000f9d 0xf0 commSPI_ADC.o
557 .debug_info 0x0000108d 0x487 fpga_port.o
558 .debug_info 0x00001514 0x2ab Ports.o
559 .debug_info 0x000017bf 0x245 sys_clock.o
560
561 .debug_abbrev 0x00000000 0x726
562 *(.debug_abbrev)
563 .debug_abbrev 0x00000000 0x21e ADC_7176_2.o
564 .debug_abbrev 0x0000021e 0x17a main.o
565 .debug_abbrev 0x00000398 0x83 commSPI_ADC.o
566 .debug_abbrev 0x0000041b 0x1a8 fpga_port.o
567 .debug_abbrev 0x000005c3 0xaa Ports.o
568 .debug_abbrev 0x0000066d 0xb9 sys_clock.o
569
570 .debug_line 0x00000000 0xc70
571 *(.debug_line .debug_line.* .debug_line_end)
572 .debug_line 0x00000000 0x43a ADC_7176_2.o
573 .debug_line 0x0000043a 0x24b main.o
574 .debug_line 0x00000685 0x127 commSPI_ADC.o
575 .debug_line 0x000007ac 0x239 fpga_port.o
576 .debug_line 0x000009e5 0x153 Ports.o
577 .debug_line 0x00000b38 0x138 sys_clock.o
578
579 .debug_frame 0x00000000 0x34c
580 *(.debug_frame)
581 .debug_frame 0x00000000 0x154 ADC_7176_2.o
582 .debug_frame 0x00000154 0xd8 main.o
583 .debug_frame 0x0000022c 0x24 commSPI_ADC.o
584 .debug_frame 0x00000250 0xb4 fpga_port.o
585 .debug_frame 0x00000304 0x24 Ports.o
586 .debug_frame 0x00000328 0x24 sys_clock.o
587
588 .debug_str 0x00000000 0x8ad
589 *(.debug_str)
590 .debug_str 0x00000000 0x417 ADC_7176_2.o
591 0x45a (size before relaxing)
592 .debug_str 0x00000417 0x9d main.o
593 0x367 (size before relaxing)
594 .debug_str 0x000004b4 0x13 commSPI_ADC.o
595 0x1c0 (size before relaxing)
596 .debug_str 0x000004c7 0x284 fpga_port.o
597 0x54e (size before relaxing)
598 .debug_str 0x0000074b 0xd Ports.o
599 0x3f1 (size before relaxing)
600 .debug_str 0x00000758 0x155 sys_clock.o
601 0x2e5 (size before relaxing)
602
603 .debug_loc 0x00000000 0x564
604 *(.debug_loc)
605 .debug_loc 0x00000000 0x26b ADC_7176_2.o
606 .debug_loc 0x0000026b 0x184 main.o
607 .debug_loc 0x000003ef 0x175 fpga_port.o
608
609 .debug_macinfo
610 *(.debug_macinfo)
611
612 .debug_weaknames
613 *(.debug_weaknames)
614
615 .debug_funcnames
616 *(.debug_funcnames)
617
618 .debug_typenames
619 *(.debug_typenames)
620
621 .debug_varnames
622 *(.debug_varnames)
623
624 .debug_pubtypes
625 *(.debug_pubtypes)
626
627 .debug_ranges 0x00000000 0x138
628 *(.debug_ranges)
629 .debug_ranges 0x00000000 0xa0 ADC_7176_2.o
630 .debug_ranges 0x000000a0 0x28 main.o
631 .debug_ranges 0x000000c8 0x10 commSPI_ADC.o
632 .debug_ranges 0x000000d8 0x40 fpga_port.o
633 .debug_ranges 0x00000118 0x10 Ports.o
634 .debug_ranges 0x00000128 0x10 sys_clock.o
635
636 .debug_macro
637 *(.debug_macro)
638 OUTPUT(ADCSPI_v01.elf elf32-avr)
639 LOAD linker stubs
Show file before | Show file after | Hide comments
@@ -0,0 +1,144
1 S01200004144435350495F7630312E7372656328
2 S11300000C94B6000C94C8000C94AC020C94C80078
3 S11300100C94C8000C94C8000C94C8000C94C8003C
4 S11300200C94C8000C94C8000C94C8000C94C8002C
5 S11300300C94C8000C94C8000C94C8000C94C8001C
6 S11300400C94C8000C94C8000C94C8000C94C8000C
7 S11300500C94C8000C94C8000C94C8000C94C800FC
8 S11300600C94C8000C94C8000C94C8000C94C800EC
9 S11300700C94C8000C94C8000C94C8000C94C800DC
10 S11300800C94C8000C94C8000C94C8000C9463022F
11 S11300900C94C8000C94C8000C94C8000C94C800BC
12 S11300A00C94C8000C94C8000C94C8000C94C800AC
13 S11300B00C94C8000C94C8000C94C8000C94C8009C
14 S11300C00C94C8000C94C8000C94C8000C94C8008C
15 S11300D00C94C8000C94C8000C94C8000C94C8007C
16 S11300E00C94C8000C94C8000C94C8000C94C8006C
17 S11300F00C94C8000C94C8000C94C8000C94C8005C
18 S11301000C942F020C94C8000C94C8000C94C800E2
19 S11301100C94C8000C94C8000C94C8000C94C8003B
20 S11301200C94C8000C94C8000C94C8000C94C8002B
21 S11301300C94C8000C94C8000C94C8000C94C8001B
22 S11301400C94C8000C94C8000C94C8000C94C8000B
23 S11301500C94C8000C94C8000C94C8000C94C800FB
24 S11301600C94C8000C94C8000C94C80011241FBE41
25 S1130170CFEFCDBFDFE2DEBF20E2A0E0B0E201C0FE
26 S11301801D92A230B207E1F70E941E020C9468048B
27 S11301900C94000024E4E0ECF8E023832281222381
28 S11301A0ECF7E0ECF8E023811616170664F4DC01A2
29 S11301B0860F971F138222812223ECF723812D932C
30 S11301C0A817B907B9F7089581E0E0ECF8E0838354
31 S11301D082818823ECF7E0ECF8E0838180E8838374
32 S11301E082818823ECF7E0ECF8E08381138282813A
33 S11301F08823ECF7E0ECF8E08381089588E2E0ECF2
34 S1130200F8E0838382818823ECF7E0ECF8E08381D3
35 S1130210138282818823ECF7E0ECF8E0838183E0A9
36 S1130220838382818823ECF7E0ECF8E083810895EE
37 S113023082E0E0ECF8E0838382818823ECF7E0EC51
38 S1130240F8E08381138282818823ECF7E0ECF8E004
39 S11302508381138282818823ECF7E0ECF8E08381C8
40 S1130260089580E1E0ECF8E0838382818823ECF751
41 S1130270E0ECF8E0838180E8838382818823ECF7D3
42 S1130280E0ECF8E0838180E2838382818823ECF7C9
43 S1130290E0ECF8E08381089581E1E0ECF8E0838309
44 S11302A082818823ECF7E0ECF8E083811382828179
45 S11302B08823ECF7E0ECF8E0838181E0838382819A
46 S11302C08823ECF7E0ECF8E08381089582E1E0EC28
47 S11302D0F8E0838382818823ECF7E0ECF8E0838103
48 S11302E0138282818823ECF7E0ECF8E0838181E0DB
49 S11302F0838382818823ECF7E0ECF8E0838108951E
50 S113030083E1E0ECF8E0838382818823ECF7E0EC7E
51 S1130310F8E08381138282818823ECF7E0ECF8E033
52 S1130320838181E0838382818823ECF7E0ECF8E029
53 S11303308381089580E2E0ECF8E08383828188235E
54 S1130340ECF7E0ECF8E0838180E183838281882309
55 S1130350ECF7E0ECF8E0838180E2838382818823F8
56 S1130360ECF7E0ECF8E0838108958FEFE0ECF8E03F
57 S1130370838382818823ECF7E0ECF8E083818FEFBC
58 S1130380838382818823ECF7E0ECF8E083818FEFAC
59 S1130390838382818823ECF7E0ECF8E083818FEF9C
60 S11303A0838382818823ECF7E0ECF8E083818FEF8C
61 S11303B0838382818823ECF7E0ECF8E083818FEF7C
62 S11303C0838382818823ECF7E0ECF8E083818FEF6C
63 S11303D0838382818823ECF7E0ECF8E083818FEF5C
64 S11303E0838382818823ECF7E0ECF8E0838108952D
65 S11303F01F93CF93DF93C0E4D6E010E11E830E94E5
66 S1130400B5011D838FE599E00197F1F700C0000065
67 S11304101E830E94E4000E9418010E94FE000E94B4
68 S11304209A010E9431010E944C010E9466010E94BF
69 S113043080011D83DF91CF911F9108950E94CF0306
70 S11304400E9449040E94E4020E94E8020E94F8010A
71 S113045084E0E0EAF0E082830E941B03FFCF1F9256
72 S11304600F920FB60F9211248F939F93EF93FF93E4
73 S1130470E0E6F6E0808581FF11C081E0E0E4F6E08B
74 S1130480848792E0E0E2F6E09487E0EAF0E092818B
75 S113049092609283E0E0F6E085830CC0E0EAF0E04D
76 S11304A082818D7F828382818E7F828381E0E0E0FE
77 S11304B0F6E08683FF91EF919F918F910F900FBE8D
78 S11304C00F901F9018951F920F920FB60F92112440
79 S11304D08F93EF93FF93E0EAF0E082818E7F828333
80 S11304E0E0E4F6E081E084878487000000000000F7
81 S11304F000001092002010920120E0EAF0E08281D6
82 S113050081608283E0E4F6E081E0848780E1858392
83 S1130510000084E0E0E6F6E08583000000000000CF
84 S113052000000000000000000000000000000000C7
85 S11305300000000080E1E0E4F6E086838AE68A9524
86 S1130540F1F700C081E08487FF91EF918F910F90C4
87 S11305500FBE0F901F9018951F920F920FB60F9217
88 S113056011242F933F934F935F936F937F938F93B4
89 S11305709F93AF93BF93EF93FF938091002090914B
90 S1130580012080329E445CF40E94B90380910020D3
91 S1130590909101200196809300209093012081E0A6
92 S11305A0E0E4F6E08487FF91EF91BF91AF919F91D2
93 S11305B08F917F916F915F914F913F912F910F9008
94 S11305C00FBE0F901F9018958CED8093C00808956E
95 S11305D0CF93DF93E0E6F6E0118A92E0928320E184
96 S11305E0228B84E081838683A0E2B6E012968C930A
97 S11305F0129752962C935297C0E0D6E021E02983BB
98 S11306002E8321852360218792879189987F918BFE
99 S11306109185937F986019969C9319971B968C9358
100 S11306201B9752968C915297887F816052968C9337
101 S1130630DF91CF91089578940895000000000000A0
102 S113064000000000000000000000000000000000A6
103 S11306500000000000000000000000000000000096
104 S1130660000084E0E0E6F6E085830000000000007E
105 S11306700000000000000000000000000000000076
106 S11306800000000000000000000000000000000066
107 S113069000008683868188E48483000000000000D3
108 S11306A00000000000000000000000000000000046
109 S11306B00000000000000000000000000000000036
110 S11306C0000084E0858300000000000000000000BA
111 S11306D00000000000000000000000000000000016
112 S11306E000000000000000000000000000008683FD
113 S11306F0868180E684830000000000000000000082
114 S113070000000000000000000000000000000000E5
115 S1130710000000000000000000000000000084E071
116 S113072085830000000000000000000000000000BD
117 S113073000000000000000000000000000000000B5
118 S113074000000000000008950F931F93CF93DF93E0
119 S11307508C01C0E0D0E0F80181918F010E941D035B
120 S11307602196C330D105B9F7DF91CF911F910F9135
121 S11307700895CF93DF9300D01F92CDB7DEB763E027
122 S113078070E0CE0101960E94CA00CE0101960E943B
123 S1130790A4032396CDBFDEBFDF91CF910895E0E09F
124 S11307A0F6E088E1878B868B858B848B838B828BA9
125 S11307B0818B9EEF928398E3908B91E09683918353
126 S11307C0E0E2F6E0838B828B818B808B2FE02283A7
127 S11307D0E0E4F6E0868B838B828B818B808B9FE4B5
128 S11307E09283158A178A148A90EB918390E99583F2
129 S11307F090E29683A0E6B6E094E011969C9311975C
130 S113080016969C93169757968C93579750968C935D
131 S1130810509793E812969C93129790E151969C936B
132 S1130820519756961C92569755961C9255975496E6
133 S11308301C92549753961C92539738E711963C9305
134 S1130840119716963C93A0E8B6E053968C93539771
135 S113085052968C93529751968C93519750968C93B1
136 S1130860509712962C93A0EEB7E051969C93519713
137 S113087093E012969C93129750968C9380E482870F
138 S113088081858C7F816081878689887F8260868B61
139 S1130890089510924100E0E5F0E080818660808355
140 S11308A0818182FFFDCFE0E5F0E0818181FFFDCF12
141 S11308B081E080936000E0E5F0E096819D7F96837F
142 S11308C098ED94BF8093400080818E7F808308954B
143 S10708D0F894FFCFC6
144 S9030000FC
Show file before | Show file after | Hide comments
@@ -0,0 +1,53
1 ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h \
15 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \
16 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \
17 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h
18
19 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
20
21 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
22
23 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
24
25 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
26
27 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
28
29 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
30
31 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
32
33 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
34
35 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
36
37 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
38
39 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
40
41 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
42
43 .././ADC_7176_2.h:
44
45 .././Ports.h:
46
47 .././commSPI_ADC.h:
48
49 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h:
50
51 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h:
52
53 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,164
1 ################################################################################
2 # Automatically-generated file. Do not edit!
3 ################################################################################
4
5 SHELL := cmd.exe
6 RM := rm -rf
7
8 USER_OBJS :=
9
10 LIBS :=
11 PROJ :=
12
13 O_SRCS :=
14 C_SRCS :=
15 S_SRCS :=
16 S_UPPER_SRCS :=
17 OBJ_SRCS :=
18 ASM_SRCS :=
19 PREPROCESSING_SRCS :=
20 OBJS :=
21 OBJS_AS_ARGS :=
22 C_DEPS :=
23 C_DEPS_AS_ARGS :=
24 EXECUTABLES :=
25 OUTPUT_FILE_PATH :=
26 OUTPUT_FILE_PATH_AS_ARGS :=
27 AVR_APP_PATH :=$$$AVR_APP_PATH$$$
28 QUOTE := "
29 ADDITIONAL_DEPENDENCIES:=
30 OUTPUT_FILE_DEP:=
31 LIB_DEP:=
32 LINKER_SCRIPT_DEP:=
33
34 # Every subdirectory with source files must be described here
35 SUBDIRS :=
36
37
38 # Add inputs and outputs from these tool invocations to the build variables
39 C_SRCS += \
40 ../ADC_7176_2.c \
41 ../main.c \
42 ../commSPI_ADC.c \
43 ../fpga_port.c \
44 ../Ports.c \
45 ../sys_clock.c
46
47
48 PREPROCESSING_SRCS +=
49
50
51 ASM_SRCS +=
52
53
54 OBJS += \
55 ADC_7176_2.o \
56 main.o \
57 commSPI_ADC.o \
58 fpga_port.o \
59 Ports.o \
60 sys_clock.o
61
62 OBJS_AS_ARGS += \
63 ADC_7176_2.o \
64 main.o \
65 commSPI_ADC.o \
66 fpga_port.o \
67 Ports.o \
68 sys_clock.o
69
70 C_DEPS += \
71 ADC_7176_2.d \
72 main.d \
73 commSPI_ADC.d \
74 fpga_port.d \
75 Ports.d \
76 sys_clock.d
77
78 C_DEPS_AS_ARGS += \
79 ADC_7176_2.d \
80 main.d \
81 commSPI_ADC.d \
82 fpga_port.d \
83 Ports.d \
84 sys_clock.d
85
86 OUTPUT_FILE_PATH +=ADCSPI_v01.elf
87
88 OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_v01.elf
89
90 ADDITIONAL_DEPENDENCIES:=
91
92 OUTPUT_FILE_DEP:= ./makedep.mk
93
94 LIB_DEP+=
95
96 LINKER_SCRIPT_DEP+=
97
98
99 # AVR32/GNU C Compiler
100
101
102
103
104
105
106
107
108
109
110
111
112
113 ./%.o: .././%.c
114 @echo Building file: $<
115 @echo Invoking: AVR/GNU C Compiler : 4.8.1
116 $(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
117 @echo Finished building: $<
118
119
120
121
122 # AVR32/GNU Preprocessing Assembler
123
124
125
126 # AVR32/GNU Assembler
127
128
129
130
131 ifneq ($(MAKECMDGOALS),clean)
132 ifneq ($(strip $(C_DEPS)),)
133 -include $(C_DEPS)
134 endif
135 endif
136
137 # Add inputs and outputs from these tool invocations to the build variables
138
139 # All Target
140 all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
141
142 $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
143 @echo Building target: $@
144 @echo Invoking: AVR/GNU Linker : 4.8.1
145 $(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_v01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4
146 @echo Finished building target: $@
147 "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_v01.elf" "ADCSPI_v01.hex"
148 "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_v01.elf" "ADCSPI_v01.eep" || exit 0
149 "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_v01.elf" > "ADCSPI_v01.lss"
150 "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_v01.elf" "ADCSPI_v01.srec"
151 "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_v01.elf"
152
153
154
155
156
157
158
159 # Other Targets
160 clean:
161 -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
162 -$(RM) $(C_DEPS_AS_ARGS)
163 rm -rf "ADCSPI_v01.elf" "ADCSPI_v01.a" "ADCSPI_v01.hex" "ADCSPI_v01.lss" "ADCSPI_v01.eep" "ADCSPI_v01.map" "ADCSPI_v01.srec" "ADCSPI_v01.usersignatures"
164 No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,42
1 Ports.d Ports.o: .././Ports.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././Ports.h .././commSPI_ADC.h
15
16 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
17
18 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
19
20 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
21
22 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
23
24 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
25
26 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
27
28 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
29
30 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
31
32 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
33
34 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
35
36 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
37
38 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
39
40 .././Ports.h:
41
42 .././commSPI_ADC.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,42
1 commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././commSPI_ADC.h .././Ports.h
15
16 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
17
18 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
19
20 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
21
22 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
23
24 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
25
26 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
27
28 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
29
30 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
31
32 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
33
34 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
35
36 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
37
38 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
39
40 .././commSPI_ADC.h:
41
42 .././Ports.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,59
1 fpga_port.d fpga_port.o: .././fpga_port.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \
15 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \
16 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h \
17 .././fpga_port.h \
18 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h \
19 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h
20
21 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
22
23 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
24
25 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
26
27 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
28
29 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
30
31 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
32
33 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
34
35 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
36
37 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
38
39 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
40
41 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
42
43 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
44
45 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h:
46
47 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h:
48
49 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h:
50
51 .././fpga_port.h:
52
53 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
54
55 .././ADC_7176_2.h:
56
57 .././Ports.h:
58
59 .././commSPI_ADC.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,61
1 main.d main.o: .././main.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././Ports.h .././sys_clock.h .././ADC_7176_2.h .././commSPI_ADC.h \
15 .././fpga_port.h \
16 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h \
17 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \
18 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \
19 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h
20
21 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
22
23 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
24
25 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
26
27 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
28
29 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
30
31 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
32
33 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
34
35 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
36
37 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
38
39 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
40
41 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
42
43 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
44
45 .././Ports.h:
46
47 .././sys_clock.h:
48
49 .././ADC_7176_2.h:
50
51 .././commSPI_ADC.h:
52
53 .././fpga_port.h:
54
55 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
56
57 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h:
58
59 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h:
60
61 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,16
1 ################################################################################
2 # Automatically-generated file. Do not edit or delete the file
3 ################################################################################
4
5 ADC_7176_2.c
6
7 main.c
8
9 commSPI_ADC.c
10
11 fpga_port.c
12
13 Ports.c
14
15 sys_clock.c
16
Show file before | Show file after | Hide comments
@@ -0,0 +1,37
1 sys_clock.d sys_clock.o: .././sys_clock.c \
2 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \
7 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \
8 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h
14
15 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h:
16
17 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
18
19 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h:
20
21 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h:
22
23 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h:
24
25 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h:
26
27 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h:
28
29 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h:
30
31 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h:
32
33 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h:
34
35 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h:
36
37 c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h:
Show file before | Show file after | Hide comments
@@ -0,0 +1,126
1 /*
2 * Ports.c
3 *
4 * Created: 26/04/16 11:39:52
5 * Author: Francisco
6 */
7 /*!
8 * \fn config_puertos
9 * \brief Configuraci�n de todos los pines de I/O a usarse
10 * para la prueba. Para el firmware final se deben dejar de configurar en este segmento
11 * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo.
12 * Los criterios de asignaci�n de control:
13 * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
14 * Se sabe que la entrada ser� casi siempre alta.
15 * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
16 * Se sabe que la entrada ser� casi siempre baja.
17 * WiredAndpull: Para evitar cortos de una salida al exterior del board.
18 * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board).
19 * \
20 */
21
22 #define F_CPU 32000000UL
23 #include <avr/io.h>
24
25 #include "Ports.h"
26 #include "commSPI_ADC.h"
27
28 inline void config_puertos(void){
29 //Configuracion pines del puerto A: PA7-PA0
30 //Pines de entrada y totem_pullup
31 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
32 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
33 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
34 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
35 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
36 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
37 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
38 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
39
40 //Pin de salida A0
41 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
42 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
43 //Valor por defecto salida: PA0 = low
44
45 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
46 PORTA.OUTCLR = PIN0_bm;
47 PORTA.DIRSET = PIN0_bm;
48
49 //Configuracion pines del puerto B: PB3-PB0
50 //Pines de entrada y totem_pullup
51 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
52 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
53 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
54 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
55 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
56
57 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
58 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
59 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
60 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
61 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
62 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
63 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
64 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
65 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
66
67 //Pines de salida wiredand-pull
68 //Valor por defecto salida: PC4,PC7 = low
69 //Valor por defecto salida: PC5 = set
70
71 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
72 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
73 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
74 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
75 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
76 PORTSPI.OUTCLR = SPI_MOSI_bm;
77
78 //Configuracion pines del puerto D: PD7-PD0
79 //Pines de entrada y totem_pullup: PIN7 y PIN0
80 //NOTA
81 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
82 //NOTA FIN
83 PORTD.DIRSET = PIN2_bm;
84 PORTD.OUTCLR = PIN2_bm;
85
86
87 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
88 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
89 PORTD.DIRCLR = PIN7_bm | PIN1_bm| PIN0_bm;
90 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
91 //PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
92
93 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
94 //Pines de salida tipo wired-and-pull
95 //Valor por defecto PD6, PD5, PD4, PD3 = low
96
97 PORTD.PIN6CTRL = PORT_OPC_TOTEM_gc;
98 PORTD.PIN5CTRL = PORT_OPC_TOTEM_gc;
99 PORTD.PIN4CTRL = PORT_OPC_TOTEM_gc;
100 PORTD.PIN3CTRL = PORT_OPC_TOTEM_gc;
101 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
102 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
103
104 //Configuracion pines del puerto E: PE3-PE0
105 //Pines de entrada y totem_pullup: PIN3 - PIN0
106
107 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
108 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
109 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
110 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
111 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
112
113 //Configuracion pines del puerto R: PR1-PR0
114 //Pines de entrada y totem_pulldown: PIN0
115 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
116 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
117 //Pines de entrada y totem_pulldup:PIN1
118 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
119
120 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
121
122 PORTSPI.INT0MASK = SPI_MISO_bm;
123 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
124 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
125
126 } No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,22
1 /*
2 * Ports.h
3 *
4 * Created: 26/04/16 11:40:34
5 * Author: Francisco
6 */
7
8
9
10 #ifndef PORTS_H_
11 #define PORTS_H_
12
13 #define F_CPU 32000000UL
14 #include <avr/io.h>
15
16 #define INT_RDY PORTC_INT0_vect
17
18 void config_puertos(void);
19
20
21
22 #endif /* PORTS_H_ */ No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,29
1 /*
2 * commSPI_ADC.c
3 *
4 * Created: 26/04/16 11:44:43
5 * Author: Francisco
6 */
7
8 #define F_CPU 32000000UL
9 #include <avr/io.h>
10 #include "commSPI_ADC.h"
11
12 /*!
13 * \fn config_spiparm
14 * \brief Configuraci�n de los par�metros de reloj SPI
15 *
16 * fspi = fper/2 = fcpu/2 = 16MHz
17 *
18 * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una
19 * nueva evaluaci�n
20 * \
21 */
22 inline void config_spiparm(void){
23 // Preescaler: clkper/2 = f_cpu/2.
24 // Master
25 // Mode 3: CPOL=1,CPHA=1
26 // MSB --- LSB
27 SPIC.CTRL = (SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE1_bm | SPI_MODE0_bm | SPI_CLK2X_bm);//SPI_PRESCALER1_bm | SPI_CLK2X_bm);
28 }
29
Show file before | Show file after | Hide comments
@@ -0,0 +1,32
1 /*
2 * commSPI_ADC.h
3 *
4 * Created: 26/04/16 11:46:06
5 * Author: Francisco
6 */
7
8
9 #ifndef COMMSPI_ADC_H_
10 #define COMMSPI_ADC_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14
15 #include "Ports.h"
16
17 #define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI
18
19 #define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS
20 #define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI
21 #define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO
22 #define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK
23
24 #define SPI_SS_bm PIN4_bm // Pin de entrada - Totem
25 #define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem
26 #define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem
27 #define SPI_SCK_bm PIN7_bm // Pin de salida - Totem
28 #define SPI_INTFLAGS INTFLAGS
29 void config_spiparm(void);
30
31
32 #endif /* COMMSPI_ADC_H_ */ No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,259
1 /*
2 * fpga_port.c
3 *
4 * Created: 26/04/16 11:42:02
5 * Author: Francisco
6 */
7
8 #define F_CPU 32000000UL
9 #include <avr/io.h>
10
11 #include <util/delay.h>
12
13 #include "fpga_port.h"
14
15 inline void config_fpgaport()
16 {
17 //Configuracion pines del puerto D: PD6-PA1
18 //Pines de entrada CLK_FPGA, LOCK_FPGA
19 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
20
21 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc;
22 PORT_FPGA.DIRCLR = LOCK_FPGA;
23
24 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
25 PORT_FPGA.DIRSET = CLK_FPGA;
26 PORT_FPGA.OUTCLR = CLK_FPGA;
27
28 //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
29 //PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
30 //PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc;
31 //PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
32
33 //Configuracion pines del puerto B: PPS
34 //Pines de entrada PPS_FPGA
35 //Pines de entrada en pulldown
36 PORT_PPS.DIRCLR = PPS_FPGA;
37 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
38
39 //Configuracion pines del puerto A: LOCKOUT
40 //Pines de salida LOCK_OUT
41 //Pines de salida en baja
42 PORT_LOCKOUT.DIRSET = LOCK_OUT;
43 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
44
45
46
47 //Configuracion de interrupciones de LOCK_FPGA
48
49 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
50 PORT_FPGA.INT0MASK = LOCK_FPGA;
51 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
52
53 //Configuracion de interrupciones de CLK
54 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
55 //PORT_FPGA.INT1MASK = CLK_FPGA;
56 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
57
58 //Configuracion de interrupciones de PPS
59 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
60 PORT_PPS.INT1MASK = PPS_FPGA;
61 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
62 }
63
64 void habilitar_interrupciones( uint8_t level_mask )
65 {
66 PMIC.CTRL |= level_mask;
67 }
68
69 void habilitar_interrupciones_globales( void )
70 {
71 sei();
72 }
73
74 void deshabilitar_interrupciones_globales( void )
75 {
76 cli();
77 }
78
79 void envio_nibble(uint8_t fpga_dato)
80 {
81 uint8_t temp_regin;
82 uint8_t temp_dato;
83 //fpga_dato = 0b100000000000100001110000;
84 //Nibble superior 7 a 4
85 asm("nop");
86 asm("nop");
87 asm("nop");
88 asm("nop");
89 asm("nop");
90 asm("nop");
91 asm("nop");
92 asm("nop");
93 asm("nop");
94 asm("nop");
95 asm("nop");
96 asm("nop");
97 asm("nop");
98 asm("nop");
99 asm("nop");
100 asm("nop");
101 asm("nop");
102 asm("nop");
103 asm("nop");
104 asm("nop");
105 PORT_FPGA.OUTSET = CLK_FPGA;
106 asm("nop");
107 asm("nop");
108 asm("nop");
109 asm("nop");
110 asm("nop");
111 asm("nop");
112 asm("nop");
113 asm("nop");
114 asm("nop");
115 asm("nop");
116 asm("nop");
117 asm("nop");
118 asm("nop");
119 asm("nop");
120 asm("nop");
121 asm("nop");
122 asm("nop");
123 asm("nop");
124 asm("nop");
125 asm("nop");
126 PORT_FPGA.OUTCLR = CLK_FPGA;
127 //_delay_ms(100);
128 temp_regin = PORT_FPGA.OUTCLR;
129 temp_dato = fpga_dato & nibble_alto_bm;
130 //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato >> fpga_salidas_nibblealto_bp);
131 PORT_FPGA.OUT = (0b01001000);
132 asm("nop");
133 asm("nop");
134 asm("nop");
135 asm("nop");
136 asm("nop");
137 asm("nop");
138 asm("nop");
139 asm("nop");
140 asm("nop");
141 asm("nop");
142 asm("nop");
143 asm("nop");
144 asm("nop");
145 asm("nop");
146 asm("nop");
147 asm("nop");
148 asm("nop");
149 asm("nop");
150 asm("nop");
151 asm("nop");
152 PORT_FPGA.OUTSET = CLK_FPGA;
153 asm("nop");
154 asm("nop");
155 asm("nop");
156 asm("nop");
157 asm("nop");
158 asm("nop");
159 asm("nop");
160 asm("nop");
161 asm("nop");
162 asm("nop");
163 asm("nop");
164 asm("nop");
165 asm("nop");
166 asm("nop");
167 asm("nop");
168 asm("nop");
169 asm("nop");
170 asm("nop");
171 asm("nop");
172 asm("nop");
173 //_delay_ms(200);
174 //Nibble inferior 3 a 0
175 PORT_FPGA.OUTCLR = CLK_FPGA;
176 temp_regin = PORT_FPGA.OUTCLR;
177 temp_dato = fpga_dato & nibble_bajo_bm;
178 //_delay_ms(100);
179 //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato << fpga_salidas_nibblebajo_bp);
180 PORT_FPGA.OUT = (0b01100000);
181 asm("nop");
182 asm("nop");
183 asm("nop");
184 asm("nop");
185 asm("nop");
186 asm("nop");
187 asm("nop");
188 asm("nop");
189 asm("nop");
190 asm("nop");
191 asm("nop");
192 asm("nop");
193 asm("nop");
194 asm("nop");
195 asm("nop");
196 asm("nop");
197 asm("nop");
198 asm("nop");
199 asm("nop");
200 asm("nop");
201 PORT_FPGA.OUTSET = CLK_FPGA;
202 asm("nop");
203 asm("nop");
204 asm("nop");
205 asm("nop");
206 asm("nop");
207 asm("nop");
208 asm("nop");
209 asm("nop");
210 asm("nop");
211 asm("nop");
212 asm("nop");
213 asm("nop");
214 asm("nop");
215 asm("nop");
216 asm("nop");
217 asm("nop");
218 asm("nop");
219 asm("nop");
220 //_delay_ms(200);
221 }
222
223 void envio_datos_fpga(void)
224 {
225 uint8_t fpga_dato[ADC_DATASZ] ;
226 //uint8_t aux_dato[ADC_DATASZ] ;
227
228 adcport_read_data(fpga_dato,ADC_DATASZ);
229 //adcport_read_data_synconv(fpga_dato,ADC_DATASZ);
230 //adcport_read_data_contread(fpga_dato,ADC_DATASZ);
231 //aux_dato[0] = fpga_dato[0];
232 //aux_dato[1] = fpga_dato[1];
233 //aux_dato[2] = fpga_dato[2];
234 //adcport_read_data(fpga_dato,ADC_DATASZ);
235
236 //envio_dato_adc(aux_dato);
237 envio_dato_adc(fpga_dato);
238 }
239
240 void envio_dato_adc(uint8_t* dato_adc)
241 {
242 //fpga_dato = 0b100000000000100001110000;
243 //dato_adc[2] = 0b11111101;
244 //dato_adc[1] = 0b11111110;
245 //dato_adc[0] = 0b11111110;
246 //dato_adc[2] = 0b11111110;
247 //dato_adc[1] = 0b11111111;
248 //dato_adc[0] = 0b11111110;
249 for(int i=0; i<ADC_DATASZ ; i++)
250 envio_nibble(dato_adc[i]);
251
252 //envio_nibble(dato_adc[0]);
253 }
254 /*
255 __attribute__((noinline)) void delay_nop(void)
256 {
257 asm("nop");
258 }
259 */
Show file before | Show file after | Hide comments
@@ -0,0 +1,70
1 /*
2 * fpga_port.h
3 *
4 * Created: 26/04/16 11:42:38
5 * Author: Francisco
6 */
7
8
9 #ifndef FPGA_PORT_H_
10 #define FPGA_PORT_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14 #include <avr/interrupt.h>
15 #include "ADC_7176_2.h"
16
17 //Port B
18 #define PORT_PPS PORTB
19 #define PPS_FPGA PIN2_bm
20 #define PPS_FPGA_CTRL PIN2CTRL
21 #define PPS_FPGA_INTFLAGS INTFLAGS
22 #define INT_PPS PORTB_INT1_vect
23
24 //Port A
25 #define PORT_LOCKOUT PORTA
26 #define LOCK_OUT PIN0_bm
27
28
29 //Port D
30 #define PORT_FPGA PORTD
31 #define LOCK_FPGA PIN1_bm
32 #define CLK_FPGA PIN2_bm
33 #define CH_BIT0_FPGA PIN3_bm
34 #define CH_BIT1_FPGA PIN4_bm
35 #define CH_BIT2_FPGA PIN5_bm
36 #define CH_BIT3_FPGA PIN6_bm
37 #define INT_LOCK_FPGA PORTD_INT0_vect
38
39 #define LOCK_FPGA_CTRL PIN1CTRL
40 #define CLK_FPGA_CTRL PIN2CTRL
41 #define CH_BIT0_FPGA_CTRL PIN3CTRL
42 #define CH_BIT1_FPGA_CTRL PIN4CTRL
43 #define CH_BIT2_FPGA_CTRL PIN5CTRL
44 #define CH_BIT3_FPGA_CTRL PIN6CTRL
45
46 void config_fpgaport();
47 void habilitar_interrupciones( uint8_t level_mask );
48 void habilitar_interrupciones_globales( );
49 void deshabilitar_interrupciones_globales( );
50
51 //Habilitar
52 #define hab_prioridad_alta PMIC_HILVLEN_bm
53 #define hab_prioridad_media PMIC_MEDLVLEN_bm
54 #define hab_prioridad_baja PMIC_LOLVLEN_bm
55
56 //M�scara de nibbles
57 #define nibble_alto_bm 0xF0
58 #define nibble_bajo_bm 0x0F
59 #define fpga_salidas_nibblealto_bp 1
60 #define fpga_salidas_nibblebajo_bp 3
61 #define fpga_salidas_bm 0x87
62
63 //funciones de env�o de datos
64 void envio_nibble(uint8_t fpga_dato);
65
66 //funcion interrupcion por flanco de subida de RDY
67 void envio_datos_fpga(void);
68 void envio_dato_adc(uint8_t* dato_adc);
69
70 #endif /* FPGA_PORT_H_ */ No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,149
1 /*
2 * ADCSPI_v01.c
3 *
4 * Created: 26/04/16 11:26:57
5 * Author: Francisco
6 */
7
8 #define F_CPU 32000000UL
9 #include <avr/io.h>
10 #include "Ports.h"
11 //#include "commSPI_ADC.h"
12 #include "sys_clock.h"
13 #include "ADC_7176_2.h"
14 #include "fpga_port.h"
15 #include <util/delay.h>
16
17 int aux = 0;
18 int main(void)
19 {
20 //uint8_t datos_adc[3];
21 config_puertos();
22 config_sysclock();
23 config_spiparm();
24 config_fpgaport();
25 config_adc();
26 //datos_adc[0] = 0x00;
27 //datos_adc[1] = 0x00;
28 //datos_adc[2] = 0x00;
29 //PORTD.OUTSET = PIN5_bm;
30
31 PMIC.CTRL = hab_prioridad_alta;
32 habilitar_interrupciones_globales();
33
34 /* Replace with your application code */
35 //adcport_write_adcmode_2();
36 while (1)
37 {
38 //PORTSPI.OUTCLR = SPI_SS_bm;
39 //if (adcport_read_filtcon0() == ADC_VALFIL0){
40 // PORTD.OUTSET = PIN6_bm | PIN5_bm;
41 // adcport_write_adcmode_2();
42 //while(1){
43 // PORTSPI.OUTCLR = SPI_SS_bm;
44 //}
45 //}
46 //else{
47 // PORTD.OUTCLR = PIN6_bm | PIN5_bm;
48 //}
49 //PORTD.OUTSET = PIN2_bm;
50 //_delay_ms(1000);
51 //PORTD.OUTCLR = PIN2_bm;
52 //_delay_ms(1000);
53 //if (test_adc() == ADC_ID){
54 // PORTD.OUTSET = PIN6_bm | PIN5_bm;
55 // _delay_ms(1000);
56 //}
57
58 //else{
59 // PORTD.OUTCLR = PIN6_bm | PIN5_bm;
60 //}
61 //_delay_ms(10);
62 //test_adc_2(datos_adc);
63 //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){
64 //PORTD.OUTSET = PIN4_bm;
65 //}
66 }
67 return 0;
68 }
69
70
71 ISR(INT_LOCK_FPGA)
72 {
73 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
74 {
75 PORTSPI.SPI_INTFLAGS =0b00000001;
76 PORT_PPS.PPS_FPGA_INTFLAGS =0b00000010;
77 PMIC.CTRL |= hab_prioridad_media;
78 PORT_LOCKOUT.OUTSET = LOCK_OUT;
79 //PORTD.OUTSET = PIN4_bm;
80 }
81 else
82 {
83 PMIC.CTRL &= ~hab_prioridad_media;
84 PMIC.CTRL &= ~hab_prioridad_baja;
85 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
86 //PORTSPI.OUTSET = SPI_SS_bm;
87 //PORTD.OUTCLR = PIN4_bm;
88 }
89 }
90
91 //Interrupcion por flanco de subida de PPS
92 //Habilito interrupciones de prioridad baja
93 //Selecciono el chip del ADC para iniciar comunicaci�n.
94 //Al iniciar esta comunicaci�n se indicar� al ADC que use el RDYbar
95 //Esta ser� nuestra interrupci�n para lectura del ADC y env�o de dato a la FPGA
96 ISR(INT_PPS)
97 {
98 PMIC.CTRL &= ~hab_prioridad_baja;
99 PORTSPI.SPI_INTFLAGS =0b00000001;
100 PORTSPI.SPI_INTFLAGS =0b00000001;
101 asm("nop");
102 asm("nop");
103 asm("nop");
104 asm("nop");
105 aux = 0;
106 //if(aux==0)
107 PMIC.CTRL |= hab_prioridad_baja;
108 PORTSPI.SPI_INTFLAGS =0b00000001;
109 PORTSPI.OUTSET = SPI_SS_bm;
110 asm("nop");
111 PORT_FPGA.OUTSET = CLK_FPGA;
112 //PORT_FPGA.OUT = (0b01111000);
113 asm("nop");
114
115 asm("nop");
116 asm("nop");
117 asm("nop");
118 asm("nop");
119 asm("nop");
120 asm("nop");
121 asm("nop");
122 asm("nop");
123 asm("nop");
124 asm("nop");
125 asm("nop");
126 asm("nop");
127 PORTSPI.OUTCLR = SPI_SS_bm;
128
129 _delay_us(10);
130 PORTSPI.SPI_INTFLAGS =0b00000001;
131 //envio_datos_fpga();
132 //PORTSPI.OUTSET = SPI_SS_bm;
133
134 }
135
136 ISR(INT_RDY)
137 {
138 //PMIC.CTRL &= ~hab_prioridad_media;
139 //PMIC.CTRL &= ~hab_prioridad_alta;
140 if(aux < 20000){
141 envio_datos_fpga();
142 aux = aux+1;
143 }
144 //PORTSPI.OUTCLR = SPI_SS_bm;
145 //adcport_read_filtcon0();
146 //PMIC.CTRL |= hab_prioridad_media;
147 //PMIC.CTRL |= hab_prioridad_alta;
148 PORTSPI.SPI_INTFLAGS =0b00000001;
149 }
Show file before | Show file after | Hide comments
@@ -0,0 +1,51
1 /*
2 * sys_clock.c
3 *
4 * Created: 26/04/16 11:32:16
5 * Author: Francisco
6 */
7 /*!
8 * \fn config_sysclock
9 * \brief Configuraci�n del reloj interno del sistema
10 * Reloj interno
11 * fsys = 32MHz
12 *
13 * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL
14 * \
15 */
16
17 #define F_CPU 32000000UL
18 #include <avr/io.h>
19
20 void config_sysclock(void){
21
22 CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1
23 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */
24 while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */
25 while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */
26 DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */
27 OSC.DFLLCTRL &= 0xFD; //Habilito calibraci�n interna mediante reloj de 32K
28 CCP = CCP_IOREG_gc; /* Disable register security for clock update */
29 CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */
30 OSC.CTRL &= ~OSC_RC2MEN_bm;
31
32 /*
33 CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1
34 OSC_XOSCCTRL = OSC_XOSCSEL_EXTCLK_gc; //usar external clock
35
36 OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | ( 0x02 & OSC_PLLFAC_gm);
37
38 OSC_CTRL |= OSC_PLLEN_bm; //usar external clock
39 while(!(OSC_STATUS & OSC_XOSCRDY_bm));
40 while(!(OSC_STATUS & OSC_PLLRDY_bm));
41
42 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
43 CLK_CTRL = (CLK_SCLKSEL_PLL_gc) & CLK_SCLKSEL_gm; //CLK usa oscilador externo
44
45 OSC_CTRL &= ~OSC_RC2MEN_bm;
46
47 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
48 OSC_XOSCFAIL = (OSC_PLLFDEN_bm)|(OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
49 */
50
51 } No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,20
1 /*
2 * sys_clock.h
3 *
4 * Created: 26/04/16 11:39:08
5 * Author: Francisco
6 */
7
8
9 #ifndef SYS_CLOCK_H_
10 #define SYS_CLOCK_H_
11
12
13 #define F_CPU 32000000UL
14 #include <avr/io.h>
15
16 void config_sysclock(void);
17
18
19
20 #endif /* SYS_CLOCK_H_ */ No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,1
1 work
Show file before | Show file after | Hide comments
@@ -0,0 +1,1
1 vhdl work "DCM_fwd_int.vhd"
Show file before | Show file after | Hide comments
@@ -0,0 +1,57
1 Release 14.7 - xst P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 --> Parameter TMPDIR set to C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst/projnav.tmp
4
5
6 Total REAL time to Xst completion: 0.00 secs
7 Total CPU time to Xst completion: 0.11 secs
8
9 --> Parameter xsthdpdir set to C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst
10
11
12 Total REAL time to Xst completion: 0.00 secs
13 Total CPU time to Xst completion: 0.12 secs
14
15 --> Reading design: DCM_fwd_int.prj
16
17 TABLE OF CONTENTS
18 1) Synthesis Options Summary
19 2) HDL Parsing
20 3) HDL Elaboration
21 4) HDL Synthesis
22 4.1) HDL Synthesis Report
23 5) Advanced HDL Synthesis
24 5.1) Advanced HDL Synthesis Report
25 6) Low Level Synthesis
26 7) Partition Report
27 8) Design Summary
28 8.1) Primitive and Black Box Usage
29 8.2) Device utilization summary
30 8.3) Partition Resource Summary
31 8.4) Timing Report
32 8.4.1) Clock Information
33 8.4.2) Asynchronous Control Signals Information
34 8.4.3) Timing Summary
35 8.4.4) Timing Details
36 8.4.5) Cross Clock Domains Report
37
38
39 =========================================================================
40 * HDL Parsing *
41 =========================================================================
42 Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\DCM_fwd_int.vhd" into library work
43 Parsing entity <DCM_fwd_int>.
44 Parsing architecture <Behavioral> of entity <dcm_fwd_int>.
45
46
47 Total REAL time to Xst completion: 5.00 secs
48 Total CPU time to Xst completion: 5.00 secs
49
50 -->
51
52 Total memory usage is 184976 kilobytes
53
54 Number of errors : 0 ( 0 filtered)
55 Number of warnings : 0 ( 0 filtered)
56 Number of infos : 0 ( 0 filtered)
57
Show file before | Show file after | Hide comments
@@ -0,0 +1,160
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 17:23:06 02/16/2016
6 -- Design Name:
7 -- Module Name: DCM_fwd_int - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 library UNISIM;
30 use UNISIM.VComponents.all;
31
32 entity DCM_fwd_int is
33 PORT(
34 clk_main_io: IN std_logic;
35 c_16MHz_io: OUT std_logic;
36 c_200MHz_in: OUT std_logic
37 );
38 end DCM_fwd_int;
39
40 architecture Behavioral of DCM_fwd_int is
41 SIGNAL clk_main: std_logic;
42 SIGNAL c_16MHz: std_logic;
43
44 SIGNAL clk_fb_aux: std_logic;
45 SIGNAL clk_fb_aux_200MHz: std_logic;
46
47 SIGNAL c_16MHz_inv: std_logic;
48
49 begin
50
51 c_16MHz_inv <= NOT(c_16MHz);
52
53 ODDR2_inst : ODDR2
54 generic map(
55 DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
56 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
57 SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
58 port map (
59 Q => c_16MHz_io, -- 1-bit output data
60 C0 => c_16MHz, -- 1-bit clock input
61 C1 => c_16MHz_inv, -- 1-bit clock input
62 CE => '1', -- 1-bit clock enable input
63 D0 => '0', -- 1-bit data input (associated with C0)
64 D1 => '1', -- 1-bit data input (associated with C1)
65 R => '0', -- 1-bit reset input
66 S => '0' -- 1-bit set input
67 );
68
69 --IBUFG_inst : IBUFG
70 -- generic map (
71 -- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
72 -- IOSTANDARD => "DEFAULT")
73 -- port map (
74 -- O => clk_main, -- Clock buffer output
75 -- I => clk_main_io -- Clock buffer input (connect directly to top-level port)
76 -- );
77
78 DCM_SP_inst : DCM_SP
79 generic map (
80 CLKDV_DIVIDE => 2.0, -- CLKDV divide value
81 -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
82 CLKFX_DIVIDE => 15, -- Divide value on CLKFX outputs - D - (1-32)
83 CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
84 CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
85 CLKIN_PERIOD => 16.667, -- Input clock period specified in nS
86 CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
87 CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
88 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
89 DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
90 DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
91 DSS_MODE => "NONE", -- Unsupported - Do not change value
92 DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
93 FACTORY_JF => X"c080", -- Unsupported - Do not change value
94 PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
95 STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
96 )
97 port map (
98 CLK0 => clk_fb_aux, -- 1-bit output: 0 degree clock output
99 CLK180 => open, -- 1-bit output: 180 degree clock output
100 CLK270 => open, -- 1-bit output: 270 degree clock output
101 CLK2X => open, -- 1-bit output: 2X clock frequency clock output
102 CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
103 CLK90 => open, -- 1-bit output: 90 degree clock output
104 CLKDV => open, -- 1-bit output: Divided clock output
105 CLKFX => c_16MHz, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
106 CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
107 LOCKED => open, -- 1-bit output: DCM_SP Lock Output
108 PSDONE => open, -- 1-bit output: Phase shift done output
109 STATUS => open, -- 8-bit output: DCM_SP status output
110 CLKFB => clk_fb_aux, -- 1-bit input: Clock feedback input
111 CLKIN => clk_main_io, -- 1-bit input: Clock input
112 DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
113 PSCLK => '1', -- 1-bit input: Phase shift clock input
114 PSEN => '0', -- 1-bit input: Phase shift enable
115 PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
116 RST => '0' -- 1-bit input: Active high reset input
117 );
118
119 DCM_SP_inst_int : DCM_SP
120 generic map (
121 CLKDV_DIVIDE => 2.0, -- CLKDV divide value
122 -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16).
123 CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32)
124 CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32)
125 CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE)
126 CLKIN_PERIOD => 16.667, -- Input clock period specified in nS
127 CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE)
128 CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X)
129 DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS
130 DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
131 DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value
132 DSS_MODE => "NONE", -- Unsupported - Do not change value
133 DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value
134 FACTORY_JF => X"c080", -- Unsupported - Do not change value
135 PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255)
136 STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE)
137 )
138 port map (
139 CLK0 => clk_fb_aux_200MHz, -- 1-bit output: 0 degree clock output
140 CLK180 => open, -- 1-bit output: 180 degree clock output
141 CLK270 => open, -- 1-bit output: 270 degree clock output
142 CLK2X => open, -- 1-bit output: 2X clock frequency clock output
143 CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output
144 CLK90 => open, -- 1-bit output: 90 degree clock output
145 CLKDV => open, -- 1-bit output: Divided clock output
146 CLKFX => c_200MHz_in, -- 1-bit output: Digital Frequency Synthesizer output (DFS)
147 CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output
148 LOCKED => open, -- 1-bit output: DCM_SP Lock Output
149 PSDONE => open, -- 1-bit output: Phase shift done output
150 STATUS => open, -- 8-bit output: DCM_SP status output
151 CLKFB => clk_fb_aux_200MHz, -- 1-bit input: Clock feedback input
152 CLKIN => clk_main_io, -- 1-bit input: Clock input
153 DSSEN => '0', -- 1-bit input: Unsupported, specify to GND.
154 PSCLK => '1', -- 1-bit input: Phase shift clock input
155 PSEN => '0', -- 1-bit input: Phase shift enable
156 PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input
157 RST => '0' -- 1-bit input: Active high reset input
158 );
159
160 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,50
1 set -tmpdir "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst/projnav.tmp"
2 set -xsthdpdir "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst"
3 run -compileonly yes
4 -p xc6slx9-3-tqg144
5 -top DCM_fwd_int
6 -opt_mode Speed
7 -opt_level 1
8 -power NO
9 -iuc NO
10 -keep_hierarchy No
11 -netlist_hierarchy As_Optimized
12 -rtlview Yes
13 -glob_opt AllClockNets
14 -read_cores YES
15 -write_timing_constraints NO
16 -cross_clock_analysis NO
17 -hierarchy_separator /
18 -bus_delimiter <>
19 -case Maintain
20 -slice_utilization_ratio 100
21 -bram_utilization_ratio 100
22 -dsp_utilization_ratio 100
23 -lc Auto
24 -reduce_control_sets Auto
25 -fsm_extract YES -fsm_encoding Auto
26 -safe_implementation No
27 -fsm_style LUT
28 -ram_extract Yes
29 -ram_style Auto
30 -rom_extract Yes
31 -shreg_extract YES
32 -rom_style Auto
33 -auto_bram_packing NO
34 -resource_sharing YES
35 -async_to_sync NO
36 -shreg_min_size 2
37 -use_dsp48 Auto
38 -iobuf YES
39 -max_fanout 100000
40 -bufg 16
41 -register_duplication YES
42 -register_balancing No
43 -optimize_primitives NO
44 -use_clock_enable Auto
45 -use_sync_set Auto
46 -use_sync_reset Auto
47 -iob Auto
48 -equivalent_register_removal YES
49 -slice_utilization_ratio_maxmargin 5
50 -ifn DCM_fwd_int.prj
Show file before | Show file after | Hide comments
@@ -0,0 +1,54
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 10:45:36 05/16/2016
6 -- Design Name:
7 -- Module Name: SEL_OEbar - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity SEL_WRbar is
33 GENERIC(RESUL_IOSEL_SZ: INTEGER :=16
34 );
35
36 PORT(
37 DATA_W : IN std_logic_vector((RESUL_IOSEL_SZ-1) downto 0);
38 DATA_R : OUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0);
39 OEbar: IN std_logic;
40 DATA_INOUT: INOUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0)
41 );
42 end SEL_WRbar;
43
44 architecture Behavioral of SEL_WRbar is
45
46 begin
47
48 DATA_INOUT <= DATA_W WHEN OEbar = '1' ELSE
49 (others => 'Z');
50
51 DATA_R <= DATA_INOUT;
52
53 end Behavioral;
54
Show file before | Show file after | Hide comments
@@ -0,0 +1,290
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 19:55:49 05/06/2016
6 -- Design Name:
7 -- Module Name: spi_slave - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 library IEEE;
33 use IEEE.STD_LOGIC_1164.ALL;
34 use IEEE.NUMERIC_STD.ALL;
35 -- Uncomment the following library declaration if using
36 -- arithmetic functions with Signed or Unsigned values
37 --use IEEE.NUMERIC_STD.ALL;
38
39 -- Uncomment the following library declaration if instantiating
40 -- any Xilinx primitives in this code.
41 --library UNISIM;
42 --use UNISIM.VComponents.all;
43
44
45 entity SPI_SLAVE is
46 GENERIC(
47 SPI_DATA_WIDTH: INTEGER :=8;
48 SPI_BIT_COUNT_WIDTH: INTEGER :=3
49 );
50
51 PORT (
52 MOSI : IN std_logic;
53 SCK : IN std_logic;
54 CS : IN std_logic;
55 data_in : IN std_logic_vector (SPI_DATA_WIDTH-1 downto 0);
56 clk_main : IN std_logic;
57 rst_bar : IN std_logic;
58 MISO : OUT std_logic;
59 data_out : OUT std_logic_vector (SPI_DATA_WIDTH-1 downto 0);
60 spi_ready : OUT std_logic;
61
62 spi_free: OUT std_logic
63 --spi_ld_8_in: IN STD_LOGIC;
64
65 --spi_req : OUT std_logic
66
67
68 );
69 end SPI_SLAVE;
70
71 architecture Behavioral of SPI_SLAVE is
72 SIGNAL SCKr : std_logic_vector (1 downto 0) :=( OTHERS => '0');
73 SIGNAL CSr : std_logic_vector (1 downto 0) :=( OTHERS => '0');
74 SIGNAL MOSIr : std_logic_vector (1 downto 0) :=( OTHERS => '0');
75 SIGNAL SCK_rise : std_logic := '0';
76 SIGNAL SCK_fall : std_logic := '0';
77 --SIGNAL CS_fall : std_logic := '0';
78
79 SIGNAL bit_counter : std_logic_vector (SPI_BIT_COUNT_WIDTH-1 downto 0) :=( OTHERS => '0');
80 SIGNAL buffer_in : std_logic_vector (SPI_DATA_WIDTH-1 downto 0) :=( OTHERS => '0');
81 SIGNAL buffer_out : std_logic_vector (SPI_DATA_WIDTH-1 downto 0) :=( OTHERS => '0');
82
83 TYPE spi_states IS (
84 idle,
85 free,
86 busy
87 );
88 SIGNAL spi_cur_state: spi_states := free;
89 SIGNAL spi_next_state: spi_states := free;
90 SIGNAL spi_ready_aux: std_logic := '0';
91 --SIGNAL spi_req_aux: std_logic := '0';
92
93 SIGNAL MISO_int: std_logic :='1';
94 begin
95
96 -- Shifting the SCK line for synchronization purposes
97 SCK_shift_register: process (clk_main)
98 --VARIABLE SCKr : std_logic_vector (2 downto 0) :=( OTHERS => '0');
99 begin
100 if rising_edge (clk_main) then
101 if rst_bar = '0' then
102 SCKr <= (others => '1');
103 else
104 SCKr <= SCKr(0) & SCK;
105 end if;
106 end if;
107 end process;
108
109 -- Shifting the SCK line for edge detection
110 SCK_edge_det: process (clk_main)
111 --VARIABLE SCKr : std_logic_vector (2 downto 0) :=( OTHERS => '0');
112 begin
113 if rising_edge (clk_main) then
114 if rst_bar = '0' then
115 SCK_rise <= '0';
116 SCK_fall <= '0';
117 else
118 IF (SCKr(1 downto 0) = "01") THEN
119 SCK_rise <= '1';
120 ELSE
121 SCK_rise <= '0';
122 END IF;
123
124 IF (SCKr(1 downto 0) = "10") THEN
125 SCK_fall <= '1';
126 ELSE
127 SCK_fall <= '0';
128 END IF;
129 end if;
130 end if;
131 end process;
132
133 -- Shifting the CS line for synchronization purposes and edge detection
134 CS_shift_register: process (clk_main)
135 begin
136 if rising_edge (clk_main) then
137 if rst_bar = '0' then
138 --CSr <= (others => '0');
139 else
140 CSr <= CSr(0) & CS;
141 end if;
142 end if;
143 end process;
144
145 -- Shifting the MOSI line for synchronization purposes
146 MOSI_shift_register: process (clk_main)
147 begin
148 if rising_edge (clk_main) then
149 if rst_bar = '0' then
150 MOSIr <= (others => '0');
151 else
152 MOSIr <= MOSIr(0) & MOSI;
153 end if;
154 end if;
155 end process;
156
157 receive_process: process (clk_main)
158 begin
159 if rising_edge (clk_main) then
160 if rst_bar = '0' then
161 bit_counter <= (others => '0');
162 buffer_in <= (others => '0');
163 spi_ready_aux <= '0';
164 --spi_req_aux <= '0';
165 else
166 if (CSr(1) = '1') then
167 bit_counter <= (others => '0');
168 elsif (SCK_rise = '1') then
169 bit_counter <= std_logic_vector(unsigned(bit_counter) + 1);
170 buffer_in <= buffer_in(SPI_DATA_WIDTH-2 downto 0) & MOSIr(1);
171 IF((bit_counter = "111")) THEN
172 bit_counter <= (others => '0');
173 END IF;
174 end if;
175
176 IF((bit_counter = "111")) THEN
177
178 IF(CSr(1) = '0') THEN
179 IF (SCK_rise = '1')THEN
180 spi_ready_aux <= '1';
181 ELSE
182 spi_ready_aux <= '0';
183 END IF;
184 ELSE
185 spi_ready_aux <= '0';
186 END IF;
187 ELSE
188 spi_ready_aux <= '0';
189 END IF;
190
191 --IF((bit_counter = "000")) THEN
192
193 --IF(CSr(1) = '0') THEN
194 -- IF (SCK_fall = '1')THEN
195 -- spi_req_aux <= '1';
196 -- ELSE
197 -- spi_req_aux <= '0';
198 -- END IF;
199 --ELSE
200 -- spi_req_aux <= '0';
201 --END IF;
202 --ELSE
203 --spi_req_aux <= '0';
204 --END IF;
205 end if;
206 end if;
207 end process;
208
209 spi_ready <= spi_ready_aux;
210 --spi_req <= spi_req_aux;
211
212 transmit_process: process (clk_main)
213 begin
214 if rising_edge (clk_main) then
215 if rst_bar = '0' then
216 buffer_out <= (others => '0');
217 elsif (CSr(1) = '0') then
218
219 if ((bit_counter = "000")) then
220 --IF (SCK_fall = '1') THEN
221 buffer_out <= data_in;
222 --buffer_out <= "01000000";
223 --end if;
224 elsif (SCK_fall = '1') then
225 --if((bit_counter /= "000")) then
226 buffer_out <= buffer_out(6 downto 0) & '0';
227 --buffer_out <= "10000000";
228 end if;
229 --end if;
230 end if;
231 end if;
232 end process;
233
234 --MISO_asignacion: PROCESS(clk_main)
235 -- BEGIN
236 -- IF(rising_edge(clk_main)) THEN
237 -- MISO_int <=buffer_out(7);
238 -- END iF;
239 -- END PROCESS;
240
241 MISO <= buffer_out(7);
242
243 data_out <= buffer_in;
244
245 -----------------------------------
246
247 cambio_estados: PROCESS(clk_main)
248 BEGIN
249 IF (rising_edge(clk_main)) THEN
250 IF(rst_bar = '0') THEN
251 spi_cur_state <= idle;
252 ELSE
253 spi_cur_state <= spi_next_state;
254 END IF;
255 END IF;
256 END PROCESS;
257
258 salidas_estados: PROCESS(spi_cur_state,spi_ready_aux,bit_counter,
259 --spi_req_aux,
260 SCK_rise)
261 BEGIN
262 CASE spi_cur_state IS
263 WHEN idle =>
264 spi_free <= '0'; --spi atendido por spi_controller
265 spi_next_state <= free;
266
267
268 WHEN free =>
269 spi_free <= '1'; --spi atendido por spi_controller
270 IF (SCK_rise = '1') THEN
271 spi_next_state <= busy;
272 ELSE
273 spi_next_state <= free;
274 END IF;
275
276 WHEN busy =>
277 spi_free <= '0';
278 IF (spi_ready_aux = '1') THEN
279 spi_next_state <= free;
280 ELSE
281 spi_next_state <= busy;
282 END IF;
283
284 WHEN OTHERS =>
285 spi_free <= '0';
286 spi_next_state <= idle;
287
288 END CASE;
289 END PROCESS;
290 end Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (1751 lines changed) Show them Hide them
@@ -0,0 +1,1751
1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 17:26:56 05/12/2016
6 -- Design Name:
7 -- Module Name: W_R_RAM_CONTROLLER - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 library UNISIM;
30 use UNISIM.VComponents.all;
31
32 entity W_R_RAM_CONTROLLER is
33 GENERIC(
34 ADDR_LENGTH: INTEGER := 19;
35 CHAN_NUM: INTEGER := 5
36
37 );
38
39 PORT(
40 --Reset general
41 rst_bar: IN std_logic;
42
43 --Entrada de reloj principal
44 clk_main: IN std_logic;
45
46 --Entradas para indicar dato preparado por leer
47 --Desde los nibble to packets
48 wr_ch_vector: IN std_logic_vector((CHAN_NUM-1) downto 0);
49
50 --Senhal para que indica que termino con una peticion
51 --Hacia los nibble to packets
52 ack_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
53
54 --Senhal de requerimiento de lectura de dato
55 --Desde el SPI_Controller
56 rd_req: IN std_logic;
57 --Hacia el SPI_Controller
58 ld_ram: OUT std_logic;
59
60 --Senhales de control de memoria RAM
61 we_bar: OUT std_logic;
62 ub_bar: OUT std_logic;
63 lb_bar: OUT std_logic;
64 cs1_bar: OUT std_logic;
65 cs2: OUT std_logic;
66 oe_ram_bar: OUT std_logic;
67
68 --Selector de canal de salida hacia RAM
69 --Hacia el multiplexor
70 oe_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0);
71 hb_lbbar: OUT std_logic;
72
73 --Direccion de escritura/lectura
74 addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0)
75 );
76
77 end W_R_RAM_CONTROLLER;
78
79 architecture Behavioral of W_R_RAM_CONTROLLER is
80 --Estados del controlador de memoria
81 --Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria
82 --espera de pedido y estados para proceder a una lectura
83 TYPE ram_cont_states IS (idle,
84 set_erase_ram, act_erase_ram,exe_erase_ram,
85 -------------------------------------------
86 -------------------------------------------
87 espera_rdy,
88 ------------------------------------------
89 set_wrt_ch1_1, act_wrt_ch1_1,exe_wrt_ch1_1,
90 set_wrt_ch1_2, act_wrt_ch1_2,exe_wrt_ch1_2,
91 ------------------------------------------
92 set_wrt_ch2_1, act_wrt_ch2_1,exe_wrt_ch2_1,
93 set_wrt_ch2_2, act_wrt_ch2_2,exe_wrt_ch2_2,
94 ------------------------------------------
95 set_wrt_ch3_1, act_wrt_ch3_1,exe_wrt_ch3_1,
96 set_wrt_ch3_2, act_wrt_ch3_2,exe_wrt_ch3_2,
97 ------------------------------------------
98 set_wrt_ch4_1, act_wrt_ch4_1,exe_wrt_ch4_1,
99 set_wrt_ch4_2, act_wrt_ch4_2,exe_wrt_ch4_2,
100 ------------------------------------------
101 set_wrt_ch5_1, act_wrt_ch5_1,exe_wrt_ch5_1,
102 set_wrt_ch5_2, act_wrt_ch5_2,exe_wrt_ch5_2,
103 -------------------------------------------
104 end_wrt_cycle_1,end_wrt_cycle_2,
105 -------------------------------------------
106 -------------------------------------------
107 espera_req,
108 set_rd, act_rd,exe_rd,end_rd
109 );
110
111 SIGNAL ram_contr_cur_state: ram_cont_states := idle;
112 SIGNAL ram_contr_next_state: ram_cont_states := idle;
113
114 --Constante del tamanho maximo por canal
115 CONSTANT TOP_GL: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000100111000011"; --5000 bytes maximo direcciones /2=2500 = 1001 1100 0100. Se coloca el -1
116 CONSTANT TOP_GL_2: std_logic_vector(11 downto 0) := "100111000011";
117 CONSTANT TOP_CH: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000000111110011"; --500 "010 1010 1010 1010 1010" se coloca el -1
118 CONSTANT TOP_CH_2: std_logic_vector(8 downto 0) := "111110011";
119
120 --Direcciones base por canal
121 CONSTANT BASE_ADD_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0');
122 CONSTANT BASE_ADD_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000000111110100"; --500
123 CONSTANT BASE_ADD_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000001111101000"; --1000
124 CONSTANT BASE_ADD_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000010111011100"; --1500
125 CONSTANT BASE_ADD_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000011111010000"; --2000
126
127 --Contador de n�mero de ciclos de reloj en los estados de lectura-escritura
128 SIGNAL count_slw: std_logic_vector(3 downto 0) := "0000";
129
130 --Constantes de espera para el proceso de lectura-escritura
131 --Recordar para 200MHz->Periodo=5ns
132 --6ciclos=30ns y 12ciclos=60ns
133 --Para el 62WV51216BLL-55T los tiempos para preparar y escribir dato son: 20ns y 55ns resp.
134 CONSTANT ramwait_const1: std_logic_vector(3 downto 0) := "1000"; --3 6
135 CONSTANT ramwait_const2: std_logic_vector(3 downto 0) := "1111"; --6 12
136
137 --Punteros de direccion para escritura por cada espacio de memoria asignado a canal
138 SIGNAL rel_pos_ch1: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
139 SIGNAL rel_pos_ch1_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0');
140 SIGNAL rel_pos_ch2: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
141 SIGNAL rel_pos_ch2_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0');
142 SIGNAL rel_pos_ch3: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
143 SIGNAL rel_pos_ch3_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0');
144 SIGNAL rel_pos_ch4: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
145 SIGNAL rel_pos_ch4_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0');
146 SIGNAL rel_pos_ch5: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
147 SIGNAL rel_pos_ch5_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0');
148
149 --Senhal auxiliar de direccion a memoria para escritura
150 SIGNAL addr_wr_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
151
152 --Senhal auxiliar de direccion a memoria para lectura
153 SIGNAL addr_rd_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
154 SIGNAL addr_rd_aux_int: std_logic_vector(11 downto 0) :=(OTHERS=>'0');
155
156 --Senhal auxiliar de direccion a memoria para borrado
157 SIGNAL addr_erase_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0');
158 SIGNAL addr_erase_aux_int: std_logic_vector(11 downto 0) :=(OTHERS=>'0');
159
160 --Estados de la atencion a ready's
161 --
162 TYPE chn_cont_states IS ( idle,
163 checking_ch1, attending_ch1,
164 checking_ch2, attending_ch2,
165 checking_ch3, attending_ch3,
166 checking_ch4, attending_ch4,
167 checking_ch5, attending_ch5
168 );
169
170 SIGNAL ch_cont_cur_state: chn_cont_states := idle;
171 SIGNAL ch_cont_next_state: chn_cont_states := idle;
172
173 --Senhal de reset interna formada de rst_bar y pps_r
174 --SIGNAL rst_bar_int: std_logic :='0';
175
176 --Registro para detecci�n de flanco
177 --SIGNAL pps_r: std_logic_vector(1 downto 0) :="00";
178 --SIGNAL pps_rst: std_logic :='0';
179
180 begin
181
182
183 --Deteccion de flanco de pps
184 --pps_bloco: PROCESS(clk_main)
185 -- BEGIN
186 -- IF (rising_edge(clk_main)) THEN
187 -- IF(rst_bar = '0') THEN
188 -- pps_rst <= '0';
189 -- pps_r <= (OTHERS=>'0');
190 -- pps_rst <= '0';
191 -- ELSE
192 -- pps_r <= pps_r(0) & pps;
193 -- IF(pps_r(1 downto 0) = "01") THEN
194 -- pps_rst <= '0';
195 -- ELSE
196 -- pps_rst <= '1';
197 -- END IF;
198 -- END IF;
199 -- END IF;
200 -- END PROCESS;
201
202 --Generacion de reset a partir del resetbar y flanco de subida del pps
203 --rst_bar_int <= rst_bar AND (pps_rst);
204
205 ---------------------
206 --Estados para atencion de canales
207 ch_cont_cambio_estados: PROCESS(clk_main)
208 BEGIN
209 IF (rising_edge(clk_main)) THEN
210 IF(rst_bar = '0') THEN
211 ch_cont_cur_state <= idle;
212 ELSE
213 ch_cont_cur_state <= ch_cont_next_state;
214 END IF;
215 END IF;
216 END PROCESS;
217
218 ch_salidas_estados: PROCESS(ch_cont_cur_state,
219 wr_ch_vector,
220 ram_contr_cur_state
221 )
222 BEGIN
223
224 CASE ch_cont_cur_state IS
225 WHEN idle =>
226 ch_cont_next_state <= checking_ch1;
227
228 WHEN checking_ch1 =>
229 IF(wr_ch_vector(0) = '1') THEN
230 ch_cont_next_state <= attending_ch1;
231 ELSE
232 ch_cont_next_state <= checking_ch2;
233 END IF;
234
235 WHEN attending_ch1 =>
236 IF(ram_contr_cur_state = end_wrt_cycle_2) THEN
237 ch_cont_next_state <= checking_ch2;
238 ELSE
239 ch_cont_next_state <= attending_ch1;
240 END IF;
241
242 WHEN checking_ch2 =>
243 IF(wr_ch_vector(1) = '1') THEN
244 ch_cont_next_state <= attending_ch2;
245 ELSE
246 ch_cont_next_state <= checking_ch3;
247 END IF;
248
249 WHEN attending_ch2 =>
250 IF(ram_contr_cur_state = end_wrt_cycle_2) THEN
251 ch_cont_next_state <= checking_ch3;
252 ELSE
253 ch_cont_next_state <= attending_ch2;
254 END IF;
255
256 WHEN checking_ch3 =>
257 IF(wr_ch_vector(2) = '1') THEN
258 ch_cont_next_state <= attending_ch3;
259 ELSE
260 ch_cont_next_state <= checking_ch4;
261 END IF;
262
263 WHEN attending_ch3 =>
264 IF(ram_contr_cur_state = end_wrt_cycle_2) THEN
265 ch_cont_next_state <= checking_ch4;
266 ELSE
267 ch_cont_next_state <= attending_ch3;
268 END IF;
269
270 WHEN checking_ch4 =>
271 IF(wr_ch_vector(3) = '1') THEN
272 ch_cont_next_state <= attending_ch4;
273 ELSE
274 ch_cont_next_state <= checking_ch5;
275 END IF;
276
277 WHEN attending_ch4 =>
278 IF(ram_contr_cur_state = end_wrt_cycle_2) THEN
279 ch_cont_next_state <= checking_ch5;
280 ELSE
281 ch_cont_next_state <= attending_ch4;
282 END IF;
283
284 WHEN checking_ch5 =>
285 IF(wr_ch_vector(4) = '1') THEN
286 ch_cont_next_state <= attending_ch5;
287 ELSE
288 ch_cont_next_state <= checking_ch1;
289 END IF;
290
291 WHEN attending_ch5 =>
292 IF(ram_contr_cur_state = end_wrt_cycle_2) THEN
293 ch_cont_next_state <= checking_ch1;
294 ELSE
295 ch_cont_next_state <= attending_ch5;
296 END IF;
297
298 WHEN OTHERS =>
299
300 ch_cont_next_state <= idle;
301
302 END CASE;
303 END PROCESS;
304
305 -----------------------------------------
306 --Asignacion de direccion de escritura
307 asignacion_direccion_base_escritura:
308 PROCESS(ch_cont_cur_state,rel_pos_ch1,rel_pos_ch2,rel_pos_ch3,rel_pos_ch4,rel_pos_ch5)
309 BEGIN
310 CASE ch_cont_cur_state IS
311 WHEN idle =>
312 addr_wr_aux <= (OTHERS => '0');
313 WHEN attending_ch1 =>
314 addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH1)+unsigned(rel_pos_ch1));
315 WHEN attending_ch2 =>
316 addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH2)+unsigned(rel_pos_ch2));
317 WHEN attending_ch3 =>
318 addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH3)+unsigned(rel_pos_ch3));
319 WHEN attending_ch4 =>
320 addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH4)+unsigned(rel_pos_ch4));
321 WHEN attending_ch5 =>
322 addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH5)+unsigned(rel_pos_ch5));
323 WHEN OTHERS =>
324 addr_wr_aux <= (OTHERS => '0');
325 END CASE;
326 END PROCESS;
327
328 --Asignacion de direccion de lectura
329 puntero_rd: PROCESS(clk_main)
330 BEGIN
331 IF (rising_edge(clk_main)) THEN
332 IF (rst_bar = '0') THEN
333 addr_rd_aux_int <= (OTHERS=>'0');
334 ELSE
335 IF(ram_contr_cur_state = idle) THEN
336 addr_rd_aux_int <= (OTHERS=>'0');
337 END IF;
338
339 --Cuentas de ram_ptr en proceso de lectura
340 IF(ram_contr_cur_state = end_rd) THEN
341 IF(addr_rd_aux_int = TOP_GL_2) THEN
342 addr_rd_aux_int <= addr_rd_aux_int;
343 ELSE
344 addr_rd_aux_int <= std_logic_vector(unsigned(addr_rd_aux_int) + 1);
345 END IF;
346 END IF;
347 END IF;
348 END IF;
349 END PROCESS;
350
351 addr_rd_aux <= "0000000" & addr_rd_aux_int;
352
353 --Asignacion de direccion de borrado
354 puntero_erase: PROCESS(clk_main)
355 --VARIABLE var_addr_erase_aux: std_logic_vector(11 downto 0) :=(OTHERS => '0');
356 BEGIN
357 IF (rising_edge(clk_main)) THEN
358 IF (rst_bar = '0') THEN
359 addr_erase_aux_int <= (OTHERS=>'0');
360 ELSE
361 IF(ram_contr_cur_state = idle) THEN
362 addr_erase_aux_int <= (OTHERS=>'0');
363 END IF;
364
365 --Cuentas de ram_ptr en proceso de borrado
366 IF(ram_contr_cur_state = exe_erase_ram) THEN
367 IF(addr_erase_aux_int = TOP_GL_2) THEN
368 addr_erase_aux_int <= (OTHERS=>'0');
369 ELSE
370 addr_erase_aux_int <= std_logic_vector(unsigned(addr_erase_aux_int) + 1);
371 END IF;
372 END IF;
373 END IF;
374 END IF;
375 END PROCESS;
376
377 addr_erase_aux <= "0000000" & addr_erase_aux_int;
378
379 --Asignaci�n de salida addr_mem
380 addr_mem_asig: PROCESS(ram_contr_cur_state,addr_erase_aux,addr_rd_aux,addr_wr_aux)
381 BEGIN
382 CASE ram_contr_cur_state IS
383 WHEN idle | espera_rdy =>
384 addr <= (OTHERS => '0');
385
386 WHEN set_erase_ram | act_erase_ram | exe_erase_ram =>
387 addr <= addr_erase_aux;
388
389 WHEN set_wrt_ch1_1 | act_wrt_ch1_1 | exe_wrt_ch1_1 |
390 set_wrt_ch1_2 | act_wrt_ch1_2 | exe_wrt_ch1_2 |
391 set_wrt_ch2_1 | act_wrt_ch2_1 | exe_wrt_ch2_1 |
392 set_wrt_ch2_2 | act_wrt_ch2_2 | exe_wrt_ch2_2 |
393 set_wrt_ch3_1 | act_wrt_ch3_1 | exe_wrt_ch3_1 |
394 set_wrt_ch3_2 | act_wrt_ch3_2 | exe_wrt_ch3_2 |
395 set_wrt_ch4_1 | act_wrt_ch4_1 | exe_wrt_ch4_1 |
396 set_wrt_ch4_2 | act_wrt_ch4_2 | exe_wrt_ch4_2 |
397 set_wrt_ch5_1 | act_wrt_ch5_1 | exe_wrt_ch5_1 |
398 set_wrt_ch5_2 | act_wrt_ch5_2 | exe_wrt_ch5_2 |
399 end_wrt_cycle_1 | end_wrt_cycle_2 =>
400 addr <= addr_wr_aux;
401
402 WHEN espera_req | set_rd | act_rd | exe_rd | end_rd =>
403 addr <= addr_rd_aux;
404
405 WHEN OTHERS =>
406 addr <= (OTHERS => '0');
407 END CASE;
408
409 END PROCESS;
410
411 --Avance de punteros de escritura
412 puntero_ch1: PROCESS(clk_main)
413 BEGIN
414 IF (rising_edge(clk_main)) THEN
415 IF (rst_bar = '0') THEN
416 rel_pos_ch1_int <= (OTHERS=>'0');
417 ELSE
418 IF(ram_contr_cur_state = idle) THEN
419 rel_pos_ch1_int <= (OTHERS=>'0');
420 END IF;
421
422 IF(ram_contr_cur_state = exe_wrt_ch1_1 OR ram_contr_cur_state = exe_wrt_ch1_2) THEN
423 IF(rel_pos_ch1_int /= TOP_CH_2) THEN
424 rel_pos_ch1_int <= std_logic_vector(unsigned(rel_pos_ch1_int) + 1);
425 END IF;
426 END IF;
427 END IF;
428 END IF;
429 END PROCESS;
430
431 rel_pos_ch1 <= "0000000000"& rel_pos_ch1_int;
432
433 puntero_ch2: PROCESS(clk_main)
434 BEGIN
435 IF (rising_edge(clk_main)) THEN
436 IF (rst_bar = '0') THEN
437 rel_pos_ch2_int <= (OTHERS=>'0');
438 ELSE
439 IF(ram_contr_cur_state = idle) THEN
440 rel_pos_ch2_int <= (OTHERS=>'0');
441 END IF;
442
443 IF(ram_contr_cur_state = exe_wrt_ch2_1 OR ram_contr_cur_state = exe_wrt_ch2_2) THEN
444 IF(rel_pos_ch2_int /= TOP_CH_2) THEN
445 rel_pos_ch2_int <= std_logic_vector(unsigned(rel_pos_ch2_int) + 1);
446 END IF;
447 END IF;
448 END IF;
449 END IF;
450 END PROCESS;
451
452 rel_pos_ch2 <= "0000000000"& rel_pos_ch2_int;
453
454 puntero_ch3: PROCESS(clk_main)
455 BEGIN
456 IF (rising_edge(clk_main)) THEN
457 IF (rst_bar = '0') THEN
458 rel_pos_ch3_int <= (OTHERS=>'0');
459 ELSE
460 IF(ram_contr_cur_state = idle) THEN
461 rel_pos_ch3_int <= (OTHERS=>'0');
462 END IF;
463
464 IF(ram_contr_cur_state = exe_wrt_ch3_1 OR ram_contr_cur_state = exe_wrt_ch3_2) THEN
465 IF(rel_pos_ch3_int /= TOP_CH_2) THEN
466 rel_pos_ch3_int <= std_logic_vector(unsigned(rel_pos_ch3_int) + 1);
467 END IF;
468 END IF;
469 END IF;
470 END IF;
471 END PROCESS;
472
473 rel_pos_ch3 <= "0000000000"& rel_pos_ch3_int;
474
475 puntero_ch4: PROCESS(clk_main)
476 BEGIN
477 IF (rising_edge(clk_main)) THEN
478 IF (rst_bar = '0') THEN
479 rel_pos_ch4_int <= (OTHERS=>'0');
480 ELSE
481 IF(ram_contr_cur_state = idle) THEN
482 rel_pos_ch4_int <= (OTHERS=>'0');
483 END IF;
484
485 IF(ram_contr_cur_state = exe_wrt_ch4_1 OR ram_contr_cur_state = exe_wrt_ch4_2) THEN
486 IF(rel_pos_ch4_int /= TOP_CH_2) THEN
487 rel_pos_ch4_int <= std_logic_vector(unsigned(rel_pos_ch4_int) + 1);
488 END IF;
489 END IF;
490 END IF;
491 END IF;
492 END PROCESS;
493
494 rel_pos_ch4 <= "0000000000"& rel_pos_ch4_int;
495
496 puntero_ch5: PROCESS(clk_main)
497 BEGIN
498 IF (rising_edge(clk_main)) THEN
499 IF (rst_bar = '0') THEN
500 rel_pos_ch5_int <= (OTHERS=>'0');
501 ELSE
502 IF(ram_contr_cur_state = idle) THEN
503 rel_pos_ch5_int <= (OTHERS=>'0');
504 END IF;
505
506 IF(ram_contr_cur_state = exe_wrt_ch5_1 OR ram_contr_cur_state = exe_wrt_ch5_2) THEN
507 IF(rel_pos_ch5_int /= TOP_CH_2) THEN
508 rel_pos_ch5_int <= std_logic_vector(unsigned(rel_pos_ch5_int) + 1);
509 END IF;
510 END IF;
511 END IF;
512 END IF;
513 END PROCESS;
514
515 rel_pos_ch5 <= "0000000000"& rel_pos_ch5_int;
516
517 --------------------------------------------------
518 --Estados de m�quina principal para control de RAM
519
520 ctrl_cambio_estados: PROCESS(clk_main)
521 BEGIN
522 IF (rising_edge(clk_main)) THEN
523 IF(rst_bar = '0') THEN
524 ram_contr_cur_state <= idle;
525 ELSE
526 ram_contr_cur_state <= ram_contr_next_state;
527 END IF;
528 END IF;
529 END PROCESS;
530
531 --Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set s�.
532 ctrl_salidas_estados: PROCESS(ram_contr_cur_state,
533 count_slw, rd_req,
534 ch_cont_cur_state,
535 addr_erase_aux,
536 addr_rd_aux,
537 rel_pos_ch1,rel_pos_ch2,rel_pos_ch3,rel_pos_ch4,rel_pos_ch5)
538 BEGIN
539
540 CASE ram_contr_cur_state IS
541 WHEN idle =>
542
543 --Senhales hacia memoria RAM
544 UB_bar <= '1';
545 LB_bar <= '1';
546 CS1_bar <= '1';
547 CS2 <= '0';
548 WE_bar <= '1';
549 OE_RAM_bar <= '1';
550
551 --Senhales hacia mutiplexor
552 oe_ch_vector <= (OTHERS=>'0');
553 hb_lbbar <= '0';
554
555 --Senhales hacia canales
556 ack_ch_vector <= (OTHERS=>'1');
557
558 --Senhales hacia SPI Controller o Cache
559 ld_ram <= '0';
560
561 ------------------------------------------
562 --Siguiente estado
563 ram_contr_next_state <= set_erase_ram;
564
565
566 WHEN set_erase_ram =>
567
568 --Senhales hacia memoria RAM
569 UB_bar <= '0';
570 LB_bar <= '0';
571 CS1_bar <= '0';
572 CS2 <= '1';
573 WE_bar <= '0';
574 OE_RAM_bar <= '1';
575
576 --Senhales hacia mutiplexor
577 oe_ch_vector <= (OTHERS=>'0');
578 hb_lbbar <= '0';
579
580 --Senhales hacia canales
581 ack_ch_vector <= (OTHERS=>'0');
582
583 --Senhales hacia SPI Controller o cache
584 ld_ram <= '0';
585
586 --Estado siguiente
587 IF (count_slw = ramwait_const1) THEN
588 ram_contr_next_state <= act_erase_ram;
589 ELSE
590 ram_contr_next_state <= set_erase_ram;
591 END IF;
592
593 WHEN act_erase_ram =>
594
595 --Senhales hacia memoria RAM
596 UB_bar <= '0';
597 LB_bar <= '0';
598 CS1_bar <= '0';
599 CS2 <= '1';
600 WE_bar <= '0';
601 OE_RAM_bar <= '1';
602
603 --Senhales hacia mutiplexor
604 oe_ch_vector <= (OTHERS=>'0');
605 hb_lbbar <= '0';
606
607 --Senhales hacia canales
608 ack_ch_vector <= (OTHERS=>'0');
609
610 --Senhales hacia SPI Controller o cache
611 ld_ram <= '0';
612
613 --Estado siguiente
614 IF (count_slw = ramwait_const2) THEN
615 ram_contr_next_state <= exe_erase_ram;
616 ELSE
617 ram_contr_next_state <= act_erase_ram;
618 END IF;
619
620 WHEN exe_erase_ram =>
621
622 --Senhales hacia memoria RAM
623 CS1_bar <= '0';
624 CS2 <= '1';
625 WE_bar <= '0';
626 OE_RAM_bar <= '1';
627 UB_bar <= '0';
628 LB_bar <= '0';
629
630 --Senhales hacia mutiplexor
631 oe_ch_vector <= (OTHERS=>'0');
632 hb_lbbar <= '0';
633
634 --Senhales hacia canales
635 ack_ch_vector <= (OTHERS=>'0');
636
637 --Senhales hacia SPI Controller o cache
638 ld_ram <= '0';
639
640 --Estado siguiente
641 IF (addr_erase_aux = TOP_GL) THEN
642 ram_contr_next_state <= espera_rdy;
643 ELSE
644 ram_contr_next_state <= set_erase_ram;
645 END IF;
646
647 WHEN espera_rdy =>
648
649 --Senhales hacia memoria RAM
650 CS1_bar <= '1';
651 CS2 <= '0';
652 WE_bar <= '1';
653 OE_RAM_bar <= '1';
654 UB_bar <= '1';
655 LB_bar <= '1';
656
657 --Senhales hacia mutiplexor
658 oe_ch_vector <= (OTHERS=>'0');
659 hb_lbbar <= '0';
660
661 --Senhales hacia canales
662 ack_ch_vector <= (OTHERS=>'0');
663
664 --Senhales hacia SPI Controller o cache
665 ld_ram <= '0';
666
667 ------------------------------------------
668 --Siguiente estado
669 IF(rd_req = '1') THEN
670 ram_contr_next_state <= set_rd;
671 ELSE
672 CASE ch_cont_cur_state IS
673 WHEN attending_ch1 =>
674 ram_contr_next_state <= set_wrt_ch1_1;
675 WHEN attending_ch2 =>
676 ram_contr_next_state <= set_wrt_ch2_1;
677 WHEN attending_ch3 =>
678 ram_contr_next_state <= set_wrt_ch3_1;
679 WHEN attending_ch4 =>
680 ram_contr_next_state <= set_wrt_ch4_1;
681 WHEN attending_ch5 =>
682 ram_contr_next_state <= set_wrt_ch5_1;
683 WHEN OTHERS =>
684 ram_contr_next_state <= espera_rdy;
685 END CASE;
686 END IF;
687
688 --Inicio proceso de escritura en canal 1
689 WHEN set_wrt_ch1_1 =>
690
691 --Senhales hacia memoria RAM
692 CS1_bar <= '0';
693 CS2 <= '1';
694 WE_bar <= '0';
695 OE_RAM_bar <= '1';
696 UB_bar <= '0';
697 LB_bar <= '0';
698
699 --Senhales hacia mutiplexor
700 oe_ch_vector <= "00001";--(OTHERS=>'0');
701 hb_lbbar <= '1';
702
703 --Senhales hacia canales
704 ack_ch_vector <= (OTHERS=>'0');
705
706 --Senhales hacia SPI Controller o cache
707 ld_ram <= '0';
708
709 --Estado siguiente
710 IF (count_slw = ramwait_const1) THEN
711 ram_contr_next_state <= act_wrt_ch1_1;
712 ELSE
713 ram_contr_next_state <= set_wrt_ch1_1;
714 END IF;
715
716 WHEN act_wrt_ch1_1 =>
717
718 --Senhales hacia memoria RAM
719 CS1_bar <= '0';
720 CS2 <= '1';
721 WE_bar <= '0';
722 OE_RAM_bar <= '1';
723 UB_bar <= '0';
724 LB_bar <= '0';
725
726 --Senhales hacia mutiplexor
727 oe_ch_vector <= "00001";
728 hb_lbbar <= '1';
729
730 --Senhales hacia canales
731 ack_ch_vector <= (OTHERS=>'0');
732
733 --Senhales hacia SPI Controller o cache
734 ld_ram <= '0';
735
736 --Estado siguiente
737 IF (count_slw = ramwait_const2) THEN
738 ram_contr_next_state <= exe_wrt_ch1_1;
739 ELSE
740 ram_contr_next_state <= act_wrt_ch1_1;
741 END IF;
742
743 WHEN exe_wrt_ch1_1 =>
744
745 --Senhales hacia memoria RAM
746 CS1_bar <= '0';
747 CS2 <= '1';
748 WE_bar <= '0';
749 OE_RAM_bar <= '1';
750 UB_bar <= '0';
751 LB_bar <= '0';
752
753 --Senhales hacia mutiplexor
754 oe_ch_vector <= "00001";
755 hb_lbbar <= '1';
756
757 --Senhales hacia canales
758 ack_ch_vector <= (OTHERS=>'0');
759
760 --Senhales hacia SPI Controller o cache
761 ld_ram <= '0';
762
763 --Estado siguiente
764 ram_contr_next_state <= end_wrt_cycle_1;
765
766 --Inicio proceso de escritura en canal 1
767 WHEN set_wrt_ch1_2 =>
768
769 --Senhales hacia memoria RAM
770 CS1_bar <= '0';
771 CS2 <= '1';
772 WE_bar <= '0';
773 OE_RAM_bar <= '1';
774 UB_bar <= '0';
775 LB_bar <= '0';
776
777 --Senhales hacia mutiplexor
778 oe_ch_vector <= "00001";--(OTHERS=>'0');
779 hb_lbbar <= '0';
780
781 --Senhales hacia canales
782 ack_ch_vector <= (OTHERS=>'0');
783
784 --Senhales hacia SPI Controller o cache
785 ld_ram <= '0';
786
787 --Estado siguiente
788 IF (count_slw = ramwait_const1) THEN
789 ram_contr_next_state <= act_wrt_ch1_2;
790 ELSE
791 ram_contr_next_state <= set_wrt_ch1_2;
792 END IF;
793
794 WHEN act_wrt_ch1_2 =>
795
796 --Senhales hacia memoria RAM
797 CS1_bar <= '0';
798 CS2 <= '1';
799 WE_bar <= '0';
800 OE_RAM_bar <= '1';
801 UB_bar <= '0';
802 LB_bar <= '0';
803
804 --Senhales hacia mutiplexor
805 oe_ch_vector <= "00001";
806 hb_lbbar <= '0';
807
808 --Senhales hacia canales
809 ack_ch_vector <= (OTHERS=>'0');
810
811 --Senhales hacia SPI Controller o cache
812 ld_ram <= '0';
813
814 --Estado siguiente
815 IF (count_slw = ramwait_const2) THEN
816 ram_contr_next_state <= exe_wrt_ch1_2;
817 ELSE
818 ram_contr_next_state <= act_wrt_ch1_2;
819 END IF;
820
821 WHEN exe_wrt_ch1_2 =>
822
823 --Senhales hacia memoria RAM
824 CS1_bar <= '0';
825 CS2 <= '1';
826 WE_bar <= '0';
827 OE_RAM_bar <= '1';
828 UB_bar <= '0';
829 LB_bar <= '0';
830
831 --Senhales hacia mutiplexor
832 oe_ch_vector <= "00001";
833 hb_lbbar <= '0';
834
835 --Senhales hacia canales
836 ack_ch_vector <= "00001";
837
838 --Senhales hacia SPI Controller o cache
839 ld_ram <= '0';
840
841 --Estado siguiente
842 ram_contr_next_state <= end_wrt_cycle_2;
843
844
845 --Inicio proceso de escritura en canal 2
846 WHEN set_wrt_ch2_1 =>
847
848 --Senhales hacia memoria RAM
849 CS1_bar <= '0';
850 CS2 <= '1';
851 WE_bar <= '0';
852 OE_RAM_bar <= '1';
853 UB_bar <= '0';
854 LB_bar <= '0';
855
856 --Senhales hacia mutiplexor
857 oe_ch_vector <= "00010";--(OTHERS=>'0');
858 hb_lbbar <= '1';
859
860 --Senhales hacia canales
861 ack_ch_vector <= (OTHERS=>'0');
862
863 --Senhales hacia SPI Controller o cache
864 ld_ram <= '0';
865
866 --Estado siguiente
867 IF (count_slw = ramwait_const1) THEN
868 ram_contr_next_state <= act_wrt_ch2_1;
869 ELSE
870 ram_contr_next_state <= set_wrt_ch2_1;
871 END IF;
872
873 WHEN act_wrt_ch2_1 =>
874
875 --Senhales hacia memoria RAM
876 CS1_bar <= '0';
877 CS2 <= '1';
878 WE_bar <= '0';
879 OE_RAM_bar <= '1';
880 UB_bar <= '0';
881 LB_bar <= '0';
882
883 --Senhales hacia mutiplexor
884 oe_ch_vector <= "00010";
885 hb_lbbar <= '1';
886
887 --Senhales hacia canales
888 ack_ch_vector <= (OTHERS=>'0');
889
890 --Senhales hacia SPI Controller o cache
891 ld_ram <= '0';
892
893 --Estado siguiente
894 IF (count_slw = ramwait_const2) THEN
895 ram_contr_next_state <= exe_wrt_ch2_1;
896 ELSE
897 ram_contr_next_state <= act_wrt_ch2_1;
898 END IF;
899
900 WHEN exe_wrt_ch2_1 =>
901
902 --Senhales hacia memoria RAM
903 CS1_bar <= '0';
904 CS2 <= '1';
905 WE_bar <= '0';
906 OE_RAM_bar <= '1';
907 UB_bar <= '0';
908 LB_bar <= '0';
909
910 --Senhales hacia mutiplexor
911 oe_ch_vector <= "00010";
912 hb_lbbar <= '1';
913
914 --Senhales hacia canales
915 ack_ch_vector <= (OTHERS=>'0');
916
917 --Senhales hacia SPI Controller o cache
918 ld_ram <= '0';
919
920 --Estado siguiente
921 ram_contr_next_state <= end_wrt_cycle_1;
922
923 --Inicio proceso de escritura en canal 2
924 WHEN set_wrt_ch2_2 =>
925
926 --Senhales hacia memoria RAM
927 CS1_bar <= '0';
928 CS2 <= '1';
929 WE_bar <= '0';
930 OE_RAM_bar <= '1';
931 UB_bar <= '0';
932 LB_bar <= '0';
933
934 --Senhales hacia mutiplexor
935 oe_ch_vector <= "00010";--(OTHERS=>'0');
936 hb_lbbar <= '0';
937
938 --Senhales hacia canales
939 ack_ch_vector <= (OTHERS=>'0');
940
941 --Senhales hacia SPI Controller o cache
942 ld_ram <= '0';
943
944 --Estado siguiente
945 IF (count_slw = ramwait_const1) THEN
946 ram_contr_next_state <= act_wrt_ch2_2;
947 ELSE
948 ram_contr_next_state <= set_wrt_ch2_2;
949 END IF;
950
951 WHEN act_wrt_ch2_2 =>
952
953 --Senhales hacia memoria RAM
954 CS1_bar <= '0';
955 CS2 <= '1';
956 WE_bar <= '0';
957 OE_RAM_bar <= '1';
958 UB_bar <= '0';
959 LB_bar <= '0';
960
961 --Senhales hacia mutiplexor
962 oe_ch_vector <= "00010";
963 hb_lbbar <= '0';
964
965 --Senhales hacia canales
966 ack_ch_vector <= (OTHERS=>'0');
967
968 --Senhales hacia SPI Controller o cache
969 ld_ram <= '0';
970
971 --Estado siguiente
972 IF (count_slw = ramwait_const2) THEN
973 ram_contr_next_state <= exe_wrt_ch2_2;
974 ELSE
975 ram_contr_next_state <= act_wrt_ch2_2;
976 END IF;
977
978 WHEN exe_wrt_ch2_2 =>
979
980 --Senhales hacia memoria RAM
981 CS1_bar <= '0';
982 CS2 <= '1';
983 WE_bar <= '0';
984 OE_RAM_bar <= '1';
985 UB_bar <= '0';
986 LB_bar <= '0';
987
988 --Senhales hacia mutiplexor
989 oe_ch_vector <= "00010";
990 hb_lbbar <= '0';
991
992 --Senhales hacia canales
993 ack_ch_vector <= "00010";
994
995 --Senhales hacia SPI Controller o cache
996 ld_ram <= '0';
997
998 --Estado siguiente
999 ram_contr_next_state <= end_wrt_cycle_2;
1000
1001
1002 --Inicio proceso de escritura en canal 3
1003 WHEN set_wrt_ch3_1 =>
1004
1005 --Senhales hacia memoria RAM
1006 CS1_bar <= '0';
1007 CS2 <= '1';
1008 WE_bar <= '0';
1009 OE_RAM_bar <= '1';
1010 UB_bar <= '0';
1011 LB_bar <= '0';
1012
1013 --Senhales hacia mutiplexor
1014 oe_ch_vector <= "00100";--(OTHERS=>'0');
1015 hb_lbbar <= '1';
1016
1017 --Senhales hacia canales
1018 ack_ch_vector <= (OTHERS=>'0');
1019
1020 --Senhales hacia SPI Controller o cache
1021 ld_ram <= '0';
1022
1023 --Estado siguiente
1024 IF (count_slw = ramwait_const1) THEN
1025 ram_contr_next_state <= act_wrt_ch3_1;
1026 ELSE
1027 ram_contr_next_state <= set_wrt_ch3_1;
1028 END IF;
1029
1030 WHEN act_wrt_ch3_1 =>
1031
1032 --Senhales hacia memoria RAM
1033 CS1_bar <= '0';
1034 CS2 <= '1';
1035 WE_bar <= '0';
1036 OE_RAM_bar <= '1';
1037 UB_bar <= '0';
1038 LB_bar <= '0';
1039
1040 --Senhales hacia mutiplexor
1041 oe_ch_vector <= "00100";
1042 hb_lbbar <= '1';
1043
1044 --Senhales hacia canales
1045 ack_ch_vector <= (OTHERS =>'0');
1046
1047 --Senhales hacia SPI Controller o cache
1048 ld_ram <= '0';
1049
1050 --Estado siguiente
1051 IF (count_slw = ramwait_const2) THEN
1052 ram_contr_next_state <= exe_wrt_ch3_1;
1053 ELSE
1054 ram_contr_next_state <= act_wrt_ch3_1;
1055 END IF;
1056
1057 WHEN exe_wrt_ch3_1 =>
1058
1059 --Senhales hacia memoria RAM
1060 CS1_bar <= '0';
1061 CS2 <= '1';
1062 WE_bar <= '0';
1063 OE_RAM_bar <= '1';
1064 UB_bar <= '0';
1065 LB_bar <= '0';
1066
1067 --Senhales hacia mutiplexor
1068 oe_ch_vector <= "00100";
1069 hb_lbbar <= '1';
1070
1071 --Senhales hacia canales
1072 ack_ch_vector <= (OTHERS=>'0');
1073
1074 --Senhales hacia SPI Controller o cache
1075 ld_ram <= '0';
1076
1077 --Estado siguiente
1078 ram_contr_next_state <= end_wrt_cycle_1;
1079
1080 --Inicio proceso de escritura en canal 3
1081 WHEN set_wrt_ch3_2 =>
1082
1083 --Senhales hacia memoria RAM
1084 CS1_bar <= '0';
1085 CS2 <= '1';
1086 WE_bar <= '0';
1087 OE_RAM_bar <= '1';
1088 UB_bar <= '0';
1089 LB_bar <= '0';
1090
1091 --Senhales hacia mutiplexor
1092 oe_ch_vector <= "00100";--(OTHERS=>'0');
1093 hb_lbbar <= '0';
1094
1095 --Senhales hacia canales
1096 ack_ch_vector <= (OTHERS=>'0');
1097
1098 --Senhales hacia SPI Controller o cache
1099 ld_ram <= '0';
1100
1101 --Estado siguiente
1102 IF (count_slw = ramwait_const1) THEN
1103 ram_contr_next_state <= act_wrt_ch3_2;
1104 ELSE
1105 ram_contr_next_state <= set_wrt_ch3_2;
1106 END IF;
1107
1108 WHEN act_wrt_ch3_2 =>
1109
1110 --Senhales hacia memoria RAM
1111 CS1_bar <= '0';
1112 CS2 <= '1';
1113 WE_bar <= '0';
1114 OE_RAM_bar <= '1';
1115 UB_bar <= '0';
1116 LB_bar <= '0';
1117
1118 --Senhales hacia mutiplexor
1119 oe_ch_vector <= "00100";
1120 hb_lbbar <= '0';
1121
1122 --Senhales hacia canales
1123 ack_ch_vector <= (OTHERS =>'0');
1124
1125 --Senhales hacia SPI Controller o cache
1126 ld_ram <= '0';
1127
1128 --Estado siguiente
1129 IF (count_slw = ramwait_const2) THEN
1130 ram_contr_next_state <= exe_wrt_ch3_2;
1131 ELSE
1132 ram_contr_next_state <= act_wrt_ch3_2;
1133 END IF;
1134
1135 WHEN exe_wrt_ch3_2 =>
1136
1137 --Senhales hacia memoria RAM
1138 CS1_bar <= '0';
1139 CS2 <= '1';
1140 WE_bar <= '0';
1141 OE_RAM_bar <= '1';
1142 UB_bar <= '0';
1143 LB_bar <= '0';
1144
1145 --Senhales hacia mutiplexor
1146 oe_ch_vector <= "00100";
1147 hb_lbbar <= '0';
1148
1149 --Senhales hacia canales
1150 ack_ch_vector <= "00100";
1151
1152 --Senhales hacia SPI Controller o cache
1153 ld_ram <= '0';
1154
1155 --Estado siguiente
1156 ram_contr_next_state <= end_wrt_cycle_2;
1157
1158 --Inicio proceso de escritura en canal 4
1159 WHEN set_wrt_ch4_1 =>
1160
1161 --Senhales hacia memoria RAM
1162 CS1_bar <= '0';
1163 CS2 <= '1';
1164 WE_bar <= '0';
1165 OE_RAM_bar <= '1';
1166 UB_bar <= '0';
1167 LB_bar <= '0';
1168
1169 --Senhales hacia mutiplexor
1170 oe_ch_vector <= "01000";
1171 hb_lbbar <= '1';
1172
1173 --Senhales hacia canales
1174 ack_ch_vector <= (OTHERS =>'0');
1175
1176 --Senhales hacia SPI Controller o cache
1177 ld_ram <= '0';
1178
1179 --Estado siguiente
1180 IF (count_slw = ramwait_const1) THEN
1181 ram_contr_next_state <= act_wrt_ch4_1;
1182 ELSE
1183 ram_contr_next_state <= set_wrt_ch4_1;
1184 END IF;
1185
1186 WHEN act_wrt_ch4_1 =>
1187
1188 --Senhales hacia memoria RAM
1189 CS1_bar <= '0';
1190 CS2 <= '1';
1191 WE_bar <= '0';
1192 OE_RAM_bar <= '1';
1193 UB_bar <= '0';
1194 LB_bar <= '0';
1195
1196 --Senhales hacia mutiplexor
1197 oe_ch_vector <= "01000";
1198 hb_lbbar <= '1';
1199
1200 --Senhales hacia canales
1201 ack_ch_vector <= (OTHERS=>'0');
1202
1203 --Senhales hacia SPI Controller o cache
1204 ld_ram <= '0';
1205
1206 --Estado siguiente
1207 IF (count_slw = ramwait_const2) THEN
1208 ram_contr_next_state <= exe_wrt_ch4_1;
1209 ELSE
1210 ram_contr_next_state <= act_wrt_ch4_1;
1211 END IF;
1212
1213 WHEN exe_wrt_ch4_1 =>
1214
1215 --Senhales hacia memoria RAM
1216 CS1_bar <= '0';
1217 CS2 <= '1';
1218 WE_bar <= '0';
1219 OE_RAM_bar <= '1';
1220 UB_bar <= '0';
1221 LB_bar <= '0';
1222
1223 --Senhales hacia mutiplexor
1224 oe_ch_vector <= "01000";
1225 hb_lbbar <= '1';
1226
1227 --Senhales hacia canales
1228 ack_ch_vector <= (OTHERS=>'0');
1229
1230 --Senhales hacia SPI Controller o cache
1231 ld_ram <= '0';
1232
1233 --Estado siguiente
1234 ram_contr_next_state <= end_wrt_cycle_1;
1235
1236 --Inicio proceso de escritura en canal 4
1237 WHEN set_wrt_ch4_2 =>
1238
1239 --Senhales hacia memoria RAM
1240 CS1_bar <= '0';
1241 CS2 <= '1';
1242 WE_bar <= '0';
1243 OE_RAM_bar <= '1';
1244 UB_bar <= '0';
1245 LB_bar <= '0';
1246
1247 --Senhales hacia mutiplexor
1248 oe_ch_vector <= "01000";
1249 hb_lbbar <= '0';
1250
1251 --Senhales hacia canales
1252 ack_ch_vector <= (OTHERS =>'0');
1253
1254 --Senhales hacia SPI Controller o cache
1255 ld_ram <= '0';
1256
1257 --Estado siguiente
1258 IF (count_slw = ramwait_const1) THEN
1259 ram_contr_next_state <= act_wrt_ch4_2;
1260 ELSE
1261 ram_contr_next_state <= set_wrt_ch4_2;
1262 END IF;
1263
1264 WHEN act_wrt_ch4_2 =>
1265
1266 --Senhales hacia memoria RAM
1267 CS1_bar <= '0';
1268 CS2 <= '1';
1269 WE_bar <= '0';
1270 OE_RAM_bar <= '1';
1271 UB_bar <= '0';
1272 LB_bar <= '0';
1273
1274 --Senhales hacia mutiplexor
1275 oe_ch_vector <= "01000";
1276 hb_lbbar <= '0';
1277
1278 --Senhales hacia canales
1279 ack_ch_vector <= (OTHERS=>'0');
1280
1281 --Senhales hacia SPI Controller o cache
1282 ld_ram <= '0';
1283
1284 --Estado siguiente
1285 IF (count_slw = ramwait_const2) THEN
1286 ram_contr_next_state <= exe_wrt_ch4_2;
1287 ELSE
1288 ram_contr_next_state <= act_wrt_ch4_2;
1289 END IF;
1290
1291 WHEN exe_wrt_ch4_2 =>
1292
1293 --Senhales hacia memoria RAM
1294 CS1_bar <= '0';
1295 CS2 <= '1';
1296 WE_bar <= '0';
1297 OE_RAM_bar <= '1';
1298 UB_bar <= '0';
1299 LB_bar <= '0';
1300
1301 --Senhales hacia mutiplexor
1302 oe_ch_vector <= "01000";
1303 hb_lbbar <= '0';
1304
1305 --Senhales hacia canales
1306 ack_ch_vector <= "01000";
1307
1308 --Senhales hacia SPI Controller o cache
1309 ld_ram <= '0';
1310
1311 --Estado siguiente
1312 ram_contr_next_state <= end_wrt_cycle_2;
1313
1314 --Inicio proceso de escritura en canal 5
1315 WHEN set_wrt_ch5_1 =>
1316
1317 --Senhales hacia memoria RAM
1318 CS1_bar <= '0';
1319 CS2 <= '1';
1320 WE_bar <= '0';
1321 OE_RAM_bar <= '1';
1322 UB_bar <= '0';
1323 LB_bar <= '0';
1324
1325 --Senhales hacia mutiplexor
1326 oe_ch_vector <= "10000";
1327 hb_lbbar <= '1';
1328
1329 --Senhales hacia canales
1330 ack_ch_vector <= (OTHERS =>'0');
1331
1332 --Senhales hacia SPI Controller o cache
1333 ld_ram <= '0';
1334
1335 --Estado siguiente
1336 IF (count_slw = ramwait_const1) THEN
1337 ram_contr_next_state <= act_wrt_ch5_1;
1338 ELSE
1339 ram_contr_next_state <= set_wrt_ch5_1;
1340 END IF;
1341
1342 WHEN act_wrt_ch5_1 =>
1343
1344 --Senhales hacia memoria RAM
1345 CS1_bar <= '0';
1346 CS2 <= '1';
1347 WE_bar <= '0';
1348 OE_RAM_bar <= '1';
1349 UB_bar <= '0';
1350 LB_bar <= '0';
1351
1352 --Senhales hacia mutiplexor
1353 oe_ch_vector <= "10000";
1354 hb_lbbar <= '1';
1355
1356 --Senhales hacia canales
1357 ack_ch_vector <= (OTHERS=>'0');
1358
1359 --Senhales hacia SPI Controller o cache
1360 ld_ram <= '0';
1361
1362 --Estado siguiente
1363 IF (count_slw = ramwait_const2) THEN
1364 ram_contr_next_state <= exe_wrt_ch5_1;
1365 ELSE
1366 ram_contr_next_state <= act_wrt_ch5_1;
1367 END IF;
1368
1369 WHEN exe_wrt_ch5_1 =>
1370
1371 --Senhales hacia memoria RAM
1372 CS1_bar <= '0';
1373 CS2 <= '1';
1374 WE_bar <= '0';
1375 OE_RAM_bar <= '1';
1376 UB_bar <= '0';
1377 LB_bar <= '0';
1378
1379 --Senhales hacia mutiplexor
1380 oe_ch_vector <= "10000";
1381 hb_lbbar <= '1';
1382
1383 --Senhales hacia canales
1384 ack_ch_vector <= (OTHERS=>'0');
1385
1386 --Senhales hacia el SPI Controller o cache
1387 ld_ram <= '0';
1388
1389 --Estado siguiente
1390 ram_contr_next_state <= end_wrt_cycle_1;
1391
1392 --Inicio proceso de escritura en canal 5
1393 WHEN set_wrt_ch5_2 =>
1394
1395 --Senhales hacia memoria RAM
1396 CS1_bar <= '0';
1397 CS2 <= '1';
1398 WE_bar <= '0';
1399 OE_RAM_bar <= '1';
1400 UB_bar <= '0';
1401 LB_bar <= '0';
1402
1403 --Senhales hacia mutiplexor
1404 oe_ch_vector <= "10000";
1405 hb_lbbar <= '0';
1406
1407 --Senhales hacia canales
1408 ack_ch_vector <= (OTHERS =>'0');
1409
1410 --Senhales hacia SPI Controller o cache
1411 ld_ram <= '0';
1412
1413 --Estado siguiente
1414 IF (count_slw = ramwait_const1) THEN
1415 ram_contr_next_state <= act_wrt_ch5_2;
1416 ELSE
1417 ram_contr_next_state <= set_wrt_ch5_2;
1418 END IF;
1419
1420 WHEN act_wrt_ch5_2 =>
1421
1422 --Senhales hacia memoria RAM
1423 CS1_bar <= '0';
1424 CS2 <= '1';
1425 WE_bar <= '0';
1426 OE_RAM_bar <= '1';
1427 UB_bar <= '0';
1428 LB_bar <= '0';
1429
1430 --Senhales hacia mutiplexor
1431 oe_ch_vector <= "10000";
1432 hb_lbbar <= '0';
1433
1434 --Senhales hacia canales
1435 ack_ch_vector <= (OTHERS=>'0');
1436
1437 --Senhales hacia SPI Controller o cache
1438 ld_ram <= '0';
1439
1440 --Estado siguiente
1441 IF (count_slw = ramwait_const2) THEN
1442 ram_contr_next_state <= exe_wrt_ch5_2;
1443 ELSE
1444 ram_contr_next_state <= act_wrt_ch5_2;
1445 END IF;
1446
1447 WHEN exe_wrt_ch5_2 =>
1448
1449 --Senhales hacia memoria RAM
1450 CS1_bar <= '0';
1451 CS2 <= '1';
1452 WE_bar <= '0';
1453 OE_RAM_bar <= '1';
1454 UB_bar <= '0';
1455 LB_bar <= '0';
1456
1457 --Senhales hacia mutiplexor
1458 oe_ch_vector <= "10000";
1459 hb_lbbar <= '0';
1460
1461 --Senhales hacia canales
1462 ack_ch_vector <= "10000";
1463
1464 --Senhales hacia el SPI Controller o cache
1465 ld_ram <= '0';
1466
1467 --Estado siguiente
1468 ram_contr_next_state <= end_wrt_cycle_2;
1469
1470 ---------------------------------
1471
1472 WHEN end_wrt_cycle_1 =>
1473
1474 --Senhales hacia memoria RAM
1475 CS1_bar <= '1';
1476 CS2 <= '0';
1477 WE_bar <= '1';
1478 OE_RAM_bar <= '1';
1479 UB_bar <= '1';
1480 LB_bar <= '1';
1481
1482 --Senhales hacia mutiplexor
1483 oe_ch_vector <= (OTHERS=>'0');
1484 hb_lbbar <= '0';
1485
1486 --Senhales hacia canales
1487 ack_ch_vector <= (OTHERS=>'0');
1488
1489 --Senhales hacia SPI Controller o cache
1490 ld_ram <= '0';
1491
1492 --Estado siguiente
1493 CASE ch_cont_cur_state IS
1494 WHEN attending_ch1 =>
1495 ram_contr_next_state <= set_wrt_ch1_2;
1496 WHEN attending_ch2 =>
1497 ram_contr_next_state <= set_wrt_ch2_2;
1498 WHEN attending_ch3 =>
1499 ram_contr_next_state <= set_wrt_ch3_2;
1500 WHEN attending_ch4 =>
1501 ram_contr_next_state <= set_wrt_ch4_2;
1502 WHEN attending_ch5 =>
1503 ram_contr_next_state <= set_wrt_ch5_2;
1504 WHEN OTHERS =>
1505 ram_contr_next_state <= espera_rdy;
1506 END CASE;
1507
1508
1509 WHEN end_wrt_cycle_2 =>
1510
1511 --Senhales hacia memoria RAM
1512 CS1_bar <= '1';
1513 CS2 <= '0';
1514 WE_bar <= '1';
1515 OE_RAM_bar <= '1';
1516 UB_bar <= '1';
1517 LB_bar <= '1';
1518
1519 --Senhales hacia mutiplexor
1520 oe_ch_vector <= (OTHERS=>'0');
1521 hb_lbbar <= '0';
1522
1523 --Senhales hacia canales
1524 ack_ch_vector <= (OTHERS=>'0');
1525
1526 --Senhales hacia SPI Controller o cache
1527 ld_ram <= '0';
1528
1529 --Estado siguiente
1530 ram_contr_next_state <= espera_rdy;
1531
1532
1533 ---------------------------------
1534
1535 WHEN espera_req =>
1536
1537 --Senhales hacia memoria RAM
1538 CS1_bar <= '1';
1539 CS2 <= '0';
1540 WE_bar <= '1';
1541 OE_RAM_bar <= '1';
1542 UB_bar <= '1';
1543 LB_bar <= '1';
1544
1545 --Senhales hacia mutiplexor
1546 oe_ch_vector <= (OTHERS => '0');
1547 hb_lbbar <= '0';
1548
1549 --Senhales hacia canales
1550 ack_ch_vector <= (OTHERS =>'0');
1551
1552 --Senhales hacia SPI Controller o cache
1553 ld_ram <= '0';
1554
1555 --Estado siguiente
1556 IF (rd_req = '1') THEN
1557 ram_contr_next_state <= set_rd;
1558 ELSE
1559 ram_contr_next_state <= espera_req;
1560 END IF;
1561
1562 WHEN set_rd =>
1563
1564 --Senhales hacia memoria RAM
1565 CS1_bar <= '0';
1566 CS2 <= '1';
1567 WE_bar <= '1';
1568 OE_RAM_bar <= '0';
1569 UB_bar <= '0';
1570 LB_bar <= '0';
1571
1572 --Senhales hacia mutiplexor
1573 oe_ch_vector <= (OTHERS => '0');
1574 hb_lbbar <= '0';
1575
1576 --Senhales hacia canales
1577 ack_ch_vector <= (OTHERS=>'0');
1578
1579 --Senhales hacia SPI Controller o cache
1580 ld_ram <= '0';
1581
1582 --Estado siguiente
1583 ram_contr_next_state <= act_rd;
1584
1585 WHEN act_rd =>
1586
1587 --Senhales hacia memoria RAM
1588 CS1_bar <= '0';
1589 CS2 <= '1';
1590 WE_bar <= '1';
1591 OE_RAM_bar <= '0';
1592 UB_bar <= '0';
1593 LB_bar <= '0';
1594
1595 --Senhales hacia mutiplexor
1596 oe_ch_vector <= (OTHERS => '0');
1597 hb_lbbar <= '0';
1598
1599 --Senhales hacia canales
1600 ack_ch_vector <= (OTHERS => '0');
1601
1602 --Senhales hacia SPI Controller o cache
1603 ld_ram <= '0';
1604
1605 --Estado siguiente
1606 IF (count_slw = ramwait_const2) THEN
1607 ram_contr_next_state <= exe_rd;
1608 ELSE
1609 ram_contr_next_state <= act_rd;
1610 END IF;
1611
1612 WHEN exe_rd =>
1613
1614 --Senhales hacia memoria RAM
1615 CS1_bar <= '0';
1616 CS2 <= '1';
1617 WE_bar <= '1';
1618 OE_RAM_bar <= '0';
1619 UB_bar <= '0';
1620 LB_bar <= '0';
1621
1622 --Senhales hacia mutiplexor
1623 oe_ch_vector <= (OTHERS=>'0');
1624 hb_lbbar <= '0';
1625
1626 --Senhales hacia canales
1627 ack_ch_vector <= (OTHERS=>'0');
1628
1629 --Senhales hacia SPI Controller o cache
1630 ld_ram <= '1';
1631
1632
1633 --Estado siguiente
1634 IF (rd_req = '0') THEN
1635 ram_contr_next_state <= end_rd;
1636 ELSE
1637 ram_contr_next_state <= exe_rd;
1638 END IF;
1639
1640 WHEN end_rd =>
1641
1642 --Senhales hacia memoria RAM
1643 CS1_bar <= '0';
1644 CS2 <= '1';
1645 WE_bar <= '1';
1646 OE_RAM_bar <= '0';
1647 UB_bar <= '0';
1648 LB_bar <= '0';
1649
1650 --Senhales hacia mutiplexor
1651 oe_ch_vector <= (OTHERS=>'0');
1652 hb_lbbar <= '0';
1653
1654 --Senhales hacia canales
1655 ack_ch_vector <= (OTHERS=>'0');
1656
1657 --Senhales hacia SPI Controller o cache
1658 ld_ram <= '0';
1659
1660 --Estado siguiente
1661 IF (addr_rd_aux = TOP_GL) THEN
1662 ram_contr_next_state <= end_rd;
1663 ELSE
1664 ram_contr_next_state <= espera_req;
1665 END IF;
1666
1667 WHEN OTHERS =>
1668
1669 --Senhales hacia memoria RAM
1670 CS1_bar <= '1';
1671 CS2 <= '0';
1672 WE_bar <= '1';
1673 OE_RAM_bar <= '1';
1674 UB_bar <= '1';
1675 LB_bar <= '1';
1676
1677 --Senhales hacia mutiplexor
1678 oe_ch_vector <= (OTHERS=>'0');
1679 hb_lbbar <= '0';
1680
1681 --Senhales hacia canales
1682 ack_ch_vector <= (OTHERS=>'0');
1683
1684 --Senhales hacia SPI Controller o cache
1685 ld_ram <= '0';
1686
1687 --Estado siguiente
1688 ram_contr_next_state <= idle;
1689
1690
1691 END CASE;
1692 END PROCESS;
1693
1694
1695 contador_10ns: PROCESS(clk_main)
1696 BEGIN
1697 IF (rising_edge(clk_main)) THEN
1698 IF(rst_bar = '0') THEN
1699 count_slw <= (OTHERS=>'0');
1700 ELSE
1701
1702 CASE ram_contr_cur_state IS
1703 WHEN set_wrt_ch1_1 |
1704 set_wrt_ch1_2 |
1705 set_wrt_ch2_1 |
1706 set_wrt_ch2_2 |
1707 set_wrt_ch3_1 |
1708 set_wrt_ch3_2 |
1709 set_wrt_ch4_1 |
1710 set_wrt_ch4_2 |
1711 set_wrt_ch5_1 |
1712 set_wrt_ch5_2 |
1713 set_erase_ram
1714 =>
1715
1716 IF(count_slw = ramwait_const1) THEN
1717 count_slw <= (OTHERS=>'0');
1718 ELSE
1719 count_slw <= std_logic_vector(unsigned(count_slw) + 1);
1720 END IF;
1721
1722 WHEN act_wrt_ch1_1 |
1723 act_wrt_ch1_2 |
1724 act_wrt_ch2_1 |
1725 act_wrt_ch2_2 |
1726 act_wrt_ch3_1 |
1727 act_wrt_ch3_2 |
1728 act_wrt_ch4_1 |
1729 act_wrt_ch4_2 |
1730 act_wrt_ch5_1 |
1731 act_wrt_ch5_2 |
1732 act_erase_ram |
1733 act_rd =>
1734 count_slw <= std_logic_vector(unsigned(count_slw) + 1);
1735 IF(count_slw = ramwait_const2) THEN
1736 count_slw <= (OTHERS=>'0');
1737 ELSE
1738 count_slw <= std_logic_vector(unsigned(count_slw) + 1);
1739 END IF;
1740
1741
1742 WHEN OTHERS =>
1743 count_slw <= (OTHERS=>'0');
1744
1745 END CASE;
1746 END IF;
1747 END IF;
1748 END PROCESS;
1749
1750 end Behavioral;
1751
Show file before | Show file after | Hide comments
@@ -0,0 +1,2
1 C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.ngc 1464025067
2 OK
Show file before | Show file after | Hide comments
@@ -0,0 +1,15
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">clk_mang/DCM_SP_inst_int</arg>, consult the device Data Sheet.
9 </msg>
10
11 <msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">clk_mang/DCM_SP_inst</arg>, consult the device Data Sheet.
12 </msg>
13
14 </messages>
15
Show file before | Show file after | Hide comments
@@ -0,0 +1,33
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
9 </msg>
10
11 <msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
12 </msg>
13
14 <msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
15 </msg>
16
17 <msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)
18 </msg>
19
20 <msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).
21 </msg>
22
23 <msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.
24 </msg>
25
26 <msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">clk_mang/DCM_SP_inst_int</arg>, consult the device Data Sheet.
27 </msg>
28
29 <msg type="info" file="PhysDesignRules" num="1861" delta="old" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp <arg fmt="%s" index="1">clk_mang/DCM_SP_inst</arg>, consult the device Data Sheet.
30 </msg>
31
32 </messages>
33
Show file before | Show file after | Hide comments
@@ -0,0 +1,18
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="NetListWriters" num="635" delta="old" >The generated VHDL netlist contains Xilinx <arg fmt="%s" index="1">SIMPRIM</arg> simulation primitives and has to be used with <arg fmt="%s" index="2">SIMPRIM</arg> library for correct compilation and simulation.
9 </msg>
10
11 <msg type="info" file="NetListWriters" num="0" delta="new" >Xilinx recommends running separate simulations to check for setup by specifying the MAX field in the SDF file and for hold by specifying the MIN field in the SDF file. Please refer to Simulator documentation for more details on specifying MIN and MAX field in the SDF.
12 </msg>
13
14 <msg type="info" file="NetListWriters" num="665" delta="old" >For more information on how to pass the SDF switches to the simulator, see your Simulator tool documentation.
15 </msg>
16
17 </messages>
18
Show file before | Show file after | Hide comments
@@ -0,0 +1,17
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">clk_main</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_clk_main</arg>&apos;, was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">clk_mang/DCM_SP_inst_int</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s):
9 <arg fmt="%s" index="7">CLKFX</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_clk_u_proc = PERIOD &quot;clk_u_proc&quot; TS_clk_main / 4 HIGH 50%&gt;</arg>
10 </msg>
11
12 <msg type="info" file="ConstraintSystem" num="178" delta="old" ><arg fmt="%s" index="1">TNM</arg> &apos;<arg fmt="%s" index="2">clk_main</arg>&apos;, used in period specification &apos;<arg fmt="%s" index="3">TS_clk_main</arg>&apos;, was traced into <arg fmt="%s" index="4">DCM_SP</arg> instance <arg fmt="%s" index="5">clk_mang/DCM_SP_inst</arg>. The following new TNM groups and period specifications were generated at the <arg fmt="%s" index="6">DCM_SP</arg> output(s):
13 <arg fmt="%s" index="7">CLKFX</arg>: <arg fmt="%s" index="8">&lt;TIMESPEC TS_clk_mang_c_16MHz = PERIOD &quot;clk_mang_c_16MHz&quot; TS_clk_main / 0.266666667 HIGH 50%&gt;</arg>
14 </msg>
15
16 </messages>
17
Show file before | Show file after | Hide comments
@@ -0,0 +1,9
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 </messages>
9
Show file before | Show file after | Hide comments
@@ -0,0 +1,15
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated -->
3 <!-- by the Xilinx ISE software. Any direct editing or -->
4 <!-- changes made to this file may result in unpredictable -->
5 <!-- behavior or data corruption. It is strongly advised that -->
6 <!-- users do not edit the contents of this file. -->
7 <!-- -->
8 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
9
10 <messages>
11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd&quot; into library work</arg>
12 </msg>
13
14 </messages>
15
Show file before | Show file after | Hide comments
@@ -0,0 +1,15
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
9
10 <msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
11
12 <msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
13
14 </messages>
15
Show file before | Show file after | Hide comments
@@ -0,0 +1,21
1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated
3 by the Xilinx ISE software. Any direct editing or
4 changes made to this file may result in unpredictable
5 behavior or data corruption. It is strongly advised that
6 users do not edit the contents of this file. -->
7 <messages>
8 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd</arg>&quot; line <arg fmt="%s" index="2">383</arg>: Output port &lt;<arg fmt="%s" index="3">cs1_bar</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">nb_mem_cont</arg>&gt; is unconnected or connected to loadless signal.
9 </msg>
10
11 <msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd</arg>&quot; line <arg fmt="%s" index="2">383</arg>: Output port &lt;<arg fmt="%s" index="3">cs2</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">nb_mem_cont</arg>&gt; is unconnected or connected to loadless signal.
12 </msg>
13
14 <msg type="info" file="Xst" num="1767" delta="old" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
15 </msg>
16
17 <msg type="info" file="Xst" num="3231" delta="old" >The small RAM &lt;<arg fmt="%s" index="1">Mram_data_header</arg>&gt; will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
18 </msg>
19
20 </messages>
21
Show file before | Show file after | Hide comments
@@ -0,0 +1,141
1 Release 14.7 - Bitgen P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 Loading device for application Rf_Device from file '6slx9.nph' in environment
4 C:\Xilinx\14.7\ISE_DS\ISE\.
5 "chn5_mem_spi_joint" is an NCD, version 3.2, device xc6slx9, package tqg144,
6 speed -3
7 Opened constraints file chn5_mem_spi_joint.pcf.
8
9 Mon May 23 12:39:01 2016
10
11 C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 chn5_mem_spi_joint.ncd
12
13 Summary of Bitgen Options:
14 +----------------------+----------------------+
15 | Option Name | Current Setting |
16 +----------------------+----------------------+
17 | Compress | (Not Specified)* |
18 +----------------------+----------------------+
19 | Readback | (Not Specified)* |
20 +----------------------+----------------------+
21 | CRC | Enable** |
22 +----------------------+----------------------+
23 | DebugBitstream | No** |
24 +----------------------+----------------------+
25 | ConfigRate | 2** |
26 +----------------------+----------------------+
27 | StartupClk | Cclk** |
28 +----------------------+----------------------+
29 | DonePin | Pullup* |
30 +----------------------+----------------------+
31 | ProgPin | Pullup** |
32 +----------------------+----------------------+
33 | TckPin | Pullup** |
34 +----------------------+----------------------+
35 | TdiPin | Pullup** |
36 +----------------------+----------------------+
37 | TdoPin | Pullup** |
38 +----------------------+----------------------+
39 | TmsPin | Pullup** |
40 +----------------------+----------------------+
41 | UnusedPin | Pulldown** |
42 +----------------------+----------------------+
43 | GWE_cycle | 6** |
44 +----------------------+----------------------+
45 | GTS_cycle | 5** |
46 +----------------------+----------------------+
47 | LCK_cycle | NoWait** |
48 +----------------------+----------------------+
49 | DONE_cycle | 4** |
50 +----------------------+----------------------+
51 | Persist | No* |
52 +----------------------+----------------------+
53 | DriveDone | No** |
54 +----------------------+----------------------+
55 | DonePipe | Yes |
56 +----------------------+----------------------+
57 | Security | None** |
58 +----------------------+----------------------+
59 | UserID | 0xFFFFFFFF** |
60 +----------------------+----------------------+
61 | ActiveReconfig | No* |
62 +----------------------+----------------------+
63 | Partial | (Not Specified)* |
64 +----------------------+----------------------+
65 | Encrypt | No* |
66 +----------------------+----------------------+
67 | Key0 | pick* |
68 +----------------------+----------------------+
69 | StartCBC | pick* |
70 +----------------------+----------------------+
71 | KeyFile | (Not Specified)* |
72 +----------------------+----------------------+
73 | drive_awake | No** |
74 +----------------------+----------------------+
75 | Reset_on_err | No** |
76 +----------------------+----------------------+
77 | suspend_filter | Yes* |
78 +----------------------+----------------------+
79 | en_sw_gsr | No** |
80 +----------------------+----------------------+
81 | en_suspend | No* |
82 +----------------------+----------------------+
83 | sw_clk | Startupclk** |
84 +----------------------+----------------------+
85 | sw_gwe_cycle | 5** |
86 +----------------------+----------------------+
87 | sw_gts_cycle | 4** |
88 +----------------------+----------------------+
89 | multipin_wakeup | No** |
90 +----------------------+----------------------+
91 | wakeup_mask | 0x00* |
92 +----------------------+----------------------+
93 | ExtMasterCclk_en | No** |
94 +----------------------+----------------------+
95 | ExtMasterCclk_divide | 1* |
96 +----------------------+----------------------+
97 | CrcCoverage | No* |
98 +----------------------+----------------------+
99 | glutmask | Yes* |
100 +----------------------+----------------------+
101 | next_config_addr | 0x00000000* |
102 +----------------------+----------------------+
103 | next_config_new_mode | No* |
104 +----------------------+----------------------+
105 | next_config_boot_mode | 001* |
106 +----------------------+----------------------+
107 | next_config_register_write | Enable* |
108 +----------------------+----------------------+
109 | next_config_reboot | Enable* |
110 +----------------------+----------------------+
111 | golden_config_addr | 0x00000000* |
112 +----------------------+----------------------+
113 | failsafe_user | 0x0000* |
114 +----------------------+----------------------+
115 | TIMER_CFG | 0xFFFF |
116 +----------------------+----------------------+
117 | spi_buswidth | 1** |
118 +----------------------+----------------------+
119 | TimeStamp | Default* |
120 +----------------------+----------------------+
121 | IEEE1532 | No* |
122 +----------------------+----------------------+
123 | Binary | No** |
124 +----------------------+----------------------+
125 * Default setting.
126 ** The specified setting matches the default setting.
127
128 There were 0 CONFIG constraint(s) processed from chn5_mem_spi_joint.pcf.
129
130
131 Running DRC.
132 INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
133 with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int,
134 consult the device Data Sheet.
135 INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
136 with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst,
137 consult the device Data Sheet.
138 DRC detected 0 errors and 0 warnings.
139 Creating bit map...
140 Saving bit stream in "chn5_mem_spi_joint.bit".
141 Bitstream generation is complete.
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
Show file before | Show file after | Hide comments
@@ -0,0 +1,52
1 Release 14.7 ngdbuild P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
5 -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p
6 xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
7
8 Reading NGO file
9 "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_s
10 pi_joint/chn5_mem_spi_joint.ngc" ...
11 Gathering constraint information from source properties...
12 Done.
13
14 Annotating constraints to design from ucf file "chn5_mem_spi_joint.ucf" ...
15 Resolving constraint associations...
16 Checking Constraint Associations...
17 INFO:ConstraintSystem:178 - TNM 'clk_main', used in period specification
18 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst_int. The
19 following new TNM groups and period specifications were generated at the
20 DCM_SP output(s):
21 CLKFX: <TIMESPEC TS_clk_u_proc = PERIOD "clk_u_proc" TS_clk_main / 4 HIGH
22 50%>
23
24 INFO:ConstraintSystem:178 - TNM 'clk_main', used in period specification
25 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst. The
26 following new TNM groups and period specifications were generated at the
27 DCM_SP output(s):
28 CLKFX: <TIMESPEC TS_clk_mang_c_16MHz = PERIOD "clk_mang_c_16MHz" TS_clk_main
29 / 0.266666667 HIGH 50%>
30
31 Done...
32
33 Checking expanded design ...
34
35 Partition Implementation Status
36 -------------------------------
37
38 No Partitions were found in this design.
39
40 -------------------------------
41
42 NGDBUILD Design Results Summary:
43 Number of errors: 0
44 Number of warnings: 0
45
46 Total memory usage is 174432 kilobytes
47
48 Writing NGD file "chn5_mem_spi_joint.ngd" ...
49 Total REAL time to NGDBUILD completion: 4 sec
50 Total CPU time to NGDBUILD completion: 4 sec
51
52 Writing NGDBUILD log file "chn5_mem_spi_joint.bld"...
Show file before | Show file after | Hide comments
@@ -0,0 +1,315
1 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
2 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
3 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
4 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
5 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
6 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
7 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
8 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
9 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
10 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
11 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
12 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
13 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
14 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
15 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
16 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
17 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
18 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
19 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
20 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
21 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
22 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
23 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
24 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
25 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
26 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
27 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
28 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
29 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
30 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
31 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
32 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
33 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
34 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
35 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
36 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
37 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
38 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
39 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
40 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
41 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
42 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
43 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
44 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
45 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
46 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
47 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
48 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
49 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
50 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
51 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
52 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
53 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
54 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
55 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
56 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
57 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
58 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
59 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
60 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
61 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
62 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
63 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
64 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
65 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
66 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
67 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
68 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
69 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
70 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
71 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
72 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
73 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
74 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
75 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
76 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
77 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
78 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
79 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
80 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
81 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
82 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
83 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
84 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
85 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
86 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
87 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
88 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
89 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
90 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
91 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
92 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
93 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
94 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
95 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
96 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
97 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
98 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
99 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
100 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
101 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
102 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
103 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
104 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
105 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
106 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
107 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
108 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
109 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
110 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
111 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
112 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
113 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
114 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
115 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
116 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
117 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
118 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
119 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
120 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
121 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
122 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
123 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
124 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
125 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
126 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
127 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
128 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
129 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
130 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
131 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
132 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
133 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
134 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
135 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
136 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
137 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
138 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
139 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
140 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
141 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
142 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
143 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
144 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
145 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
146 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
147 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
148 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
149 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
150 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
151 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
152 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
153 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
154 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
155 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
156 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
157 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
158 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
159 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
160 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
161 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
162 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
163 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
164 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
165 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
166 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
167 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
168 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
169 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
170 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
171 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
172 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
173 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
174 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
175 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
176 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
177 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
178 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
179 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
180 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
181 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
182 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
183 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
184 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
185 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
186 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
187 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
188 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
189 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
190 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
191 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
192 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
193 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
194 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
195 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
196 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
197 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
198 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
199 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
200 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
201 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
202 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
203 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
204 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
205 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
206 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
207 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
208 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
209 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
210 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
211 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
212 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
213 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
214 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
215 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
216 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
217 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
218 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
219 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
220 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
221 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
222 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
223 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
224 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
225 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
226 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
227 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
228 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
229 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
230 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
231 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
232 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
233 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
234 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
235 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
236 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
237 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
238 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
239 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
240 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
241 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
242 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
243 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
244 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
245 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
246 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
247 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
248 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
249 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
250 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
251 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
252 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
253 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
254 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
255 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
256 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
257 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
258 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
259 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
260 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
261 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
262 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
263 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
264 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
265 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
266 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
267 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
268 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
269 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
270 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
271 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
272 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
273 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
274 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
275 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
276 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
277 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
278 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
279 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
280 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
281 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
282 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
283 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
284 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
285 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
286 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
287 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
288 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
289 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
290 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
291 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
292 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
293 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
294 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
295 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
296 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
297 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
298 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
299 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
300 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
301 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
302 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
303 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
304 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
305 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
306 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
307 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
308 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
309 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
310 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr"
311 ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd
312 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf
313 par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
314 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf
315 bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd
Show file before | Show file after | Hide comments
@@ -0,0 +1,14
1 Release 14.7 Drc P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 Mon May 23 12:39:01 2016
5
6 drc -z chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf
7
8 INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
9 with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int,
10 consult the device Data Sheet.
11 INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance
12 with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst,
13 consult the device Data Sheet.
14 DRC detected 0 errors and 0 warnings.
Show file before | Show file after | Hide comments
@@ -0,0 +1,201
1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2 <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4 <!-- -->
5
6 <!-- For tool use only. Do not edit. -->
7
8 <!-- -->
9
10 <!-- ProjectNavigator created generated project file. -->
11
12 <!-- For use in tracking generated file and other information -->
13
14 <!-- allowing preservation of process status. -->
15
16 <!-- -->
17
18 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
19
20 <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21
22 <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="chn5_mem_spi_joint.xise"/>
23
24 <files xmlns="http://www.xilinx.com/XMLSchema">
25 <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="DCM_fwd_int.prj"/>
26 <file xil_pn:fileType="FILE_XST_STX" xil_pn:name="DCM_fwd_int.stx"/>
27 <file xil_pn:fileType="FILE_XST" xil_pn:name="DCM_fwd_int.xst"/>
28 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
29 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
30 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
31 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
32 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
33 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
34 <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
35 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="chn5_mem_spi_joint.bgn" xil_pn:subbranch="FPGAConfiguration"/>
36 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="chn5_mem_spi_joint.bit" xil_pn:subbranch="FPGAConfiguration"/>
37 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="chn5_mem_spi_joint.bld"/>
38 <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="chn5_mem_spi_joint.cmd_log"/>
39 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="chn5_mem_spi_joint.drc" xil_pn:subbranch="FPGAConfiguration"/>
40 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="chn5_mem_spi_joint.lso"/>
41 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="chn5_mem_spi_joint.ncd" xil_pn:subbranch="Par"/>
42 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="chn5_mem_spi_joint.ngc"/>
43 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="chn5_mem_spi_joint.ngd"/>
44 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="chn5_mem_spi_joint.ngr"/>
45 <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="chn5_mem_spi_joint.pad"/>
46 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="chn5_mem_spi_joint.par" xil_pn:subbranch="Par"/>
47 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="chn5_mem_spi_joint.pcf" xil_pn:subbranch="Map"/>
48 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="chn5_mem_spi_joint.prj"/>
49 <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="chn5_mem_spi_joint.ptwx"/>
50 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="chn5_mem_spi_joint.stx"/>
51 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="chn5_mem_spi_joint.syr"/>
52 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="chn5_mem_spi_joint.twr" xil_pn:subbranch="Par"/>
53 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="chn5_mem_spi_joint.twx" xil_pn:subbranch="Par"/>
54 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="chn5_mem_spi_joint.unroutes" xil_pn:subbranch="Par"/>
55 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="chn5_mem_spi_joint.ut" xil_pn:subbranch="FPGAConfiguration"/>
56 <file xil_pn:fileType="FILE_XPI" xil_pn:name="chn5_mem_spi_joint.xpi"/>
57 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="chn5_mem_spi_joint.xst"/>
58 <file xil_pn:fileType="FILE_HTML" xil_pn:name="chn5_mem_spi_joint_envsettings.html"/>
59 <file xil_pn:fileType="FILE_NCD" xil_pn:name="chn5_mem_spi_joint_guide.ncd" xil_pn:origination="imported"/>
60 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="chn5_mem_spi_joint_map.map" xil_pn:subbranch="Map"/>
61 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="chn5_mem_spi_joint_map.mrp" xil_pn:subbranch="Map"/>
62 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="chn5_mem_spi_joint_map.ncd" xil_pn:subbranch="Map"/>
63 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="chn5_mem_spi_joint_map.ngm" xil_pn:subbranch="Map"/>
64 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="chn5_mem_spi_joint_map.xrpt"/>
65 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="chn5_mem_spi_joint_ngdbuild.xrpt"/>
66 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="chn5_mem_spi_joint_pad.csv" xil_pn:subbranch="Par"/>
67 <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="chn5_mem_spi_joint_pad.txt" xil_pn:subbranch="Par"/>
68 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="chn5_mem_spi_joint_par.xrpt"/>
69 <file xil_pn:fileType="FILE_HTML" xil_pn:name="chn5_mem_spi_joint_summary.html"/>
70 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="chn5_mem_spi_joint_summary.xml"/>
71 <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="chn5_mem_spi_joint_usage.xml"/>
72 <file xil_pn:fileType="FILE_XRPT" xil_pn:name="chn5_mem_spi_joint_xst.xrpt"/>
73 <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
74 <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
75 <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
76 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
77 <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
78 </files>
79
80 <transforms xmlns="http://www.xilinx.com/XMLSchema">
81 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1463687880">
82 <status xil_pn:value="SuccessfullyRun"/>
83 <status xil_pn:value="ReadyToRun"/>
84 </transform>
85 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8155895965503948603" xil_pn:start_ts="1463687880">
86 <status xil_pn:value="SuccessfullyRun"/>
87 <status xil_pn:value="ReadyToRun"/>
88 </transform>
89 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-7290404255456149813" xil_pn:start_ts="1463687880">
90 <status xil_pn:value="SuccessfullyRun"/>
91 <status xil_pn:value="ReadyToRun"/>
92 </transform>
93 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1463687880">
94 <status xil_pn:value="SuccessfullyRun"/>
95 <status xil_pn:value="ReadyToRun"/>
96 </transform>
97 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-6416231055069081795" xil_pn:start_ts="1463687880">
98 <status xil_pn:value="SuccessfullyRun"/>
99 <status xil_pn:value="ReadyToRun"/>
100 </transform>
101 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1463687880">
102 <status xil_pn:value="SuccessfullyRun"/>
103 <status xil_pn:value="ReadyToRun"/>
104 </transform>
105 <transform xil_pn:end_ts="1463687880" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="7433658368434266261" xil_pn:start_ts="1463687880">
106 <status xil_pn:value="SuccessfullyRun"/>
107 <status xil_pn:value="ReadyToRun"/>
108 </transform>
109 <transform xil_pn:end_ts="1464025068" xil_pn:in_ck="5522722112263450563" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-6219456823016501276" xil_pn:start_ts="1464025053">
110 <status xil_pn:value="SuccessfullyRun"/>
111 <status xil_pn:value="ReadyToRun"/>
112 <status xil_pn:value="OutOfDateForInputs"/>
113 <status xil_pn:value="OutOfDateForOutputs"/>
114 <status xil_pn:value="InputChanged"/>
115 <status xil_pn:value="OutputChanged"/>
116 <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
117 <outfile xil_pn:name="chn5_mem_spi_joint.lso"/>
118 <outfile xil_pn:name="chn5_mem_spi_joint.ngc"/>
119 <outfile xil_pn:name="chn5_mem_spi_joint.ngr"/>
120 <outfile xil_pn:name="chn5_mem_spi_joint.prj"/>
121 <outfile xil_pn:name="chn5_mem_spi_joint.stx"/>
122 <outfile xil_pn:name="chn5_mem_spi_joint.syr"/>
123 <outfile xil_pn:name="chn5_mem_spi_joint.xst"/>
124 <outfile xil_pn:name="chn5_mem_spi_joint_xst.xrpt"/>
125 <outfile xil_pn:name="webtalk_pn.xml"/>
126 <outfile xil_pn:name="xst"/>
127 </transform>
128 <transform xil_pn:end_ts="1464015766" xil_pn:in_ck="-7487914070404904058" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5602151997339985106" xil_pn:start_ts="1464015766">
129 <status xil_pn:value="SuccessfullyRun"/>
130 <status xil_pn:value="ReadyToRun"/>
131 </transform>
132 <transform xil_pn:end_ts="1464025075" xil_pn:in_ck="5201827462493350342" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4275896679710679670" xil_pn:start_ts="1464025068">
133 <status xil_pn:value="SuccessfullyRun"/>
134 <status xil_pn:value="ReadyToRun"/>
135 <status xil_pn:value="OutOfDateForPredecessor"/>
136 <outfile xil_pn:name="_ngo"/>
137 <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
138 <outfile xil_pn:name="chn5_mem_spi_joint.bld"/>
139 <outfile xil_pn:name="chn5_mem_spi_joint.ngd"/>
140 <outfile xil_pn:name="chn5_mem_spi_joint_ngdbuild.xrpt"/>
141 </transform>
142 <transform xil_pn:end_ts="1464025099" xil_pn:in_ck="-2026532210470860665" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="6093601622908603872" xil_pn:start_ts="1464025075">
143 <status xil_pn:value="SuccessfullyRun"/>
144 <status xil_pn:value="ReadyToRun"/>
145 <status xil_pn:value="OutOfDateForPredecessor"/>
146 <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
147 <outfile xil_pn:name="chn5_mem_spi_joint.pcf"/>
148 <outfile xil_pn:name="chn5_mem_spi_joint_map.map"/>
149 <outfile xil_pn:name="chn5_mem_spi_joint_map.mrp"/>
150 <outfile xil_pn:name="chn5_mem_spi_joint_map.ncd"/>
151 <outfile xil_pn:name="chn5_mem_spi_joint_map.ngm"/>
152 <outfile xil_pn:name="chn5_mem_spi_joint_map.xrpt"/>
153 <outfile xil_pn:name="chn5_mem_spi_joint_summary.xml"/>
154 <outfile xil_pn:name="chn5_mem_spi_joint_usage.xml"/>
155 </transform>
156 <transform xil_pn:end_ts="1464025136" xil_pn:in_ck="-4754640365542085408" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1464025099">
157 <status xil_pn:value="SuccessfullyRun"/>
158 <status xil_pn:value="ReadyToRun"/>
159 <status xil_pn:value="OutOfDateForPredecessor"/>
160 <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
161 <outfile xil_pn:name="chn5_mem_spi_joint.ncd"/>
162 <outfile xil_pn:name="chn5_mem_spi_joint.pad"/>
163 <outfile xil_pn:name="chn5_mem_spi_joint.par"/>
164 <outfile xil_pn:name="chn5_mem_spi_joint.ptwx"/>
165 <outfile xil_pn:name="chn5_mem_spi_joint.unroutes"/>
166 <outfile xil_pn:name="chn5_mem_spi_joint.xpi"/>
167 <outfile xil_pn:name="chn5_mem_spi_joint_pad.csv"/>
168 <outfile xil_pn:name="chn5_mem_spi_joint_pad.txt"/>
169 <outfile xil_pn:name="chn5_mem_spi_joint_par.xrpt"/>
170 </transform>
171 <transform xil_pn:end_ts="1464025155" xil_pn:in_ck="-7487914070404911683" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1464025136">
172 <status xil_pn:value="SuccessfullyRun"/>
173 <status xil_pn:value="ReadyToRun"/>
174 <status xil_pn:value="OutOfDateForPredecessor"/>
175 <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
176 <outfile xil_pn:name="chn5_mem_spi_joint.bgn"/>
177 <outfile xil_pn:name="chn5_mem_spi_joint.bit"/>
178 <outfile xil_pn:name="chn5_mem_spi_joint.drc"/>
179 <outfile xil_pn:name="chn5_mem_spi_joint.ut"/>
180 <outfile xil_pn:name="usage_statistics_webtalk.html"/>
181 <outfile xil_pn:name="webtalk.log"/>
182 <outfile xil_pn:name="webtalk_pn.xml"/>
183 </transform>
184 <transform xil_pn:end_ts="1464025136" xil_pn:in_ck="-7113747212091691773" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1464025129">
185 <status xil_pn:value="SuccessfullyRun"/>
186 <status xil_pn:value="ReadyToRun"/>
187 <status xil_pn:value="OutOfDateForPredecessor"/>
188 <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
189 <outfile xil_pn:name="chn5_mem_spi_joint.twr"/>
190 <outfile xil_pn:name="chn5_mem_spi_joint.twx"/>
191 </transform>
192 <transform xil_pn:end_ts="1464015678" xil_pn:in_ck="-2026532210470860665" xil_pn:name="TRAN_createTimingConstraints" xil_pn:start_ts="1464015678">
193 <status xil_pn:value="SuccessfullyRun"/>
194 <status xil_pn:value="ReadyToRun"/>
195 <status xil_pn:value="OutOfDateForInputs"/>
196 <status xil_pn:value="OutOfDateForPredecessor"/>
197 <status xil_pn:value="InputChanged"/>
198 </transform>
199 </transforms>
200
201 </generated_project>
Show file before | Show file after | Hide comments
@@ -0,0 +1,1
1 work
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
General Comments 0
You need to be logged in to leave comments. Login now