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53 | </toolChain> | |||
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55 | </configuration> | |||
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59 | </storageModule> | |||
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60 | <storageModule moduleId="cdtBuildSystem" version="4.0.0"> | |||
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74 | </cproject> | |||
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1 | <?xml version="1.0" encoding="UTF-8"?> | |||
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2 | <projectDescription> | |||
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3 | <name>acquisitiond</name> | |||
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4 | <comment></comment> | |||
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5 | <projects> | |||
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6 | </projects> | |||
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7 | <buildSpec> | |||
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8 | <buildCommand> | |||
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9 | <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> | |||
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10 | <triggers>clean,full,incremental,</triggers> | |||
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11 | <arguments> | |||
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12 | </arguments> | |||
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13 | </buildCommand> | |||
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14 | <buildCommand> | |||
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15 | <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> | |||
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16 | <triggers>full,incremental,</triggers> | |||
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17 | <arguments> | |||
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18 | </arguments> | |||
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19 | </buildCommand> | |||
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20 | </buildSpec> | |||
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21 | <natures> | |||
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22 | <nature>org.eclipse.cdt.core.cnature</nature> | |||
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23 | <nature>org.eclipse.cdt.core.ccnature</nature> | |||
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24 | <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> | |||
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25 | <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> | |||
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26 | <nature>de.innot.avreclipse.core.avrnature</nature> | |||
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27 | </natures> | |||
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28 | </projectDescription> | |||
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1 | /* | |||
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2 | * acquisitiond.c | |||
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3 | * | |||
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4 | * Created on: Mar 24, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #include "acquisitiond.h" | |||
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9 | #include "fpgaport.h" | |||
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10 | ||||
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11 | volatile uint8_t is_acquiring = 0; | |||
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12 | volatile uint8_t send_flg = 0; | |||
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13 | ||||
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14 | // Comandos para el ADC | |||
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15 | #define CMD_ACTV 0 | |||
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16 | #define CMD_DACTV 1 | |||
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17 | #define CMD_RATE 2 | |||
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18 | #define CMD_RPARAM 3 | |||
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19 | #define CMD_WPARAM 4 | |||
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20 | #define CMD_START 5 | |||
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21 | #define CMD_STOP 6 | |||
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22 | #define CMD_INFO 7 | |||
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23 | #define CMD_GAIN 8 | |||
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24 | #define CMD_ID 9 | |||
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25 | #define CMD_STATUS 10 | |||
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26 | #define CMD_PPS 11 | |||
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27 | ||||
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28 | ||||
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29 | /*! | |||
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30 | * \fn acq_chn_activate | |||
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31 | * \breif activa la comunicacion con el IC ADC | |||
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32 | * \see acq_chn_deactivate | |||
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33 | */ | |||
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34 | void acq_chn_activate(){ | |||
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35 | adcport_open(); | |||
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36 | } | |||
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37 | ||||
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38 | ||||
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39 | /*! | |||
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40 | * \fn acq_chn_deactivate | |||
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41 | * \breif desactiva la comunicacion con el IC ADC | |||
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42 | * \see acq_chn_activate | |||
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43 | */ | |||
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44 | void acq_chn_deactivate(){ | |||
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45 | adcport_close(); | |||
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46 | } | |||
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47 | ||||
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48 | ||||
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49 | /*! | |||
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50 | * \fn acq_chn_datarate | |||
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51 | * \breif Configura el datarate del ADC | |||
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52 | * \param datarate El datarate deseado | |||
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53 | */ | |||
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54 | void acq_chn_datarate(uint16_t datarate){ | |||
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55 | if(is_acquiring==1){ | |||
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56 | acq_stop_acquisiton(); | |||
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57 | } | |||
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58 | acq_set_param_to_adc(CMD_RATE,datarate); | |||
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59 | } | |||
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60 | ||||
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61 | ||||
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62 | /*! | |||
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63 | * \fn acq_send_information | |||
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64 | * \breif Envia informacion relevante al Embebido (a traves de FPGA) | |||
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65 | */ | |||
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66 | void acq_send_information(){ | |||
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67 | if(is_acquiring==1){ | |||
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68 | acq_stop_acquisiton(); | |||
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69 | } | |||
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70 | acq_send_param(CMD_RATE); | |||
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71 | acq_send_param(CMD_GAIN); | |||
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72 | acq_send_param(CMD_ID); | |||
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73 | acq_send_param(CMD_STATUS); | |||
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74 | acq_send_param(CMD_PPS); | |||
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75 | } | |||
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76 | ||||
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77 | ||||
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78 | /*! | |||
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79 | * \fn acq_chn_datarate | |||
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80 | * \breif Envia parametros al embebido a traves del FPGA (este se debe encargar | |||
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81 | * de hacer el puente al embebido) | |||
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82 | * \param param El parametro que se quiere enviar al embebido | |||
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83 | */ | |||
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84 | void acq_send_param(uint8_t param){ | |||
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85 | uint8_t data; | |||
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86 | fpgaport_open(); | |||
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87 | fpgaport_write(param); | |||
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88 | switch(param){ | |||
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89 | case CMD_RATE: | |||
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90 | // TODO secuencia de comandos para obtener el datarate del ADC | |||
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91 | break; | |||
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92 | case CMD_GAIN: | |||
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93 | data=adcport_get_param(GAIN0); | |||
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94 | break; | |||
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95 | case CMD_ID: | |||
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96 | data=adcport_get_param(ID); | |||
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97 | break; | |||
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98 | case CMD_STATUS: | |||
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99 | data=adcport_get_param(STATUS); | |||
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100 | break; | |||
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101 | case CMD_PPS: | |||
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102 | break;// TODO | |||
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103 | default: | |||
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104 | // con esta opcion se puede leer los registros del ADC definidos en | |||
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105 | // "adcpot.h" y enviarlos al embebido | |||
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106 | data= adcport_get_param(param); | |||
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107 | break; | |||
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108 | } | |||
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109 | ||||
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110 | fpgaport_write(data); | |||
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111 | fpgaport_close(); | |||
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112 | } | |||
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113 | ||||
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114 | ||||
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115 | /*! | |||
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116 | * \fn acq_send_buff | |||
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117 | * \breif Envia el contenido de un buffer de datos hacia el | |||
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118 | * FPGA para que sean pre-procesados. | |||
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119 | */ | |||
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120 | /* | |||
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121 | * Esta funcion debe ser ejecutada con la señal de una interrupcion externa | |||
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122 | * manejada por software, que le indicara que hay un buffer lleno listo | |||
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123 | * para pre-procesar (vea adcport.c ). | |||
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124 | */ | |||
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125 | void acq_send_buff(){ | |||
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126 | uint8_t i=0; | |||
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127 | uint32_t* pbuff = adcport_getbuff(); | |||
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128 | fpgaport_open(); | |||
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129 | while(!(i==BUFF_SIZE)){ | |||
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130 | fpgaport_write(pbuff[i]); | |||
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131 | i++; | |||
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132 | } | |||
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133 | fpgaport_close(); | |||
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134 | } | |||
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135 | ||||
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136 | ||||
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137 | /*! | |||
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138 | * \fn acq_chn_set_datarate | |||
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139 | * \breif configura edl datarate del ADC | |||
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140 | * \param datarate | |||
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141 | */ | |||
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142 | void acq_chn_set_datarate(uint8_t datarate){ | |||
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143 | // TODO secuencia de comandos para configurar el data rate | |||
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144 | } | |||
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145 | ||||
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146 | ||||
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147 | /*! | |||
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148 | * \fn acq_process_cmd | |||
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149 | * \breif Procesa todos los comandos enviados desde el FPGA. | |||
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150 | * \param cmd Comando a procesar. | |||
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151 | */ | |||
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152 | /* | |||
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153 | * Esta funcion debe ejecutarse al haber una interrupcion en el puerto que | |||
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154 | * conecta al FPGA | |||
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155 | */ | |||
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156 | void acq_process_cmd(uint8_t cmd){ | |||
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157 | static uint8_t param; | |||
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158 | static uint8_t data; | |||
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159 | cli();// desactiva interrupciones | |||
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160 | fpgaport_open(); | |||
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161 | switch(cmd){ | |||
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162 | case CMD_ACTV: acq_chn_activate(); | |||
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163 | break; | |||
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164 | case CMD_DACTV:acq_chn_deactivate(); | |||
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165 | break; | |||
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166 | case CMD_RATE: | |||
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167 | param=fpgaport_read(); | |||
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168 | acq_chn_set_datarate(param); | |||
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169 | break; | |||
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170 | case CMD_RPARAM: | |||
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171 | param=fpgaport_read(); | |||
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172 | acq_send_param(param); | |||
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173 | break; | |||
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174 | case CMD_WPARAM: | |||
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175 | cmd=fpgaport_read();//lee | |||
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176 | data=fpgaport_read();//lee valor | |||
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177 | acq_set_param_to_adc(cmd,data); | |||
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178 | break; | |||
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179 | case CMD_START: | |||
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180 | acq_start_acquisition(); | |||
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181 | break; | |||
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182 | case CMD_STOP: | |||
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183 | acq_stop_acquisition(); | |||
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184 | break; | |||
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185 | case CMD_INFO: | |||
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186 | acq_send_information(); | |||
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187 | break; | |||
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188 | default: break; | |||
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189 | } | |||
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190 | fpgaport_close(); | |||
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191 | sei();//acvtiva interrupciones | |||
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192 | } | |||
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193 | ||||
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194 | ||||
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195 | /*! | |||
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|
196 | * \fn acq_set_param | |||
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197 | * \breif Procesa todos los comandos enviados desde el FPGA. | |||
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198 | * \param param Parametro a configurar. | |||
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199 | * \param value Valor del parametro | |||
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|
200 | */ | |||
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|
201 | void acq_set_param(uint8_t param, uint8_t value){ | |||
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202 | adcport_tranceiv(param); | |||
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203 | adcport_tranceiv(value); | |||
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204 | } | |||
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|
205 | ||||
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206 | ||||
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207 | /*! | |||
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208 | * \fn acq_start_acquisition | |||
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209 | * \breif Inicia la adquisicion de datos, esta se hara a traves de interrupciones | |||
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210 | * "software" (ver adcport.c) | |||
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211 | */ | |||
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212 | void acq_start_acquisition(){ | |||
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213 | is_acquiring = 1; | |||
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214 | adcport_start(); | |||
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215 | } | |||
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216 | ||||
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217 | /*! | |||
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|
218 | * \fn acq_stop_acquisition | |||
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|
219 | * \breif Para la adquisicion de datos. Las interrupciones utilizadas para | |||
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220 | * este fin son desactivadas. | |||
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221 | */ | |||
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222 | void acq_stop_acquisition(){ | |||
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223 | is_acquiring=0; | |||
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224 | adcport_stop(); | |||
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225 | } | |||
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226 | ||||
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227 | ||||
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228 | /* | |||
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|
229 | * interrupcion en algun pin que no se este usdando. | |||
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230 | * Interrupcion software. No puede ser PORTC_INT0_vect | |||
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231 | * Se usara para le indiquen que ya hay un buffer lleno | |||
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232 | * (ver adcport.c) | |||
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233 | */ | |||
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234 | ISR(PORTx_INTx_vect){ // FIXME | |||
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235 | send_flg=1; | |||
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236 | } | |||
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237 | ||||
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238 | ||||
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239 | ||||
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240 | /* | |||
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|
241 | * interrupcion en algun pin que no se este usdando. | |||
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242 | * Interrupcion software. No puede ser PORTC_INT0_vect | |||
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|
243 | * Se usara para le indiquen que ya hay un buffer lleno | |||
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|
244 | * (ver adcport.c) | |||
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245 | */ | |||
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246 | ISR(PORTx_INTx_vect){ // FIXME | |||
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247 | send_flg=1; | |||
|
|
248 | } | |||
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249 | ||||
|
|
250 | /*! | |||
|
|
251 | * \brief Espera que un buffer este lleno para enviarlo al fpga | |||
|
|
252 | */ | |||
|
|
253 | int main(){ | |||
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|
254 | do{ | |||
|
|
255 | if(send_flg==1){ | |||
|
|
256 | send_flg=0; | |||
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|
257 | acq_send_buff(); | |||
|
|
258 | } | |||
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|
259 | }while(1); | |||
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|
260 | return 0; | |||
|
|
261 | } | |||
| @@ -0,0 +1,35 | |||||
|
|
1 | /* | |||
|
|
2 | * acquisitiond.h | |||
|
|
3 | * | |||
|
|
4 | * Created on: Mar 24, 2015 | |||
|
|
5 | * Author: shinobi | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #ifndef ACQUISITIOND_H_ | |||
|
|
9 | #define ACQUISITIOND_H_ | |||
|
|
10 | ||||
|
|
11 | #include <avr/io.h> | |||
|
|
12 | #include <avr/interrupt.h> | |||
|
|
13 | #include "adcport.h" | |||
|
|
14 | ||||
|
|
15 | void acq_chn_activate(); | |||
|
|
16 | void acq_chn_deactivate(); | |||
|
|
17 | void acq_chn_datarate(uint16_t datarate); | |||
|
|
18 | ||||
|
|
19 | ||||
|
|
20 | void acq_send_information(); | |||
|
|
21 | void acq_send_param(uint8_t param); | |||
|
|
22 | void acq_send_buff(); | |||
|
|
23 | ||||
|
|
24 | ||||
|
|
25 | void acq_process_cmd(uint8_t cmd); | |||
|
|
26 | ||||
|
|
27 | void acq_set_param_to_adc(uint8_t cmd, uint8_t data); | |||
|
|
28 | ||||
|
|
29 | ||||
|
|
30 | void acq_start_acquisition(); | |||
|
|
31 | void acq_stop_acquisition(); | |||
|
|
32 | ||||
|
|
33 | ||||
|
|
34 | ||||
|
|
35 | #endif /* ACQUISITIOND_H_ */ | |||
| @@ -0,0 +1,266 | |||||
|
|
1 | /* | |||
|
|
2 | * adcport.c | |||
|
|
3 | * | |||
|
|
4 | * Created on: Mar 25, 2015 | |||
|
|
5 | * Author: shinobi | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #include "adcport.h" | |||
|
|
9 | #include <avr/io.h> | |||
|
|
10 | #include <avr/interrupt.h> | |||
|
|
11 | ||||
|
|
12 | ||||
|
|
13 | #define SPI_SS_bm PIN4_bm /*!< \brief Bit mask para el pin SS. */ | |||
|
|
14 | #define SPI_MOSI_bm PIN5_bm /*!< \brief Bit mask para el pin MOSI. */ | |||
|
|
15 | #define SPI_MISO_bm PIN6_bm /*!< \brief Bit mask para el pin MISO. */ | |||
|
|
16 | #define SPI_SCK_bm PIN7_bm /*!< \brief Bit mask para el pin SCK. */ | |||
|
|
17 | ||||
|
|
18 | ||||
|
|
19 | #define SS_OFF PORTC.OUTSET=PIN4_bm;/*!< \brief Deselecciona el ADC (puerto SPI) */ | |||
|
|
20 | #define SS_ON PORTC.OUTCLR=PIN4_bm;/*!< \brief Selecciona el ADC (puerto SPI) */ | |||
|
|
21 | ||||
|
|
22 | ||||
|
|
23 | /* | |||
|
|
24 | * Al iniciar la adquisicion se debe activar la interrupcion del pin RDY a | |||
|
|
25 | * traves del PINC6 del XMEGA. | |||
|
|
26 | * Luego al leer los datos digitalizados, se debe desactivar. Al terminar | |||
|
|
27 | * se reactiva para esperar la siguiente interrupcion. | |||
|
|
28 | * Esto se debe a que el DOUT y el RDY del ADC comparten el pin. Si se dejara | |||
|
|
29 | * activa la interrupcion al leer, se generarian interrupciones e los flancos | |||
|
|
30 | * de bajada generados por la transferencia de las muestras | |||
|
|
31 | */ | |||
|
|
32 | #define WAIT_DATA PORTC.INT0MASK=PIN6_bm/*!< \brief Activa interrupcion que indica dato nuevo */ | |||
|
|
33 | #define GET_DATA PORTC.INT0MASK=0/*!< \brief Desactiva iterrupcion que indica dato nuevo */ | |||
|
|
34 | ||||
|
|
35 | ||||
|
|
36 | volatile uint8_t buff_idx; | |||
|
|
37 | uint32_t * pfull_buff; | |||
|
|
38 | uint32_t * pread_buff; | |||
|
|
39 | volatile uint8_t buff_full_flg = 0; | |||
|
|
40 | ||||
|
|
41 | /*! | |||
|
|
42 | * \fn adcport_ready_interrupt_config | |||
|
|
43 | * \brief configura el pin de MISO (conectado a DOUT del ADC), para que dispare | |||
|
|
44 | * una interrupcion por flanco de bajada. | |||
|
|
45 | * una vez disparada la interrupcion, se puede leer el pin; sin embargo, debe | |||
|
|
46 | * desactivarse antes de leer la interrupcion por flanco (con GET_DATA). De lo | |||
|
|
47 | * contrario se disparara la interrupcion varias veces al leer los datos, ya | |||
|
|
48 | * que ese el pin RDY y DOUT es el mismo en el ADC. | |||
|
|
49 | */ | |||
|
|
50 | inline void adcport_ready_interrupt_config(){ | |||
|
|
51 | // pin6: MISO(xmega) --> DOUT/RDY(ADC) => pin6 entrada | |||
|
|
52 | PORTC.DIRCLR=PIN6_bm; | |||
|
|
53 | // El ADC llevara a "low" RDY cuando la conversion de un dato haya concluido | |||
|
|
54 | // Se debe leer el dato generado luego. Se espera una interrupcion de flanco | |||
|
|
55 | // de bajada para manejar esto | |||
|
|
56 | PORTC.PIN6CTRL=PORT_ISC_FALLING_gc; | |||
|
|
57 | // Se mapea la interrupcion externa INT0 de PORTC a PINC6 | |||
|
|
58 | PORTC.INT0MASK=PIN6_bm; | |||
|
|
59 | // Debido a que esta interrupcion va a manejar la adquisicion de datos, se | |||
|
|
60 | // le da maxima prioridad (nivel alto) | |||
|
|
61 | PORTC.INTCTRL=PORT_INT0LVL_HI_gc; | |||
|
|
62 | // Se habilita la atencion de interrupciones de nivel alto | |||
|
|
63 | PMIC.CTRL|= PMIC_HILVLEN_bm; | |||
|
|
64 | } | |||
|
|
65 | ||||
|
|
66 | ||||
|
|
67 | /*! | |||
|
|
68 | * \fn adcport_spi_config | |||
|
|
69 | * \brief configura el puerto SPI para que coincida con el requerimiento del ADC | |||
|
|
70 | * AD7178-2 | |||
|
|
71 | */ | |||
|
|
72 | inline void adcport_spi_config(){ | |||
|
|
73 | PORTC.DIRSET = SPI_MOSI_bm | SPI_SCK_bm | SPI_SS_bm; | |||
|
|
74 | // Preescaler: clkper/2 (con clk2x). Maestro. CPOL=1,CPHA=1 | |||
|
|
75 | // MSB primero | |||
|
|
76 | SPIC.CTRL = SPI_CLK2X_bm|SPI_ENABLE_bm|SPI_MASTER_bm| | |||
|
|
77 | SPI_MODE1_bm|SPI_MODE0_bm; | |||
|
|
78 | } | |||
|
|
79 | ||||
|
|
80 | ||||
|
|
81 | /*! | |||
|
|
82 | * \fn adcport_config | |||
|
|
83 | * \brief Configura el microcontrolador para darle servicio a la interrupcion | |||
|
|
84 | * del pin "RDY" del ADC, que reacciona con un flanco de bajada cuando se ha | |||
|
|
85 | * terminado de digitalar una muestra nueva. | |||
|
|
86 | * Tambien configura el puerto SPI que servira para comunicarse con el ADC. | |||
|
|
87 | * \see adcport_ready_interrupt_config | |||
|
|
88 | * \see adcport_spi_config | |||
|
|
89 | */ | |||
|
|
90 | inline void adcport_config(){ | |||
|
|
91 | adcport_ready_interrupt_config(); | |||
|
|
92 | adcport_spi_config(); | |||
|
|
93 | // TODO configurar ADC: datarate, ganancia, desactivar CRC, formato numerico | |||
|
|
94 | // de muestras debe ser "bipolar offset binary"(canales diferenciales). | |||
|
|
95 | } | |||
|
|
96 | ||||
|
|
97 | ||||
|
|
98 | /*! | |||
|
|
99 | * \fn adcport_open | |||
|
|
100 | * \brief Inicializa el buffer de entrada (para datos de 24bits del ADC) y | |||
|
|
101 | * activa la comunicacion a traves del pin "SS" del puerto SPI. | |||
|
|
102 | * \see adcport_close | |||
|
|
103 | */ | |||
|
|
104 | inline void adcport_open(){ | |||
|
|
105 | buff_idx=0; | |||
|
|
106 | // TODO configurar interrupcion externa PPS (pin 6) | |||
|
|
107 | // TODO configurar interrupcion externa LOCK (pin 21) | |||
|
|
108 | pfull_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); | |||
|
|
109 | pread_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); | |||
|
|
110 | adcport_config(); | |||
|
|
111 | SS_ON; | |||
|
|
112 | } | |||
|
|
113 | ||||
|
|
114 | ||||
|
|
115 | /*! | |||
|
|
116 | * \fn adcport_close | |||
|
|
117 | * \brief Desactiva la comunicacion con el ADC a traves del pin "SS" del puerto | |||
|
|
118 | * SPI. | |||
|
|
119 | * \see adcport_open | |||
|
|
120 | */ | |||
|
|
121 | inline void adcport_close(){ | |||
|
|
122 | SS_OFF; | |||
|
|
123 | free(pfull_buff); | |||
|
|
124 | free(pread_buff); | |||
|
|
125 | } | |||
|
|
126 | ||||
|
|
127 | ||||
|
|
128 | /*! | |||
|
|
129 | * \fn adcport_start | |||
|
|
130 | * \brief Inicia la digitalizacion de muestras del sensor. | |||
|
|
131 | * SPI. | |||
|
|
132 | * \see adcport_stop | |||
|
|
133 | * \see adcport_open | |||
|
|
134 | * \see adcport_close | |||
|
|
135 | */ | |||
|
|
136 | inline void adcport_start(){ | |||
|
|
137 | // necesario para darle servicio con interrupciones al flanco de bajada | |||
|
|
138 | // del pin "RDY" | |||
|
|
139 | WAIT_DATA; | |||
|
|
140 | // TODO enviar comandos al ADC para que inicie la adquisicion. | |||
|
|
141 | } | |||
|
|
142 | ||||
|
|
143 | ||||
|
|
144 | /*! | |||
|
|
145 | * \fn adcport_stop | |||
|
|
146 | * \brief Pausa la digitalizacion de muestras del sensor. | |||
|
|
147 | * SPI. | |||
|
|
148 | * \see adcport_start | |||
|
|
149 | * \see adcport_open | |||
|
|
150 | * \see adcport_close | |||
|
|
151 | */ | |||
|
|
152 | inline void adcport_stop(){ | |||
|
|
153 | // TODO enviar comandos al ADC para que deje de adquirir. | |||
|
|
154 | // necesario para cortar el servicio interrupcion del pin "RDY" | |||
|
|
155 | GET_DATA; | |||
|
|
156 | } | |||
|
|
157 | ||||
|
|
158 | ||||
|
|
159 | /*! | |||
|
|
160 | * \fn adcport_tranceiv | |||
|
|
161 | * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y | |||
|
|
162 | * el microcontrolador. | |||
|
|
163 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
|
|
164 | * transmision genera clock en el pin "sclk" | |||
|
|
165 | * \param El dato a transmitir | |||
|
|
166 | * \return El dato leido del ADC | |||
|
|
167 | */ | |||
|
|
168 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
169 | // | |||
|
|
170 | SPIC.DATA = data; | |||
|
|
171 | ||||
|
|
172 | //Wait until transmission complete | |||
|
|
173 | while(!(SPIC.STATUS)&SPI_IF_bm); | |||
|
|
174 | ||||
|
|
175 | // Return received data | |||
|
|
176 | return SPIC.DATA; | |||
|
|
177 | } | |||
|
|
178 | ||||
|
|
179 | ||||
|
|
180 | /*! | |||
|
|
181 | * \fn adcport_start | |||
|
|
182 | * \brief Inicia la digitalizacion de muestras del sensor. | |||
|
|
183 | * SPI. | |||
|
|
184 | * \see adcport_open | |||
|
|
185 | */ | |||
|
|
186 | void adcport_read_sample(){ | |||
|
|
187 | uint32_t aux; | |||
|
|
188 | GET_DATA; // desactiva interrupciones de flaco de bajada | |||
|
|
189 | // Se le indica al adc que se va a leer el registro de data. | |||
|
|
190 | adcport_tranceiv(0x44); | |||
|
|
191 | // El byte mas significativo de la variable de 32bits es cero | |||
|
|
192 | // La codificacion de los numeros es "bipolar offset binary" y | |||
|
|
193 | // la transmision es MSB first | |||
|
|
194 | aux = adcport_tranceiv(0); | |||
|
|
195 | aux = (aux<<8)|adcport_tranceiv(0); | |||
|
|
196 | aux = (aux<<8)|adcport_tranceiv(0); | |||
|
|
197 | aux = (aux<<8)|adcport_tranceiv(0); | |||
|
|
198 | pread_buff[buff_idx]=aux; | |||
|
|
199 | ||||
|
|
200 | WAIT_DATA; // reactiva interrupciones de flanco de bajada | |||
|
|
201 | } | |||
|
|
202 | ||||
|
|
203 | ||||
|
|
204 | /*! | |||
|
|
205 | * \fn adcport_getbuff | |||
|
|
206 | * \brief Devuelve la direccion del buffer lleno | |||
|
|
207 | * \return Direccion del buffer lleno. 0 si no esta lleno aun | |||
|
|
208 | */ | |||
|
|
209 | inline uint32_t* adcport_getbuff(){ | |||
|
|
210 | if(buff_full_flg==1){ | |||
|
|
211 | buff_full_flg=0; | |||
|
|
212 | return pfull_buff; | |||
|
|
213 | } | |||
|
|
214 | return 0; | |||
|
|
215 | } | |||
|
|
216 | ||||
|
|
217 | ||||
|
|
218 | uint8_t adcport_get_param(uint8_t data){ | |||
|
|
219 | adcport_tranceiv(data); | |||
|
|
220 | return adcport_tranceiv(0); | |||
|
|
221 | } | |||
|
|
222 | ||||
|
|
223 | ||||
|
|
224 | /*! | |||
|
|
225 | * \brief interrupcion externa debe dispararse en flanco de bajada en PC6 (RDY del ADC). | |||
|
|
226 | * Cuando el ADC lleva este pin a "low", se debe leer el dato nuevo | |||
|
|
227 | */ | |||
|
|
228 | ISR(PORTC_INT0_vect){ | |||
|
|
229 | adcport_read_sample(); | |||
|
|
230 | buff_idx++; | |||
|
|
231 | if(buff_idx>=100){ | |||
|
|
232 | uint32_t* paux = pread_buff; | |||
|
|
233 | pread_buff = pfull_buff; | |||
|
|
234 | pfull_buff = paux; | |||
|
|
235 | buff_full_flg=1; | |||
|
|
236 | // TODO dar aviso al programa principal que el buffer esta lleno. | |||
|
|
237 | // Puede ser a traves de una interrupcion "externa" en un pin que no se | |||
|
|
238 | // use, para lo cual debe estar configurado como salida y para recibir | |||
|
|
239 | // interrupciones de IO. | |||
|
|
240 | // para hacer que funcione como una interrupcion software, solo escribir | |||
|
|
241 | // en ese pin un valor segun se configure la interrupcion | |||
|
|
242 | } | |||
|
|
243 | } | |||
|
|
244 | ||||
|
|
245 | ||||
|
|
246 | /* TODO | |||
|
|
247 | * interrupcion del LOCK del GNSS (pin numero 21 del xmega) | |||
|
|
248 | * servira para indicar que el GNSS esta sincronizado con satelites y la hora y | |||
|
|
249 | * PPS son correctos, a partir de ese momento se pueden contar los PPS y | |||
|
|
250 | * identificarlos en el header. | |||
|
|
251 | */ | |||
|
|
252 | ISR(PORTx_INTx_vect){ // FIXME | |||
|
|
253 | ||||
|
|
254 | } | |||
|
|
255 | ||||
|
|
256 | ||||
|
|
257 | /* TODO | |||
|
|
258 | * interrupcion del PPS del GNSS (pin numero 6 del xmega) | |||
|
|
259 | * servira para sincronizar la hora. Debe agregar un numero de serie entre 0 y 255 | |||
|
|
260 | * a la cabecera del buffer que indentifique al PPS; y el numero de muestra que se adquirio | |||
|
|
261 | * en el momento de la llegada de esta interrupcion. | |||
|
|
262 | */ | |||
|
|
263 | ISR(PORTx_INTx_vect){ // FIXME | |||
|
|
264 | ||||
|
|
265 | } | |||
|
|
266 | ||||
| @@ -0,0 +1,60 | |||||
|
|
1 | /* | |||
|
|
2 | * adcport.h | |||
|
|
3 | * | |||
|
|
4 | * Created on: Mar 25, 2015 | |||
|
|
5 | * Author: shinobi | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #ifndef ADCPORT_H_ | |||
|
|
9 | #define ADCPORT_H_ | |||
|
|
10 | ||||
|
|
11 | #include <inttypes.h> | |||
|
|
12 | ||||
|
|
13 | #define BUFF_SIZE 100 | |||
|
|
14 | ||||
|
|
15 | /* Direcciones de registros del ADC */ | |||
|
|
16 | ||||
|
|
17 | #define COMMS 0x00 | |||
|
|
18 | #define STATUS 0x00 | |||
|
|
19 | #define ADCMODE 0x01 | |||
|
|
20 | #define IFMODE 0x02 | |||
|
|
21 | #define REGCHECK 0x03 | |||
|
|
22 | #define DATA 0X04 | |||
|
|
23 | #define GPIOCON 0x06 | |||
|
|
24 | #define ID 0x07 | |||
|
|
25 | ||||
|
|
26 | #define CHMAP0 0x10 | |||
|
|
27 | #define CHMAP1 0x11 | |||
|
|
28 | #define CHMAP2 0x12 | |||
|
|
29 | #define CHMAP3 0x13 | |||
|
|
30 | ||||
|
|
31 | #define SETUPCON0 0x20 | |||
|
|
32 | #define SETUPCON1 0x21 | |||
|
|
33 | #define SETUPCON2 0x22 | |||
|
|
34 | #define SETUPCON3 0x23 | |||
|
|
35 | ||||
|
|
36 | #define FILTCON0 0x28 | |||
|
|
37 | #define FILTCON1 0x29 | |||
|
|
38 | #define FILTCON2 0x2A | |||
|
|
39 | #define FILTCON3 0x2B | |||
|
|
40 | ||||
|
|
41 | #define OFFSET0 0x30 | |||
|
|
42 | #define OFFSET1 0x31 | |||
|
|
43 | #define OFFSET2 0x32 | |||
|
|
44 | #define OFFSET3 0x33 | |||
|
|
45 | ||||
|
|
46 | #define GAIN0 0x38 | |||
|
|
47 | #define GAIN1 0x39 | |||
|
|
48 | #define GAIN2 0x2A | |||
|
|
49 | #define GAIN3 0x2B | |||
|
|
50 | ||||
|
|
51 | ||||
|
|
52 | void adcport_open(); | |||
|
|
53 | void adcport_close(); | |||
|
|
54 | void adcport_start(); | |||
|
|
55 | void adcport_stop(); | |||
|
|
56 | uint32_t* adcport_getbuff(); | |||
|
|
57 | uint8_t adcport_tranceiv(uint8_t data); | |||
|
|
58 | uint8_t adcport_get_param(uint8_t data); | |||
|
|
59 | ||||
|
|
60 | #endif /* ADCPORT_H_ */ | |||
| @@ -0,0 +1,57 | |||||
|
|
1 | /* | |||
|
|
2 | * fpgaport.c | |||
|
|
3 | * | |||
|
|
4 | * Created on: Mar 26, 2015 | |||
|
|
5 | * Author: shinobi | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | /*! | |||
|
|
10 | * \fn fpgaport_open | |||
|
|
11 | * \brief actima la comunicacion con el FPGA | |||
|
|
12 | */ | |||
|
|
13 | inline void fpgaport_open(){ | |||
|
|
14 | // TODO configurar puerto pfga e interrupcion externa (pin 22) | |||
|
|
15 | // TODO configurar interrupcion externa PPS (pin 6) | |||
|
|
16 | // TODO configurar interrupcion externa LOCK (pin 21) | |||
|
|
17 | } | |||
|
|
18 | ||||
|
|
19 | ||||
|
|
20 | /*! | |||
|
|
21 | * \fn fpgaport_close | |||
|
|
22 | * \brief Desactiva la comunicacion con el FPGA | |||
|
|
23 | */ | |||
|
|
24 | inline void fpgaport_close(){ | |||
|
|
25 | // TODO configurar puerto pfga e interrupcion externa (pin 22) para | |||
|
|
26 | // clock | |||
|
|
27 | } | |||
|
|
28 | ||||
|
|
29 | ||||
|
|
30 | /*! | |||
|
|
31 | * \fn fpgaport_write | |||
|
|
32 | * \breif activa la comunicacion con el IC ADC | |||
|
|
33 | * \see acq_chn_deactivate | |||
|
|
34 | */ | |||
|
|
35 | inline void fpgaport_write(uint8_t data){ | |||
|
|
36 | // TODO | |||
|
|
37 | } | |||
|
|
38 | ||||
|
|
39 | ||||
|
|
40 | /*! | |||
|
|
41 | * \fn fpgaport_read | |||
|
|
42 | * \breif activa la comunicacion con el IC ADC | |||
|
|
43 | * \see acq_chn_deactivate | |||
|
|
44 | */ | |||
|
|
45 | inline uint8_t fpgaport_read(){ | |||
|
|
46 | // TODO | |||
|
|
47 | } | |||
|
|
48 | ||||
|
|
49 | ||||
|
|
50 | /* | |||
|
|
51 | * Interrupcion de dato entrante por el puerto FPGA. El pin debe ser alguno de los | |||
|
|
52 | * que estan conectatos al FPGA (el bus) | |||
|
|
53 | */ | |||
|
|
54 | ISR(PORTx_INTx_vect){ | |||
|
|
55 | // TODO debe idicar que se ejecute la funcion que procesa los comandos | |||
|
|
56 | // que bienen del FPGA | |||
|
|
57 | } | |||
| @@ -0,0 +1,19 | |||||
|
|
1 | /* | |||
|
|
2 | * fpgaport.h | |||
|
|
3 | * | |||
|
|
4 | * Created on: Mar 26, 2015 | |||
|
|
5 | * Author: shinobi | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #ifndef FPGAPORT_H_ | |||
|
|
9 | #define FPGAPORT_H_ | |||
|
|
10 | ||||
|
|
11 | #include <inttypes.h> | |||
|
|
12 | ||||
|
|
13 | void fpgaport_open(); | |||
|
|
14 | void fpgaport_close(); | |||
|
|
15 | void fpgaport_write(uint8_t data); | |||
|
|
16 | uint8_t fpgaport_read(); | |||
|
|
17 | ||||
|
|
18 | ||||
|
|
19 | #endif /* FPGAPORT_H_ */ | |||
| 1 | NO CONTENT: new file 10644 |
|
NO CONTENT: new file 10644 |
| @@ -0,0 +1,22 | |||||
|
|
1 | | |||
|
|
2 | Microsoft Visual Studio Solution File, Format Version 12.00 | |||
|
|
3 | # Atmel Studio Solution File, Format Version 11.00 | |||
|
|
4 | VisualStudioVersion = 14.0.23107.0 | |||
|
|
5 | MinimumVisualStudioVersion = 10.0.40219.1 | |||
|
|
6 | Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_ver01", "ADCSPI_ver01\ADCSPI_ver01.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" | |||
|
|
7 | EndProject | |||
|
|
8 | Global | |||
|
|
9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution | |||
|
|
10 | Debug|AVR = Debug|AVR | |||
|
|
11 | Release|AVR = Release|AVR | |||
|
|
12 | EndGlobalSection | |||
|
|
13 | GlobalSection(ProjectConfigurationPlatforms) = postSolution | |||
|
|
14 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.ActiveCfg = Debug|AVR | |||
|
|
15 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.Build.0 = Debug|AVR | |||
|
|
16 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.ActiveCfg = Release|AVR | |||
|
|
17 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.Build.0 = Release|AVR | |||
|
|
18 | EndGlobalSection | |||
|
|
19 | GlobalSection(SolutionProperties) = preSolution | |||
|
|
20 | HideSolutionNode = FALSE | |||
|
|
21 | EndGlobalSection | |||
|
|
22 | EndGlobal | |||
| @@ -0,0 +1,86 | |||||
|
|
1 | <?xml version="1.0" encoding="utf-8"?> | |||
|
|
2 | <Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement"> | |||
|
|
3 | <ProjectComponents> | |||
|
|
4 | <ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/"> | |||
|
|
5 | <CApiVersion></CApiVersion> | |||
|
|
6 | <CBundle></CBundle> | |||
|
|
7 | <CClass>Device</CClass> | |||
|
|
8 | <CGroup>Startup</CGroup> | |||
|
|
9 | <CSub></CSub> | |||
|
|
10 | <CVariant></CVariant> | |||
|
|
11 | <CVendor>Atmel</CVendor> | |||
|
|
12 | <CVersion>1.0.0</CVersion> | |||
|
|
13 | <DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath> | |||
|
|
14 | <DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" /> | |||
|
|
15 | <Description></Description> | |||
|
|
16 | <Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays"> | |||
|
|
17 | <d4p1:anyType i:type="FileInfo"> | |||
|
|
18 | <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include</AbsolutePath> | |||
|
|
19 | <Attribute></Attribute> | |||
|
|
20 | <Category>include</Category> | |||
|
|
21 | <Condition>C</Condition> | |||
|
|
22 | <FileContentHash i:nil="true" /> | |||
|
|
23 | <FileVersion></FileVersion> | |||
|
|
24 | <Name>include</Name> | |||
|
|
25 | <SelectString></SelectString> | |||
|
|
26 | <SourcePath></SourcePath> | |||
|
|
27 | </d4p1:anyType> | |||
|
|
28 | <d4p1:anyType i:type="FileInfo"> | |||
|
|
29 | <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include\avr\iox32d4.h</AbsolutePath> | |||
|
|
30 | <Attribute></Attribute> | |||
|
|
31 | <Category>header</Category> | |||
|
|
32 | <Condition>C</Condition> | |||
|
|
33 | <FileContentHash>Fb3v/Gsyx/fNhVPcSy4byA==</FileContentHash> | |||
|
|
34 | <FileVersion></FileVersion> | |||
|
|
35 | <Name>include/avr/iox32d4.h</Name> | |||
|
|
36 | <SelectString></SelectString> | |||
|
|
37 | <SourcePath></SourcePath> | |||
|
|
38 | </d4p1:anyType> | |||
|
|
39 | <d4p1:anyType i:type="FileInfo"> | |||
|
|
40 | <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.c</AbsolutePath> | |||
|
|
41 | <Attribute>template</Attribute> | |||
|
|
42 | <Category>source</Category> | |||
|
|
43 | <Condition>C Exe</Condition> | |||
|
|
44 | <FileContentHash>8XJjXFQBySw6iim2xAnW5g==</FileContentHash> | |||
|
|
45 | <FileVersion></FileVersion> | |||
|
|
46 | <Name>templates/main.c</Name> | |||
|
|
47 | <SelectString>Main file (.c)</SelectString> | |||
|
|
48 | <SourcePath></SourcePath> | |||
|
|
49 | </d4p1:anyType> | |||
|
|
50 | <d4p1:anyType i:type="FileInfo"> | |||
|
|
51 | <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.cpp</AbsolutePath> | |||
|
|
52 | <Attribute>template</Attribute> | |||
|
|
53 | <Category>source</Category> | |||
|
|
54 | <Condition>C Exe</Condition> | |||
|
|
55 | <FileContentHash>YXFphlh0CtZJU+ebktABgQ==</FileContentHash> | |||
|
|
56 | <FileVersion></FileVersion> | |||
|
|
57 | <Name>templates/main.cpp</Name> | |||
|
|
58 | <SelectString>Main file (.cpp)</SelectString> | |||
|
|
59 | <SourcePath></SourcePath> | |||
|
|
60 | </d4p1:anyType> | |||
|
|
61 | <d4p1:anyType i:type="FileInfo"> | |||
|
|
62 | <AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4</AbsolutePath> | |||
|
|
63 | <Attribute></Attribute> | |||
|
|
64 | <Category>libraryPrefix</Category> | |||
|
|
65 | <Condition>GCC</Condition> | |||
|
|
66 | <FileContentHash i:nil="true" /> | |||
|
|
67 | <FileVersion></FileVersion> | |||
|
|
68 | <Name>gcc/dev/atxmega32d4</Name> | |||
|
|
69 | <SelectString></SelectString> | |||
|
|
70 | <SourcePath></SourcePath> | |||
|
|
71 | </d4p1:anyType> | |||
|
|
72 | </Files> | |||
|
|
73 | <PackName>XMEGAD_DFP</PackName> | |||
|
|
74 | <PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/Atmel.XMEGAD_DFP.pdsc</PackPath> | |||
|
|
75 | <PackVersion>1.0.29</PackVersion> | |||
|
|
76 | <PresentInProject>true</PresentInProject> | |||
|
|
77 | <ReferenceConditionId>ATxmega32D4</ReferenceConditionId> | |||
|
|
78 | <RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays"> | |||
|
|
79 | <d4p1:string></d4p1:string> | |||
|
|
80 | </RteComponents> | |||
|
|
81 | <Status>Resolved</Status> | |||
|
|
82 | <VersionMode>Fixed</VersionMode> | |||
|
|
83 | <IsComponentInAtProject>true</IsComponentInAtProject> | |||
|
|
84 | </ProjectComponent> | |||
|
|
85 | </ProjectComponents> | |||
|
|
86 | </Store> No newline at end of file | |||
| @@ -0,0 +1,161 | |||||
|
|
1 | <?xml version="1.0" encoding="utf-8"?> | |||
|
|
2 | <Project DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003" ToolsVersion="14.0"> | |||
|
|
3 | <PropertyGroup> | |||
|
|
4 | <SchemaVersion>2.0</SchemaVersion> | |||
|
|
5 | <ProjectVersion>7.0</ProjectVersion> | |||
|
|
6 | <ToolchainName>com.Atmel.AVRGCC8.C</ToolchainName> | |||
|
|
7 | <ProjectGuid>dce6c7e3-ee26-4d79-826b-08594b9ad897</ProjectGuid> | |||
|
|
8 | <avrdevice>ATxmega32D4</avrdevice> | |||
|
|
9 | <avrdeviceseries>none</avrdeviceseries> | |||
|
|
10 | <OutputType>Executable</OutputType> | |||
|
|
11 | <Language>C</Language> | |||
|
|
12 | <OutputFileName>$(MSBuildProjectName)</OutputFileName> | |||
|
|
13 | <OutputFileExtension>.elf</OutputFileExtension> | |||
|
|
14 | <OutputDirectory>$(MSBuildProjectDirectory)\$(Configuration)</OutputDirectory> | |||
|
|
15 | <AssemblyName>ADCSPI_ver01</AssemblyName> | |||
|
|
16 | <Name>ADCSPI_ver01</Name> | |||
|
|
17 | <RootNamespace>ADCSPI_ver01</RootNamespace> | |||
|
|
18 | <ToolchainFlavour>Native</ToolchainFlavour> | |||
|
|
19 | <KeepTimersRunning>true</KeepTimersRunning> | |||
|
|
20 | <OverrideVtor>false</OverrideVtor> | |||
|
|
21 | <CacheFlash>true</CacheFlash> | |||
|
|
22 | <ProgFlashFromRam>true</ProgFlashFromRam> | |||
|
|
23 | <RamSnippetAddress>0x20000000</RamSnippetAddress> | |||
|
|
24 | <UncachedRange /> | |||
|
|
25 | <preserveEEPROM>true</preserveEEPROM> | |||
|
|
26 | <OverrideVtorValue>exception_table</OverrideVtorValue> | |||
|
|
27 | <BootSegment>2</BootSegment> | |||
|
|
28 | <eraseonlaunchrule>0</eraseonlaunchrule> | |||
|
|
29 | <ExternalProgrammingToolCommand /> | |||
|
|
30 | <AsfFrameworkConfig> | |||
|
|
31 | <framework-data xmlns=""> | |||
|
|
32 | <options /> | |||
|
|
33 | <configurations /> | |||
|
|
34 | <files /> | |||
|
|
35 | <documentation help="" /> | |||
|
|
36 | <offline-documentation help="" /> | |||
|
|
37 | <dependencies> | |||
|
|
38 | <content-extension eid="atmel.asf" uuidref="Atmel.ASF" version="3.27.3" /> | |||
|
|
39 | </dependencies> | |||
|
|
40 | </framework-data> | |||
|
|
41 | </AsfFrameworkConfig> | |||
|
|
42 | <avrtool>com.atmel.avrdbg.tool.simulator</avrtool> | |||
|
|
43 | <avrtoolserialnumber /> | |||
|
|
44 | <avrdeviceexpectedsignature>0x1E9542</avrdeviceexpectedsignature> | |||
|
|
45 | <com_atmel_avrdbg_tool_simulator> | |||
|
|
46 | <ToolOptions xmlns=""> | |||
|
|
47 | <InterfaceProperties> | |||
|
|
48 | </InterfaceProperties> | |||
|
|
49 | </ToolOptions> | |||
|
|
50 | <ToolType xmlns="">com.atmel.avrdbg.tool.simulator</ToolType> | |||
|
|
51 | <ToolNumber xmlns=""> | |||
|
|
52 | </ToolNumber> | |||
|
|
53 | <ToolName xmlns="">Simulator</ToolName> | |||
|
|
54 | </com_atmel_avrdbg_tool_simulator> | |||
|
|
55 | <ExternalProgrammingToolCommandDisabledValue /> | |||
|
|
56 | </PropertyGroup> | |||
|
|
57 | <PropertyGroup Condition=" '$(Configuration)' == 'Release' "> | |||
|
|
58 | <ToolchainSettings> | |||
|
|
59 | <AvrGcc> | |||
|
|
60 | <avrgcc.common.Device>-mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4"</avrgcc.common.Device> | |||
|
|
61 | <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex> | |||
|
|
62 | <avrgcc.common.outputfiles.lss>True</avrgcc.common.outputfiles.lss> | |||
|
|
63 | <avrgcc.common.outputfiles.eep>True</avrgcc.common.outputfiles.eep> | |||
|
|
64 | <avrgcc.common.outputfiles.srec>True</avrgcc.common.outputfiles.srec> | |||
|
|
65 | <avrgcc.common.outputfiles.usersignatures>False</avrgcc.common.outputfiles.usersignatures> | |||
|
|
66 | <avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned>True</avrgcc.compiler.general.ChangeDefaultCharTypeUnsigned> | |||
|
|
67 | <avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned>True</avrgcc.compiler.general.ChangeDefaultBitFieldUnsigned> | |||
|
|
68 | <avrgcc.compiler.symbols.DefSymbols> | |||
|
|
69 | <ListValues> | |||
|
|
70 | <Value>NDEBUG</Value> | |||
|
|
71 | </ListValues> | |||
|
|
72 | </avrgcc.compiler.symbols.DefSymbols> | |||
|
|
73 | <avrgcc.compiler.directories.IncludePaths> | |||
|
|
74 | <ListValues> | |||
|
|
75 | <Value>%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\include</Value> | |||
|
|
76 | </ListValues> | |||
|
|
77 | </avrgcc.compiler.directories.IncludePaths> | |||
|
|
78 | <avrgcc.compiler.optimization.level>Optimize for size (-Os)</avrgcc.compiler.optimization.level> | |||
|
|
79 | <avrgcc.compiler.optimization.PackStructureMembers>True</avrgcc.compiler.optimization.PackStructureMembers> | |||
|
|
80 | <avrgcc.compiler.optimization.AllocateBytesNeededForEnum>True</avrgcc.compiler.optimization.AllocateBytesNeededForEnum> | |||
|
|
81 | <avrgcc.compiler.warnings.AllWarnings>True</avrgcc.compiler.warnings.AllWarnings> | |||
|
|
82 | <avrgcc.linker.libraries.Libraries> | |||
|
|
83 | <ListValues> | |||
|
|
84 | <Value>libm</Value> | |||
|
|
85 | </ListValues> | |||
|
|
86 | </avrgcc.linker.libraries.Libraries> | |||
|
|
87 | </AvrGcc> | |||
|
|
88 | </ToolchainSettings> | |||
|
|
89 | </PropertyGroup> | |||
|
|
90 | <PropertyGroup Condition=" '$(Configuration)' == 'Debug' "> | |||
|
|
91 | <ToolchainSettings> | |||
|
|
92 | <AvrGcc> | |||
|
|
93 | <avrgcc.common.Device>-mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4"</avrgcc.common.Device> | |||
|
|
94 | <avrgcc.common.outputfiles.hex>True</avrgcc.common.outputfiles.hex> | |||
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123 | </ToolchainSettings> | |||
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124 | </PropertyGroup> | |||
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126 | <Compile Include="ADC_7176_2.c"> | |||
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127 | <SubType>compile</SubType> | |||
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128 | </Compile> | |||
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129 | <Compile Include="ADC_7176_2.h"> | |||
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130 | <SubType>compile</SubType> | |||
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131 | </Compile> | |||
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132 | <Compile Include="commSPI_ADC.c"> | |||
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133 | <SubType>compile</SubType> | |||
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134 | </Compile> | |||
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135 | <Compile Include="commSPI_ADC.h"> | |||
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136 | <SubType>compile</SubType> | |||
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137 | </Compile> | |||
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138 | <Compile Include="fpga_port.c"> | |||
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139 | <SubType>compile</SubType> | |||
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140 | </Compile> | |||
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141 | <Compile Include="fpga_port.h"> | |||
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142 | <SubType>compile</SubType> | |||
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143 | </Compile> | |||
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144 | <Compile Include="main.c"> | |||
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145 | <SubType>compile</SubType> | |||
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146 | </Compile> | |||
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147 | <Compile Include="Ports.c"> | |||
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148 | <SubType>compile</SubType> | |||
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149 | </Compile> | |||
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150 | <Compile Include="Ports.h"> | |||
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151 | <SubType>compile</SubType> | |||
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155 | </Compile> | |||
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156 | <Compile Include="sys_clock.h"> | |||
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157 | <SubType>compile</SubType> | |||
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158 | </Compile> | |||
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159 | </ItemGroup> | |||
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160 | <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" /> | |||
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161 | </Project> No newline at end of file | |||
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1 | /* | |||
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2 | * ADC_7176_2.c | |||
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3 | * | |||
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4 | * Created: 23/11/15 14:01:02 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | /*! | |||
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9 | * \fn test_adc | |||
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10 | * \brief Lectura de ID del adc | |||
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11 | * | |||
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12 | * Lectura esperada: 0x0C94 | |||
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13 | * | |||
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14 | * Esta funci�n tiene como fin probar la comunicaci�n on el ADC | |||
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15 | * | |||
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16 | #define ADC_WENbar_bm (1<<7) | |||
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17 | #define ADC_RWbar_bm (1<<6) | |||
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18 | #define ADC_ADDR_READ_ID 0x07 | |||
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19 | * \ | |||
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20 | */ | |||
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21 | ||||
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22 | #define F_CPU 32000000UL | |||
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23 | #include <avr/io.h> | |||
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24 | #include "ADC_7176_2.h" | |||
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25 | ||||
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26 | inline uint16_t test_adc(void){ | |||
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27 | uint16_t aux; | |||
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28 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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29 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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30 | aux = adcport_tranceiv(0); | |||
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31 | aux = (aux << 8) | adcport_tranceiv(0); | |||
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32 | PORTSPI.OUTSET = SPI_SS_bm; | |||
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33 | return aux; | |||
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34 | } | |||
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35 | ||||
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36 | inline void test_adc_2(uint8_t* dato){ | |||
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37 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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38 | adcport_read_data(dato,ADC_DATASZ); | |||
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39 | PORTSPI.OUTSET = SPI_SS_bm; | |||
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40 | } | |||
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41 | /*! | |||
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42 | * \fn adcport_tranceiv | |||
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43 | * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y | |||
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44 | * el microcontrolador. | |||
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45 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
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46 | * transmision genera clock en el pin "sclk" | |||
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47 | * \param El dato a transmitir | |||
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48 | * \return El dato leido del ADC | |||
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49 | */ | |||
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50 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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51 | // | |||
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52 | SPIC.DATA = data; | |||
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53 | ||||
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54 | //Wait until transmission complete | |||
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55 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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56 | ||||
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57 | // Return received data | |||
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58 | ||||
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59 | return SPIC.DATA; | |||
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60 | } | |||
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61 | ||||
|
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62 | /*! | |||
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63 | * \fn adcport_readdata | |||
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64 | * \brief Realiza la lectura de datos en modo de conversi�n continua | |||
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65 | * el microcontrolador. | |||
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66 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
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67 | * transmision genera clock en el pin "sclk" | |||
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68 | * \param La direcci�n del puntero a dato | |||
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69 | * \return Ninguno s�lo se llena el puntero al dato | |||
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70 | */ | |||
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71 | inline void adcport_read_data(uint8_t* dato,int j) | |||
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72 | { | |||
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73 | ||||
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74 | //Env�o del comando de lectura de datos 0x44 | |||
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75 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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76 | ||||
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77 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
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78 | ||||
|
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79 | // Save received data | |||
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80 | for(int i=0; i<j ; i++) | |||
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81 | dato[j-i-1] = adcport_tranceiv(0); | |||
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82 | } | |||
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83 | ||||
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84 | void config_adc(void) | |||
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85 | { | |||
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86 | adcport_write_filtcon0(); | |||
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87 | //adcport_write_interfmode(); | |||
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88 | ||||
|
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89 | } | |||
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90 | ||||
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91 | void adcport_write_filtcon0(void) | |||
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92 | { | |||
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93 | adcport_tranceiv((ADC_FILTCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm)); | |||
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94 | adcport_tranceiv(0); | |||
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95 | adcport_tranceiv((0b00<<ADC_FILT0_ORDER0_bp)|(0b01010<<ADC_FILT0_ODR0_bp)); | |||
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|
96 | } | |||
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97 | ||||
|
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98 | void adcport_write_interfmode(void) | |||
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99 | { | |||
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100 | adcport_tranceiv((ADC_INTERFMODE) & (~ADC_WENbar_bm | ~ADC_RWbar_bm)); | |||
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101 | adcport_tranceiv(0); | |||
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|
102 | adcport_tranceiv((1<<ADC_CONTREAD_bp)|(1<<ADC_WL16_bp)); | |||
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|
103 | } No newline at end of file | |||
| @@ -0,0 +1,45 | |||||
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|
1 | /* | |||
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|
2 | * ADC_7176_2.h | |||
|
|
3 | * | |||
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|
4 | * Created: 23/11/15 13:59:46 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
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|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef ADC_7176_2_H_ | |||
|
|
10 | #define ADC_7176_2_H_ | |||
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11 | ||||
|
|
12 | #define F_CPU 32000000UL | |||
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|
13 | #include <avr/io.h> | |||
|
|
14 | #include "Ports.h" | |||
|
|
15 | #include "commSPI_ADC.h" | |||
|
|
16 | ||||
|
|
17 | //ID esperada | |||
|
|
18 | //tama�o 16 bits | |||
|
|
19 | //Valor 0x0C94 | |||
|
|
20 | #define ADC_ID 0x0C94 | |||
|
|
21 | #define ADC_RD 0x04 | |||
|
|
22 | #define ADC_FILTCON0 0x28 | |||
|
|
23 | #define ADC_INTERFMODE 0x02 | |||
|
|
24 | #define ADC_DATASZ 3 | |||
|
|
25 | ||||
|
|
26 | //Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n | |||
|
|
27 | #define ADC_WENbar_bm (1<<7) | |||
|
|
28 | #define ADC_RWbar_bm (1<<6) | |||
|
|
29 | #define ADC_ADDR_READ_ID (0x07) | |||
|
|
30 | #define ADC_FILT0_ORDER0_bp 5 | |||
|
|
31 | #define ADC_FILT0_ODR0_bp 0 | |||
|
|
32 | #define ADC_CONTREAD_bp 7 | |||
|
|
33 | #define ADC_WL16_bp 0 | |||
|
|
34 | ||||
|
|
35 | uint8_t adcport_tranceiv(uint8_t data); | |||
|
|
36 | void adcport_read_data(uint8_t* dato,int j); | |||
|
|
37 | ||||
|
|
38 | void adcport_write_filtcon0(void); | |||
|
|
39 | void adcport_write_interfmode(void); | |||
|
|
40 | ||||
|
|
41 | uint16_t test_adc(void); | |||
|
|
42 | void test_adc_2(uint8_t* dato); | |||
|
|
43 | void config_adc(void); | |||
|
|
44 | ||||
|
|
45 | #endif /* ADC_7176_2_H_ */ No newline at end of file | |||
| @@ -0,0 +1,1 | |||||
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1 | ||||
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2 | ADCSPI_ver01.elf: file format elf32-avr | |||
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3 | ||||
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4 | Sections: | |||
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5 | Idx Name Size VMA LMA File off Algn | |||
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6 | 0 .text 0000055e 00000000 00000000 00000054 2**1 | |||
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7 | CONTENTS, ALLOC, LOAD, READONLY, CODE | |||
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8 | 1 .data 00000000 00802000 00802000 000005b2 2**0 | |||
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9 | CONTENTS, ALLOC, LOAD, DATA | |||
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10 | 2 .comment 00000030 00000000 00000000 000005b2 2**0 | |||
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11 | CONTENTS, READONLY | |||
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12 | 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 000005e4 2**2 | |||
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13 | CONTENTS, READONLY | |||
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14 | 4 .debug_aranges 00000138 00000000 00000000 00000624 2**0 | |||
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15 | CONTENTS, READONLY, DEBUGGING | |||
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16 | 5 .debug_info 000014b5 00000000 00000000 0000075c 2**0 | |||
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17 | CONTENTS, READONLY, DEBUGGING | |||
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18 | 6 .debug_abbrev 00000644 00000000 00000000 00001c11 2**0 | |||
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19 | CONTENTS, READONLY, DEBUGGING | |||
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20 | 7 .debug_line 00000827 00000000 00000000 00002255 2**0 | |||
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21 | CONTENTS, READONLY, DEBUGGING | |||
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22 | 8 .debug_frame 00000278 00000000 00000000 00002a7c 2**2 | |||
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23 | CONTENTS, READONLY, DEBUGGING | |||
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24 | 9 .debug_str 000007d6 00000000 00000000 00002cf4 2**0 | |||
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25 | CONTENTS, READONLY, DEBUGGING | |||
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26 | 10 .debug_loc 000003d0 00000000 00000000 000034ca 2**0 | |||
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27 | CONTENTS, READONLY, DEBUGGING | |||
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28 | 11 .debug_ranges 000000d8 00000000 00000000 0000389a 2**0 | |||
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29 | CONTENTS, READONLY, DEBUGGING | |||
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30 | ||||
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31 | Disassembly of section .text: | |||
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32 | ||||
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33 | 00000000 <__vectors>: | |||
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34 | 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end> | |||
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35 | 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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36 | 8: 0c 94 f1 01 jmp 0x3e2 ; 0x3e2 <__vector_2> | |||
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37 | c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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38 | 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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39 | 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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40 | 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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41 | 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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42 | 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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43 | 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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44 | 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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45 | 2c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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46 | 30: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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47 | 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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48 | 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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49 | 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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50 | 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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51 | 44: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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52 | 48: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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53 | 4c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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54 | 50: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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55 | 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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56 | 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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57 | 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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58 | 60: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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59 | 64: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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60 | 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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61 | 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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62 | 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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63 | 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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64 | 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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65 | 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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66 | 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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67 | 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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68 | 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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69 | 8c: 0c 94 d2 01 jmp 0x3a4 ; 0x3a4 <__vector_35> | |||
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70 | 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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71 | 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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72 | 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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73 | 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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74 | a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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75 | a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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76 | a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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77 | ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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78 | b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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79 | b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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80 | b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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81 | bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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82 | c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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83 | c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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84 | c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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85 | cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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86 | d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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87 | d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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88 | d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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89 | dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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90 | e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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91 | e4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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92 | e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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93 | ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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94 | f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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95 | f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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96 | f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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97 | fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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98 | 100: 0c 94 ad 01 jmp 0x35a ; 0x35a <__vector_64> | |||
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99 | 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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100 | 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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101 | 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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102 | 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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103 | 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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104 | 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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105 | 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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106 | 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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107 | 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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108 | 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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109 | 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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110 | 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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111 | 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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112 | 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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113 | 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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114 | 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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115 | 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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116 | 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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117 | 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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118 | 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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119 | 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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120 | 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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121 | 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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122 | 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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123 | 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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124 | 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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125 | ||||
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126 | 0000016c <__ctors_end>: | |||
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127 | 16c: 11 24 eor r1, r1 | |||
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128 | 16e: 1f be out 0x3f, r1 ; 63 | |||
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129 | 170: cf ef ldi r28, 0xFF ; 255 | |||
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130 | 172: cd bf out 0x3d, r28 ; 61 | |||
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131 | 174: df e2 ldi r29, 0x2F ; 47 | |||
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132 | 176: de bf out 0x3e, r29 ; 62 | |||
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133 | 178: 0e 94 95 01 call 0x32a ; 0x32a <main> | |||
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134 | 17c: 0c 94 ad 02 jmp 0x55a ; 0x55a <_exit> | |||
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135 | ||||
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136 | 00000180 <__bad_interrupt>: | |||
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137 | 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> | |||
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138 | ||||
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139 | 00000184 <test_adc>: | |||
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140 | #include <avr/io.h> | |||
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141 | #include "ADC_7176_2.h" | |||
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142 | ||||
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143 | inline uint16_t test_adc(void){ | |||
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144 | uint16_t aux; | |||
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145 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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146 | 184: 80 e1 ldi r24, 0x10 ; 16 | |||
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147 | 186: 80 93 46 06 sts 0x0646, r24 | |||
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148 | * \param El dato a transmitir | |||
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149 | * \return El dato leido del ADC | |||
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150 | */ | |||
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151 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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152 | // | |||
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153 | SPIC.DATA = data; | |||
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154 | 18a: 87 e4 ldi r24, 0x47 ; 71 | |||
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155 | 18c: 80 93 c3 08 sts 0x08C3, r24 | |||
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156 | ||||
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157 | //Wait until transmission complete | |||
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158 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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159 | 190: e0 ec ldi r30, 0xC0 ; 192 | |||
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160 | 192: f8 e0 ldi r31, 0x08 ; 8 | |||
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161 | 194: 82 81 ldd r24, Z+2 ; 0x02 | |||
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162 | 196: 88 23 and r24, r24 | |||
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163 | 198: ec f7 brge .-6 ; 0x194 <test_adc+0x10> | |||
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164 | ||||
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165 | // Return received data | |||
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166 | ||||
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167 | return SPIC.DATA; | |||
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168 | 19a: e0 ec ldi r30, 0xC0 ; 192 | |||
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169 | 19c: f8 e0 ldi r31, 0x08 ; 8 | |||
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170 | 19e: 83 81 ldd r24, Z+3 ; 0x03 | |||
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171 | * \param El dato a transmitir | |||
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172 | * \return El dato leido del ADC | |||
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173 | */ | |||
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174 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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175 | // | |||
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176 | SPIC.DATA = data; | |||
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177 | 1a0: 13 82 std Z+3, r1 ; 0x03 | |||
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178 | ||||
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179 | //Wait until transmission complete | |||
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180 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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181 | 1a2: 82 81 ldd r24, Z+2 ; 0x02 | |||
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182 | 1a4: 88 23 and r24, r24 | |||
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183 | 1a6: ec f7 brge .-6 ; 0x1a2 <test_adc+0x1e> | |||
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184 | ||||
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185 | // Return received data | |||
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186 | ||||
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187 | return SPIC.DATA; | |||
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188 | 1a8: e0 ec ldi r30, 0xC0 ; 192 | |||
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189 | 1aa: f8 e0 ldi r31, 0x08 ; 8 | |||
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190 | 1ac: 23 81 ldd r18, Z+3 ; 0x03 | |||
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191 | ||||
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192 | inline uint16_t test_adc(void){ | |||
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193 | uint16_t aux; | |||
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194 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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195 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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196 | aux = adcport_tranceiv(0); | |||
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197 | 1ae: 30 e0 ldi r19, 0x00 ; 0 | |||
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198 | aux = (aux << 8) | adcport_tranceiv(0); | |||
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199 | 1b0: 32 2f mov r19, r18 | |||
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200 | 1b2: 22 27 eor r18, r18 | |||
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201 | * \param El dato a transmitir | |||
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202 | * \return El dato leido del ADC | |||
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203 | */ | |||
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204 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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205 | // | |||
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206 | SPIC.DATA = data; | |||
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207 | 1b4: 13 82 std Z+3, r1 ; 0x03 | |||
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208 | ||||
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209 | //Wait until transmission complete | |||
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210 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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211 | 1b6: 92 81 ldd r25, Z+2 ; 0x02 | |||
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212 | 1b8: 99 23 and r25, r25 | |||
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213 | 1ba: ec f7 brge .-6 ; 0x1b6 <test_adc+0x32> | |||
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214 | ||||
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215 | // Return received data | |||
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216 | ||||
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217 | return SPIC.DATA; | |||
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218 | 1bc: 80 91 c3 08 lds r24, 0x08C3 | |||
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219 | uint16_t aux; | |||
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220 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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221 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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222 | aux = adcport_tranceiv(0); | |||
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223 | aux = (aux << 8) | adcport_tranceiv(0); | |||
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224 | PORTSPI.OUTSET = SPI_SS_bm; | |||
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225 | 1c0: 90 e1 ldi r25, 0x10 ; 16 | |||
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226 | 1c2: 90 93 45 06 sts 0x0645, r25 | |||
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227 | return aux; | |||
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228 | } | |||
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229 | 1c6: a9 01 movw r20, r18 | |||
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230 | 1c8: 48 2b or r20, r24 | |||
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231 | 1ca: ca 01 movw r24, r20 | |||
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232 | 1cc: 08 95 ret | |||
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233 | ||||
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234 | 000001ce <adcport_read_data>: | |||
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235 | * transmision genera clock en el pin "sclk" | |||
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236 | * \param La direcci�n del puntero a dato | |||
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237 | * \return Ninguno s�lo se llena el puntero al dato | |||
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238 | */ | |||
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239 | inline void adcport_read_data(uint8_t* dato,int j) | |||
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240 | { | |||
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241 | 1ce: 9c 01 movw r18, r24 | |||
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242 | * \param El dato a transmitir | |||
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243 | * \return El dato leido del ADC | |||
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244 | */ | |||
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245 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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246 | // | |||
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247 | SPIC.DATA = data; | |||
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248 | 1d0: 84 e4 ldi r24, 0x44 ; 68 | |||
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249 | 1d2: 80 93 c3 08 sts 0x08C3, r24 | |||
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250 | ||||
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251 | //Wait until transmission complete | |||
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252 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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253 | 1d6: e0 ec ldi r30, 0xC0 ; 192 | |||
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254 | 1d8: f8 e0 ldi r31, 0x08 ; 8 | |||
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255 | 1da: 92 81 ldd r25, Z+2 ; 0x02 | |||
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256 | 1dc: 99 23 and r25, r25 | |||
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257 | 1de: ec f7 brge .-6 ; 0x1da <adcport_read_data+0xc> | |||
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258 | ||||
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259 | // Return received data | |||
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260 | ||||
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261 | return SPIC.DATA; | |||
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262 | 1e0: 80 91 c3 08 lds r24, 0x08C3 | |||
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263 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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264 | ||||
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265 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
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266 | ||||
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267 | // Save received data | |||
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268 | for(int i=0; i<j ; i++) | |||
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269 | 1e4: 16 16 cp r1, r22 | |||
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270 | 1e6: 17 06 cpc r1, r23 | |||
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271 | 1e8: 74 f4 brge .+28 ; 0x206 <adcport_read_data+0x38> | |||
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272 | 1ea: d9 01 movw r26, r18 | |||
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273 | 1ec: a6 0f add r26, r22 | |||
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274 | 1ee: b7 1f adc r27, r23 | |||
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275 | * \param El dato a transmitir | |||
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276 | * \return El dato leido del ADC | |||
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277 | */ | |||
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278 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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279 | // | |||
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280 | SPIC.DATA = data; | |||
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281 | 1f0: e0 ec ldi r30, 0xC0 ; 192 | |||
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282 | 1f2: f8 e0 ldi r31, 0x08 ; 8 | |||
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283 | 1f4: 13 82 std Z+3, r1 ; 0x03 | |||
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284 | ||||
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285 | //Wait until transmission complete | |||
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286 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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287 | 1f6: 92 81 ldd r25, Z+2 ; 0x02 | |||
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288 | 1f8: 99 23 and r25, r25 | |||
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289 | 1fa: ec f7 brge .-6 ; 0x1f6 <adcport_read_data+0x28> | |||
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290 | ||||
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291 | // Return received data | |||
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292 | ||||
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293 | return SPIC.DATA; | |||
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294 | 1fc: 93 81 ldd r25, Z+3 ; 0x03 | |||
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295 | ||||
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296 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
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297 | ||||
|
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298 | // Save received data | |||
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299 | for(int i=0; i<j ; i++) | |||
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300 | dato[j-i-1] = adcport_tranceiv(0); | |||
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301 | 1fe: 9e 93 st -X, r25 | |||
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|
302 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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303 | ||||
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|
304 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
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305 | ||||
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|
306 | // Save received data | |||
|
|
307 | for(int i=0; i<j ; i++) | |||
|
|
308 | 200: a2 17 cp r26, r18 | |||
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309 | 202: b3 07 cpc r27, r19 | |||
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|
310 | 204: b9 f7 brne .-18 ; 0x1f4 <adcport_read_data+0x26> | |||
|
|
311 | 206: 08 95 ret | |||
|
|
312 | ||||
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313 | 00000208 <config_spiparm>: | |||
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|
314 | inline void config_spiparm(void){ | |||
|
|
315 | // Preescaler: clkper/2 = f_cpu/2. | |||
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|
316 | // Master | |||
|
|
317 | // Mode 3: CPOL=1,CPHA=1 | |||
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|
318 | // MSB --- LSB | |||
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319 | SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | | |||
|
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320 | 208: 8c ed ldi r24, 0xDC ; 220 | |||
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|
321 | 20a: 80 93 c0 08 sts 0x08C0, r24 | |||
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322 | 20e: 08 95 ret | |||
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323 | ||||
|
|
324 | 00000210 <config_fpgaport>: | |||
|
|
325 | #include <avr/io.h> | |||
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326 | ||||
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|
327 | #include "fpga_port.h" | |||
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|
328 | ||||
|
|
329 | inline void config_fpgaport() | |||
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|
330 | { | |||
|
|
331 | 210: cf 93 push r28 | |||
|
|
332 | 212: df 93 push r29 | |||
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|
333 | //Configuracion pines del puerto D: PD6-PA1 | |||
|
|
334 | //Pines de entrada CLK_FPGA, LOCK_FPGA | |||
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335 | //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
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336 | PORT_FPGA.DIRCLR = LOCK_FPGA; | |||
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337 | 214: e0 e6 ldi r30, 0x60 ; 96 | |||
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338 | 216: f6 e0 ldi r31, 0x06 ; 6 | |||
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|
339 | 218: 22 e0 ldi r18, 0x02 ; 2 | |||
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340 | 21a: 22 83 std Z+2, r18 ; 0x02 | |||
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341 | PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
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342 | 21c: 80 e1 ldi r24, 0x10 ; 16 | |||
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343 | 21e: 81 8b std Z+17, r24 ; 0x11 | |||
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344 | PORT_FPGA.DIRSET = CLK_FPGA; | |||
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345 | 220: 94 e0 ldi r25, 0x04 ; 4 | |||
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346 | 222: 91 83 std Z+1, r25 ; 0x01 | |||
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347 | PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; | |||
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348 | 224: 38 e1 ldi r19, 0x18 ; 24 | |||
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349 | 226: 32 8b std Z+18, r19 ; 0x12 | |||
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350 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
351 | 228: 95 83 std Z+5, r25 ; 0x05 | |||
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|
352 | ||||
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353 | //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
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354 | PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
|
|
355 | 22a: 38 e7 ldi r19, 0x78 ; 120 | |||
|
|
356 | 22c: 31 83 std Z+1, r19 ; 0x01 | |||
|
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357 | PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; | |||
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|
358 | 22e: 13 8a std Z+19, r1 ; 0x13 | |||
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|
359 | PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
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|
360 | 230: 35 83 std Z+5, r19 ; 0x05 | |||
|
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361 | ||||
|
|
362 | //Configuracion pines del puerto B: PPS | |||
|
|
363 | //Pines de entrada PPS_FPGA | |||
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|
364 | //Pines de entrada en pulldown | |||
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365 | PORT_PPS.DIRCLR = PPS_FPGA; | |||
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366 | 232: a0 e2 ldi r26, 0x20 ; 32 | |||
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367 | 234: b6 e0 ldi r27, 0x06 ; 6 | |||
|
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368 | 236: 12 96 adiw r26, 0x02 ; 2 | |||
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369 | 238: 9c 93 st X, r25 | |||
|
|
370 | 23a: 12 97 sbiw r26, 0x02 ; 2 | |||
|
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371 | PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
372 | 23c: 52 96 adiw r26, 0x12 ; 18 | |||
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373 | 23e: 8c 93 st X, r24 | |||
|
|
374 | 240: 52 97 sbiw r26, 0x12 ; 18 | |||
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|
375 | ||||
|
|
376 | //Configuracion pines del puerto A: LOCKOUT | |||
|
|
377 | //Pines de salida LOCK_OUT | |||
|
|
378 | //Pines de salida en baja | |||
|
|
379 | PORT_LOCKOUT.DIRSET = LOCK_OUT; | |||
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|
380 | 242: c0 e0 ldi r28, 0x00 ; 0 | |||
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381 | 244: d6 e0 ldi r29, 0x06 ; 6 | |||
|
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382 | 246: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
383 | 248: 89 83 std Y+1, r24 ; 0x01 | |||
|
|
384 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
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385 | 24a: 8e 83 std Y+6, r24 ; 0x06 | |||
|
|
386 | ||||
|
|
387 | ||||
|
|
388 | ||||
|
|
389 | //Configuracion de interrupciones de LOCK_FPGA | |||
|
|
390 | ||||
|
|
391 | PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; | |||
|
|
392 | 24c: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
393 | 24e: 83 60 ori r24, 0x03 ; 3 | |||
|
|
394 | 250: 81 87 std Z+9, r24 ; 0x09 | |||
|
|
395 | PORT_FPGA.INT0MASK = LOCK_FPGA; | |||
|
|
396 | 252: 22 87 std Z+10, r18 ; 0x0a | |||
|
|
397 | PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; | |||
|
|
398 | 254: 81 89 ldd r24, Z+17 ; 0x11 | |||
|
|
399 | 256: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
400 | 258: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
401 | //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
402 | //PORT_FPGA.INT1MASK = CLK_FPGA; | |||
|
|
403 | //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
404 | ||||
|
|
405 | //Configuracion de interrupciones de PPS | |||
|
|
406 | PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
407 | 25a: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
408 | 25c: 83 7f andi r24, 0xF3 ; 243 | |||
|
|
409 | 25e: 88 60 ori r24, 0x08 ; 8 | |||
|
|
410 | 260: 19 96 adiw r26, 0x09 ; 9 | |||
|
|
411 | 262: 8c 93 st X, r24 | |||
|
|
412 | 264: 19 97 sbiw r26, 0x09 ; 9 | |||
|
|
413 | PORT_PPS.INT1MASK = PPS_FPGA; | |||
|
|
414 | 266: 1b 96 adiw r26, 0x0b ; 11 | |||
|
|
415 | 268: 9c 93 st X, r25 | |||
|
|
416 | 26a: 1b 97 sbiw r26, 0x0b ; 11 | |||
|
|
417 | PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; | |||
|
|
418 | 26c: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
419 | 26e: 8c 91 ld r24, X | |||
|
|
420 | 270: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
421 | 272: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
422 | 274: 81 60 ori r24, 0x01 ; 1 | |||
|
|
423 | 276: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
424 | 278: 8c 93 st X, r24 | |||
|
|
425 | } | |||
|
|
426 | 27a: df 91 pop r29 | |||
|
|
427 | 27c: cf 91 pop r28 | |||
|
|
428 | 27e: 08 95 ret | |||
|
|
429 | ||||
|
|
430 | 00000280 <habilitar_interrupciones_globales>: | |||
|
|
431 | PMIC.CTRL = level_mask; | |||
|
|
432 | } | |||
|
|
433 | ||||
|
|
434 | void habilitar_interrupciones_globales( void ) | |||
|
|
435 | { | |||
|
|
436 | sei(); | |||
|
|
437 | 280: 78 94 sei | |||
|
|
438 | 282: 08 95 ret | |||
|
|
439 | ||||
|
|
440 | 00000284 <envio_nibble>: | |||
|
|
441 | cli(); | |||
|
|
442 | } | |||
|
|
443 | ||||
|
|
444 | void envio_nibble(uint8_t fpga_dato) | |||
|
|
445 | { | |||
|
|
446 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
447 | 284: e0 e6 ldi r30, 0x60 ; 96 | |||
|
|
448 | 286: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
449 | 288: 24 e0 ldi r18, 0x04 ; 4 | |||
|
|
450 | 28a: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
451 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); | |||
|
|
452 | 28c: 94 81 ldd r25, Z+4 ; 0x04 | |||
|
|
453 | 28e: 38 2f mov r19, r24 | |||
|
|
454 | 290: 30 7f andi r19, 0xF0 ; 240 | |||
|
|
455 | 292: 33 0f add r19, r19 | |||
|
|
456 | 294: 33 0f add r19, r19 | |||
|
|
457 | 296: 33 0f add r19, r19 | |||
|
|
458 | 298: 98 73 andi r25, 0x38 ; 56 | |||
|
|
459 | 29a: 93 2b or r25, r19 | |||
|
|
460 | 29c: 94 83 std Z+4, r25 ; 0x04 | |||
|
|
461 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
462 | 29e: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
463 | //asm("nop"); | |||
|
|
464 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
465 | 2a0: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
466 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); | |||
|
|
467 | 2a2: 94 81 ldd r25, Z+4 ; 0x04 | |||
|
|
468 | 2a4: 8f 70 andi r24, 0x0F ; 15 | |||
|
|
469 | 2a6: 88 0f add r24, r24 | |||
|
|
470 | 2a8: 88 0f add r24, r24 | |||
|
|
471 | 2aa: 88 0f add r24, r24 | |||
|
|
472 | 2ac: 98 73 andi r25, 0x38 ; 56 | |||
|
|
473 | 2ae: 89 2b or r24, r25 | |||
|
|
474 | 2b0: 84 83 std Z+4, r24 ; 0x04 | |||
|
|
475 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
476 | 2b2: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
477 | 2b4: 08 95 ret | |||
|
|
478 | ||||
|
|
479 | 000002b6 <envio_dato_adc>: | |||
|
|
480 | envio_dato_adc(aux_dato); | |||
|
|
481 | envio_dato_adc(fpga_dato); | |||
|
|
482 | } | |||
|
|
483 | ||||
|
|
484 | void envio_dato_adc(uint8_t* dato_adc) | |||
|
|
485 | { | |||
|
|
486 | 2b6: 0f 93 push r16 | |||
|
|
487 | 2b8: 1f 93 push r17 | |||
|
|
488 | 2ba: cf 93 push r28 | |||
|
|
489 | 2bc: df 93 push r29 | |||
|
|
490 | 2be: ec 01 movw r28, r24 | |||
|
|
491 | 2c0: 8c 01 movw r16, r24 | |||
|
|
492 | 2c2: 0d 5f subi r16, 0xFD ; 253 | |||
|
|
493 | 2c4: 1f 4f sbci r17, 0xFF ; 255 | |||
|
|
494 | for(int i=0; i<3 ; i++) | |||
|
|
495 | envio_nibble(dato_adc[i]); | |||
|
|
496 | 2c6: 89 91 ld r24, Y+ | |||
|
|
497 | 2c8: 0e 94 42 01 call 0x284 ; 0x284 <envio_nibble> | |||
|
|
498 | envio_dato_adc(fpga_dato); | |||
|
|
499 | } | |||
|
|
500 | ||||
|
|
501 | void envio_dato_adc(uint8_t* dato_adc) | |||
|
|
502 | { | |||
|
|
503 | for(int i=0; i<3 ; i++) | |||
|
|
504 | 2cc: c0 17 cp r28, r16 | |||
|
|
505 | 2ce: d1 07 cpc r29, r17 | |||
|
|
506 | 2d0: d1 f7 brne .-12 ; 0x2c6 <envio_dato_adc+0x10> | |||
|
|
507 | envio_nibble(dato_adc[i]); | |||
|
|
508 | } | |||
|
|
509 | 2d2: df 91 pop r29 | |||
|
|
510 | 2d4: cf 91 pop r28 | |||
|
|
511 | 2d6: 1f 91 pop r17 | |||
|
|
512 | 2d8: 0f 91 pop r16 | |||
|
|
513 | 2da: 08 95 ret | |||
|
|
514 | ||||
|
|
515 | 000002dc <envio_datos_fpga>: | |||
|
|
516 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
517 | ||||
|
|
518 | } | |||
|
|
519 | ||||
|
|
520 | void envio_datos_fpga(void) | |||
|
|
521 | { | |||
|
|
522 | 2dc: cf 93 push r28 | |||
|
|
523 | 2de: df 93 push r29 | |||
|
|
524 | 2e0: cd b7 in r28, 0x3d ; 61 | |||
|
|
525 | 2e2: de b7 in r29, 0x3e ; 62 | |||
|
|
526 | 2e4: 26 97 sbiw r28, 0x06 ; 6 | |||
|
|
527 | 2e6: cd bf out 0x3d, r28 ; 61 | |||
|
|
528 | 2e8: de bf out 0x3e, r29 ; 62 | |||
|
|
529 | uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; | |||
|
|
530 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
531 | 2ea: 63 e0 ldi r22, 0x03 ; 3 | |||
|
|
532 | 2ec: 70 e0 ldi r23, 0x00 ; 0 | |||
|
|
533 | 2ee: ce 01 movw r24, r28 | |||
|
|
534 | 2f0: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
535 | 2f2: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data> | |||
|
|
536 | aux_dato[0] = fpga_dato[0]; | |||
|
|
537 | 2f6: 89 81 ldd r24, Y+1 ; 0x01 | |||
|
|
538 | 2f8: 8c 83 std Y+4, r24 ; 0x04 | |||
|
|
539 | aux_dato[1] = fpga_dato[1]; | |||
|
|
540 | 2fa: 8a 81 ldd r24, Y+2 ; 0x02 | |||
|
|
541 | 2fc: 8d 83 std Y+5, r24 ; 0x05 | |||
|
|
542 | aux_dato[2] = fpga_dato[2]; | |||
|
|
543 | 2fe: 8b 81 ldd r24, Y+3 ; 0x03 | |||
|
|
544 | 300: 8e 83 std Y+6, r24 ; 0x06 | |||
|
|
545 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
546 | 302: 63 e0 ldi r22, 0x03 ; 3 | |||
|
|
547 | 304: 70 e0 ldi r23, 0x00 ; 0 | |||
|
|
548 | 306: ce 01 movw r24, r28 | |||
|
|
549 | 308: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
550 | 30a: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data> | |||
|
|
551 | ||||
|
|
552 | envio_dato_adc(aux_dato); | |||
|
|
553 | 30e: ce 01 movw r24, r28 | |||
|
|
554 | 310: 04 96 adiw r24, 0x04 ; 4 | |||
|
|
555 | 312: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc> | |||
|
|
556 | envio_dato_adc(fpga_dato); | |||
|
|
557 | 316: ce 01 movw r24, r28 | |||
|
|
558 | 318: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
559 | 31a: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc> | |||
|
|
560 | } | |||
|
|
561 | 31e: 26 96 adiw r28, 0x06 ; 6 | |||
|
|
562 | 320: cd bf out 0x3d, r28 ; 61 | |||
|
|
563 | 322: de bf out 0x3e, r29 ; 62 | |||
|
|
564 | 324: df 91 pop r29 | |||
|
|
565 | 326: cf 91 pop r28 | |||
|
|
566 | 328: 08 95 ret | |||
|
|
567 | ||||
|
|
568 | 0000032a <main>: | |||
|
|
569 | ||||
|
|
570 | ||||
|
|
571 | int main(void) | |||
|
|
572 | { | |||
|
|
573 | //uint8_t datos_adc[3]; | |||
|
|
574 | config_puertos(); | |||
|
|
575 | 32a: 0e 94 15 02 call 0x42a ; 0x42a <config_puertos> | |||
|
|
576 | config_sysclock(); | |||
|
|
577 | 32e: 0e 94 8b 02 call 0x516 ; 0x516 <config_sysclock> | |||
|
|
578 | config_spiparm(); | |||
|
|
579 | 332: 0e 94 04 01 call 0x208 ; 0x208 <config_spiparm> | |||
|
|
580 | config_fpgaport(); | |||
|
|
581 | 336: 0e 94 08 01 call 0x210 ; 0x210 <config_fpgaport> | |||
|
|
582 | //datos_adc[0] = 0x00; | |||
|
|
583 | //datos_adc[1] = 0x00; | |||
|
|
584 | //datos_adc[2] = 0x00; | |||
|
|
585 | //PORTD.OUTSET = PIN5_bm; | |||
|
|
586 | ||||
|
|
587 | PMIC.CTRL = hab_prioridad_alta; | |||
|
|
588 | 33a: 84 e0 ldi r24, 0x04 ; 4 | |||
|
|
589 | 33c: 80 93 a2 00 sts 0x00A2, r24 | |||
|
|
590 | habilitar_interrupciones_globales(); | |||
|
|
591 | 340: 0e 94 40 01 call 0x280 ; 0x280 <habilitar_interrupciones_globales> | |||
|
|
592 | ||||
|
|
593 | /* Replace with your application code */ | |||
|
|
594 | while (1) | |||
|
|
595 | { | |||
|
|
596 | if (test_adc() == ADC_ID){ | |||
|
|
597 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
598 | 344: 00 e6 ldi r16, 0x60 ; 96 | |||
|
|
599 | 346: 16 e0 ldi r17, 0x06 ; 6 | |||
|
|
600 | 348: c0 e6 ldi r28, 0x60 ; 96 | |||
|
|
601 | habilitar_interrupciones_globales(); | |||
|
|
602 | ||||
|
|
603 | /* Replace with your application code */ | |||
|
|
604 | while (1) | |||
|
|
605 | { | |||
|
|
606 | if (test_adc() == ADC_ID){ | |||
|
|
607 | 34a: 0e 94 c2 00 call 0x184 ; 0x184 <test_adc> | |||
|
|
608 | 34e: 84 39 cpi r24, 0x94 ; 148 | |||
|
|
609 | 350: 9c 40 sbci r25, 0x0C ; 12 | |||
|
|
610 | 352: d9 f7 brne .-10 ; 0x34a <main+0x20> | |||
|
|
611 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
612 | 354: f8 01 movw r30, r16 | |||
|
|
613 | 356: c5 83 std Z+5, r28 ; 0x05 | |||
|
|
614 | 358: f8 cf rjmp .-16 ; 0x34a <main+0x20> | |||
|
|
615 | ||||
|
|
616 | 0000035a <__vector_64>: | |||
|
|
617 | return 0; | |||
|
|
618 | } | |||
|
|
619 | ||||
|
|
620 | ||||
|
|
621 | ISR(INT_LOCK_FPGA) | |||
|
|
622 | { | |||
|
|
623 | 35a: 1f 92 push r1 | |||
|
|
624 | 35c: 0f 92 push r0 | |||
|
|
625 | 35e: 0f b6 in r0, 0x3f ; 63 | |||
|
|
626 | 360: 0f 92 push r0 | |||
|
|
627 | 362: 11 24 eor r1, r1 | |||
|
|
628 | 364: 8f 93 push r24 | |||
|
|
629 | 366: ef 93 push r30 | |||
|
|
630 | 368: ff 93 push r31 | |||
|
|
631 | if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) | |||
|
|
632 | 36a: 80 91 68 06 lds r24, 0x0668 | |||
|
|
633 | 36e: 81 ff sbrs r24, 1 | |||
|
|
634 | 370: 09 c0 rjmp .+18 ; 0x384 <__vector_64+0x2a> | |||
|
|
635 | { | |||
|
|
636 | PMIC.CTRL |= hab_prioridad_media; | |||
|
|
637 | 372: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
638 | 374: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
639 | 376: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
640 | 378: 82 60 ori r24, 0x02 ; 2 | |||
|
|
641 | 37a: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
642 | PORT_LOCKOUT.OUTSET = LOCK_OUT; | |||
|
|
643 | 37c: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
644 | 37e: 80 93 05 06 sts 0x0605, r24 | |||
|
|
645 | 382: 08 c0 rjmp .+16 ; 0x394 <__vector_64+0x3a> | |||
|
|
646 | } | |||
|
|
647 | else | |||
|
|
648 | { | |||
|
|
649 | PMIC.CTRL &= ~hab_prioridad_media; | |||
|
|
650 | 384: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
651 | 386: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
652 | 388: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
653 | 38a: 8d 7f andi r24, 0xFD ; 253 | |||
|
|
654 | 38c: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
655 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
656 | 38e: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
657 | 390: 80 93 06 06 sts 0x0606, r24 | |||
|
|
658 | } | |||
|
|
659 | } | |||
|
|
660 | 394: ff 91 pop r31 | |||
|
|
661 | 396: ef 91 pop r30 | |||
|
|
662 | 398: 8f 91 pop r24 | |||
|
|
663 | 39a: 0f 90 pop r0 | |||
|
|
664 | 39c: 0f be out 0x3f, r0 ; 63 | |||
|
|
665 | 39e: 0f 90 pop r0 | |||
|
|
666 | 3a0: 1f 90 pop r1 | |||
|
|
667 | 3a2: 18 95 reti | |||
|
|
668 | ||||
|
|
669 | 000003a4 <__vector_35>: | |||
|
|
670 | ||||
|
|
671 | ISR(INT_PPS) | |||
|
|
672 | { | |||
|
|
673 | 3a4: 1f 92 push r1 | |||
|
|
674 | 3a6: 0f 92 push r0 | |||
|
|
675 | 3a8: 0f b6 in r0, 0x3f ; 63 | |||
|
|
676 | 3aa: 0f 92 push r0 | |||
|
|
677 | 3ac: 11 24 eor r1, r1 | |||
|
|
678 | 3ae: 8f 93 push r24 | |||
|
|
679 | 3b0: ef 93 push r30 | |||
|
|
680 | 3b2: ff 93 push r31 | |||
|
|
681 | if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA) | |||
|
|
682 | 3b4: 80 91 28 06 lds r24, 0x0628 | |||
|
|
683 | 3b8: 82 ff sbrs r24, 2 | |||
|
|
684 | 3ba: 06 c0 rjmp .+12 ; 0x3c8 <__vector_35+0x24> | |||
|
|
685 | PMIC.CTRL |= hab_prioridad_baja; | |||
|
|
686 | 3bc: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
687 | 3be: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
688 | 3c0: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
689 | 3c2: 81 60 ori r24, 0x01 ; 1 | |||
|
|
690 | 3c4: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
691 | 3c6: 05 c0 rjmp .+10 ; 0x3d2 <__vector_35+0x2e> | |||
|
|
692 | else | |||
|
|
693 | PMIC.CTRL &= ~hab_prioridad_baja; | |||
|
|
694 | 3c8: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
695 | 3ca: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
696 | 3cc: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
697 | 3ce: 8e 7f andi r24, 0xFE ; 254 | |||
|
|
698 | 3d0: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
699 | } | |||
|
|
700 | 3d2: ff 91 pop r31 | |||
|
|
701 | 3d4: ef 91 pop r30 | |||
|
|
702 | 3d6: 8f 91 pop r24 | |||
|
|
703 | 3d8: 0f 90 pop r0 | |||
|
|
704 | 3da: 0f be out 0x3f, r0 ; 63 | |||
|
|
705 | 3dc: 0f 90 pop r0 | |||
|
|
706 | 3de: 1f 90 pop r1 | |||
|
|
707 | 3e0: 18 95 reti | |||
|
|
708 | ||||
|
|
709 | 000003e2 <__vector_2>: | |||
|
|
710 | ||||
|
|
711 | ISR(INT_RDY) | |||
|
|
712 | { | |||
|
|
713 | 3e2: 1f 92 push r1 | |||
|
|
714 | 3e4: 0f 92 push r0 | |||
|
|
715 | 3e6: 0f b6 in r0, 0x3f ; 63 | |||
|
|
716 | 3e8: 0f 92 push r0 | |||
|
|
717 | 3ea: 11 24 eor r1, r1 | |||
|
|
718 | 3ec: 2f 93 push r18 | |||
|
|
719 | 3ee: 3f 93 push r19 | |||
|
|
720 | 3f0: 4f 93 push r20 | |||
|
|
721 | 3f2: 5f 93 push r21 | |||
|
|
722 | 3f4: 6f 93 push r22 | |||
|
|
723 | 3f6: 7f 93 push r23 | |||
|
|
724 | 3f8: 8f 93 push r24 | |||
|
|
725 | 3fa: 9f 93 push r25 | |||
|
|
726 | 3fc: af 93 push r26 | |||
|
|
727 | 3fe: bf 93 push r27 | |||
|
|
728 | 400: ef 93 push r30 | |||
|
|
729 | 402: ff 93 push r31 | |||
|
|
730 | envio_datos_fpga(); | |||
|
|
731 | 404: 0e 94 6e 01 call 0x2dc ; 0x2dc <envio_datos_fpga> | |||
|
|
732 | } | |||
|
|
733 | 408: ff 91 pop r31 | |||
|
|
734 | 40a: ef 91 pop r30 | |||
|
|
735 | 40c: bf 91 pop r27 | |||
|
|
736 | 40e: af 91 pop r26 | |||
|
|
737 | 410: 9f 91 pop r25 | |||
|
|
738 | 412: 8f 91 pop r24 | |||
|
|
739 | 414: 7f 91 pop r23 | |||
|
|
740 | 416: 6f 91 pop r22 | |||
|
|
741 | 418: 5f 91 pop r21 | |||
|
|
742 | 41a: 4f 91 pop r20 | |||
|
|
743 | 41c: 3f 91 pop r19 | |||
|
|
744 | 41e: 2f 91 pop r18 | |||
|
|
745 | 420: 0f 90 pop r0 | |||
|
|
746 | 422: 0f be out 0x3f, r0 ; 63 | |||
|
|
747 | 424: 0f 90 pop r0 | |||
|
|
748 | 426: 1f 90 pop r1 | |||
|
|
749 | 428: 18 95 reti | |||
|
|
750 | ||||
|
|
751 | 0000042a <config_puertos>: | |||
|
|
752 | #include "commSPI_ADC.h" | |||
|
|
753 | ||||
|
|
754 | inline void config_puertos(void){ | |||
|
|
755 | //Configuracion pines del puerto A: PA7-PA0 | |||
|
|
756 | //Pines de entrada y totem_pullup | |||
|
|
757 | PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; | |||
|
|
758 | 42a: e0 e0 ldi r30, 0x00 ; 0 | |||
|
|
759 | 42c: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
760 | 42e: 8e ef ldi r24, 0xFE ; 254 | |||
|
|
761 | 430: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
762 | PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
763 | 432: 88 e1 ldi r24, 0x18 ; 24 | |||
|
|
764 | 434: 87 8b std Z+23, r24 ; 0x17 | |||
|
|
765 | PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
766 | 436: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
767 | PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
768 | 438: 85 8b std Z+21, r24 ; 0x15 | |||
|
|
769 | PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
770 | 43a: 84 8b std Z+20, r24 ; 0x14 | |||
|
|
771 | PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
772 | 43c: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
773 | PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
774 | 43e: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
775 | PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
776 | 440: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
777 | //Pin de salida A0 | |||
|
|
778 | //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n | |||
|
|
779 | //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta | |||
|
|
780 | //Valor por defecto salida: PA0 = low | |||
|
|
781 | PORTA.DIRSET = PIN0_bm; | |||
|
|
782 | 442: 21 e0 ldi r18, 0x01 ; 1 | |||
|
|
783 | 444: 21 83 std Z+1, r18 ; 0x01 | |||
|
|
784 | PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
785 | 446: 98 e3 ldi r25, 0x38 ; 56 | |||
|
|
786 | 448: 90 8b std Z+16, r25 ; 0x10 | |||
|
|
787 | PORTA.OUTCLR = PIN0_bm; | |||
|
|
788 | 44a: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
789 | ||||
|
|
790 | //Configuracion pines del puerto B: PB3-PB0 | |||
|
|
791 | //Pines de entrada y totem_pullup | |||
|
|
792 | PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; | |||
|
|
793 | 44c: e0 e2 ldi r30, 0x20 ; 32 | |||
|
|
794 | 44e: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
795 | 450: 3f e0 ldi r19, 0x0F ; 15 | |||
|
|
796 | 452: 32 83 std Z+2, r19 ; 0x02 | |||
|
|
797 | PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
798 | 454: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
799 | PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
800 | 456: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
801 | PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
802 | 458: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
803 | PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
804 | 45a: 80 8b std Z+16, r24 ; 0x10 | |||
|
|
805 | ||||
|
|
806 | //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI | |||
|
|
807 | //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 | |||
|
|
808 | //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. | |||
|
|
809 | PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C | |||
|
|
810 | 45c: e0 e4 ldi r30, 0x40 ; 64 | |||
|
|
811 | 45e: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
812 | 460: 2f e4 ldi r18, 0x4F ; 79 | |||
|
|
813 | 462: 22 83 std Z+2, r18 ; 0x02 | |||
|
|
814 | PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; | |||
|
|
815 | 464: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
816 | PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
817 | 466: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
818 | PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
819 | 468: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
820 | PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
821 | 46a: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
822 | PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
823 | 46c: 80 8b std Z+16, r24 ; 0x10 | |||
|
|
824 | //Pines de salida wiredand-pull | |||
|
|
825 | //Valor por defecto salida: PC4,PC7 = low | |||
|
|
826 | //Valor por defecto salida: PC5 = set | |||
|
|
827 | PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; | |||
|
|
828 | 46e: 20 eb ldi r18, 0xB0 ; 176 | |||
|
|
829 | 470: 21 83 std Z+1, r18 ; 0x01 | |||
|
|
830 | PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; | |||
|
|
831 | 472: 15 8a std Z+21, r1 ; 0x15 | |||
|
|
832 | PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
833 | 474: 17 8a std Z+23, r1 ; 0x17 | |||
|
|
834 | PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
835 | 476: 14 8a std Z+20, r1 ; 0x14 | |||
|
|
836 | PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; | |||
|
|
837 | 478: 20 e9 ldi r18, 0x90 ; 144 | |||
|
|
838 | 47a: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
839 | PORTSPI.OUTCLR = SPI_MOSI_bm; | |||
|
|
840 | 47c: 20 e2 ldi r18, 0x20 ; 32 | |||
|
|
841 | 47e: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
842 | //Configuracion pines del puerto D: PD7-PD0 | |||
|
|
843 | //Pines de entrada y totem_pullup: PIN7 y PIN0 | |||
|
|
844 | //NOTA | |||
|
|
845 | //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO | |||
|
|
846 | //NOTA FIN | |||
|
|
847 | PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
848 | 480: a0 e6 ldi r26, 0x60 ; 96 | |||
|
|
849 | 482: b6 e0 ldi r27, 0x06 ; 6 | |||
|
|
850 | 484: 27 e8 ldi r18, 0x87 ; 135 | |||
|
|
851 | 486: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
852 | 488: 2c 93 st X, r18 | |||
|
|
853 | 48a: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
854 | PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
855 | 48c: 57 96 adiw r26, 0x17 ; 23 | |||
|
|
856 | 48e: 8c 93 st X, r24 | |||
|
|
857 | 490: 57 97 sbiw r26, 0x17 ; 23 | |||
|
|
858 | PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
859 | 492: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
860 | 494: 8c 93 st X, r24 | |||
|
|
861 | 496: 50 97 sbiw r26, 0x10 ; 16 | |||
|
|
862 | //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga | |||
|
|
863 | PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
864 | 498: 20 e1 ldi r18, 0x10 ; 16 | |||
|
|
865 | 49a: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
866 | 49c: 2c 93 st X, r18 | |||
|
|
867 | 49e: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
868 | PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
869 | 4a0: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
870 | 4a2: 2c 93 st X, r18 | |||
|
|
871 | 4a4: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
872 | //Pines de salida tipo wired-and-pull | |||
|
|
873 | //Valor por defecto PD6, PD5, PD4, PD3 = low | |||
|
|
874 | PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
875 | 4a6: 48 e7 ldi r20, 0x78 ; 120 | |||
|
|
876 | 4a8: 11 96 adiw r26, 0x01 ; 1 | |||
|
|
877 | 4aa: 4c 93 st X, r20 | |||
|
|
878 | 4ac: 11 97 sbiw r26, 0x01 ; 1 | |||
|
|
879 | PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
880 | 4ae: 56 96 adiw r26, 0x16 ; 22 | |||
|
|
881 | 4b0: 9c 93 st X, r25 | |||
|
|
882 | 4b2: 56 97 sbiw r26, 0x16 ; 22 | |||
|
|
883 | PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
884 | 4b4: 55 96 adiw r26, 0x15 ; 21 | |||
|
|
885 | 4b6: 9c 93 st X, r25 | |||
|
|
886 | 4b8: 55 97 sbiw r26, 0x15 ; 21 | |||
|
|
887 | PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
888 | 4ba: 54 96 adiw r26, 0x14 ; 20 | |||
|
|
889 | 4bc: 9c 93 st X, r25 | |||
|
|
890 | 4be: 54 97 sbiw r26, 0x14 ; 20 | |||
|
|
891 | PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
892 | 4c0: 53 96 adiw r26, 0x13 ; 19 | |||
|
|
893 | 4c2: 9c 93 st X, r25 | |||
|
|
894 | 4c4: 53 97 sbiw r26, 0x13 ; 19 | |||
|
|
895 | PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
896 | 4c6: 16 96 adiw r26, 0x06 ; 6 | |||
|
|
897 | 4c8: 4c 93 st X, r20 | |||
|
|
898 | ||||
|
|
899 | //Configuracion pines del puerto E: PE3-PE0 | |||
|
|
900 | //Pines de entrada y totem_pullup: PIN3 - PIN0 | |||
|
|
901 | PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
902 | 4ca: a0 e8 ldi r26, 0x80 ; 128 | |||
|
|
903 | 4cc: b6 e0 ldi r27, 0x06 ; 6 | |||
|
|
904 | 4ce: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
905 | 4d0: 3c 93 st X, r19 | |||
|
|
906 | 4d2: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
907 | PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
908 | 4d4: 53 96 adiw r26, 0x13 ; 19 | |||
|
|
909 | 4d6: 8c 93 st X, r24 | |||
|
|
910 | 4d8: 53 97 sbiw r26, 0x13 ; 19 | |||
|
|
911 | PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
912 | 4da: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
913 | 4dc: 8c 93 st X, r24 | |||
|
|
914 | 4de: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
915 | PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
916 | 4e0: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
917 | 4e2: 8c 93 st X, r24 | |||
|
|
918 | 4e4: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
919 | PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
920 | 4e6: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
921 | 4e8: 8c 93 st X, r24 | |||
|
|
922 | ||||
|
|
923 | //Configuracion pines del puerto R: PR1-PR0 | |||
|
|
924 | //Pines de entrada y totem_pulldown: PIN0 | |||
|
|
925 | PORTR.DIRCLR = PIN1_bm| PIN0_bm; | |||
|
|
926 | 4ea: a0 ee ldi r26, 0xE0 ; 224 | |||
|
|
927 | 4ec: b7 e0 ldi r27, 0x07 ; 7 | |||
|
|
928 | 4ee: 93 e0 ldi r25, 0x03 ; 3 | |||
|
|
929 | 4f0: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
930 | 4f2: 9c 93 st X, r25 | |||
|
|
931 | 4f4: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
932 | PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
933 | 4f6: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
934 | 4f8: 2c 93 st X, r18 | |||
|
|
935 | 4fa: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
936 | //Pines de entrada y totem_pulldup:PIN1 | |||
|
|
937 | PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
938 | 4fc: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
939 | 4fe: 8c 93 st X, r24 | |||
|
|
940 | ||||
|
|
941 | //Configuraci�n como interrupci�n del pin SPI_MISO_RDY | |||
|
|
942 | ||||
|
|
943 | PORTSPI.INT0MASK = SPI_MISO_bm; | |||
|
|
944 | 500: 80 e4 ldi r24, 0x40 ; 64 | |||
|
|
945 | 502: 82 87 std Z+10, r24 ; 0x0a | |||
|
|
946 | PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; | |||
|
|
947 | 504: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
948 | 506: 8c 7f andi r24, 0xFC ; 252 | |||
|
|
949 | 508: 81 60 ori r24, 0x01 ; 1 | |||
|
|
950 | 50a: 81 87 std Z+9, r24 ; 0x09 | |||
|
|
951 | PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
952 | 50c: 86 89 ldd r24, Z+22 ; 0x16 | |||
|
|
953 | 50e: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
954 | 510: 82 60 ori r24, 0x02 ; 2 | |||
|
|
955 | 512: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
956 | 514: 08 95 ret | |||
|
|
957 | ||||
|
|
958 | 00000516 <config_sysclock>: | |||
|
|
959 | #define F_CPU 32000000UL | |||
|
|
960 | #include <avr/io.h> | |||
|
|
961 | ||||
|
|
962 | void config_sysclock(void){ | |||
|
|
963 | ||||
|
|
964 | OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz | |||
|
|
965 | 516: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
966 | 518: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
967 | 51a: 80 81 ld r24, Z | |||
|
|
968 | 51c: 86 60 ori r24, 0x06 ; 6 | |||
|
|
969 | 51e: 80 83 st Z, r24 | |||
|
|
970 | do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj | |||
|
|
971 | 520: 81 81 ldd r24, Z+1 ; 0x01 | |||
|
|
972 | 522: 81 ff sbrs r24, 1 | |||
|
|
973 | 524: fd cf rjmp .-6 ; 0x520 <config_sysclock+0xa> | |||
|
|
974 | do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj | |||
|
|
975 | 526: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
976 | 528: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
977 | 52a: 81 81 ldd r24, Z+1 ; 0x01 | |||
|
|
978 | 52c: 82 ff sbrs r24, 2 | |||
|
|
979 | 52e: fd cf rjmp .-6 ; 0x52a <config_sysclock+0x14> | |||
|
|
980 | CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla | |||
|
|
981 | 530: 28 ed ldi r18, 0xD8 ; 216 | |||
|
|
982 | 532: 24 bf out 0x34, r18 ; 52 | |||
|
|
983 | //con instrucciones en assembler | |||
|
|
984 | CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler | |||
|
|
985 | 534: e0 e4 ldi r30, 0x40 ; 64 | |||
|
|
986 | 536: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
987 | 538: 80 81 ld r24, Z | |||
|
|
988 | 53a: 81 60 ori r24, 0x01 ; 1 | |||
|
|
989 | 53c: 80 83 st Z, r24 | |||
|
|
990 | DFLLRC32M.CTRL = DFLL_ENABLE_bm; | |||
|
|
991 | 53e: 91 e0 ldi r25, 0x01 ; 1 | |||
|
|
992 | 540: 90 93 60 00 sts 0x0060, r25 | |||
|
|
993 | OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K | |||
|
|
994 | 544: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
995 | 546: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
996 | 548: 86 81 ldd r24, Z+6 ; 0x06 | |||
|
|
997 | 54a: 16 82 std Z+6, r1 ; 0x06 | |||
|
|
998 | OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno | |||
|
|
999 | 54c: 80 81 ld r24, Z | |||
|
|
1000 | 54e: 8e 7f andi r24, 0xFE ; 254 | |||
|
|
1001 | 550: 80 83 st Z, r24 | |||
|
|
1002 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
1003 | 552: 24 bf out 0x34, r18 ; 52 | |||
|
|
1004 | OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de | |||
|
|
1005 | 554: 90 93 53 00 sts 0x0053, r25 | |||
|
|
1006 | 558: 08 95 ret | |||
|
|
1007 | ||||
|
|
1008 | 0000055a <_exit>: | |||
|
|
1009 | 55a: f8 94 cli | |||
|
|
1010 | ||||
|
|
1011 | 0000055c <__stop_program>: | |||
|
|
1012 | 55c: ff cf rjmp .-2 ; 0x55c <__stop_program> | |||
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1 | Archive member included to satisfy reference by file (symbol) | |||
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2 | ||||
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3 | c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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4 | C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o (exit) | |||
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5 | ||||
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6 | Discarded input sections | |||
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7 | ||||
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8 | .data 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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9 | .bss 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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10 | .text 0x00000000 0x0 ADC_7176_2.o | |||
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11 | .data 0x00000000 0x0 ADC_7176_2.o | |||
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12 | .bss 0x00000000 0x0 ADC_7176_2.o | |||
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13 | .text.test_adc_2 | |||
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14 | 0x00000000 0x3e ADC_7176_2.o | |||
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15 | .text.adcport_tranceiv | |||
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16 | 0x00000000 0x14 ADC_7176_2.o | |||
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17 | .text.adcport_write_filtcon0 | |||
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18 | 0x00000000 0x34 ADC_7176_2.o | |||
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19 | .text.config_adc | |||
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20 | 0x00000000 0x6 ADC_7176_2.o | |||
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21 | .text.adcport_write_interfmode | |||
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22 | 0x00000000 0x34 ADC_7176_2.o | |||
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23 | .text 0x00000000 0x0 commSPI_ADC.o | |||
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24 | .data 0x00000000 0x0 commSPI_ADC.o | |||
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25 | .bss 0x00000000 0x0 commSPI_ADC.o | |||
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26 | .text 0x00000000 0x0 fpga_port.o | |||
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27 | .data 0x00000000 0x0 fpga_port.o | |||
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28 | .bss 0x00000000 0x0 fpga_port.o | |||
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29 | .text.habilitar_interrupciones | |||
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30 | 0x00000000 0x6 fpga_port.o | |||
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31 | .text.deshabilitar_interrupciones_globales | |||
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32 | 0x00000000 0x4 fpga_port.o | |||
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33 | .text 0x00000000 0x0 main.o | |||
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34 | .data 0x00000000 0x0 main.o | |||
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35 | .bss 0x00000000 0x0 main.o | |||
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36 | .text 0x00000000 0x0 Ports.o | |||
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37 | .data 0x00000000 0x0 Ports.o | |||
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38 | .bss 0x00000000 0x0 Ports.o | |||
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39 | .text 0x00000000 0x0 sys_clock.o | |||
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40 | .data 0x00000000 0x0 sys_clock.o | |||
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41 | .bss 0x00000000 0x0 sys_clock.o | |||
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42 | .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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43 | .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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44 | .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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45 | .text.libgcc.mul | |||
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46 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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47 | .text.libgcc.div | |||
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48 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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49 | .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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50 | .text.libgcc.prologue | |||
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51 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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52 | .text.libgcc.builtins | |||
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53 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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54 | .text.libgcc.fmul | |||
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55 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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56 | .text.libgcc.fixed | |||
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57 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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58 | ||||
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59 | Memory Configuration | |||
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60 | ||||
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61 | Name Origin Length Attributes | |||
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62 | text 0x00000000 0x00100000 xr | |||
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63 | data 0x00802000 0x0000ffa0 rw !x | |||
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64 | eeprom 0x00810000 0x00010000 rw !x | |||
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65 | fuse 0x00820000 0x00000400 rw !x | |||
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66 | lock 0x00830000 0x00000400 rw !x | |||
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67 | signature 0x00840000 0x00000400 rw !x | |||
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68 | user_signatures 0x00850000 0x00000400 rw !x | |||
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69 | *default* 0x00000000 0xffffffff | |||
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70 | ||||
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71 | Linker script and memory map | |||
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72 | ||||
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73 | LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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74 | LOAD ADC_7176_2.o | |||
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75 | LOAD commSPI_ADC.o | |||
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76 | LOAD fpga_port.o | |||
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77 | LOAD main.o | |||
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78 | LOAD Ports.o | |||
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79 | LOAD sys_clock.o | |||
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80 | START GROUP | |||
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81 | LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a | |||
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82 | END GROUP | |||
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83 | START GROUP | |||
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84 | LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a | |||
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85 | LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a | |||
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86 | LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libc.a | |||
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87 | LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2\libatxmega32d4.a | |||
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88 | END GROUP | |||
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89 | ||||
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90 | .hash | |||
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91 | *(.hash) | |||
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92 | ||||
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93 | .dynsym | |||
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94 | *(.dynsym) | |||
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95 | ||||
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96 | .dynstr | |||
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97 | *(.dynstr) | |||
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98 | ||||
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99 | .gnu.version | |||
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100 | *(.gnu.version) | |||
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101 | ||||
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102 | .gnu.version_d | |||
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103 | *(.gnu.version_d) | |||
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104 | ||||
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105 | .gnu.version_r | |||
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106 | *(.gnu.version_r) | |||
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107 | ||||
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108 | .rel.init | |||
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109 | *(.rel.init) | |||
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110 | ||||
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111 | .rela.init | |||
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112 | *(.rela.init) | |||
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113 | ||||
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114 | .rel.text | |||
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115 | *(.rel.text) | |||
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116 | *(.rel.text.*) | |||
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117 | *(.rel.gnu.linkonce.t*) | |||
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118 | ||||
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119 | .rela.text | |||
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120 | *(.rela.text) | |||
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121 | *(.rela.text.*) | |||
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122 | *(.rela.gnu.linkonce.t*) | |||
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123 | ||||
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124 | .rel.fini | |||
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125 | *(.rel.fini) | |||
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126 | ||||
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127 | .rela.fini | |||
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128 | *(.rela.fini) | |||
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129 | ||||
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130 | .rel.rodata | |||
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131 | *(.rel.rodata) | |||
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132 | *(.rel.rodata.*) | |||
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133 | *(.rel.gnu.linkonce.r*) | |||
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134 | ||||
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135 | .rela.rodata | |||
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136 | *(.rela.rodata) | |||
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137 | *(.rela.rodata.*) | |||
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138 | *(.rela.gnu.linkonce.r*) | |||
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139 | ||||
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140 | .rel.data | |||
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141 | *(.rel.data) | |||
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142 | *(.rel.data.*) | |||
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143 | *(.rel.gnu.linkonce.d*) | |||
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144 | ||||
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145 | .rela.data | |||
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146 | *(.rela.data) | |||
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147 | *(.rela.data.*) | |||
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148 | *(.rela.gnu.linkonce.d*) | |||
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149 | ||||
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150 | .rel.ctors | |||
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151 | *(.rel.ctors) | |||
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152 | ||||
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153 | .rela.ctors | |||
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154 | *(.rela.ctors) | |||
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155 | ||||
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156 | .rel.dtors | |||
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157 | *(.rel.dtors) | |||
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158 | ||||
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159 | .rela.dtors | |||
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160 | *(.rela.dtors) | |||
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161 | ||||
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162 | .rel.got | |||
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163 | *(.rel.got) | |||
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164 | ||||
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165 | .rela.got | |||
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166 | *(.rela.got) | |||
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167 | ||||
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168 | .rel.bss | |||
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169 | *(.rel.bss) | |||
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170 | ||||
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171 | .rela.bss | |||
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172 | *(.rela.bss) | |||
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173 | ||||
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174 | .rel.plt | |||
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175 | *(.rel.plt) | |||
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176 | ||||
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177 | .rela.plt | |||
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178 | *(.rela.plt) | |||
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179 | ||||
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180 | .text 0x00000000 0x55e | |||
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181 | *(.vectors) | |||
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182 | .vectors 0x00000000 0x16c C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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183 | 0x00000000 __vector_default | |||
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184 | 0x00000000 __vectors | |||
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185 | *(.vectors) | |||
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186 | *(.progmem.gcc*) | |||
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187 | 0x0000016c . = ALIGN (0x2) | |||
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188 | 0x0000016c __trampolines_start = . | |||
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189 | *(.trampolines) | |||
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190 | .trampolines 0x0000016c 0x0 linker stubs | |||
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191 | *(.trampolines*) | |||
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192 | 0x0000016c __trampolines_end = . | |||
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193 | *(.progmem*) | |||
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194 | 0x0000016c . = ALIGN (0x2) | |||
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195 | *(.jumptables) | |||
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196 | *(.jumptables*) | |||
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197 | *(.lowtext) | |||
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198 | *(.lowtext*) | |||
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199 | 0x0000016c __ctors_start = . | |||
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200 | *(.ctors) | |||
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201 | 0x0000016c __ctors_end = . | |||
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202 | 0x0000016c __dtors_start = . | |||
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203 | *(.dtors) | |||
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204 | 0x0000016c __dtors_end = . | |||
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205 | SORT(*)(.ctors) | |||
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206 | SORT(*)(.dtors) | |||
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207 | *(.init0) | |||
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208 | .init0 0x0000016c 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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209 | 0x0000016c __init | |||
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210 | *(.init0) | |||
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211 | *(.init1) | |||
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212 | *(.init1) | |||
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213 | *(.init2) | |||
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214 | .init2 0x0000016c 0xc C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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215 | *(.init2) | |||
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216 | *(.init3) | |||
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217 | *(.init3) | |||
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218 | *(.init4) | |||
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219 | *(.init4) | |||
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220 | *(.init5) | |||
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221 | *(.init5) | |||
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222 | *(.init6) | |||
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223 | *(.init6) | |||
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224 | *(.init7) | |||
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225 | *(.init7) | |||
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226 | *(.init8) | |||
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227 | *(.init8) | |||
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228 | *(.init9) | |||
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229 | .init9 0x00000178 0x8 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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230 | *(.init9) | |||
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231 | *(.text) | |||
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232 | .text 0x00000180 0x4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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233 | 0x00000180 __vector_38 | |||
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234 | 0x00000180 __vector_22 | |||
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235 | 0x00000180 __vector_63 | |||
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236 | 0x00000180 __vector_28 | |||
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237 | 0x00000180 __vector_67 | |||
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238 | 0x00000180 __vector_1 | |||
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239 | 0x00000180 __vector_32 | |||
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240 | 0x00000180 __vector_75 | |||
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241 | 0x00000180 __vector_71 | |||
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242 | 0x00000180 __vector_34 | |||
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243 | 0x00000180 __vector_62 | |||
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244 | 0x00000180 __vector_77 | |||
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245 | 0x00000180 __vector_24 | |||
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246 | 0x00000180 __vector_12 | |||
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247 | 0x00000180 __vector_55 | |||
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248 | 0x00000180 __vector_69 | |||
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249 | 0x00000180 __vector_81 | |||
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250 | 0x00000180 __vector_90 | |||
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251 | 0x00000180 __vector_46 | |||
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252 | 0x00000180 __bad_interrupt | |||
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253 | 0x00000180 __vector_72 | |||
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254 | 0x00000180 __vector_6 | |||
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255 | 0x00000180 __vector_31 | |||
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256 | 0x00000180 __vector_78 | |||
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257 | 0x00000180 __vector_74 | |||
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258 | 0x00000180 __vector_39 | |||
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259 | 0x00000180 __vector_3 | |||
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260 | 0x00000180 __vector_23 | |||
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261 | 0x00000180 __vector_68 | |||
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262 | 0x00000180 __vector_30 | |||
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263 | 0x00000180 __vector_73 | |||
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264 | 0x00000180 __vector_45 | |||
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265 | 0x00000180 __vector_25 | |||
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266 | 0x00000180 __vector_61 | |||
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267 | 0x00000180 __vector_11 | |||
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268 | 0x00000180 __vector_54 | |||
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269 | 0x00000180 __vector_13 | |||
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270 | 0x00000180 __vector_17 | |||
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271 | 0x00000180 __vector_19 | |||
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272 | 0x00000180 __vector_56 | |||
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273 | 0x00000180 __vector_7 | |||
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274 | 0x00000180 __vector_49 | |||
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275 | 0x00000180 __vector_41 | |||
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276 | 0x00000180 __vector_86 | |||
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277 | 0x00000180 __vector_88 | |||
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278 | 0x00000180 __vector_43 | |||
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279 | 0x00000180 __vector_27 | |||
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280 | 0x00000180 __vector_5 | |||
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281 | 0x00000180 __vector_33 | |||
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282 | 0x00000180 __vector_76 | |||
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283 | 0x00000180 __vector_47 | |||
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284 | 0x00000180 __vector_52 | |||
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285 | 0x00000180 __vector_37 | |||
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286 | 0x00000180 __vector_89 | |||
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287 | 0x00000180 __vector_4 | |||
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288 | 0x00000180 __vector_44 | |||
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289 | 0x00000180 __vector_82 | |||
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290 | 0x00000180 __vector_51 | |||
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291 | 0x00000180 __vector_9 | |||
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292 | 0x00000180 __vector_21 | |||
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293 | 0x00000180 __vector_15 | |||
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294 | 0x00000180 __vector_66 | |||
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295 | 0x00000180 __vector_36 | |||
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296 | 0x00000180 __vector_79 | |||
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297 | 0x00000180 __vector_58 | |||
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298 | 0x00000180 __vector_70 | |||
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299 | 0x00000180 __vector_83 | |||
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300 | 0x00000180 __vector_29 | |||
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301 | 0x00000180 __vector_60 | |||
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302 | 0x00000180 __vector_40 | |||
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303 | 0x00000180 __vector_85 | |||
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304 | 0x00000180 __vector_8 | |||
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305 | 0x00000180 __vector_26 | |||
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306 | 0x00000180 __vector_48 | |||
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307 | 0x00000180 __vector_80 | |||
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308 | 0x00000180 __vector_14 | |||
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309 | 0x00000180 __vector_84 | |||
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310 | 0x00000180 __vector_57 | |||
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311 | 0x00000180 __vector_53 | |||
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312 | 0x00000180 __vector_10 | |||
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313 | 0x00000180 __vector_50 | |||
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314 | 0x00000180 __vector_16 | |||
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315 | 0x00000180 __vector_59 | |||
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316 | 0x00000180 __vector_18 | |||
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317 | 0x00000180 __vector_20 | |||
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318 | 0x00000180 __vector_42 | |||
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319 | 0x00000180 __vector_87 | |||
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320 | 0x00000180 __vector_65 | |||
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321 | 0x00000184 . = ALIGN (0x2) | |||
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322 | *(.text.*) | |||
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323 | .text.test_adc | |||
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324 | 0x00000184 0x4a ADC_7176_2.o | |||
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325 | 0x00000184 test_adc | |||
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326 | .text.adcport_read_data | |||
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327 | 0x000001ce 0x3a ADC_7176_2.o | |||
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328 | 0x000001ce adcport_read_data | |||
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329 | .text.config_spiparm | |||
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330 | 0x00000208 0x8 commSPI_ADC.o | |||
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331 | 0x00000208 config_spiparm | |||
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332 | .text.config_fpgaport | |||
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333 | 0x00000210 0x70 fpga_port.o | |||
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334 | 0x00000210 config_fpgaport | |||
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335 | .text.habilitar_interrupciones_globales | |||
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336 | 0x00000280 0x4 fpga_port.o | |||
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337 | 0x00000280 habilitar_interrupciones_globales | |||
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338 | .text.envio_nibble | |||
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339 | 0x00000284 0x32 fpga_port.o | |||
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340 | 0x00000284 envio_nibble | |||
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341 | .text.envio_dato_adc | |||
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342 | 0x000002b6 0x26 fpga_port.o | |||
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343 | 0x000002b6 envio_dato_adc | |||
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344 | .text.envio_datos_fpga | |||
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345 | 0x000002dc 0x4e fpga_port.o | |||
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346 | 0x000002dc envio_datos_fpga | |||
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347 | .text.main 0x0000032a 0x30 main.o | |||
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348 | 0x0000032a main | |||
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349 | .text.__vector_64 | |||
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350 | 0x0000035a 0x4a main.o | |||
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351 | 0x0000035a __vector_64 | |||
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352 | .text.__vector_35 | |||
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353 | 0x000003a4 0x3e main.o | |||
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354 | 0x000003a4 __vector_35 | |||
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355 | .text.__vector_2 | |||
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356 | 0x000003e2 0x48 main.o | |||
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357 | 0x000003e2 __vector_2 | |||
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358 | .text.config_puertos | |||
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359 | 0x0000042a 0xec Ports.o | |||
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360 | 0x0000042a config_puertos | |||
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361 | .text.config_sysclock | |||
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362 | 0x00000516 0x44 sys_clock.o | |||
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363 | 0x00000516 config_sysclock | |||
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364 | 0x0000055a . = ALIGN (0x2) | |||
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365 | *(.fini9) | |||
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366 | .fini9 0x0000055a 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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367 | 0x0000055a _exit | |||
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368 | 0x0000055a exit | |||
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369 | *(.fini9) | |||
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370 | *(.fini8) | |||
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371 | *(.fini8) | |||
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372 | *(.fini7) | |||
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373 | *(.fini7) | |||
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374 | *(.fini6) | |||
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375 | *(.fini6) | |||
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376 | *(.fini5) | |||
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377 | *(.fini5) | |||
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378 | *(.fini4) | |||
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379 | *(.fini4) | |||
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380 | *(.fini3) | |||
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381 | *(.fini3) | |||
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382 | *(.fini2) | |||
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383 | *(.fini2) | |||
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384 | *(.fini1) | |||
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385 | *(.fini1) | |||
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386 | *(.fini0) | |||
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387 | .fini0 0x0000055a 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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388 | *(.fini0) | |||
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389 | 0x0000055e _etext = . | |||
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390 | ||||
|
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391 | .data 0x00802000 0x0 load address 0x0000055e | |||
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392 | 0x00802000 PROVIDE (__data_start, .) | |||
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393 | *(.data) | |||
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394 | *(.data*) | |||
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395 | *(.rodata) | |||
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396 | *(.rodata*) | |||
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397 | *(.gnu.linkonce.d*) | |||
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398 | 0x00802000 . = ALIGN (0x2) | |||
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399 | 0x00802000 _edata = . | |||
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400 | 0x00802000 PROVIDE (__data_end, .) | |||
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401 | ||||
|
|
402 | .bss 0x00802000 0x0 | |||
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|
403 | 0x00802000 PROVIDE (__bss_start, .) | |||
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|
404 | *(.bss) | |||
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|
405 | *(.bss*) | |||
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406 | *(COMMON) | |||
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407 | 0x00802000 PROVIDE (__bss_end, .) | |||
|
|
408 | 0x0000055e __data_load_start = LOADADDR (.data) | |||
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|
409 | 0x0000055e __data_load_end = (__data_load_start + SIZEOF (.data)) | |||
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410 | ||||
|
|
411 | .noinit 0x00802000 0x0 | |||
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|
412 | 0x00802000 PROVIDE (__noinit_start, .) | |||
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|
413 | *(.noinit*) | |||
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414 | 0x00802000 PROVIDE (__noinit_end, .) | |||
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|
415 | 0x00802000 _end = . | |||
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|
416 | 0x00802000 PROVIDE (__heap_start, .) | |||
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|
417 | ||||
|
|
418 | .eeprom 0x00810000 0x0 | |||
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|
419 | *(.eeprom*) | |||
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|
420 | 0x00810000 __eeprom_end = . | |||
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421 | ||||
|
|
422 | .fuse | |||
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|
423 | *(.fuse) | |||
|
|
424 | *(.lfuse) | |||
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|
425 | *(.hfuse) | |||
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|
426 | *(.efuse) | |||
|
|
427 | ||||
|
|
428 | .lock | |||
|
|
429 | *(.lock*) | |||
|
|
430 | ||||
|
|
431 | .signature | |||
|
|
432 | *(.signature*) | |||
|
|
433 | ||||
|
|
434 | .user_signatures | |||
|
|
435 | *(.user_signatures*) | |||
|
|
436 | ||||
|
|
437 | .stab | |||
|
|
438 | *(.stab) | |||
|
|
439 | ||||
|
|
440 | .stabstr | |||
|
|
441 | *(.stabstr) | |||
|
|
442 | ||||
|
|
443 | .stab.excl | |||
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|
444 | *(.stab.excl) | |||
|
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445 | ||||
|
|
446 | .stab.exclstr | |||
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|
447 | *(.stab.exclstr) | |||
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448 | ||||
|
|
449 | .stab.index | |||
|
|
450 | *(.stab.index) | |||
|
|
451 | ||||
|
|
452 | .stab.indexstr | |||
|
|
453 | *(.stab.indexstr) | |||
|
|
454 | ||||
|
|
455 | .comment 0x00000000 0x30 | |||
|
|
456 | *(.comment) | |||
|
|
457 | .comment 0x00000000 0x30 ADC_7176_2.o | |||
|
|
458 | 0x31 (size before relaxing) | |||
|
|
459 | .comment 0x00000030 0x31 commSPI_ADC.o | |||
|
|
460 | .comment 0x00000030 0x31 fpga_port.o | |||
|
|
461 | .comment 0x00000030 0x31 main.o | |||
|
|
462 | .comment 0x00000030 0x31 Ports.o | |||
|
|
463 | .comment 0x00000030 0x31 sys_clock.o | |||
|
|
464 | ||||
|
|
465 | .note.gnu.avr.deviceinfo | |||
|
|
466 | 0x00000000 0x40 | |||
|
|
467 | .note.gnu.avr.deviceinfo | |||
|
|
468 | 0x00000000 0x40 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
|
|
469 | ||||
|
|
470 | .note.gnu.build-id | |||
|
|
471 | *(.note.gnu.build-id) | |||
|
|
472 | ||||
|
|
473 | .debug | |||
|
|
474 | *(.debug) | |||
|
|
475 | ||||
|
|
476 | .line | |||
|
|
477 | *(.line) | |||
|
|
478 | ||||
|
|
479 | .debug_srcinfo | |||
|
|
480 | *(.debug_srcinfo) | |||
|
|
481 | ||||
|
|
482 | .debug_sfnames | |||
|
|
483 | *(.debug_sfnames) | |||
|
|
484 | ||||
|
|
485 | .debug_aranges 0x00000000 0x138 | |||
|
|
486 | *(.debug_aranges) | |||
|
|
487 | .debug_aranges | |||
|
|
488 | 0x00000000 0x50 ADC_7176_2.o | |||
|
|
489 | .debug_aranges | |||
|
|
490 | 0x00000050 0x20 commSPI_ADC.o | |||
|
|
491 | .debug_aranges | |||
|
|
492 | 0x00000070 0x50 fpga_port.o | |||
|
|
493 | .debug_aranges | |||
|
|
494 | 0x000000c0 0x38 main.o | |||
|
|
495 | .debug_aranges | |||
|
|
496 | 0x000000f8 0x20 Ports.o | |||
|
|
497 | .debug_aranges | |||
|
|
498 | 0x00000118 0x20 sys_clock.o | |||
|
|
499 | ||||
|
|
500 | .debug_pubnames | |||
|
|
501 | *(.debug_pubnames) | |||
|
|
502 | ||||
|
|
503 | .debug_info 0x00000000 0x14b5 | |||
|
|
504 | *(.debug_info .gnu.linkonce.wi.*) | |||
|
|
505 | .debug_info 0x00000000 0x53c ADC_7176_2.o | |||
|
|
506 | .debug_info 0x0000053c 0xf0 commSPI_ADC.o | |||
|
|
507 | .debug_info 0x0000062c 0x578 fpga_port.o | |||
|
|
508 | .debug_info 0x00000ba4 0x413 main.o | |||
|
|
509 | .debug_info 0x00000fb7 0x2ab Ports.o | |||
|
|
510 | .debug_info 0x00001262 0x253 sys_clock.o | |||
|
|
511 | ||||
|
|
512 | .debug_abbrev 0x00000000 0x644 | |||
|
|
513 | *(.debug_abbrev) | |||
|
|
514 | .debug_abbrev 0x00000000 0x1b6 ADC_7176_2.o | |||
|
|
515 | .debug_abbrev 0x000001b6 0x83 commSPI_ADC.o | |||
|
|
516 | .debug_abbrev 0x00000239 0x19b fpga_port.o | |||
|
|
517 | .debug_abbrev 0x000003d4 0x10d main.o | |||
|
|
518 | .debug_abbrev 0x000004e1 0xaa Ports.o | |||
|
|
519 | .debug_abbrev 0x0000058b 0xb9 sys_clock.o | |||
|
|
520 | ||||
|
|
521 | .debug_line 0x00000000 0x827 | |||
|
|
522 | *(.debug_line .debug_line.* .debug_line_end) | |||
|
|
523 | .debug_line 0x00000000 0x1c9 ADC_7176_2.o | |||
|
|
524 | .debug_line 0x000001c9 0x101 commSPI_ADC.o | |||
|
|
525 | .debug_line 0x000002ca 0x19c fpga_port.o | |||
|
|
526 | .debug_line 0x00000466 0x185 main.o | |||
|
|
527 | .debug_line 0x000005eb 0x12c Ports.o | |||
|
|
528 | .debug_line 0x00000717 0x110 sys_clock.o | |||
|
|
529 | ||||
|
|
530 | .debug_frame 0x00000000 0x278 | |||
|
|
531 | *(.debug_frame) | |||
|
|
532 | .debug_frame 0x00000000 0x84 ADC_7176_2.o | |||
|
|
533 | .debug_frame 0x00000084 0x24 commSPI_ADC.o | |||
|
|
534 | .debug_frame 0x000000a8 0xb4 fpga_port.o | |||
|
|
535 | .debug_frame 0x0000015c 0xd4 main.o | |||
|
|
536 | .debug_frame 0x00000230 0x24 Ports.o | |||
|
|
537 | .debug_frame 0x00000254 0x24 sys_clock.o | |||
|
|
538 | ||||
|
|
539 | .debug_str 0x00000000 0x7d6 | |||
|
|
540 | *(.debug_str) | |||
|
|
541 | .debug_str 0x00000000 0x2c0 ADC_7176_2.o | |||
|
|
542 | 0x303 (size before relaxing) | |||
|
|
543 | .debug_str 0x000002c0 0x22 commSPI_ADC.o | |||
|
|
544 | 0x1cc (size before relaxing) | |||
|
|
545 | .debug_str 0x000002e2 0x34d fpga_port.o | |||
|
|
546 | 0x5e0 (size before relaxing) | |||
|
|
547 | .debug_str 0x0000062f 0x53 main.o | |||
|
|
548 | 0x3c1 (size before relaxing) | |||
|
|
549 | .debug_str 0x00000682 0xd Ports.o | |||
|
|
550 | 0x3f5 (size before relaxing) | |||
|
|
551 | .debug_str 0x0000068f 0x147 sys_clock.o | |||
|
|
552 | 0x2ff (size before relaxing) | |||
|
|
553 | ||||
|
|
554 | .debug_loc 0x00000000 0x3d0 | |||
|
|
555 | *(.debug_loc) | |||
|
|
556 | .debug_loc 0x00000000 0xfc ADC_7176_2.o | |||
|
|
557 | .debug_loc 0x000000fc 0x15d fpga_port.o | |||
|
|
558 | .debug_loc 0x00000259 0x177 main.o | |||
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559 | ||||
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560 | .debug_macinfo | |||
|
|
561 | *(.debug_macinfo) | |||
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562 | ||||
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563 | .debug_weaknames | |||
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564 | *(.debug_weaknames) | |||
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565 | ||||
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566 | .debug_funcnames | |||
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567 | *(.debug_funcnames) | |||
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568 | ||||
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569 | .debug_typenames | |||
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570 | *(.debug_typenames) | |||
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571 | ||||
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572 | .debug_varnames | |||
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573 | *(.debug_varnames) | |||
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574 | ||||
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575 | .debug_pubtypes | |||
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576 | *(.debug_pubtypes) | |||
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577 | ||||
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578 | .debug_ranges 0x00000000 0xd8 | |||
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579 | *(.debug_ranges) | |||
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580 | .debug_ranges 0x00000000 0x40 ADC_7176_2.o | |||
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581 | .debug_ranges 0x00000040 0x10 commSPI_ADC.o | |||
|
|
582 | .debug_ranges 0x00000050 0x40 fpga_port.o | |||
|
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583 | .debug_ranges 0x00000090 0x28 main.o | |||
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584 | .debug_ranges 0x000000b8 0x10 Ports.o | |||
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585 | .debug_ranges 0x000000c8 0x10 sys_clock.o | |||
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586 | ||||
|
|
587 | .debug_macro | |||
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588 | *(.debug_macro) | |||
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589 | OUTPUT(ADCSPI_ver01.elf elf32-avr) | |||
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590 | LOAD linker stubs | |||
| @@ -0,0 +1,88 | |||||
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88 | S9030000FC | |||
| @@ -0,0 +1,44 | |||||
|
|
1 | ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
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11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././ADC_7176_2.h: | |||
|
|
41 | ||||
|
|
42 | .././Ports.h: | |||
|
|
43 | ||||
|
|
44 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,164 | |||||
|
|
1 | ################################################################################ | |||
|
|
2 | # Automatically-generated file. Do not edit! | |||
|
|
3 | ################################################################################ | |||
|
|
4 | ||||
|
|
5 | SHELL := cmd.exe | |||
|
|
6 | RM := rm -rf | |||
|
|
7 | ||||
|
|
8 | USER_OBJS := | |||
|
|
9 | ||||
|
|
10 | LIBS := | |||
|
|
11 | PROJ := | |||
|
|
12 | ||||
|
|
13 | O_SRCS := | |||
|
|
14 | C_SRCS := | |||
|
|
15 | S_SRCS := | |||
|
|
16 | S_UPPER_SRCS := | |||
|
|
17 | OBJ_SRCS := | |||
|
|
18 | ASM_SRCS := | |||
|
|
19 | PREPROCESSING_SRCS := | |||
|
|
20 | OBJS := | |||
|
|
21 | OBJS_AS_ARGS := | |||
|
|
22 | C_DEPS := | |||
|
|
23 | C_DEPS_AS_ARGS := | |||
|
|
24 | EXECUTABLES := | |||
|
|
25 | OUTPUT_FILE_PATH := | |||
|
|
26 | OUTPUT_FILE_PATH_AS_ARGS := | |||
|
|
27 | AVR_APP_PATH :=$$$AVR_APP_PATH$$$ | |||
|
|
28 | QUOTE := " | |||
|
|
29 | ADDITIONAL_DEPENDENCIES:= | |||
|
|
30 | OUTPUT_FILE_DEP:= | |||
|
|
31 | LIB_DEP:= | |||
|
|
32 | LINKER_SCRIPT_DEP:= | |||
|
|
33 | ||||
|
|
34 | # Every subdirectory with source files must be described here | |||
|
|
35 | SUBDIRS := | |||
|
|
36 | ||||
|
|
37 | ||||
|
|
38 | # Add inputs and outputs from these tool invocations to the build variables | |||
|
|
39 | C_SRCS += \ | |||
|
|
40 | ../ADC_7176_2.c \ | |||
|
|
41 | ../commSPI_ADC.c \ | |||
|
|
42 | ../fpga_port.c \ | |||
|
|
43 | ../main.c \ | |||
|
|
44 | ../Ports.c \ | |||
|
|
45 | ../sys_clock.c | |||
|
|
46 | ||||
|
|
47 | ||||
|
|
48 | PREPROCESSING_SRCS += | |||
|
|
49 | ||||
|
|
50 | ||||
|
|
51 | ASM_SRCS += | |||
|
|
52 | ||||
|
|
53 | ||||
|
|
54 | OBJS += \ | |||
|
|
55 | ADC_7176_2.o \ | |||
|
|
56 | commSPI_ADC.o \ | |||
|
|
57 | fpga_port.o \ | |||
|
|
58 | main.o \ | |||
|
|
59 | Ports.o \ | |||
|
|
60 | sys_clock.o | |||
|
|
61 | ||||
|
|
62 | OBJS_AS_ARGS += \ | |||
|
|
63 | ADC_7176_2.o \ | |||
|
|
64 | commSPI_ADC.o \ | |||
|
|
65 | fpga_port.o \ | |||
|
|
66 | main.o \ | |||
|
|
67 | Ports.o \ | |||
|
|
68 | sys_clock.o | |||
|
|
69 | ||||
|
|
70 | C_DEPS += \ | |||
|
|
71 | ADC_7176_2.d \ | |||
|
|
72 | commSPI_ADC.d \ | |||
|
|
73 | fpga_port.d \ | |||
|
|
74 | main.d \ | |||
|
|
75 | Ports.d \ | |||
|
|
76 | sys_clock.d | |||
|
|
77 | ||||
|
|
78 | C_DEPS_AS_ARGS += \ | |||
|
|
79 | ADC_7176_2.d \ | |||
|
|
80 | commSPI_ADC.d \ | |||
|
|
81 | fpga_port.d \ | |||
|
|
82 | main.d \ | |||
|
|
83 | Ports.d \ | |||
|
|
84 | sys_clock.d | |||
|
|
85 | ||||
|
|
86 | OUTPUT_FILE_PATH +=ADCSPI_ver01.elf | |||
|
|
87 | ||||
|
|
88 | OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf | |||
|
|
89 | ||||
|
|
90 | ADDITIONAL_DEPENDENCIES:= | |||
|
|
91 | ||||
|
|
92 | OUTPUT_FILE_DEP:= ./makedep.mk | |||
|
|
93 | ||||
|
|
94 | LIB_DEP+= | |||
|
|
95 | ||||
|
|
96 | LINKER_SCRIPT_DEP+= | |||
|
|
97 | ||||
|
|
98 | ||||
|
|
99 | # AVR32/GNU C Compiler | |||
|
|
100 | ||||
|
|
101 | ||||
|
|
102 | ||||
|
|
103 | ||||
|
|
104 | ||||
|
|
105 | ||||
|
|
106 | ||||
|
|
107 | ||||
|
|
108 | ||||
|
|
109 | ||||
|
|
110 | ||||
|
|
111 | ||||
|
|
112 | ||||
|
|
113 | ./%.o: .././%.c | |||
|
|
114 | @echo Building file: $< | |||
|
|
115 | @echo Invoking: AVR/GNU C Compiler : 4.9.2 | |||
|
|
116 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" | |||
|
|
117 | @echo Finished building: $< | |||
|
|
118 | ||||
|
|
119 | ||||
|
|
120 | ||||
|
|
121 | ||||
|
|
122 | # AVR32/GNU Preprocessing Assembler | |||
|
|
123 | ||||
|
|
124 | ||||
|
|
125 | ||||
|
|
126 | # AVR32/GNU Assembler | |||
|
|
127 | ||||
|
|
128 | ||||
|
|
129 | ||||
|
|
130 | ||||
|
|
131 | ifneq ($(MAKECMDGOALS),clean) | |||
|
|
132 | ifneq ($(strip $(C_DEPS)),) | |||
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133 | -include $(C_DEPS) | |||
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134 | endif | |||
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135 | endif | |||
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136 | ||||
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137 | # Add inputs and outputs from these tool invocations to the build variables | |||
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138 | ||||
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|
139 | # All Target | |||
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|
140 | all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) | |||
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141 | ||||
|
|
142 | $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) | |||
|
|
143 | @echo Building target: $@ | |||
|
|
144 | @echo Invoking: AVR/GNU Linker : 4.9.2 | |||
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|
145 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" | |||
|
|
146 | @echo Finished building target: $@ | |||
|
|
147 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex" | |||
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|
148 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0 | |||
|
|
149 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss" | |||
|
|
150 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec" | |||
|
|
151 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf" | |||
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152 | ||||
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153 | ||||
|
|
154 | ||||
|
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155 | ||||
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156 | ||||
|
|
157 | ||||
|
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158 | ||||
|
|
159 | # Other Targets | |||
|
|
160 | clean: | |||
|
|
161 | -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) | |||
|
|
162 | -$(RM) $(C_DEPS_AS_ARGS) | |||
|
|
163 | rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures" | |||
|
|
164 | No newline at end of file | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | Ports.d Ports.o: .././Ports.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././Ports.h .././commSPI_ADC.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././Ports.h: | |||
|
|
41 | ||||
|
|
42 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././commSPI_ADC.h .././Ports.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././commSPI_ADC.h: | |||
|
|
41 | ||||
|
|
42 | .././Ports.h: | |||
| @@ -0,0 +1,50 | |||||
|
|
1 | fpga_port.d fpga_port.o: .././fpga_port.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././fpga_port.h \ | |||
|
|
15 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ | |||
|
|
16 | .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
27 | ||||
|
|
28 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
39 | ||||
|
|
40 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
41 | ||||
|
|
42 | .././fpga_port.h: | |||
|
|
43 | ||||
|
|
44 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: | |||
|
|
45 | ||||
|
|
46 | .././ADC_7176_2.h: | |||
|
|
47 | ||||
|
|
48 | .././Ports.h: | |||
|
|
49 | ||||
|
|
50 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,52 | |||||
|
|
1 | main.d main.o: .././main.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././Ports.h .././commSPI_ADC.h .././sys_clock.h .././ADC_7176_2.h \ | |||
|
|
15 | .././fpga_port.h \ | |||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
27 | ||||
|
|
28 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
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29 | ||||
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30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
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31 | ||||
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32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
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33 | ||||
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34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
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|
35 | ||||
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36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
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37 | ||||
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38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
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39 | ||||
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40 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
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|
41 | ||||
|
|
42 | .././Ports.h: | |||
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|
43 | ||||
|
|
44 | .././commSPI_ADC.h: | |||
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|
45 | ||||
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|
46 | .././sys_clock.h: | |||
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|
47 | ||||
|
|
48 | .././ADC_7176_2.h: | |||
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49 | ||||
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|
50 | .././fpga_port.h: | |||
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51 | ||||
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52 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: | |||
| @@ -0,0 +1,16 | |||||
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|
1 | ################################################################################ | |||
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2 | # Automatically-generated file. Do not edit or delete the file | |||
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3 | ################################################################################ | |||
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4 | ||||
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5 | ADC_7176_2.c | |||
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6 | ||||
|
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7 | commSPI_ADC.c | |||
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|
8 | ||||
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|
9 | fpga_port.c | |||
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10 | ||||
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|
11 | main.c | |||
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12 | ||||
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|
13 | Ports.c | |||
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14 | ||||
|
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15 | sys_clock.c | |||
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16 | ||||
| @@ -0,0 +1,37 | |||||
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1 | sys_clock.d sys_clock.o: .././sys_clock.c \ | |||
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2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
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3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
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4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
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5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
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6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
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7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
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8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
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9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
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10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
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11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
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12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
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13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h | |||
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14 | ||||
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15 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
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16 | ||||
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17 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
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18 | ||||
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19 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
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20 | ||||
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21 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
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22 | ||||
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23 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
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24 | ||||
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25 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
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|
26 | ||||
|
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27 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
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28 | ||||
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29 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
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30 | ||||
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31 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
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32 | ||||
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33 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
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34 | ||||
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35 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
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36 | ||||
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37 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
| @@ -0,0 +1,116 | |||||
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1 | /* | |||
|
|
2 | * Ports.c | |||
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|
3 | * | |||
|
|
4 | * Created: 23/11/15 13:57:48 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
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|
7 | ||||
|
|
8 | /*! | |||
|
|
9 | * \fn config_puertos | |||
|
|
10 | * \brief Configuraci�n de todos los pines de I/O a usarse | |||
|
|
11 | * para la prueba. Para el firmware final se deben dejar de configurar en este segmento | |||
|
|
12 | * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo. | |||
|
|
13 | * Los criterios de asignaci�n de control: | |||
|
|
14 | * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si | |||
|
|
15 | * Se sabe que la entrada ser� casi siempre alta. | |||
|
|
16 | * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si | |||
|
|
17 | * Se sabe que la entrada ser� casi siempre baja. | |||
|
|
18 | * WiredAndpull: Para evitar cortos de una salida al exterior del board. | |||
|
|
19 | * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board). | |||
|
|
20 | * \ | |||
|
|
21 | */ | |||
|
|
22 | ||||
|
|
23 | #define F_CPU 32000000UL | |||
|
|
24 | #include <avr/io.h> | |||
|
|
25 | ||||
|
|
26 | #include "Ports.h" | |||
|
|
27 | #include "commSPI_ADC.h" | |||
|
|
28 | ||||
|
|
29 | inline void config_puertos(void){ | |||
|
|
30 | //Configuracion pines del puerto A: PA7-PA0 | |||
|
|
31 | //Pines de entrada y totem_pullup | |||
|
|
32 | PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; | |||
|
|
33 | PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
34 | PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
35 | PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
36 | PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
37 | PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
38 | PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
39 | PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
40 | //Pin de salida A0 | |||
|
|
41 | //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n | |||
|
|
42 | //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta | |||
|
|
43 | //Valor por defecto salida: PA0 = low | |||
|
|
44 | PORTA.DIRSET = PIN0_bm; | |||
|
|
45 | PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
46 | PORTA.OUTCLR = PIN0_bm; | |||
|
|
47 | ||||
|
|
48 | //Configuracion pines del puerto B: PB3-PB0 | |||
|
|
49 | //Pines de entrada y totem_pullup | |||
|
|
50 | PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; | |||
|
|
51 | PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
52 | PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
53 | PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
54 | PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
55 | ||||
|
|
56 | //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI | |||
|
|
57 | //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 | |||
|
|
58 | //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. | |||
|
|
59 | PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C | |||
|
|
60 | PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; | |||
|
|
61 | PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
62 | PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
63 | PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
64 | PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
65 | //Pines de salida wiredand-pull | |||
|
|
66 | //Valor por defecto salida: PC4,PC7 = low | |||
|
|
67 | //Valor por defecto salida: PC5 = set | |||
|
|
68 | PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; | |||
|
|
69 | PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; | |||
|
|
70 | PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
71 | PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
72 | PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; | |||
|
|
73 | PORTSPI.OUTCLR = SPI_MOSI_bm; | |||
|
|
74 | ||||
|
|
75 | //Configuracion pines del puerto D: PD7-PD0 | |||
|
|
76 | //Pines de entrada y totem_pullup: PIN7 y PIN0 | |||
|
|
77 | //NOTA | |||
|
|
78 | //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO | |||
|
|
79 | //NOTA FIN | |||
|
|
80 | PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
81 | PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
82 | PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
83 | //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga | |||
|
|
84 | PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
85 | PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
86 | //Pines de salida tipo wired-and-pull | |||
|
|
87 | //Valor por defecto PD6, PD5, PD4, PD3 = low | |||
|
|
88 | PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
89 | PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
90 | PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
91 | PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
92 | PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
93 | PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
94 | ||||
|
|
95 | //Configuracion pines del puerto E: PE3-PE0 | |||
|
|
96 | //Pines de entrada y totem_pullup: PIN3 - PIN0 | |||
|
|
97 | PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
98 | PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
99 | PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
100 | PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
101 | PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
102 | ||||
|
|
103 | //Configuracion pines del puerto R: PR1-PR0 | |||
|
|
104 | //Pines de entrada y totem_pulldown: PIN0 | |||
|
|
105 | PORTR.DIRCLR = PIN1_bm| PIN0_bm; | |||
|
|
106 | PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
107 | //Pines de entrada y totem_pulldup:PIN1 | |||
|
|
108 | PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
109 | ||||
|
|
110 | //Configuraci�n como interrupci�n del pin SPI_MISO_RDY | |||
|
|
111 | ||||
|
|
112 | PORTSPI.INT0MASK = SPI_MISO_bm; | |||
|
|
113 | PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; | |||
|
|
114 | PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
115 | ||||
|
|
116 | } No newline at end of file | |||
| @@ -0,0 +1,21 | |||||
|
|
1 | /* | |||
|
|
2 | * Ports.h | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 13:55:28 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef PORTS_H_ | |||
|
|
10 | #define PORTS_H_ | |||
|
|
11 | ||||
|
|
12 | #define F_CPU 32000000UL | |||
|
|
13 | #include <avr/io.h> | |||
|
|
14 | ||||
|
|
15 | #define INT_RDY PORTC_INT0_vect | |||
|
|
16 | ||||
|
|
17 | void config_puertos(void); | |||
|
|
18 | ||||
|
|
19 | ||||
|
|
20 | ||||
|
|
21 | #endif /* PORTS_H_ */ No newline at end of file | |||
| @@ -0,0 +1,31 | |||||
|
|
1 | /* | |||
|
|
2 | * commSPI_ADC.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:08:25 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #define F_CPU 32000000UL | |||
|
|
10 | #include <avr/io.h> | |||
|
|
11 | #include "commSPI_ADC.h" | |||
|
|
12 | ||||
|
|
13 | /*! | |||
|
|
14 | * \fn config_spiparm | |||
|
|
15 | * \brief Configuraci�n de los par�metros de reloj SPI | |||
|
|
16 | * | |||
|
|
17 | * fspi = fper/2 = fcpu/2 = 16MHz | |||
|
|
18 | * | |||
|
|
19 | * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una | |||
|
|
20 | * nueva evaluaci�n | |||
|
|
21 | * \ | |||
|
|
22 | */ | |||
|
|
23 | inline void config_spiparm(void){ | |||
|
|
24 | // Preescaler: clkper/2 = f_cpu/2. | |||
|
|
25 | // Master | |||
|
|
26 | // Mode 3: CPOL=1,CPHA=1 | |||
|
|
27 | // MSB --- LSB | |||
|
|
28 | SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | | |||
|
|
29 | SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm; | |||
|
|
30 | } | |||
|
|
31 | ||||
| @@ -0,0 +1,32 | |||||
|
|
1 | /* | |||
|
|
2 | * commSPI_ADC.h | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:06:45 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef COMMSPI_ADC_H_ | |||
|
|
10 | #define COMMSPI_ADC_H_ | |||
|
|
11 | ||||
|
|
12 | #define F_CPU 32000000UL | |||
|
|
13 | #include <avr/io.h> | |||
|
|
14 | ||||
|
|
15 | #include "Ports.h" | |||
|
|
16 | ||||
|
|
17 | #define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI | |||
|
|
18 | ||||
|
|
19 | #define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS | |||
|
|
20 | #define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI | |||
|
|
21 | #define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO | |||
|
|
22 | #define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK | |||
|
|
23 | ||||
|
|
24 | #define SPI_SS_bm PIN4_bm // Pin de entrada - Totem | |||
|
|
25 | #define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem | |||
|
|
26 | #define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem | |||
|
|
27 | #define SPI_SCK_bm PIN7_bm // Pin de salida - Totem | |||
|
|
28 | ||||
|
|
29 | void config_spiparm(void); | |||
|
|
30 | ||||
|
|
31 | ||||
|
|
32 | #endif /* COMMSPI_ADC_H_ */ No newline at end of file | |||
| @@ -0,0 +1,111 | |||||
|
|
1 | /* | |||
|
|
2 | * fpga_port.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:33:16 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #define F_CPU 32000000UL | |||
|
|
9 | #include <avr/io.h> | |||
|
|
10 | ||||
|
|
11 | #include "fpga_port.h" | |||
|
|
12 | ||||
|
|
13 | inline void config_fpgaport() | |||
|
|
14 | { | |||
|
|
15 | //Configuracion pines del puerto D: PD6-PA1 | |||
|
|
16 | //Pines de entrada CLK_FPGA, LOCK_FPGA | |||
|
|
17 | //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
|
|
18 | PORT_FPGA.DIRCLR = LOCK_FPGA; | |||
|
|
19 | PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
20 | PORT_FPGA.DIRSET = CLK_FPGA; | |||
|
|
21 | PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
22 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
23 | ||||
|
|
24 | //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
|
|
25 | PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
|
|
26 | PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; | |||
|
|
27 | PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
|
|
28 | ||||
|
|
29 | //Configuracion pines del puerto B: PPS | |||
|
|
30 | //Pines de entrada PPS_FPGA | |||
|
|
31 | //Pines de entrada en pulldown | |||
|
|
32 | PORT_PPS.DIRCLR = PPS_FPGA; | |||
|
|
33 | PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
34 | ||||
|
|
35 | //Configuracion pines del puerto A: LOCKOUT | |||
|
|
36 | //Pines de salida LOCK_OUT | |||
|
|
37 | //Pines de salida en baja | |||
|
|
38 | PORT_LOCKOUT.DIRSET = LOCK_OUT; | |||
|
|
39 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
40 | ||||
|
|
41 | ||||
|
|
42 | ||||
|
|
43 | //Configuracion de interrupciones de LOCK_FPGA | |||
|
|
44 | ||||
|
|
45 | PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; | |||
|
|
46 | PORT_FPGA.INT0MASK = LOCK_FPGA; | |||
|
|
47 | PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; | |||
|
|
48 | ||||
|
|
49 | //Configuracion de interrupciones de CLK | |||
|
|
50 | //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
51 | //PORT_FPGA.INT1MASK = CLK_FPGA; | |||
|
|
52 | //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
53 | ||||
|
|
54 | //Configuracion de interrupciones de PPS | |||
|
|
55 | PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
56 | PORT_PPS.INT1MASK = PPS_FPGA; | |||
|
|
57 | PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; | |||
|
|
58 | } | |||
|
|
59 | ||||
|
|
60 | void habilitar_interrupciones( uint8_t level_mask ) | |||
|
|
61 | { | |||
|
|
62 | PMIC.CTRL = level_mask; | |||
|
|
63 | } | |||
|
|
64 | ||||
|
|
65 | void habilitar_interrupciones_globales( void ) | |||
|
|
66 | { | |||
|
|
67 | sei(); | |||
|
|
68 | } | |||
|
|
69 | ||||
|
|
70 | void deshabilitar_interrupciones_globales( void ) | |||
|
|
71 | { | |||
|
|
72 | cli(); | |||
|
|
73 | } | |||
|
|
74 | ||||
|
|
75 | void envio_nibble(uint8_t fpga_dato) | |||
|
|
76 | { | |||
|
|
77 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
78 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); | |||
|
|
79 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
80 | //asm("nop"); | |||
|
|
81 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
82 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); | |||
|
|
83 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
84 | ||||
|
|
85 | } | |||
|
|
86 | ||||
|
|
87 | void envio_datos_fpga(void) | |||
|
|
88 | { | |||
|
|
89 | uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; | |||
|
|
90 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
91 | aux_dato[0] = fpga_dato[0]; | |||
|
|
92 | aux_dato[1] = fpga_dato[1]; | |||
|
|
93 | aux_dato[2] = fpga_dato[2]; | |||
|
|
94 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
95 | ||||
|
|
96 | envio_dato_adc(aux_dato); | |||
|
|
97 | envio_dato_adc(fpga_dato); | |||
|
|
98 | } | |||
|
|
99 | ||||
|
|
100 | void envio_dato_adc(uint8_t* dato_adc) | |||
|
|
101 | { | |||
|
|
102 | for(int i=0; i<3 ; i++) | |||
|
|
103 | envio_nibble(dato_adc[i]); | |||
|
|
104 | } | |||
|
|
105 | /* | |||
|
|
106 | __attribute__((noinline)) void delay_nop(void) | |||
|
|
107 | { | |||
|
|
108 | asm("nop"); | |||
|
|
109 | } | |||
|
|
110 | */ | |||
|
|
111 | ||||
| @@ -0,0 +1,68 | |||||
|
|
1 | /* | |||
|
|
2 | * fpga_port.h | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:20:25 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef FPGA_PORT_H_ | |||
|
|
10 | #define FPGA_PORT_H_ | |||
|
|
11 | ||||
|
|
12 | #define F_CPU 32000000UL | |||
|
|
13 | #include <avr/io.h> | |||
|
|
14 | #include <avr/interrupt.h> | |||
|
|
15 | #include "ADC_7176_2.h" | |||
|
|
16 | ||||
|
|
17 | //Port B | |||
|
|
18 | #define PORT_PPS PORTB | |||
|
|
19 | #define PPS_FPGA PIN2_bm | |||
|
|
20 | #define PPS_FPGA_CTRL PIN2CTRL | |||
|
|
21 | #define INT_PPS PORTB_INT1_vect | |||
|
|
22 | ||||
|
|
23 | //Port A | |||
|
|
24 | #define PORT_LOCKOUT PORTA | |||
|
|
25 | #define LOCK_OUT PIN0_bm | |||
|
|
26 | ||||
|
|
27 | ||||
|
|
28 | //Port D | |||
|
|
29 | #define PORT_FPGA PORTD | |||
|
|
30 | #define LOCK_FPGA PIN1_bm | |||
|
|
31 | #define CLK_FPGA PIN2_bm | |||
|
|
32 | #define CH_BIT0_FPGA PIN3_bm | |||
|
|
33 | #define CH_BIT1_FPGA PIN4_bm | |||
|
|
34 | #define CH_BIT2_FPGA PIN5_bm | |||
|
|
35 | #define CH_BIT3_FPGA PIN6_bm | |||
|
|
36 | #define INT_LOCK_FPGA PORTD_INT0_vect | |||
|
|
37 | ||||
|
|
38 | #define LOCK_FPGA_CTRL PIN1CTRL | |||
|
|
39 | #define CLK_FPGA_CTRL PIN2CTRL | |||
|
|
40 | #define CH_BIT0_FPGA_CTRL PIN3CTRL | |||
|
|
41 | #define CH_BIT1_FPGA_CTRL PIN4CTRL | |||
|
|
42 | #define CH_BIT2_FPGA_CTRL PIN5CTRL | |||
|
|
43 | #define CH_BIT3_FPGA_CTRL PIN6CTRL | |||
|
|
44 | ||||
|
|
45 | void config_fpgaport(); | |||
|
|
46 | void habilitar_interrupciones( uint8_t level_mask ); | |||
|
|
47 | void habilitar_interrupciones_globales( ); | |||
|
|
48 | void deshabilitar_interrupciones_globales( ); | |||
|
|
49 | ||||
|
|
50 | //Habilitar | |||
|
|
51 | #define hab_prioridad_alta PMIC_HILVLEN_bm | |||
|
|
52 | #define hab_prioridad_media PMIC_MEDLVLEN_bm | |||
|
|
53 | #define hab_prioridad_baja PMIC_LOLVLEN_bm | |||
|
|
54 | ||||
|
|
55 | //M�scara de nibbles | |||
|
|
56 | #define nibble_alto_bm 0xF0 | |||
|
|
57 | #define nibble_bajo_bm 0x0F | |||
|
|
58 | #define fpga_salidas_bp 3 | |||
|
|
59 | #define fpga_salidas_bm 0x38 | |||
|
|
60 | ||||
|
|
61 | //funciones de env�o de datos | |||
|
|
62 | void envio_nibble(uint8_t fpga_dato); | |||
|
|
63 | ||||
|
|
64 | //funcion interrupcion por flanco de subida de RDY | |||
|
|
65 | void envio_datos_fpga(void); | |||
|
|
66 | void envio_dato_adc(uint8_t* dato_adc); | |||
|
|
67 | ||||
|
|
68 | #endif /* FPGA_PORT_H_ */ No newline at end of file | |||
| @@ -0,0 +1,77 | |||||
|
|
1 | /* | |||
|
|
2 | * ADCSPI_ver01.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 26/10/15 12:02:22 | |||
|
|
5 | * Author : Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #define F_CPU 32000000UL | |||
|
|
9 | #include <avr/io.h> | |||
|
|
10 | #include "Ports.h" | |||
|
|
11 | #include "commSPI_ADC.h" | |||
|
|
12 | #include "sys_clock.h" | |||
|
|
13 | #include "ADC_7176_2.h" | |||
|
|
14 | #include "fpga_port.h" | |||
|
|
15 | ||||
|
|
16 | ||||
|
|
17 | int main(void) | |||
|
|
18 | { | |||
|
|
19 | //uint8_t datos_adc[3]; | |||
|
|
20 | config_puertos(); | |||
|
|
21 | config_sysclock(); | |||
|
|
22 | config_spiparm(); | |||
|
|
23 | config_fpgaport(); | |||
|
|
24 | ||||
|
|
25 | //datos_adc[0] = 0x00; | |||
|
|
26 | //datos_adc[1] = 0x00; | |||
|
|
27 | //datos_adc[2] = 0x00; | |||
|
|
28 | //PORTD.OUTSET = PIN5_bm; | |||
|
|
29 | ||||
|
|
30 | PMIC.CTRL = hab_prioridad_alta; | |||
|
|
31 | habilitar_interrupciones_globales(); | |||
|
|
32 | ||||
|
|
33 | /* Replace with your application code */ | |||
|
|
34 | while (1) | |||
|
|
35 | { | |||
|
|
36 | if (test_adc() == ADC_ID){ | |||
|
|
37 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
38 | } | |||
|
|
39 | //test_adc_2(datos_adc); | |||
|
|
40 | //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){ | |||
|
|
41 | //PORTD.OUTSET = PIN4_bm; | |||
|
|
42 | //} | |||
|
|
43 | } | |||
|
|
44 | return 0; | |||
|
|
45 | } | |||
|
|
46 | ||||
|
|
47 | ||||
|
|
48 | ISR(INT_LOCK_FPGA) | |||
|
|
49 | { | |||
|
|
50 | if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) | |||
|
|
51 | { | |||
|
|
52 | PMIC.CTRL |= hab_prioridad_media; | |||
|
|
53 | PORT_LOCKOUT.OUTSET = LOCK_OUT; | |||
|
|
54 | } | |||
|
|
55 | else | |||
|
|
56 | { | |||
|
|
57 | PMIC.CTRL &= ~hab_prioridad_media; | |||
|
|
58 | PMIC.CTRL &= ~hab_prioridad_baja; | |||
|
|
59 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
60 | } | |||
|
|
61 | } | |||
|
|
62 | ||||
|
|
63 | ISR(INT_PPS) | |||
|
|
64 | { | |||
|
|
65 | if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA) | |||
|
|
66 | PMIC.CTRL |= hab_prioridad_baja; | |||
|
|
67 | else | |||
|
|
68 | PMIC.CTRL &= ~hab_prioridad_baja; | |||
|
|
69 | } | |||
|
|
70 | ||||
|
|
71 | ISR(INT_RDY) | |||
|
|
72 | { | |||
|
|
73 | envio_datos_fpga(); | |||
|
|
74 | } | |||
|
|
75 | ||||
|
|
76 | ||||
|
|
77 | ||||
| @@ -0,0 +1,55 | |||||
|
|
1 | /* | |||
|
|
2 | * sys_clock.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:04:36 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | /*! | |||
|
|
10 | * \fn config_sysclock | |||
|
|
11 | * \brief Configuraci�n del reloj interno del sistema | |||
|
|
12 | * Reloj interno | |||
|
|
13 | * fsys = 32MHz | |||
|
|
14 | * | |||
|
|
15 | * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL | |||
|
|
16 | * \ | |||
|
|
17 | */ | |||
|
|
18 | ||||
|
|
19 | #define F_CPU 32000000UL | |||
|
|
20 | #include <avr/io.h> | |||
|
|
21 | ||||
|
|
22 | void config_sysclock(void){ | |||
|
|
23 | ||||
|
|
24 | OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz | |||
|
|
25 | do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj | |||
|
|
26 | do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj | |||
|
|
27 | CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla | |||
|
|
28 | //con instrucciones en assembler | |||
|
|
29 | CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler | |||
|
|
30 | DFLLRC32M.CTRL = DFLL_ENABLE_bm; | |||
|
|
31 | OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K | |||
|
|
32 | OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno | |||
|
|
33 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
34 | OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de | |||
|
|
35 | ||||
|
|
36 | /* | |||
|
|
37 | CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1 | |||
|
|
38 | OSC_XOSCCTRL = OSC_XOSCSEL_EXTCLK_gc; //usar external clock | |||
|
|
39 | ||||
|
|
40 | OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | ( 0x02 & OSC_PLLFAC_gm); | |||
|
|
41 | ||||
|
|
42 | OSC_CTRL |= OSC_PLLEN_bm; //usar external clock | |||
|
|
43 | while(!(OSC_STATUS & OSC_XOSCRDY_bm)); | |||
|
|
44 | while(!(OSC_STATUS & OSC_PLLRDY_bm)); | |||
|
|
45 | ||||
|
|
46 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
47 | CLK_CTRL = (CLK_SCLKSEL_PLL_gc) & CLK_SCLKSEL_gm; //CLK usa oscilador externo | |||
|
|
48 | ||||
|
|
49 | OSC_CTRL &= ~OSC_RC2MEN_bm; | |||
|
|
50 | ||||
|
|
51 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
52 | OSC_XOSCFAIL = (OSC_PLLFDEN_bm)|(OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de | |||
|
|
53 | */ | |||
|
|
54 | ||||
|
|
55 | } No newline at end of file | |||
| @@ -0,0 +1,20 | |||||
|
|
1 | /* | |||
|
|
2 | * sys_clock.h | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:03:16 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef SYS_CLOCK_H_ | |||
|
|
10 | #define SYS_CLOCK_H_ | |||
|
|
11 | ||||
|
|
12 | ||||
|
|
13 | #define F_CPU 32000000UL | |||
|
|
14 | #include <avr/io.h> | |||
|
|
15 | ||||
|
|
16 | void config_sysclock(void); | |||
|
|
17 | ||||
|
|
18 | ||||
|
|
19 | ||||
|
|
20 | #endif /* SYS_CLOCK_H_ */ No newline at end of file | |||
| @@ -0,0 +1,4 | |||||
|
|
1 | En esta primera versi�n los activadores de interrupciones son LOCK y PPS. | |||
|
|
2 | LOCK activa la interrupci�n deprioridad media. | |||
|
|
3 | PPS activa la interrupci�n de prioridad baja. | |||
|
|
4 | ||||
| @@ -0,0 +1,22 | |||||
|
|
1 | | |||
|
|
2 | Microsoft Visual Studio Solution File, Format Version 12.00 | |||
|
|
3 | # Atmel Studio Solution File, Format Version 11.00 | |||
|
|
4 | VisualStudioVersion = 14.0.23107.0 | |||
|
|
5 | MinimumVisualStudioVersion = 10.0.40219.1 | |||
|
|
6 | Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_ver01", "ADCSPI_ver01\ADCSPI_ver01.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" | |||
|
|
7 | EndProject | |||
|
|
8 | Global | |||
|
|
9 | GlobalSection(SolutionConfigurationPlatforms) = preSolution | |||
|
|
10 | Debug|AVR = Debug|AVR | |||
|
|
11 | Release|AVR = Release|AVR | |||
|
|
12 | EndGlobalSection | |||
|
|
13 | GlobalSection(ProjectConfigurationPlatforms) = postSolution | |||
|
|
14 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.ActiveCfg = Debug|AVR | |||
|
|
15 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.Build.0 = Debug|AVR | |||
|
|
16 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.ActiveCfg = Release|AVR | |||
|
|
17 | {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.Build.0 = Release|AVR | |||
|
|
18 | EndGlobalSection | |||
|
|
19 | GlobalSection(SolutionProperties) = preSolution | |||
|
|
20 | HideSolutionNode = FALSE | |||
|
|
21 | EndGlobalSection | |||
|
|
22 | EndGlobal | |||
| @@ -0,0 +1,86 | |||||
|
|
1 | <?xml version="1.0" encoding="utf-8"?> | |||
|
|
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1 | <?xml version="1.0" encoding="utf-8"?> | |||
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121 | <avrgcc.assembler.debugging.DebugLevel>Default (-Wa,-g)</avrgcc.assembler.debugging.DebugLevel> | |||
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122 | </AvrGcc> | |||
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123 | </ToolchainSettings> | |||
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124 | </PropertyGroup> | |||
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125 | <ItemGroup> | |||
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126 | <Compile Include="ADC_7176_2.c"> | |||
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127 | <SubType>compile</SubType> | |||
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128 | </Compile> | |||
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129 | <Compile Include="ADC_7176_2.h"> | |||
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130 | <SubType>compile</SubType> | |||
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131 | </Compile> | |||
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132 | <Compile Include="commSPI_ADC.c"> | |||
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133 | <SubType>compile</SubType> | |||
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134 | </Compile> | |||
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135 | <Compile Include="commSPI_ADC.h"> | |||
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136 | <SubType>compile</SubType> | |||
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137 | </Compile> | |||
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138 | <Compile Include="fpga_port.c"> | |||
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139 | <SubType>compile</SubType> | |||
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140 | </Compile> | |||
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141 | <Compile Include="fpga_port.h"> | |||
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142 | <SubType>compile</SubType> | |||
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143 | </Compile> | |||
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144 | <Compile Include="main.c"> | |||
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145 | <SubType>compile</SubType> | |||
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146 | </Compile> | |||
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147 | <Compile Include="Ports.c"> | |||
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148 | <SubType>compile</SubType> | |||
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149 | </Compile> | |||
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150 | <Compile Include="Ports.h"> | |||
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151 | <SubType>compile</SubType> | |||
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152 | </Compile> | |||
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153 | <Compile Include="sys_clock.c"> | |||
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154 | <SubType>compile</SubType> | |||
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155 | </Compile> | |||
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156 | <Compile Include="sys_clock.h"> | |||
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157 | <SubType>compile</SubType> | |||
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158 | </Compile> | |||
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159 | </ItemGroup> | |||
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|
160 | <Import Project="$(AVRSTUDIO_EXE_PATH)\\Vs\\Compiler.targets" /> | |||
|
|
161 | </Project> No newline at end of file | |||
| @@ -0,0 +1,106 | |||||
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1 | /* | |||
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|
2 | * ADC_7176_2.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:01:02 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
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|
7 | ||||
|
|
8 | /*! | |||
|
|
9 | * \fn test_adc | |||
|
|
10 | * \brief Lectura de ID del adc | |||
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|
11 | * | |||
|
|
12 | * Lectura esperada: 0x0C94 | |||
|
|
13 | * | |||
|
|
14 | * Esta funci�n tiene como fin probar la comunicaci�n on el ADC | |||
|
|
15 | * | |||
|
|
16 | #define ADC_WENbar_bm (1<<7) | |||
|
|
17 | #define ADC_RWbar_bm (1<<6) | |||
|
|
18 | #define ADC_ADDR_READ_ID 0x07 | |||
|
|
19 | * \ | |||
|
|
20 | */ | |||
|
|
21 | ||||
|
|
22 | #define F_CPU 32000000UL | |||
|
|
23 | #include <avr/io.h> | |||
|
|
24 | #include "ADC_7176_2.h" | |||
|
|
25 | ||||
|
|
26 | inline uint16_t test_adc(void){ | |||
|
|
27 | uint16_t aux; | |||
|
|
28 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
|
29 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
|
|
30 | aux = adcport_tranceiv(0); | |||
|
|
31 | aux = (aux << 8) | adcport_tranceiv(0); | |||
|
|
32 | PORTSPI.OUTSET = SPI_SS_bm; | |||
|
|
33 | return aux; | |||
|
|
34 | } | |||
|
|
35 | ||||
|
|
36 | inline void test_adc_2(uint8_t* dato){ | |||
|
|
37 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
|
38 | adcport_read_data(dato,ADC_DATASZ); | |||
|
|
39 | PORTSPI.OUTSET = SPI_SS_bm; | |||
|
|
40 | } | |||
|
|
41 | /*! | |||
|
|
42 | * \fn adcport_tranceiv | |||
|
|
43 | * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y | |||
|
|
44 | * el microcontrolador. | |||
|
|
45 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
|
|
46 | * transmision genera clock en el pin "sclk" | |||
|
|
47 | * \param El dato a transmitir | |||
|
|
48 | * \return El dato leido del ADC | |||
|
|
49 | */ | |||
|
|
50 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
51 | // | |||
|
|
52 | SPIC.DATA = data; | |||
|
|
53 | ||||
|
|
54 | //Wait until transmission complete | |||
|
|
55 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
56 | ||||
|
|
57 | // Return received data | |||
|
|
58 | ||||
|
|
59 | return SPIC.DATA; | |||
|
|
60 | } | |||
|
|
61 | ||||
|
|
62 | /*! | |||
|
|
63 | * \fn adcport_readdata | |||
|
|
64 | * \brief Realiza la lectura de datos en modo de conversi�n continua | |||
|
|
65 | * el microcontrolador. | |||
|
|
66 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
|
|
67 | * transmision genera clock en el pin "sclk" | |||
|
|
68 | * \param La direcci�n del puntero a dato | |||
|
|
69 | * \return Ninguno s�lo se llena el puntero al dato | |||
|
|
70 | */ | |||
|
|
71 | inline void adcport_read_data(uint8_t* dato,int j) | |||
|
|
72 | { | |||
|
|
73 | ||||
|
|
74 | //Env�o del comando de lectura de datos 0x44 | |||
|
|
75 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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76 | ||||
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77 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
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78 | ||||
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79 | // Save received data | |||
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80 | for(int i=0; i<j ; i++) | |||
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81 | dato[i] = adcport_tranceiv(0); //Escribo el bit m�s significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1) | |||
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82 | //Si se desease almacenar el dato de byte menos significativo a m�s signficativo: dato[j-i-1] = adcport_tranceiv(0); | |||
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83 | } | |||
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84 | ||||
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85 | void config_adc(void) | |||
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86 | { | |||
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87 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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88 | adcport_write_filtcon0(); | |||
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89 | //adcport_write_interfmode(); | |||
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90 | PORTSPI.OUTSET = SPI_SS_bm; | |||
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91 | ||||
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92 | } | |||
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93 | ||||
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94 | void adcport_write_filtcon0(void) | |||
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95 | { | |||
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96 | adcport_tranceiv((ADC_FILTCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm)); | |||
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97 | adcport_tranceiv(0); | |||
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98 | adcport_tranceiv((0b00<<ADC_FILT0_ORDER0_bp)|(0b01010<<ADC_FILT0_ODR0_bp)); | |||
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99 | } | |||
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100 | ||||
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101 | void adcport_write_interfmode(void) | |||
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102 | { | |||
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103 | adcport_tranceiv((ADC_INTERFMODE) & (~ADC_WENbar_bm | ~ADC_RWbar_bm)); | |||
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104 | adcport_tranceiv(0); | |||
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105 | adcport_tranceiv((1<<ADC_CONTREAD_bp)|(1<<ADC_WL16_bp)); | |||
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|
106 | } No newline at end of file | |||
| @@ -0,0 +1,45 | |||||
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1 | /* | |||
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2 | * ADC_7176_2.h | |||
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3 | * | |||
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4 | * Created: 23/11/15 13:59:46 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
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7 | ||||
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8 | ||||
|
|
9 | #ifndef ADC_7176_2_H_ | |||
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|
10 | #define ADC_7176_2_H_ | |||
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11 | ||||
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12 | #define F_CPU 32000000UL | |||
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|
13 | #include <avr/io.h> | |||
|
|
14 | #include "Ports.h" | |||
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|
15 | #include "commSPI_ADC.h" | |||
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16 | ||||
|
|
17 | //ID esperada | |||
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18 | //tama�o 16 bits | |||
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19 | //Valor 0x0C94 | |||
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20 | #define ADC_ID 0x0C94 | |||
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21 | #define ADC_RD 0x04 | |||
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|
22 | #define ADC_FILTCON0 0x28 | |||
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23 | #define ADC_INTERFMODE 0x02 | |||
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|
24 | #define ADC_DATASZ 3 | |||
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25 | ||||
|
|
26 | //Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n | |||
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27 | #define ADC_WENbar_bm (1<<7) | |||
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28 | #define ADC_RWbar_bm (1<<6) | |||
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|
29 | #define ADC_ADDR_READ_ID (0x07) | |||
|
|
30 | #define ADC_FILT0_ORDER0_bp 5 | |||
|
|
31 | #define ADC_FILT0_ODR0_bp 0 | |||
|
|
32 | #define ADC_CONTREAD_bp 7 | |||
|
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33 | #define ADC_WL16_bp 0 | |||
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|
34 | ||||
|
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35 | uint8_t adcport_tranceiv(uint8_t data); | |||
|
|
36 | void adcport_read_data(uint8_t* dato,int j); | |||
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|
37 | ||||
|
|
38 | void adcport_write_filtcon0(void); | |||
|
|
39 | void adcport_write_interfmode(void); | |||
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|
40 | ||||
|
|
41 | uint16_t test_adc(void); | |||
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42 | void test_adc_2(uint8_t* dato); | |||
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|
43 | void config_adc(void); | |||
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44 | ||||
|
|
45 | #endif /* ADC_7176_2_H_ */ No newline at end of file | |||
| @@ -0,0 +1,1 | |||||
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1 | :00000001FF | |||
| 1 | NO CONTENT: new file 10644 |
|
NO CONTENT: new file 10644 |
| @@ -0,0 +1,92 | |||||
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1 | :100000000C94B6000C94C0000C941A020C94C0001E | |||
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2 | :100010000C94C0000C94C0000C94C0000C94C00060 | |||
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3 | :100020000C94C0000C94C0000C94C0000C94C00050 | |||
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4 | :100030000C94C0000C94C0000C94C0000C94C00040 | |||
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5 | :100040000C94C0000C94C0000C94C0000C94C00030 | |||
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6 | :100050000C94C0000C94C0000C94C0000C94C00020 | |||
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7 | :100060000C94C0000C94C0000C94C0000C94C00010 | |||
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8 | :100070000C94C0000C94C0000C94C0000C94C00000 | |||
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9 | :100080000C94C0000C94C0000C94C0000C940202AC | |||
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10 | :100090000C94C0000C94C0000C94C0000C94C000E0 | |||
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11 | :1000A0000C94C0000C94C0000C94C0000C94C000D0 | |||
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12 | :1000B0000C94C0000C94C0000C94C0000C94C000C0 | |||
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13 | :1000C0000C94C0000C94C0000C94C0000C94C000B0 | |||
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14 | :1000D0000C94C0000C94C0000C94C0000C94C000A0 | |||
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15 | :1000E0000C94C0000C94C0000C94C0000C94C00090 | |||
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16 | :1000F0000C94C0000C94C0000C94C0000C94C00080 | |||
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17 | :100100000C94D7010C94C0000C94C0000C94C00057 | |||
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18 | :100110000C94C0000C94C0000C94C0000C94C0005F | |||
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19 | :100120000C94C0000C94C0000C94C0000C94C0004F | |||
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20 | :100130000C94C0000C94C0000C94C0000C94C0003F | |||
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21 | :100140000C94C0000C94C0000C94C0000C94C0002F | |||
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22 | :100150000C94C0000C94C0000C94C0000C94C0001F | |||
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23 | :100160000C94C0000C94C0000C94C00011241FBE5D | |||
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24 | :10017000CFEFCDBFDFE2DEBF0E94BD010C94D30202 | |||
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25 | :100180000C94000080E18093460687E48093C308C6 | |||
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26 | :10019000E0ECF8E082818823ECF7E0ECF8E0838182 | |||
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27 | :1001A000138282818823ECF7E0ECF8E0238130E0D1 | |||
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28 | :1001B000322F2227138292819923ECF78091C30872 | |||
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29 | :1001C00090E190934506A901482BCA0108959C012E | |||
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30 | :1001D00084E48093C308E0ECF8E092819923ECF783 | |||
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31 | :1001E0008091C3081616170674F4D901A60FB71F1D | |||
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32 | :1001F000E0ECF8E0138292819923ECF793819E93CF | |||
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33 | :10020000A217B307B9F7089588E28093C308E0EC1A | |||
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34 | :10021000F8E082818823ECF7E0ECF8E08381138238 | |||
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35 | :1002200082818823ECF7E0ECF8E083818AE0838325 | |||
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36 | :1002300082818823ECF78091C30808951F93CF93A0 | |||
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37 | :10024000DF93C0E4D6E010E11E830E9404011D8309 | |||
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38 | :10025000DF91CF911F9108958CED8093C008089590 | |||
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39 | :10026000CF93DF93E0E6F6E022E02283118A94E068 | |||
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40 | :10027000918388E1828B958388E78183138A8683C3 | |||
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41 | :10028000A0E2B6E012969C93129780E152968C936E | |||
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42 | :100290005297C0E0D6E081E089838E8381858360B8 | |||
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43 | :1002A000818722878189887F818B8185837F886090 | |||
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44 | :1002B00019968C9319971B969C931B9752968C9129 | |||
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45 | :1002C0005297887F816052968C93DF91CF910895E9 | |||
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46 | :1002D00078940895E0E6F6E024E026839481382FB0 | |||
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47 | :1002E000307F330F330F330F9873932B9483258311 | |||
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48 | :1002F000268394818F70880F880F880F9873892BBD | |||
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49 | :100300008483258308950F931F93CF93DF93EC018C | |||
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50 | :100310008C010D5F1F4F89910E946A01C017D107A0 | |||
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51 | :10032000D1F7DF91CF911F910F910895CF93DF9374 | |||
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52 | :10033000CDB7DEB72697CDBFDEBF63E070E0CE015C | |||
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53 | :1003400001960E94E70089818C838A818D838B814D | |||
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54 | :100350008E8363E070E0CE0101960E94E700CE013B | |||
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55 | :1003600004960E948301CE0101960E948301269685 | |||
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56 | :10037000CDBFDEBFDF91CF9108950E943E020E9463 | |||
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57 | :10038000B4020E942C010E9430010E941E0184E0F0 | |||
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58 | :100390008093A2000E94680100E616E0C0E60E9479 | |||
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59 | :1003A000C20084399C40D9F7F801C583F8CF1F9269 | |||
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60 | :1003B0000F920FB60F9211248F93EF93FF938091BA | |||
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61 | :1003C000680681FF0CC0E0EAF0E0828182608283EF | |||
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62 | :1003D00081E08093050680E1809365060BC0E0EA2A | |||
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63 | :1003E000F0E082818D7F828382818E7F828381E0B3 | |||
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64 | :1003F00080930606FF91EF918F910F900FBE0F90A3 | |||
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65 | :100400001F9018951F920F920FB60F9211248F9381 | |||
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66 | :10041000EF93FF93E0EAF0E082818160828380E1E4 | |||
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67 | :1004200080934606FF91EF918F910F900FBE0F9032 | |||
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68 | :100430001F9018951F920F920FB60F9211242F93B1 | |||
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69 | :100440003F934F935F936F937F938F939F93AF935C | |||
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70 | :10045000BF93EF93FF930E949601FF91EF91BF919D | |||
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71 | :10046000AF919F918F917F916F915F914F913F914C | |||
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72 | :100470002F910F900FBE0F901F901895E0E0F6E0BF | |||
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73 | :100480008EEF828388E1878B868B858B848B838B31 | |||
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74 | :10049000828B818B21E0218398E3908B2683E0E29D | |||
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|
75 | :1004A000F6E03FE03283838B828B818B808BE0E4AC | |||
|
|
76 | :1004B000F6E02FE42283868B838B828B818B808B6B | |||
|
|
77 | :1004C00020EB2183158A178A148A20E9258320E2EC | |||
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|
78 | :1004D0002683A0E6B6E027E812962C93129757964B | |||
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79 | :1004E0008C93579750968C93509720E152962C936B | |||
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80 | :1004F000529751962C93519748E711964C93119728 | |||
|
|
81 | :1005000056969C93569755969C93559754969C93C4 | |||
|
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82 | :10051000549753969C93539716964C93A0E8B6E045 | |||
|
|
83 | :1005200012963C93129753968C93539752968C93B2 | |||
|
|
84 | :10053000529751968C93519750968C93A0EEB7E0BA | |||
|
|
85 | :1005400093E012969C93129751962C935197509644 | |||
|
|
86 | :100550008C9380E4828781858C7F81608187868906 | |||
|
|
87 | :10056000887F8260868B089510924100E0E5F0E07C | |||
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|
88 | :10057000808186608083818182FFFDCFE0E5F0E0AD | |||
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89 | :10058000818181FFFDCF91E090936000E0E5F0E094 | |||
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90 | :1005900086818D7F868388ED84BF90934000808123 | |||
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91 | :0A05A0008E7F80830895F894FFCF4A | |||
|
|
92 | :00000001FF | |||
| This diff has been collapsed as it changes many lines, (1099 lines changed) Show them Hide them | |||||
| @@ -0,0 +1,1099 | |||||
|
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1 | ||||
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2 | ADCSPI_ver01.elf: file format elf32-avr | |||
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3 | ||||
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4 | Sections: | |||
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5 | Idx Name Size VMA LMA File off Algn | |||
|
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6 | 0 .text 000005aa 00000000 00000000 00000054 2**1 | |||
|
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7 | CONTENTS, ALLOC, LOAD, READONLY, CODE | |||
|
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8 | 1 .data 00000000 00802000 00802000 000005fe 2**0 | |||
|
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9 | CONTENTS, ALLOC, LOAD, DATA | |||
|
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10 | 2 .comment 00000030 00000000 00000000 000005fe 2**0 | |||
|
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11 | CONTENTS, READONLY | |||
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12 | 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 00000630 2**2 | |||
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13 | CONTENTS, READONLY | |||
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14 | 4 .debug_aranges 00000138 00000000 00000000 00000670 2**0 | |||
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15 | CONTENTS, READONLY, DEBUGGING | |||
|
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16 | 5 .debug_info 000014ca 00000000 00000000 000007a8 2**0 | |||
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17 | CONTENTS, READONLY, DEBUGGING | |||
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18 | 6 .debug_abbrev 0000064f 00000000 00000000 00001c72 2**0 | |||
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19 | CONTENTS, READONLY, DEBUGGING | |||
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20 | 7 .debug_line 0000082c 00000000 00000000 000022c1 2**0 | |||
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21 | CONTENTS, READONLY, DEBUGGING | |||
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22 | 8 .debug_frame 00000288 00000000 00000000 00002af0 2**2 | |||
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23 | CONTENTS, READONLY, DEBUGGING | |||
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24 | 9 .debug_str 000007d6 00000000 00000000 00002d78 2**0 | |||
|
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25 | CONTENTS, READONLY, DEBUGGING | |||
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26 | 10 .debug_loc 0000042d 00000000 00000000 0000354e 2**0 | |||
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27 | CONTENTS, READONLY, DEBUGGING | |||
|
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28 | 11 .debug_ranges 000000d8 00000000 00000000 0000397b 2**0 | |||
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29 | CONTENTS, READONLY, DEBUGGING | |||
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30 | ||||
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|
31 | Disassembly of section .text: | |||
|
|
32 | ||||
|
|
33 | 00000000 <__vectors>: | |||
|
|
34 | 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end> | |||
|
|
35 | 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
36 | 8: 0c 94 1a 02 jmp 0x434 ; 0x434 <__vector_2> | |||
|
|
37 | c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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38 | 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
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39 | 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
40 | 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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41 | 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
42 | 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
43 | 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
44 | 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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45 | 2c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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46 | 30: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
47 | 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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48 | 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
49 | 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
50 | 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
51 | 44: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
52 | 48: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
53 | 4c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
54 | 50: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
55 | 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
56 | 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
57 | 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
58 | 60: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
59 | 64: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
60 | 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
61 | 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
62 | 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
63 | 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
64 | 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
65 | 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
66 | 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
67 | 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
68 | 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
69 | 8c: 0c 94 02 02 jmp 0x404 ; 0x404 <__vector_35> | |||
|
|
70 | 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
71 | 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
72 | 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
73 | 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
74 | a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
75 | a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
76 | a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
77 | ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
78 | b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
79 | b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
80 | b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
81 | bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
82 | c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
83 | c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
84 | c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
85 | cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
86 | d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
87 | d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
88 | d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
89 | dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
90 | e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
91 | e4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
92 | e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
|
|
93 | ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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|
94 | f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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95 | f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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96 | f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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97 | fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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98 | 100: 0c 94 d7 01 jmp 0x3ae ; 0x3ae <__vector_64> | |||
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99 | 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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100 | 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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101 | 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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102 | 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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103 | 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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104 | 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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105 | 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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106 | 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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107 | 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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108 | 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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109 | 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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110 | 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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111 | 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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112 | 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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113 | 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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114 | 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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115 | 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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116 | 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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117 | 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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118 | 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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119 | 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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120 | 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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121 | 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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122 | 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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123 | 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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124 | 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> | |||
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125 | ||||
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126 | 0000016c <__ctors_end>: | |||
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127 | 16c: 11 24 eor r1, r1 | |||
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128 | 16e: 1f be out 0x3f, r1 ; 63 | |||
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129 | 170: cf ef ldi r28, 0xFF ; 255 | |||
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130 | 172: cd bf out 0x3d, r28 ; 61 | |||
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131 | 174: df e2 ldi r29, 0x2F ; 47 | |||
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132 | 176: de bf out 0x3e, r29 ; 62 | |||
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133 | 178: 0e 94 bd 01 call 0x37a ; 0x37a <main> | |||
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134 | 17c: 0c 94 d3 02 jmp 0x5a6 ; 0x5a6 <_exit> | |||
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135 | ||||
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136 | 00000180 <__bad_interrupt>: | |||
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137 | 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> | |||
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138 | ||||
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139 | 00000184 <test_adc>: | |||
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140 | #include <avr/io.h> | |||
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141 | #include "ADC_7176_2.h" | |||
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142 | ||||
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143 | inline uint16_t test_adc(void){ | |||
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144 | uint16_t aux; | |||
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145 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
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146 | 184: 80 e1 ldi r24, 0x10 ; 16 | |||
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147 | 186: 80 93 46 06 sts 0x0646, r24 | |||
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148 | * \param El dato a transmitir | |||
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149 | * \return El dato leido del ADC | |||
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150 | */ | |||
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151 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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152 | // | |||
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153 | SPIC.DATA = data; | |||
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154 | 18a: 87 e4 ldi r24, 0x47 ; 71 | |||
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155 | 18c: 80 93 c3 08 sts 0x08C3, r24 | |||
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156 | ||||
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157 | //Wait until transmission complete | |||
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158 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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159 | 190: e0 ec ldi r30, 0xC0 ; 192 | |||
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160 | 192: f8 e0 ldi r31, 0x08 ; 8 | |||
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161 | 194: 82 81 ldd r24, Z+2 ; 0x02 | |||
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162 | 196: 88 23 and r24, r24 | |||
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163 | 198: ec f7 brge .-6 ; 0x194 <test_adc+0x10> | |||
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164 | ||||
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165 | // Return received data | |||
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166 | ||||
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167 | return SPIC.DATA; | |||
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168 | 19a: e0 ec ldi r30, 0xC0 ; 192 | |||
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169 | 19c: f8 e0 ldi r31, 0x08 ; 8 | |||
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170 | 19e: 83 81 ldd r24, Z+3 ; 0x03 | |||
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171 | * \param El dato a transmitir | |||
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172 | * \return El dato leido del ADC | |||
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173 | */ | |||
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174 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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175 | // | |||
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176 | SPIC.DATA = data; | |||
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177 | 1a0: 13 82 std Z+3, r1 ; 0x03 | |||
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178 | ||||
|
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179 | //Wait until transmission complete | |||
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180 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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181 | 1a2: 82 81 ldd r24, Z+2 ; 0x02 | |||
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182 | 1a4: 88 23 and r24, r24 | |||
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183 | 1a6: ec f7 brge .-6 ; 0x1a2 <test_adc+0x1e> | |||
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184 | ||||
|
|
185 | // Return received data | |||
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186 | ||||
|
|
187 | return SPIC.DATA; | |||
|
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188 | 1a8: e0 ec ldi r30, 0xC0 ; 192 | |||
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189 | 1aa: f8 e0 ldi r31, 0x08 ; 8 | |||
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190 | 1ac: 23 81 ldd r18, Z+3 ; 0x03 | |||
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191 | ||||
|
|
192 | inline uint16_t test_adc(void){ | |||
|
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193 | uint16_t aux; | |||
|
|
194 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
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195 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
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196 | aux = adcport_tranceiv(0); | |||
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197 | 1ae: 30 e0 ldi r19, 0x00 ; 0 | |||
|
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198 | aux = (aux << 8) | adcport_tranceiv(0); | |||
|
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199 | 1b0: 32 2f mov r19, r18 | |||
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200 | 1b2: 22 27 eor r18, r18 | |||
|
|
201 | * \param El dato a transmitir | |||
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|
202 | * \return El dato leido del ADC | |||
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|
203 | */ | |||
|
|
204 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
205 | // | |||
|
|
206 | SPIC.DATA = data; | |||
|
|
207 | 1b4: 13 82 std Z+3, r1 ; 0x03 | |||
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208 | ||||
|
|
209 | //Wait until transmission complete | |||
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|
210 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
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|
211 | 1b6: 92 81 ldd r25, Z+2 ; 0x02 | |||
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212 | 1b8: 99 23 and r25, r25 | |||
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213 | 1ba: ec f7 brge .-6 ; 0x1b6 <test_adc+0x32> | |||
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214 | ||||
|
|
215 | // Return received data | |||
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216 | ||||
|
|
217 | return SPIC.DATA; | |||
|
|
218 | 1bc: 80 91 c3 08 lds r24, 0x08C3 | |||
|
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219 | uint16_t aux; | |||
|
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220 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
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221 | adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
|
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222 | aux = adcport_tranceiv(0); | |||
|
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223 | aux = (aux << 8) | adcport_tranceiv(0); | |||
|
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224 | PORTSPI.OUTSET = SPI_SS_bm; | |||
|
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225 | 1c0: 90 e1 ldi r25, 0x10 ; 16 | |||
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226 | 1c2: 90 93 45 06 sts 0x0645, r25 | |||
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227 | return aux; | |||
|
|
228 | } | |||
|
|
229 | 1c6: a9 01 movw r20, r18 | |||
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230 | 1c8: 48 2b or r20, r24 | |||
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231 | 1ca: ca 01 movw r24, r20 | |||
|
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232 | 1cc: 08 95 ret | |||
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|
233 | ||||
|
|
234 | 000001ce <adcport_read_data>: | |||
|
|
235 | * transmision genera clock en el pin "sclk" | |||
|
|
236 | * \param La direcci�n del puntero a dato | |||
|
|
237 | * \return Ninguno s�lo se llena el puntero al dato | |||
|
|
238 | */ | |||
|
|
239 | inline void adcport_read_data(uint8_t* dato,int j) | |||
|
|
240 | { | |||
|
|
241 | 1ce: 9c 01 movw r18, r24 | |||
|
|
242 | * \param El dato a transmitir | |||
|
|
243 | * \return El dato leido del ADC | |||
|
|
244 | */ | |||
|
|
245 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
246 | // | |||
|
|
247 | SPIC.DATA = data; | |||
|
|
248 | 1d0: 84 e4 ldi r24, 0x44 ; 68 | |||
|
|
249 | 1d2: 80 93 c3 08 sts 0x08C3, r24 | |||
|
|
250 | ||||
|
|
251 | //Wait until transmission complete | |||
|
|
252 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
253 | 1d6: e0 ec ldi r30, 0xC0 ; 192 | |||
|
|
254 | 1d8: f8 e0 ldi r31, 0x08 ; 8 | |||
|
|
255 | 1da: 92 81 ldd r25, Z+2 ; 0x02 | |||
|
|
256 | 1dc: 99 23 and r25, r25 | |||
|
|
257 | 1de: ec f7 brge .-6 ; 0x1da <adcport_read_data+0xc> | |||
|
|
258 | ||||
|
|
259 | // Return received data | |||
|
|
260 | ||||
|
|
261 | return SPIC.DATA; | |||
|
|
262 | 1e0: 80 91 c3 08 lds r24, 0x08C3 | |||
|
|
263 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
|
|
264 | ||||
|
|
265 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
|
|
266 | ||||
|
|
267 | // Save received data | |||
|
|
268 | for(int i=0; i<j ; i++) | |||
|
|
269 | 1e4: 16 16 cp r1, r22 | |||
|
|
270 | 1e6: 17 06 cpc r1, r23 | |||
|
|
271 | 1e8: 74 f4 brge .+28 ; 0x206 <adcport_read_data+0x38> | |||
|
|
272 | 1ea: d9 01 movw r26, r18 | |||
|
|
273 | 1ec: a6 0f add r26, r22 | |||
|
|
274 | 1ee: b7 1f adc r27, r23 | |||
|
|
275 | * \param El dato a transmitir | |||
|
|
276 | * \return El dato leido del ADC | |||
|
|
277 | */ | |||
|
|
278 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
279 | // | |||
|
|
280 | SPIC.DATA = data; | |||
|
|
281 | 1f0: e0 ec ldi r30, 0xC0 ; 192 | |||
|
|
282 | 1f2: f8 e0 ldi r31, 0x08 ; 8 | |||
|
|
283 | 1f4: 13 82 std Z+3, r1 ; 0x03 | |||
|
|
284 | ||||
|
|
285 | //Wait until transmission complete | |||
|
|
286 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
287 | 1f6: 92 81 ldd r25, Z+2 ; 0x02 | |||
|
|
288 | 1f8: 99 23 and r25, r25 | |||
|
|
289 | 1fa: ec f7 brge .-6 ; 0x1f6 <adcport_read_data+0x28> | |||
|
|
290 | ||||
|
|
291 | // Return received data | |||
|
|
292 | ||||
|
|
293 | return SPIC.DATA; | |||
|
|
294 | 1fc: 93 81 ldd r25, Z+3 ; 0x03 | |||
|
|
295 | ||||
|
|
296 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
|
|
297 | ||||
|
|
298 | // Save received data | |||
|
|
299 | for(int i=0; i<j ; i++) | |||
|
|
300 | dato[j-i-1] = adcport_tranceiv(0); | |||
|
|
301 | 1fe: 9e 93 st -X, r25 | |||
|
|
302 | adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); | |||
|
|
303 | ||||
|
|
304 | //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) | |||
|
|
305 | ||||
|
|
306 | // Save received data | |||
|
|
307 | for(int i=0; i<j ; i++) | |||
|
|
308 | 200: a2 17 cp r26, r18 | |||
|
|
309 | 202: b3 07 cpc r27, r19 | |||
|
|
310 | 204: b9 f7 brne .-18 ; 0x1f4 <adcport_read_data+0x26> | |||
|
|
311 | 206: 08 95 ret | |||
|
|
312 | ||||
|
|
313 | 00000208 <adcport_write_filtcon0>: | |||
|
|
314 | * \param El dato a transmitir | |||
|
|
315 | * \return El dato leido del ADC | |||
|
|
316 | */ | |||
|
|
317 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
318 | // | |||
|
|
319 | SPIC.DATA = data; | |||
|
|
320 | 208: 88 e2 ldi r24, 0x28 ; 40 | |||
|
|
321 | 20a: 80 93 c3 08 sts 0x08C3, r24 | |||
|
|
322 | ||||
|
|
323 | //Wait until transmission complete | |||
|
|
324 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
325 | 20e: e0 ec ldi r30, 0xC0 ; 192 | |||
|
|
326 | 210: f8 e0 ldi r31, 0x08 ; 8 | |||
|
|
327 | 212: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
328 | 214: 88 23 and r24, r24 | |||
|
|
329 | 216: ec f7 brge .-6 ; 0x212 <adcport_write_filtcon0+0xa> | |||
|
|
330 | ||||
|
|
331 | // Return received data | |||
|
|
332 | ||||
|
|
333 | return SPIC.DATA; | |||
|
|
334 | 218: e0 ec ldi r30, 0xC0 ; 192 | |||
|
|
335 | 21a: f8 e0 ldi r31, 0x08 ; 8 | |||
|
|
336 | 21c: 83 81 ldd r24, Z+3 ; 0x03 | |||
|
|
337 | * \param El dato a transmitir | |||
|
|
338 | * \return El dato leido del ADC | |||
|
|
339 | */ | |||
|
|
340 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
341 | // | |||
|
|
342 | SPIC.DATA = data; | |||
|
|
343 | 21e: 13 82 std Z+3, r1 ; 0x03 | |||
|
|
344 | ||||
|
|
345 | //Wait until transmission complete | |||
|
|
346 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
347 | 220: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
348 | 222: 88 23 and r24, r24 | |||
|
|
349 | 224: ec f7 brge .-6 ; 0x220 <adcport_write_filtcon0+0x18> | |||
|
|
350 | ||||
|
|
351 | // Return received data | |||
|
|
352 | ||||
|
|
353 | return SPIC.DATA; | |||
|
|
354 | 226: e0 ec ldi r30, 0xC0 ; 192 | |||
|
|
355 | 228: f8 e0 ldi r31, 0x08 ; 8 | |||
|
|
356 | 22a: 83 81 ldd r24, Z+3 ; 0x03 | |||
|
|
357 | * \param El dato a transmitir | |||
|
|
358 | * \return El dato leido del ADC | |||
|
|
359 | */ | |||
|
|
360 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
|
|
361 | // | |||
|
|
362 | SPIC.DATA = data; | |||
|
|
363 | 22c: 8a e0 ldi r24, 0x0A ; 10 | |||
|
|
364 | 22e: 83 83 std Z+3, r24 ; 0x03 | |||
|
|
365 | ||||
|
|
366 | //Wait until transmission complete | |||
|
|
367 | while( !(SPIC.STATUS & SPI_IF_bm)); | |||
|
|
368 | 230: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
369 | 232: 88 23 and r24, r24 | |||
|
|
370 | 234: ec f7 brge .-6 ; 0x230 <adcport_write_filtcon0+0x28> | |||
|
|
371 | ||||
|
|
372 | // Return received data | |||
|
|
373 | ||||
|
|
374 | return SPIC.DATA; | |||
|
|
375 | 236: 80 91 c3 08 lds r24, 0x08C3 | |||
|
|
376 | 23a: 08 95 ret | |||
|
|
377 | ||||
|
|
378 | 0000023c <config_adc>: | |||
|
|
379 | for(int i=0; i<j ; i++) | |||
|
|
380 | dato[j-i-1] = adcport_tranceiv(0); | |||
|
|
381 | } | |||
|
|
382 | ||||
|
|
383 | void config_adc(void) | |||
|
|
384 | { | |||
|
|
385 | 23c: 1f 93 push r17 | |||
|
|
386 | 23e: cf 93 push r28 | |||
|
|
387 | 240: df 93 push r29 | |||
|
|
388 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
|
389 | 242: c0 e4 ldi r28, 0x40 ; 64 | |||
|
|
390 | 244: d6 e0 ldi r29, 0x06 ; 6 | |||
|
|
391 | 246: 10 e1 ldi r17, 0x10 ; 16 | |||
|
|
392 | 248: 1e 83 std Y+6, r17 ; 0x06 | |||
|
|
393 | adcport_write_filtcon0(); | |||
|
|
394 | 24a: 0e 94 04 01 call 0x208 ; 0x208 <adcport_write_filtcon0> | |||
|
|
395 | //adcport_write_interfmode(); | |||
|
|
396 | PORTSPI.OUTSET = SPI_SS_bm; | |||
|
|
397 | 24e: 1d 83 std Y+5, r17 ; 0x05 | |||
|
|
398 | ||||
|
|
399 | } | |||
|
|
400 | 250: df 91 pop r29 | |||
|
|
401 | 252: cf 91 pop r28 | |||
|
|
402 | 254: 1f 91 pop r17 | |||
|
|
403 | 256: 08 95 ret | |||
|
|
404 | ||||
|
|
405 | 00000258 <config_spiparm>: | |||
|
|
406 | inline void config_spiparm(void){ | |||
|
|
407 | // Preescaler: clkper/2 = f_cpu/2. | |||
|
|
408 | // Master | |||
|
|
409 | // Mode 3: CPOL=1,CPHA=1 | |||
|
|
410 | // MSB --- LSB | |||
|
|
411 | SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | | |||
|
|
412 | 258: 8c ed ldi r24, 0xDC ; 220 | |||
|
|
413 | 25a: 80 93 c0 08 sts 0x08C0, r24 | |||
|
|
414 | 25e: 08 95 ret | |||
|
|
415 | ||||
|
|
416 | 00000260 <config_fpgaport>: | |||
|
|
417 | #include <avr/io.h> | |||
|
|
418 | ||||
|
|
419 | #include "fpga_port.h" | |||
|
|
420 | ||||
|
|
421 | inline void config_fpgaport() | |||
|
|
422 | { | |||
|
|
423 | 260: cf 93 push r28 | |||
|
|
424 | 262: df 93 push r29 | |||
|
|
425 | //Configuracion pines del puerto D: PD6-PA1 | |||
|
|
426 | //Pines de entrada CLK_FPGA, LOCK_FPGA | |||
|
|
427 | //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
|
|
428 | PORT_FPGA.DIRCLR = LOCK_FPGA; | |||
|
|
429 | 264: e0 e6 ldi r30, 0x60 ; 96 | |||
|
|
430 | 266: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
431 | 268: 22 e0 ldi r18, 0x02 ; 2 | |||
|
|
432 | 26a: 22 83 std Z+2, r18 ; 0x02 | |||
|
|
433 | PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; | |||
|
|
434 | 26c: 11 8a std Z+17, r1 ; 0x11 | |||
|
|
435 | PORT_FPGA.DIRSET = CLK_FPGA; | |||
|
|
436 | 26e: 94 e0 ldi r25, 0x04 ; 4 | |||
|
|
437 | 270: 91 83 std Z+1, r25 ; 0x01 | |||
|
|
438 | PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
439 | 272: 88 e1 ldi r24, 0x18 ; 24 | |||
|
|
440 | 274: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
441 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
442 | 276: 95 83 std Z+5, r25 ; 0x05 | |||
|
|
443 | ||||
|
|
444 | //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
|
|
445 | PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
|
|
446 | 278: 88 e7 ldi r24, 0x78 ; 120 | |||
|
|
447 | 27a: 81 83 std Z+1, r24 ; 0x01 | |||
|
|
448 | PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; | |||
|
|
449 | 27c: 13 8a std Z+19, r1 ; 0x13 | |||
|
|
450 | PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
|
|
451 | 27e: 86 83 std Z+6, r24 ; 0x06 | |||
|
|
452 | ||||
|
|
453 | //Configuracion pines del puerto B: PPS | |||
|
|
454 | //Pines de entrada PPS_FPGA | |||
|
|
455 | //Pines de entrada en pulldown | |||
|
|
456 | PORT_PPS.DIRCLR = PPS_FPGA; | |||
|
|
457 | 280: a0 e2 ldi r26, 0x20 ; 32 | |||
|
|
458 | 282: b6 e0 ldi r27, 0x06 ; 6 | |||
|
|
459 | 284: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
460 | 286: 9c 93 st X, r25 | |||
|
|
461 | 288: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
462 | PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
463 | 28a: 80 e1 ldi r24, 0x10 ; 16 | |||
|
|
464 | 28c: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
465 | 28e: 8c 93 st X, r24 | |||
|
|
466 | 290: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
467 | ||||
|
|
468 | //Configuracion pines del puerto A: LOCKOUT | |||
|
|
469 | //Pines de salida LOCK_OUT | |||
|
|
470 | //Pines de salida en baja | |||
|
|
471 | PORT_LOCKOUT.DIRSET = LOCK_OUT; | |||
|
|
472 | 292: c0 e0 ldi r28, 0x00 ; 0 | |||
|
|
473 | 294: d6 e0 ldi r29, 0x06 ; 6 | |||
|
|
474 | 296: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
475 | 298: 89 83 std Y+1, r24 ; 0x01 | |||
|
|
476 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
477 | 29a: 8e 83 std Y+6, r24 ; 0x06 | |||
|
|
478 | ||||
|
|
479 | ||||
|
|
480 | ||||
|
|
481 | //Configuracion de interrupciones de LOCK_FPGA | |||
|
|
482 | ||||
|
|
483 | PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; | |||
|
|
484 | 29c: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
485 | 29e: 83 60 ori r24, 0x03 ; 3 | |||
|
|
486 | 2a0: 81 87 std Z+9, r24 ; 0x09 | |||
|
|
487 | PORT_FPGA.INT0MASK = LOCK_FPGA; | |||
|
|
488 | 2a2: 22 87 std Z+10, r18 ; 0x0a | |||
|
|
489 | PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; | |||
|
|
490 | 2a4: 81 89 ldd r24, Z+17 ; 0x11 | |||
|
|
491 | 2a6: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
492 | 2a8: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
493 | //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
494 | //PORT_FPGA.INT1MASK = CLK_FPGA; | |||
|
|
495 | //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
496 | ||||
|
|
497 | //Configuracion de interrupciones de PPS | |||
|
|
498 | PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
|
|
499 | 2aa: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
500 | 2ac: 83 7f andi r24, 0xF3 ; 243 | |||
|
|
501 | 2ae: 88 60 ori r24, 0x08 ; 8 | |||
|
|
502 | 2b0: 19 96 adiw r26, 0x09 ; 9 | |||
|
|
503 | 2b2: 8c 93 st X, r24 | |||
|
|
504 | 2b4: 19 97 sbiw r26, 0x09 ; 9 | |||
|
|
505 | PORT_PPS.INT1MASK = PPS_FPGA; | |||
|
|
506 | 2b6: 1b 96 adiw r26, 0x0b ; 11 | |||
|
|
507 | 2b8: 9c 93 st X, r25 | |||
|
|
508 | 2ba: 1b 97 sbiw r26, 0x0b ; 11 | |||
|
|
509 | PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; | |||
|
|
510 | 2bc: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
511 | 2be: 8c 91 ld r24, X | |||
|
|
512 | 2c0: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
513 | 2c2: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
514 | 2c4: 81 60 ori r24, 0x01 ; 1 | |||
|
|
515 | 2c6: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
516 | 2c8: 8c 93 st X, r24 | |||
|
|
517 | } | |||
|
|
518 | 2ca: df 91 pop r29 | |||
|
|
519 | 2cc: cf 91 pop r28 | |||
|
|
520 | 2ce: 08 95 ret | |||
|
|
521 | ||||
|
|
522 | 000002d0 <habilitar_interrupciones_globales>: | |||
|
|
523 | PMIC.CTRL |= level_mask; | |||
|
|
524 | } | |||
|
|
525 | ||||
|
|
526 | void habilitar_interrupciones_globales( void ) | |||
|
|
527 | { | |||
|
|
528 | sei(); | |||
|
|
529 | 2d0: 78 94 sei | |||
|
|
530 | 2d2: 08 95 ret | |||
|
|
531 | ||||
|
|
532 | 000002d4 <envio_nibble>: | |||
|
|
533 | cli(); | |||
|
|
534 | } | |||
|
|
535 | ||||
|
|
536 | void envio_nibble(uint8_t fpga_dato) | |||
|
|
537 | { | |||
|
|
538 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
539 | 2d4: e0 e6 ldi r30, 0x60 ; 96 | |||
|
|
540 | 2d6: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
541 | 2d8: 24 e0 ldi r18, 0x04 ; 4 | |||
|
|
542 | 2da: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
543 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); | |||
|
|
544 | 2dc: 94 81 ldd r25, Z+4 ; 0x04 | |||
|
|
545 | 2de: 38 2f mov r19, r24 | |||
|
|
546 | 2e0: 30 7f andi r19, 0xF0 ; 240 | |||
|
|
547 | 2e2: 33 0f add r19, r19 | |||
|
|
548 | 2e4: 33 0f add r19, r19 | |||
|
|
549 | 2e6: 33 0f add r19, r19 | |||
|
|
550 | 2e8: 98 73 andi r25, 0x38 ; 56 | |||
|
|
551 | 2ea: 93 2b or r25, r19 | |||
|
|
552 | 2ec: 94 83 std Z+4, r25 ; 0x04 | |||
|
|
553 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
554 | 2ee: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
555 | //asm("nop"); | |||
|
|
556 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
|
|
557 | 2f0: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
558 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); | |||
|
|
559 | 2f2: 94 81 ldd r25, Z+4 ; 0x04 | |||
|
|
560 | 2f4: 8f 70 andi r24, 0x0F ; 15 | |||
|
|
561 | 2f6: 88 0f add r24, r24 | |||
|
|
562 | 2f8: 88 0f add r24, r24 | |||
|
|
563 | 2fa: 88 0f add r24, r24 | |||
|
|
564 | 2fc: 98 73 andi r25, 0x38 ; 56 | |||
|
|
565 | 2fe: 89 2b or r24, r25 | |||
|
|
566 | 300: 84 83 std Z+4, r24 ; 0x04 | |||
|
|
567 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
568 | 302: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
569 | 304: 08 95 ret | |||
|
|
570 | ||||
|
|
571 | 00000306 <envio_dato_adc>: | |||
|
|
572 | envio_dato_adc(aux_dato); | |||
|
|
573 | envio_dato_adc(fpga_dato); | |||
|
|
574 | } | |||
|
|
575 | ||||
|
|
576 | void envio_dato_adc(uint8_t* dato_adc) | |||
|
|
577 | { | |||
|
|
578 | 306: 0f 93 push r16 | |||
|
|
579 | 308: 1f 93 push r17 | |||
|
|
580 | 30a: cf 93 push r28 | |||
|
|
581 | 30c: df 93 push r29 | |||
|
|
582 | 30e: ec 01 movw r28, r24 | |||
|
|
583 | 310: 8c 01 movw r16, r24 | |||
|
|
584 | 312: 0d 5f subi r16, 0xFD ; 253 | |||
|
|
585 | 314: 1f 4f sbci r17, 0xFF ; 255 | |||
|
|
586 | for(int i=0; i<3 ; i++) | |||
|
|
587 | envio_nibble(dato_adc[i]); | |||
|
|
588 | 316: 89 91 ld r24, Y+ | |||
|
|
589 | 318: 0e 94 6a 01 call 0x2d4 ; 0x2d4 <envio_nibble> | |||
|
|
590 | envio_dato_adc(fpga_dato); | |||
|
|
591 | } | |||
|
|
592 | ||||
|
|
593 | void envio_dato_adc(uint8_t* dato_adc) | |||
|
|
594 | { | |||
|
|
595 | for(int i=0; i<3 ; i++) | |||
|
|
596 | 31c: c0 17 cp r28, r16 | |||
|
|
597 | 31e: d1 07 cpc r29, r17 | |||
|
|
598 | 320: d1 f7 brne .-12 ; 0x316 <envio_dato_adc+0x10> | |||
|
|
599 | envio_nibble(dato_adc[i]); | |||
|
|
600 | } | |||
|
|
601 | 322: df 91 pop r29 | |||
|
|
602 | 324: cf 91 pop r28 | |||
|
|
603 | 326: 1f 91 pop r17 | |||
|
|
604 | 328: 0f 91 pop r16 | |||
|
|
605 | 32a: 08 95 ret | |||
|
|
606 | ||||
|
|
607 | 0000032c <envio_datos_fpga>: | |||
|
|
608 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
|
|
609 | ||||
|
|
610 | } | |||
|
|
611 | ||||
|
|
612 | void envio_datos_fpga(void) | |||
|
|
613 | { | |||
|
|
614 | 32c: cf 93 push r28 | |||
|
|
615 | 32e: df 93 push r29 | |||
|
|
616 | 330: cd b7 in r28, 0x3d ; 61 | |||
|
|
617 | 332: de b7 in r29, 0x3e ; 62 | |||
|
|
618 | 334: 26 97 sbiw r28, 0x06 ; 6 | |||
|
|
619 | 336: cd bf out 0x3d, r28 ; 61 | |||
|
|
620 | 338: de bf out 0x3e, r29 ; 62 | |||
|
|
621 | uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; | |||
|
|
622 | ||||
|
|
623 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
624 | 33a: 63 e0 ldi r22, 0x03 ; 3 | |||
|
|
625 | 33c: 70 e0 ldi r23, 0x00 ; 0 | |||
|
|
626 | 33e: ce 01 movw r24, r28 | |||
|
|
627 | 340: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
628 | 342: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data> | |||
|
|
629 | aux_dato[0] = fpga_dato[0]; | |||
|
|
630 | 346: 89 81 ldd r24, Y+1 ; 0x01 | |||
|
|
631 | 348: 8c 83 std Y+4, r24 ; 0x04 | |||
|
|
632 | aux_dato[1] = fpga_dato[1]; | |||
|
|
633 | 34a: 8a 81 ldd r24, Y+2 ; 0x02 | |||
|
|
634 | 34c: 8d 83 std Y+5, r24 ; 0x05 | |||
|
|
635 | aux_dato[2] = fpga_dato[2]; | |||
|
|
636 | 34e: 8b 81 ldd r24, Y+3 ; 0x03 | |||
|
|
637 | 350: 8e 83 std Y+6, r24 ; 0x06 | |||
|
|
638 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
|
|
639 | 352: 63 e0 ldi r22, 0x03 ; 3 | |||
|
|
640 | 354: 70 e0 ldi r23, 0x00 ; 0 | |||
|
|
641 | 356: ce 01 movw r24, r28 | |||
|
|
642 | 358: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
643 | 35a: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data> | |||
|
|
644 | ||||
|
|
645 | envio_dato_adc(aux_dato); | |||
|
|
646 | 35e: ce 01 movw r24, r28 | |||
|
|
647 | 360: 04 96 adiw r24, 0x04 ; 4 | |||
|
|
648 | 362: 0e 94 83 01 call 0x306 ; 0x306 <envio_dato_adc> | |||
|
|
649 | envio_dato_adc(fpga_dato); | |||
|
|
650 | 366: ce 01 movw r24, r28 | |||
|
|
651 | 368: 01 96 adiw r24, 0x01 ; 1 | |||
|
|
652 | 36a: 0e 94 83 01 call 0x306 ; 0x306 <envio_dato_adc> | |||
|
|
653 | } | |||
|
|
654 | 36e: 26 96 adiw r28, 0x06 ; 6 | |||
|
|
655 | 370: cd bf out 0x3d, r28 ; 61 | |||
|
|
656 | 372: de bf out 0x3e, r29 ; 62 | |||
|
|
657 | 374: df 91 pop r29 | |||
|
|
658 | 376: cf 91 pop r28 | |||
|
|
659 | 378: 08 95 ret | |||
|
|
660 | ||||
|
|
661 | 0000037a <main>: | |||
|
|
662 | ||||
|
|
663 | ||||
|
|
664 | int main(void) | |||
|
|
665 | { | |||
|
|
666 | //uint8_t datos_adc[3]; | |||
|
|
667 | config_puertos(); | |||
|
|
668 | 37a: 0e 94 3e 02 call 0x47c ; 0x47c <config_puertos> | |||
|
|
669 | config_sysclock(); | |||
|
|
670 | 37e: 0e 94 b4 02 call 0x568 ; 0x568 <config_sysclock> | |||
|
|
671 | config_spiparm(); | |||
|
|
672 | 382: 0e 94 2c 01 call 0x258 ; 0x258 <config_spiparm> | |||
|
|
673 | config_fpgaport(); | |||
|
|
674 | 386: 0e 94 30 01 call 0x260 ; 0x260 <config_fpgaport> | |||
|
|
675 | config_adc(); | |||
|
|
676 | 38a: 0e 94 1e 01 call 0x23c ; 0x23c <config_adc> | |||
|
|
677 | //datos_adc[0] = 0x00; | |||
|
|
678 | //datos_adc[1] = 0x00; | |||
|
|
679 | //datos_adc[2] = 0x00; | |||
|
|
680 | //PORTD.OUTSET = PIN5_bm; | |||
|
|
681 | ||||
|
|
682 | PMIC.CTRL = hab_prioridad_alta; | |||
|
|
683 | 38e: 84 e0 ldi r24, 0x04 ; 4 | |||
|
|
684 | 390: 80 93 a2 00 sts 0x00A2, r24 | |||
|
|
685 | habilitar_interrupciones_globales(); | |||
|
|
686 | 394: 0e 94 68 01 call 0x2d0 ; 0x2d0 <habilitar_interrupciones_globales> | |||
|
|
687 | ||||
|
|
688 | /* Replace with your application code */ | |||
|
|
689 | while (1) | |||
|
|
690 | { | |||
|
|
691 | if (test_adc() == ADC_ID){ | |||
|
|
692 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
693 | 398: 00 e6 ldi r16, 0x60 ; 96 | |||
|
|
694 | 39a: 16 e0 ldi r17, 0x06 ; 6 | |||
|
|
695 | 39c: c0 e6 ldi r28, 0x60 ; 96 | |||
|
|
696 | habilitar_interrupciones_globales(); | |||
|
|
697 | ||||
|
|
698 | /* Replace with your application code */ | |||
|
|
699 | while (1) | |||
|
|
700 | { | |||
|
|
701 | if (test_adc() == ADC_ID){ | |||
|
|
702 | 39e: 0e 94 c2 00 call 0x184 ; 0x184 <test_adc> | |||
|
|
703 | 3a2: 84 39 cpi r24, 0x94 ; 148 | |||
|
|
704 | 3a4: 9c 40 sbci r25, 0x0C ; 12 | |||
|
|
705 | 3a6: d9 f7 brne .-10 ; 0x39e <main+0x24> | |||
|
|
706 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
707 | 3a8: f8 01 movw r30, r16 | |||
|
|
708 | 3aa: c5 83 std Z+5, r28 ; 0x05 | |||
|
|
709 | 3ac: f8 cf rjmp .-16 ; 0x39e <main+0x24> | |||
|
|
710 | ||||
|
|
711 | 000003ae <__vector_64>: | |||
|
|
712 | return 0; | |||
|
|
713 | } | |||
|
|
714 | ||||
|
|
715 | ||||
|
|
716 | ISR(INT_LOCK_FPGA) | |||
|
|
717 | { | |||
|
|
718 | 3ae: 1f 92 push r1 | |||
|
|
719 | 3b0: 0f 92 push r0 | |||
|
|
720 | 3b2: 0f b6 in r0, 0x3f ; 63 | |||
|
|
721 | 3b4: 0f 92 push r0 | |||
|
|
722 | 3b6: 11 24 eor r1, r1 | |||
|
|
723 | 3b8: 8f 93 push r24 | |||
|
|
724 | 3ba: ef 93 push r30 | |||
|
|
725 | 3bc: ff 93 push r31 | |||
|
|
726 | if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) | |||
|
|
727 | 3be: 80 91 68 06 lds r24, 0x0668 | |||
|
|
728 | 3c2: 81 ff sbrs r24, 1 | |||
|
|
729 | 3c4: 0c c0 rjmp .+24 ; 0x3de <__vector_64+0x30> | |||
|
|
730 | { | |||
|
|
731 | PMIC.CTRL |= hab_prioridad_media; | |||
|
|
732 | 3c6: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
733 | 3c8: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
734 | 3ca: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
735 | 3cc: 82 60 ori r24, 0x02 ; 2 | |||
|
|
736 | 3ce: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
737 | PORT_LOCKOUT.OUTSET = LOCK_OUT; | |||
|
|
738 | 3d0: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
739 | 3d2: 80 93 05 06 sts 0x0605, r24 | |||
|
|
740 | PORTD.OUTSET = PIN4_bm; | |||
|
|
741 | 3d6: 80 e1 ldi r24, 0x10 ; 16 | |||
|
|
742 | 3d8: 80 93 65 06 sts 0x0665, r24 | |||
|
|
743 | 3dc: 0b c0 rjmp .+22 ; 0x3f4 <__vector_64+0x46> | |||
|
|
744 | } | |||
|
|
745 | else | |||
|
|
746 | { | |||
|
|
747 | PMIC.CTRL &= ~hab_prioridad_media; | |||
|
|
748 | 3de: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
749 | 3e0: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
750 | 3e2: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
751 | 3e4: 8d 7f andi r24, 0xFD ; 253 | |||
|
|
752 | 3e6: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
753 | PMIC.CTRL &= ~hab_prioridad_baja; | |||
|
|
754 | 3e8: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
755 | 3ea: 8e 7f andi r24, 0xFE ; 254 | |||
|
|
756 | 3ec: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
757 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
758 | 3ee: 81 e0 ldi r24, 0x01 ; 1 | |||
|
|
759 | 3f0: 80 93 06 06 sts 0x0606, r24 | |||
|
|
760 | } | |||
|
|
761 | } | |||
|
|
762 | 3f4: ff 91 pop r31 | |||
|
|
763 | 3f6: ef 91 pop r30 | |||
|
|
764 | 3f8: 8f 91 pop r24 | |||
|
|
765 | 3fa: 0f 90 pop r0 | |||
|
|
766 | 3fc: 0f be out 0x3f, r0 ; 63 | |||
|
|
767 | 3fe: 0f 90 pop r0 | |||
|
|
768 | 400: 1f 90 pop r1 | |||
|
|
769 | 402: 18 95 reti | |||
|
|
770 | ||||
|
|
771 | 00000404 <__vector_35>: | |||
|
|
772 | ||||
|
|
773 | ISR(INT_PPS) | |||
|
|
774 | { | |||
|
|
775 | 404: 1f 92 push r1 | |||
|
|
776 | 406: 0f 92 push r0 | |||
|
|
777 | 408: 0f b6 in r0, 0x3f ; 63 | |||
|
|
778 | 40a: 0f 92 push r0 | |||
|
|
779 | 40c: 11 24 eor r1, r1 | |||
|
|
780 | 40e: 8f 93 push r24 | |||
|
|
781 | 410: ef 93 push r30 | |||
|
|
782 | 412: ff 93 push r31 | |||
|
|
783 | PMIC.CTRL |= hab_prioridad_baja; | |||
|
|
784 | 414: e0 ea ldi r30, 0xA0 ; 160 | |||
|
|
785 | 416: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
786 | 418: 82 81 ldd r24, Z+2 ; 0x02 | |||
|
|
787 | 41a: 81 60 ori r24, 0x01 ; 1 | |||
|
|
788 | 41c: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
789 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
|
790 | 41e: 80 e1 ldi r24, 0x10 ; 16 | |||
|
|
791 | 420: 80 93 46 06 sts 0x0646, r24 | |||
|
|
792 | } | |||
|
|
793 | 424: ff 91 pop r31 | |||
|
|
794 | 426: ef 91 pop r30 | |||
|
|
795 | 428: 8f 91 pop r24 | |||
|
|
796 | 42a: 0f 90 pop r0 | |||
|
|
797 | 42c: 0f be out 0x3f, r0 ; 63 | |||
|
|
798 | 42e: 0f 90 pop r0 | |||
|
|
799 | 430: 1f 90 pop r1 | |||
|
|
800 | 432: 18 95 reti | |||
|
|
801 | ||||
|
|
802 | 00000434 <__vector_2>: | |||
|
|
803 | ||||
|
|
804 | ISR(INT_RDY) | |||
|
|
805 | { | |||
|
|
806 | 434: 1f 92 push r1 | |||
|
|
807 | 436: 0f 92 push r0 | |||
|
|
808 | 438: 0f b6 in r0, 0x3f ; 63 | |||
|
|
809 | 43a: 0f 92 push r0 | |||
|
|
810 | 43c: 11 24 eor r1, r1 | |||
|
|
811 | 43e: 2f 93 push r18 | |||
|
|
812 | 440: 3f 93 push r19 | |||
|
|
813 | 442: 4f 93 push r20 | |||
|
|
814 | 444: 5f 93 push r21 | |||
|
|
815 | 446: 6f 93 push r22 | |||
|
|
816 | 448: 7f 93 push r23 | |||
|
|
817 | 44a: 8f 93 push r24 | |||
|
|
818 | 44c: 9f 93 push r25 | |||
|
|
819 | 44e: af 93 push r26 | |||
|
|
820 | 450: bf 93 push r27 | |||
|
|
821 | 452: ef 93 push r30 | |||
|
|
822 | 454: ff 93 push r31 | |||
|
|
823 | envio_datos_fpga(); | |||
|
|
824 | 456: 0e 94 96 01 call 0x32c ; 0x32c <envio_datos_fpga> | |||
|
|
825 | } | |||
|
|
826 | 45a: ff 91 pop r31 | |||
|
|
827 | 45c: ef 91 pop r30 | |||
|
|
828 | 45e: bf 91 pop r27 | |||
|
|
829 | 460: af 91 pop r26 | |||
|
|
830 | 462: 9f 91 pop r25 | |||
|
|
831 | 464: 8f 91 pop r24 | |||
|
|
832 | 466: 7f 91 pop r23 | |||
|
|
833 | 468: 6f 91 pop r22 | |||
|
|
834 | 46a: 5f 91 pop r21 | |||
|
|
835 | 46c: 4f 91 pop r20 | |||
|
|
836 | 46e: 3f 91 pop r19 | |||
|
|
837 | 470: 2f 91 pop r18 | |||
|
|
838 | 472: 0f 90 pop r0 | |||
|
|
839 | 474: 0f be out 0x3f, r0 ; 63 | |||
|
|
840 | 476: 0f 90 pop r0 | |||
|
|
841 | 478: 1f 90 pop r1 | |||
|
|
842 | 47a: 18 95 reti | |||
|
|
843 | ||||
|
|
844 | 0000047c <config_puertos>: | |||
|
|
845 | #include "commSPI_ADC.h" | |||
|
|
846 | ||||
|
|
847 | inline void config_puertos(void){ | |||
|
|
848 | //Configuracion pines del puerto A: PA7-PA0 | |||
|
|
849 | //Pines de entrada y totem_pullup | |||
|
|
850 | PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; | |||
|
|
851 | 47c: e0 e0 ldi r30, 0x00 ; 0 | |||
|
|
852 | 47e: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
853 | 480: 8e ef ldi r24, 0xFE ; 254 | |||
|
|
854 | 482: 82 83 std Z+2, r24 ; 0x02 | |||
|
|
855 | PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
856 | 484: 88 e1 ldi r24, 0x18 ; 24 | |||
|
|
857 | 486: 87 8b std Z+23, r24 ; 0x17 | |||
|
|
858 | PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
859 | 488: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
860 | PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
861 | 48a: 85 8b std Z+21, r24 ; 0x15 | |||
|
|
862 | PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
863 | 48c: 84 8b std Z+20, r24 ; 0x14 | |||
|
|
864 | PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
865 | 48e: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
866 | PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
867 | 490: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
868 | PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
869 | 492: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
870 | //Pin de salida A0 | |||
|
|
871 | //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n | |||
|
|
872 | //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta | |||
|
|
873 | //Valor por defecto salida: PA0 = low | |||
|
|
874 | PORTA.DIRSET = PIN0_bm; | |||
|
|
875 | 494: 21 e0 ldi r18, 0x01 ; 1 | |||
|
|
876 | 496: 21 83 std Z+1, r18 ; 0x01 | |||
|
|
877 | PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
878 | 498: 98 e3 ldi r25, 0x38 ; 56 | |||
|
|
879 | 49a: 90 8b std Z+16, r25 ; 0x10 | |||
|
|
880 | PORTA.OUTCLR = PIN0_bm; | |||
|
|
881 | 49c: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
882 | ||||
|
|
883 | //Configuracion pines del puerto B: PB3-PB0 | |||
|
|
884 | //Pines de entrada y totem_pullup | |||
|
|
885 | PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; | |||
|
|
886 | 49e: e0 e2 ldi r30, 0x20 ; 32 | |||
|
|
887 | 4a0: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
888 | 4a2: 3f e0 ldi r19, 0x0F ; 15 | |||
|
|
889 | 4a4: 32 83 std Z+2, r19 ; 0x02 | |||
|
|
890 | PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
891 | 4a6: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
892 | PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
893 | 4a8: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
894 | PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
895 | 4aa: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
896 | PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
897 | 4ac: 80 8b std Z+16, r24 ; 0x10 | |||
|
|
898 | ||||
|
|
899 | //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI | |||
|
|
900 | //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 | |||
|
|
901 | //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. | |||
|
|
902 | PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C | |||
|
|
903 | 4ae: e0 e4 ldi r30, 0x40 ; 64 | |||
|
|
904 | 4b0: f6 e0 ldi r31, 0x06 ; 6 | |||
|
|
905 | 4b2: 2f e4 ldi r18, 0x4F ; 79 | |||
|
|
906 | 4b4: 22 83 std Z+2, r18 ; 0x02 | |||
|
|
907 | PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; | |||
|
|
908 | 4b6: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
909 | PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
910 | 4b8: 83 8b std Z+19, r24 ; 0x13 | |||
|
|
911 | PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
912 | 4ba: 82 8b std Z+18, r24 ; 0x12 | |||
|
|
913 | PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
914 | 4bc: 81 8b std Z+17, r24 ; 0x11 | |||
|
|
915 | PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
916 | 4be: 80 8b std Z+16, r24 ; 0x10 | |||
|
|
917 | //Pines de salida wiredand-pull | |||
|
|
918 | //Valor por defecto salida: PC4,PC7 = low | |||
|
|
919 | //Valor por defecto salida: PC5 = set | |||
|
|
920 | PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; | |||
|
|
921 | 4c0: 20 eb ldi r18, 0xB0 ; 176 | |||
|
|
922 | 4c2: 21 83 std Z+1, r18 ; 0x01 | |||
|
|
923 | PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; | |||
|
|
924 | 4c4: 15 8a std Z+21, r1 ; 0x15 | |||
|
|
925 | PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
926 | 4c6: 17 8a std Z+23, r1 ; 0x17 | |||
|
|
927 | PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; | |||
|
|
928 | 4c8: 14 8a std Z+20, r1 ; 0x14 | |||
|
|
929 | PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; | |||
|
|
930 | 4ca: 20 e9 ldi r18, 0x90 ; 144 | |||
|
|
931 | 4cc: 25 83 std Z+5, r18 ; 0x05 | |||
|
|
932 | PORTSPI.OUTCLR = SPI_MOSI_bm; | |||
|
|
933 | 4ce: 20 e2 ldi r18, 0x20 ; 32 | |||
|
|
934 | 4d0: 26 83 std Z+6, r18 ; 0x06 | |||
|
|
935 | //Configuracion pines del puerto D: PD7-PD0 | |||
|
|
936 | //Pines de entrada y totem_pullup: PIN7 y PIN0 | |||
|
|
937 | //NOTA | |||
|
|
938 | //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO | |||
|
|
939 | //NOTA FIN | |||
|
|
940 | PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
941 | 4d2: a0 e6 ldi r26, 0x60 ; 96 | |||
|
|
942 | 4d4: b6 e0 ldi r27, 0x06 ; 6 | |||
|
|
943 | 4d6: 27 e8 ldi r18, 0x87 ; 135 | |||
|
|
944 | 4d8: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
945 | 4da: 2c 93 st X, r18 | |||
|
|
946 | 4dc: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
947 | PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
948 | 4de: 57 96 adiw r26, 0x17 ; 23 | |||
|
|
949 | 4e0: 8c 93 st X, r24 | |||
|
|
950 | 4e2: 57 97 sbiw r26, 0x17 ; 23 | |||
|
|
951 | PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
952 | 4e4: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
953 | 4e6: 8c 93 st X, r24 | |||
|
|
954 | 4e8: 50 97 sbiw r26, 0x10 ; 16 | |||
|
|
955 | //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga | |||
|
|
956 | PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
957 | 4ea: 20 e1 ldi r18, 0x10 ; 16 | |||
|
|
958 | 4ec: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
959 | 4ee: 2c 93 st X, r18 | |||
|
|
960 | 4f0: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
961 | PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
962 | 4f2: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
963 | 4f4: 2c 93 st X, r18 | |||
|
|
964 | 4f6: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
965 | //Pines de salida tipo wired-and-pull | |||
|
|
966 | //Valor por defecto PD6, PD5, PD4, PD3 = low | |||
|
|
967 | PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
968 | 4f8: 48 e7 ldi r20, 0x78 ; 120 | |||
|
|
969 | 4fa: 11 96 adiw r26, 0x01 ; 1 | |||
|
|
970 | 4fc: 4c 93 st X, r20 | |||
|
|
971 | 4fe: 11 97 sbiw r26, 0x01 ; 1 | |||
|
|
972 | PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
973 | 500: 56 96 adiw r26, 0x16 ; 22 | |||
|
|
974 | 502: 9c 93 st X, r25 | |||
|
|
975 | 504: 56 97 sbiw r26, 0x16 ; 22 | |||
|
|
976 | PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
977 | 506: 55 96 adiw r26, 0x15 ; 21 | |||
|
|
978 | 508: 9c 93 st X, r25 | |||
|
|
979 | 50a: 55 97 sbiw r26, 0x15 ; 21 | |||
|
|
980 | PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
981 | 50c: 54 96 adiw r26, 0x14 ; 20 | |||
|
|
982 | 50e: 9c 93 st X, r25 | |||
|
|
983 | 510: 54 97 sbiw r26, 0x14 ; 20 | |||
|
|
984 | PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
|
|
985 | 512: 53 96 adiw r26, 0x13 ; 19 | |||
|
|
986 | 514: 9c 93 st X, r25 | |||
|
|
987 | 516: 53 97 sbiw r26, 0x13 ; 19 | |||
|
|
988 | PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
|
|
989 | 518: 16 96 adiw r26, 0x06 ; 6 | |||
|
|
990 | 51a: 4c 93 st X, r20 | |||
|
|
991 | ||||
|
|
992 | //Configuracion pines del puerto E: PE3-PE0 | |||
|
|
993 | //Pines de entrada y totem_pullup: PIN3 - PIN0 | |||
|
|
994 | PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
|
|
995 | 51c: a0 e8 ldi r26, 0x80 ; 128 | |||
|
|
996 | 51e: b6 e0 ldi r27, 0x06 ; 6 | |||
|
|
997 | 520: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
998 | 522: 3c 93 st X, r19 | |||
|
|
999 | 524: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
1000 | PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
1001 | 526: 53 96 adiw r26, 0x13 ; 19 | |||
|
|
1002 | 528: 8c 93 st X, r24 | |||
|
|
1003 | 52a: 53 97 sbiw r26, 0x13 ; 19 | |||
|
|
1004 | PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
1005 | 52c: 52 96 adiw r26, 0x12 ; 18 | |||
|
|
1006 | 52e: 8c 93 st X, r24 | |||
|
|
1007 | 530: 52 97 sbiw r26, 0x12 ; 18 | |||
|
|
1008 | PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
1009 | 532: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
1010 | 534: 8c 93 st X, r24 | |||
|
|
1011 | 536: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
1012 | PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
1013 | 538: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
1014 | 53a: 8c 93 st X, r24 | |||
|
|
1015 | ||||
|
|
1016 | //Configuracion pines del puerto R: PR1-PR0 | |||
|
|
1017 | //Pines de entrada y totem_pulldown: PIN0 | |||
|
|
1018 | PORTR.DIRCLR = PIN1_bm| PIN0_bm; | |||
|
|
1019 | 53c: a0 ee ldi r26, 0xE0 ; 224 | |||
|
|
1020 | 53e: b7 e0 ldi r27, 0x07 ; 7 | |||
|
|
1021 | 540: 93 e0 ldi r25, 0x03 ; 3 | |||
|
|
1022 | 542: 12 96 adiw r26, 0x02 ; 2 | |||
|
|
1023 | 544: 9c 93 st X, r25 | |||
|
|
1024 | 546: 12 97 sbiw r26, 0x02 ; 2 | |||
|
|
1025 | PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
|
|
1026 | 548: 51 96 adiw r26, 0x11 ; 17 | |||
|
|
1027 | 54a: 2c 93 st X, r18 | |||
|
|
1028 | 54c: 51 97 sbiw r26, 0x11 ; 17 | |||
|
|
1029 | //Pines de entrada y totem_pulldup:PIN1 | |||
|
|
1030 | PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
|
|
1031 | 54e: 50 96 adiw r26, 0x10 ; 16 | |||
|
|
1032 | 550: 8c 93 st X, r24 | |||
|
|
1033 | ||||
|
|
1034 | //Configuraci�n como interrupci�n del pin SPI_MISO_RDY | |||
|
|
1035 | ||||
|
|
1036 | PORTSPI.INT0MASK = SPI_MISO_bm; | |||
|
|
1037 | 552: 80 e4 ldi r24, 0x40 ; 64 | |||
|
|
1038 | 554: 82 87 std Z+10, r24 ; 0x0a | |||
|
|
1039 | PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; | |||
|
|
1040 | 556: 81 85 ldd r24, Z+9 ; 0x09 | |||
|
|
1041 | 558: 8c 7f andi r24, 0xFC ; 252 | |||
|
|
1042 | 55a: 81 60 ori r24, 0x01 ; 1 | |||
|
|
1043 | 55c: 81 87 std Z+9, r24 ; 0x09 | |||
|
|
1044 | PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
|
|
1045 | 55e: 86 89 ldd r24, Z+22 ; 0x16 | |||
|
|
1046 | 560: 88 7f andi r24, 0xF8 ; 248 | |||
|
|
1047 | 562: 82 60 ori r24, 0x02 ; 2 | |||
|
|
1048 | 564: 86 8b std Z+22, r24 ; 0x16 | |||
|
|
1049 | 566: 08 95 ret | |||
|
|
1050 | ||||
|
|
1051 | 00000568 <config_sysclock>: | |||
|
|
1052 | #define F_CPU 32000000UL | |||
|
|
1053 | #include <avr/io.h> | |||
|
|
1054 | ||||
|
|
1055 | void config_sysclock(void){ | |||
|
|
1056 | ||||
|
|
1057 | CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1 | |||
|
|
1058 | 568: 10 92 41 00 sts 0x0041, r1 | |||
|
|
1059 | OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */ | |||
|
|
1060 | 56c: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
1061 | 56e: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
1062 | 570: 80 81 ld r24, Z | |||
|
|
1063 | 572: 86 60 ori r24, 0x06 ; 6 | |||
|
|
1064 | 574: 80 83 st Z, r24 | |||
|
|
1065 | while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */ | |||
|
|
1066 | 576: 81 81 ldd r24, Z+1 ; 0x01 | |||
|
|
1067 | 578: 82 ff sbrs r24, 2 | |||
|
|
1068 | 57a: fd cf rjmp .-6 ; 0x576 <config_sysclock+0xe> | |||
|
|
1069 | while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */ | |||
|
|
1070 | 57c: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
1071 | 57e: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
1072 | 580: 81 81 ldd r24, Z+1 ; 0x01 | |||
|
|
1073 | 582: 81 ff sbrs r24, 1 | |||
|
|
1074 | 584: fd cf rjmp .-6 ; 0x580 <config_sysclock+0x18> | |||
|
|
1075 | DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ | |||
|
|
1076 | 586: 91 e0 ldi r25, 0x01 ; 1 | |||
|
|
1077 | 588: 90 93 60 00 sts 0x0060, r25 | |||
|
|
1078 | OSC.DFLLCTRL &= 0xFD; //Habilito calibraci�n interna mediante reloj de 32K | |||
|
|
1079 | 58c: e0 e5 ldi r30, 0x50 ; 80 | |||
|
|
1080 | 58e: f0 e0 ldi r31, 0x00 ; 0 | |||
|
|
1081 | 590: 86 81 ldd r24, Z+6 ; 0x06 | |||
|
|
1082 | 592: 8d 7f andi r24, 0xFD ; 253 | |||
|
|
1083 | 594: 86 83 std Z+6, r24 ; 0x06 | |||
|
|
1084 | CCP = CCP_IOREG_gc; /* Disable register security for clock update */ | |||
|
|
1085 | 596: 88 ed ldi r24, 0xD8 ; 216 | |||
|
|
1086 | 598: 84 bf out 0x34, r24 ; 52 | |||
|
|
1087 | CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */ | |||
|
|
1088 | 59a: 90 93 40 00 sts 0x0040, r25 | |||
|
|
1089 | OSC.CTRL &= ~OSC_RC2MEN_bm; | |||
|
|
1090 | 59e: 80 81 ld r24, Z | |||
|
|
1091 | 5a0: 8e 7f andi r24, 0xFE ; 254 | |||
|
|
1092 | 5a2: 80 83 st Z, r24 | |||
|
|
1093 | 5a4: 08 95 ret | |||
|
|
1094 | ||||
|
|
1095 | 000005a6 <_exit>: | |||
|
|
1096 | 5a6: f8 94 cli | |||
|
|
1097 | ||||
|
|
1098 | 000005a8 <__stop_program>: | |||
|
|
1099 | 5a8: ff cf rjmp .-2 ; 0x5a8 <__stop_program> | |||
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3 | c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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4 | C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o (exit) | |||
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5 | ||||
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6 | Discarded input sections | |||
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8 | .data 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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9 | .bss 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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10 | .text 0x00000000 0x0 ADC_7176_2.o | |||
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11 | .data 0x00000000 0x0 ADC_7176_2.o | |||
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12 | .bss 0x00000000 0x0 ADC_7176_2.o | |||
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13 | .text.test_adc_2 | |||
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14 | 0x00000000 0x3e ADC_7176_2.o | |||
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15 | .text.adcport_tranceiv | |||
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16 | 0x00000000 0x14 ADC_7176_2.o | |||
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17 | .text.adcport_write_interfmode | |||
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18 | 0x00000000 0x34 ADC_7176_2.o | |||
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19 | .text 0x00000000 0x0 commSPI_ADC.o | |||
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20 | .data 0x00000000 0x0 commSPI_ADC.o | |||
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21 | .bss 0x00000000 0x0 commSPI_ADC.o | |||
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22 | .text 0x00000000 0x0 fpga_port.o | |||
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23 | .data 0x00000000 0x0 fpga_port.o | |||
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24 | .bss 0x00000000 0x0 fpga_port.o | |||
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25 | .text.habilitar_interrupciones | |||
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26 | 0x00000000 0xc fpga_port.o | |||
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27 | .text.deshabilitar_interrupciones_globales | |||
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28 | 0x00000000 0x4 fpga_port.o | |||
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29 | .text 0x00000000 0x0 main.o | |||
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30 | .data 0x00000000 0x0 main.o | |||
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31 | .bss 0x00000000 0x0 main.o | |||
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32 | .text 0x00000000 0x0 Ports.o | |||
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33 | .data 0x00000000 0x0 Ports.o | |||
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34 | .bss 0x00000000 0x0 Ports.o | |||
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35 | .text 0x00000000 0x0 sys_clock.o | |||
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36 | .data 0x00000000 0x0 sys_clock.o | |||
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37 | .bss 0x00000000 0x0 sys_clock.o | |||
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38 | .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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40 | .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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41 | .text.libgcc.mul | |||
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42 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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43 | .text.libgcc.div | |||
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44 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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45 | .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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46 | .text.libgcc.prologue | |||
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47 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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48 | .text.libgcc.builtins | |||
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49 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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50 | .text.libgcc.fmul | |||
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52 | .text.libgcc.fixed | |||
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53 | 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) | |||
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54 | ||||
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55 | Memory Configuration | |||
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56 | ||||
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57 | Name Origin Length Attributes | |||
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66 | ||||
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68 | ||||
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69 | LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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70 | LOAD ADC_7176_2.o | |||
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71 | LOAD commSPI_ADC.o | |||
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72 | LOAD fpga_port.o | |||
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73 | LOAD main.o | |||
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74 | LOAD Ports.o | |||
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78 | END GROUP | |||
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79 | START GROUP | |||
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81 | LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a | |||
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84 | END GROUP | |||
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86 | .hash | |||
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88 | ||||
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89 | .dynsym | |||
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91 | ||||
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92 | .dynstr | |||
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93 | *(.dynstr) | |||
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94 | ||||
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95 | .gnu.version | |||
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96 | *(.gnu.version) | |||
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97 | ||||
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98 | .gnu.version_d | |||
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99 | *(.gnu.version_d) | |||
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100 | ||||
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101 | .gnu.version_r | |||
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102 | *(.gnu.version_r) | |||
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103 | ||||
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104 | .rel.init | |||
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105 | *(.rel.init) | |||
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106 | ||||
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107 | .rela.init | |||
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108 | *(.rela.init) | |||
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109 | ||||
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110 | .rel.text | |||
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111 | *(.rel.text) | |||
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112 | *(.rel.text.*) | |||
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113 | *(.rel.gnu.linkonce.t*) | |||
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117 | *(.rela.text.*) | |||
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140 | ||||
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144 | *(.rela.gnu.linkonce.d*) | |||
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145 | ||||
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146 | .rel.ctors | |||
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147 | *(.rel.ctors) | |||
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148 | ||||
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149 | .rela.ctors | |||
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150 | *(.rela.ctors) | |||
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151 | ||||
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152 | .rel.dtors | |||
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153 | *(.rel.dtors) | |||
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154 | ||||
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155 | .rela.dtors | |||
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156 | *(.rela.dtors) | |||
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157 | ||||
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158 | .rel.got | |||
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159 | *(.rel.got) | |||
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160 | ||||
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161 | .rela.got | |||
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163 | ||||
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166 | ||||
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167 | .rela.bss | |||
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169 | ||||
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176 | .text 0x00000000 0x5aa | |||
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179 | 0x00000000 __vector_default | |||
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180 | 0x00000000 __vectors | |||
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181 | *(.vectors) | |||
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182 | *(.progmem.gcc*) | |||
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183 | 0x0000016c . = ALIGN (0x2) | |||
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184 | 0x0000016c __trampolines_start = . | |||
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185 | *(.trampolines) | |||
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186 | .trampolines 0x0000016c 0x0 linker stubs | |||
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187 | *(.trampolines*) | |||
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188 | 0x0000016c __trampolines_end = . | |||
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189 | *(.progmem*) | |||
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190 | 0x0000016c . = ALIGN (0x2) | |||
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191 | *(.jumptables) | |||
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192 | *(.jumptables*) | |||
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193 | *(.lowtext) | |||
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194 | *(.lowtext*) | |||
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195 | 0x0000016c __ctors_start = . | |||
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196 | *(.ctors) | |||
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197 | 0x0000016c __ctors_end = . | |||
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198 | 0x0000016c __dtors_start = . | |||
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199 | *(.dtors) | |||
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200 | 0x0000016c __dtors_end = . | |||
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201 | SORT(*)(.ctors) | |||
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202 | SORT(*)(.dtors) | |||
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203 | *(.init0) | |||
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204 | .init0 0x0000016c 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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205 | 0x0000016c __init | |||
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206 | *(.init0) | |||
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207 | *(.init1) | |||
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208 | *(.init1) | |||
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209 | *(.init2) | |||
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210 | .init2 0x0000016c 0xc C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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211 | *(.init2) | |||
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212 | *(.init3) | |||
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213 | *(.init3) | |||
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214 | *(.init4) | |||
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215 | *(.init4) | |||
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216 | *(.init5) | |||
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217 | *(.init5) | |||
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219 | *(.init6) | |||
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220 | *(.init7) | |||
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222 | *(.init8) | |||
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223 | *(.init8) | |||
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226 | *(.init9) | |||
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227 | *(.text) | |||
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228 | .text 0x00000180 0x4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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229 | 0x00000180 __vector_38 | |||
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230 | 0x00000180 __vector_22 | |||
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232 | 0x00000180 __vector_28 | |||
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233 | 0x00000180 __vector_67 | |||
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234 | 0x00000180 __vector_1 | |||
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403 | ||||
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423 | ||||
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429 | ||||
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430 | .lock | |||
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432 | ||||
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435 | ||||
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438 | ||||
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439 | .stab | |||
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441 | ||||
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442 | .stabstr | |||
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444 | ||||
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445 | .stab.excl | |||
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446 | *(.stab.excl) | |||
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447 | ||||
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448 | .stab.exclstr | |||
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449 | *(.stab.exclstr) | |||
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450 | ||||
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451 | .stab.index | |||
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453 | ||||
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454 | .stab.indexstr | |||
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455 | *(.stab.indexstr) | |||
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456 | ||||
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457 | .comment 0x00000000 0x30 | |||
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458 | *(.comment) | |||
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459 | .comment 0x00000000 0x30 ADC_7176_2.o | |||
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460 | 0x31 (size before relaxing) | |||
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461 | .comment 0x00000030 0x31 commSPI_ADC.o | |||
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462 | .comment 0x00000030 0x31 fpga_port.o | |||
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463 | .comment 0x00000030 0x31 main.o | |||
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464 | .comment 0x00000030 0x31 Ports.o | |||
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465 | .comment 0x00000030 0x31 sys_clock.o | |||
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466 | ||||
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467 | .note.gnu.avr.deviceinfo | |||
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468 | 0x00000000 0x40 | |||
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469 | .note.gnu.avr.deviceinfo | |||
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470 | 0x00000000 0x40 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o | |||
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471 | ||||
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472 | .note.gnu.build-id | |||
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473 | *(.note.gnu.build-id) | |||
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474 | ||||
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475 | .debug | |||
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476 | *(.debug) | |||
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477 | ||||
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478 | .line | |||
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479 | *(.line) | |||
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480 | ||||
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481 | .debug_srcinfo | |||
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482 | *(.debug_srcinfo) | |||
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483 | ||||
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484 | .debug_sfnames | |||
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485 | *(.debug_sfnames) | |||
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486 | ||||
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487 | .debug_aranges 0x00000000 0x138 | |||
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488 | *(.debug_aranges) | |||
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489 | .debug_aranges | |||
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490 | 0x00000000 0x50 ADC_7176_2.o | |||
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491 | .debug_aranges | |||
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492 | 0x00000050 0x20 commSPI_ADC.o | |||
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493 | .debug_aranges | |||
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494 | 0x00000070 0x50 fpga_port.o | |||
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495 | .debug_aranges | |||
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496 | 0x000000c0 0x38 main.o | |||
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497 | .debug_aranges | |||
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498 | 0x000000f8 0x20 Ports.o | |||
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499 | .debug_aranges | |||
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500 | 0x00000118 0x20 sys_clock.o | |||
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501 | ||||
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502 | .debug_pubnames | |||
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503 | *(.debug_pubnames) | |||
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504 | ||||
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505 | .debug_info 0x00000000 0x14ca | |||
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506 | *(.debug_info .gnu.linkonce.wi.*) | |||
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507 | .debug_info 0x00000000 0x53c ADC_7176_2.o | |||
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508 | .debug_info 0x0000053c 0xf0 commSPI_ADC.o | |||
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509 | .debug_info 0x0000062c 0x57a fpga_port.o | |||
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510 | .debug_info 0x00000ba6 0x426 main.o | |||
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511 | .debug_info 0x00000fcc 0x2ab Ports.o | |||
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512 | .debug_info 0x00001277 0x253 sys_clock.o | |||
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513 | ||||
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|
514 | .debug_abbrev 0x00000000 0x64f | |||
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515 | *(.debug_abbrev) | |||
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516 | .debug_abbrev 0x00000000 0x1d0 ADC_7176_2.o | |||
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517 | .debug_abbrev 0x000001d0 0x83 commSPI_ADC.o | |||
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518 | .debug_abbrev 0x00000253 0x18c fpga_port.o | |||
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519 | .debug_abbrev 0x000003df 0x10d main.o | |||
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520 | .debug_abbrev 0x000004ec 0xaa Ports.o | |||
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|
521 | .debug_abbrev 0x00000596 0xb9 sys_clock.o | |||
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522 | ||||
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|
523 | .debug_line 0x00000000 0x82c | |||
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|
524 | *(.debug_line .debug_line.* .debug_line_end) | |||
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|
525 | .debug_line 0x00000000 0x1cc ADC_7176_2.o | |||
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|
526 | .debug_line 0x000001cc 0x101 commSPI_ADC.o | |||
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527 | .debug_line 0x000002cd 0x19c fpga_port.o | |||
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528 | .debug_line 0x00000469 0x188 main.o | |||
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529 | .debug_line 0x000005f1 0x12c Ports.o | |||
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530 | .debug_line 0x0000071d 0x10f sys_clock.o | |||
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531 | ||||
|
|
532 | .debug_frame 0x00000000 0x288 | |||
|
|
533 | *(.debug_frame) | |||
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|
534 | .debug_frame 0x00000000 0x94 ADC_7176_2.o | |||
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|
535 | .debug_frame 0x00000094 0x24 commSPI_ADC.o | |||
|
|
536 | .debug_frame 0x000000b8 0xb4 fpga_port.o | |||
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|
537 | .debug_frame 0x0000016c 0xd4 main.o | |||
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|
538 | .debug_frame 0x00000240 0x24 Ports.o | |||
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|
539 | .debug_frame 0x00000264 0x24 sys_clock.o | |||
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|
540 | ||||
|
|
541 | .debug_str 0x00000000 0x7d6 | |||
|
|
542 | *(.debug_str) | |||
|
|
543 | .debug_str 0x00000000 0x2c0 ADC_7176_2.o | |||
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|
544 | 0x303 (size before relaxing) | |||
|
|
545 | .debug_str 0x000002c0 0x22 commSPI_ADC.o | |||
|
|
546 | 0x1cc (size before relaxing) | |||
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|
547 | .debug_str 0x000002e2 0x34d fpga_port.o | |||
|
|
548 | 0x5e0 (size before relaxing) | |||
|
|
549 | .debug_str 0x0000062f 0x53 main.o | |||
|
|
550 | 0x3cc (size before relaxing) | |||
|
|
551 | .debug_str 0x00000682 0xd Ports.o | |||
|
|
552 | 0x3f5 (size before relaxing) | |||
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|
553 | .debug_str 0x0000068f 0x147 sys_clock.o | |||
|
|
554 | 0x2ff (size before relaxing) | |||
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|
555 | ||||
|
|
556 | .debug_loc 0x00000000 0x42d | |||
|
|
557 | *(.debug_loc) | |||
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|
558 | .debug_loc 0x00000000 0x138 ADC_7176_2.o | |||
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|
559 | .debug_loc 0x00000138 0x17e fpga_port.o | |||
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|
560 | .debug_loc 0x000002b6 0x177 main.o | |||
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|
561 | ||||
|
|
562 | .debug_macinfo | |||
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563 | *(.debug_macinfo) | |||
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|
564 | ||||
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|
565 | .debug_weaknames | |||
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566 | *(.debug_weaknames) | |||
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567 | ||||
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|
568 | .debug_funcnames | |||
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569 | *(.debug_funcnames) | |||
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570 | ||||
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|
571 | .debug_typenames | |||
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572 | *(.debug_typenames) | |||
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|
573 | ||||
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|
574 | .debug_varnames | |||
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575 | *(.debug_varnames) | |||
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576 | ||||
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|
577 | .debug_pubtypes | |||
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578 | *(.debug_pubtypes) | |||
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579 | ||||
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|
580 | .debug_ranges 0x00000000 0xd8 | |||
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581 | *(.debug_ranges) | |||
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582 | .debug_ranges 0x00000000 0x40 ADC_7176_2.o | |||
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|
583 | .debug_ranges 0x00000040 0x10 commSPI_ADC.o | |||
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584 | .debug_ranges 0x00000050 0x40 fpga_port.o | |||
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585 | .debug_ranges 0x00000090 0x28 main.o | |||
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586 | .debug_ranges 0x000000b8 0x10 Ports.o | |||
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|
587 | .debug_ranges 0x000000c8 0x10 sys_clock.o | |||
|
|
588 | ||||
|
|
589 | .debug_macro | |||
|
|
590 | *(.debug_macro) | |||
|
|
591 | OUTPUT(ADCSPI_ver01.elf elf32-avr) | |||
|
|
592 | LOAD linker stubs | |||
| @@ -0,0 +1,93 | |||||
|
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1 | S01400004144435350495F76657230312E737265634F | |||
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93 | S9030000FC | |||
| @@ -0,0 +1,44 | |||||
|
|
1 | ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
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3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././ADC_7176_2.h: | |||
|
|
41 | ||||
|
|
42 | .././Ports.h: | |||
|
|
43 | ||||
|
|
44 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,164 | |||||
|
|
1 | ################################################################################ | |||
|
|
2 | # Automatically-generated file. Do not edit! | |||
|
|
3 | ################################################################################ | |||
|
|
4 | ||||
|
|
5 | SHELL := cmd.exe | |||
|
|
6 | RM := rm -rf | |||
|
|
7 | ||||
|
|
8 | USER_OBJS := | |||
|
|
9 | ||||
|
|
10 | LIBS := | |||
|
|
11 | PROJ := | |||
|
|
12 | ||||
|
|
13 | O_SRCS := | |||
|
|
14 | C_SRCS := | |||
|
|
15 | S_SRCS := | |||
|
|
16 | S_UPPER_SRCS := | |||
|
|
17 | OBJ_SRCS := | |||
|
|
18 | ASM_SRCS := | |||
|
|
19 | PREPROCESSING_SRCS := | |||
|
|
20 | OBJS := | |||
|
|
21 | OBJS_AS_ARGS := | |||
|
|
22 | C_DEPS := | |||
|
|
23 | C_DEPS_AS_ARGS := | |||
|
|
24 | EXECUTABLES := | |||
|
|
25 | OUTPUT_FILE_PATH := | |||
|
|
26 | OUTPUT_FILE_PATH_AS_ARGS := | |||
|
|
27 | AVR_APP_PATH :=$$$AVR_APP_PATH$$$ | |||
|
|
28 | QUOTE := " | |||
|
|
29 | ADDITIONAL_DEPENDENCIES:= | |||
|
|
30 | OUTPUT_FILE_DEP:= | |||
|
|
31 | LIB_DEP:= | |||
|
|
32 | LINKER_SCRIPT_DEP:= | |||
|
|
33 | ||||
|
|
34 | # Every subdirectory with source files must be described here | |||
|
|
35 | SUBDIRS := | |||
|
|
36 | ||||
|
|
37 | ||||
|
|
38 | # Add inputs and outputs from these tool invocations to the build variables | |||
|
|
39 | C_SRCS += \ | |||
|
|
40 | ../ADC_7176_2.c \ | |||
|
|
41 | ../commSPI_ADC.c \ | |||
|
|
42 | ../fpga_port.c \ | |||
|
|
43 | ../main.c \ | |||
|
|
44 | ../Ports.c \ | |||
|
|
45 | ../sys_clock.c | |||
|
|
46 | ||||
|
|
47 | ||||
|
|
48 | PREPROCESSING_SRCS += | |||
|
|
49 | ||||
|
|
50 | ||||
|
|
51 | ASM_SRCS += | |||
|
|
52 | ||||
|
|
53 | ||||
|
|
54 | OBJS += \ | |||
|
|
55 | ADC_7176_2.o \ | |||
|
|
56 | commSPI_ADC.o \ | |||
|
|
57 | fpga_port.o \ | |||
|
|
58 | main.o \ | |||
|
|
59 | Ports.o \ | |||
|
|
60 | sys_clock.o | |||
|
|
61 | ||||
|
|
62 | OBJS_AS_ARGS += \ | |||
|
|
63 | ADC_7176_2.o \ | |||
|
|
64 | commSPI_ADC.o \ | |||
|
|
65 | fpga_port.o \ | |||
|
|
66 | main.o \ | |||
|
|
67 | Ports.o \ | |||
|
|
68 | sys_clock.o | |||
|
|
69 | ||||
|
|
70 | C_DEPS += \ | |||
|
|
71 | ADC_7176_2.d \ | |||
|
|
72 | commSPI_ADC.d \ | |||
|
|
73 | fpga_port.d \ | |||
|
|
74 | main.d \ | |||
|
|
75 | Ports.d \ | |||
|
|
76 | sys_clock.d | |||
|
|
77 | ||||
|
|
78 | C_DEPS_AS_ARGS += \ | |||
|
|
79 | ADC_7176_2.d \ | |||
|
|
80 | commSPI_ADC.d \ | |||
|
|
81 | fpga_port.d \ | |||
|
|
82 | main.d \ | |||
|
|
83 | Ports.d \ | |||
|
|
84 | sys_clock.d | |||
|
|
85 | ||||
|
|
86 | OUTPUT_FILE_PATH +=ADCSPI_ver01.elf | |||
|
|
87 | ||||
|
|
88 | OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf | |||
|
|
89 | ||||
|
|
90 | ADDITIONAL_DEPENDENCIES:= | |||
|
|
91 | ||||
|
|
92 | OUTPUT_FILE_DEP:= ./makedep.mk | |||
|
|
93 | ||||
|
|
94 | LIB_DEP+= | |||
|
|
95 | ||||
|
|
96 | LINKER_SCRIPT_DEP+= | |||
|
|
97 | ||||
|
|
98 | ||||
|
|
99 | # AVR32/GNU C Compiler | |||
|
|
100 | ||||
|
|
101 | ||||
|
|
102 | ||||
|
|
103 | ||||
|
|
104 | ||||
|
|
105 | ||||
|
|
106 | ||||
|
|
107 | ||||
|
|
108 | ||||
|
|
109 | ||||
|
|
110 | ||||
|
|
111 | ||||
|
|
112 | ||||
|
|
113 | ./%.o: .././%.c | |||
|
|
114 | @echo Building file: $< | |||
|
|
115 | @echo Invoking: AVR/GNU C Compiler : 4.9.2 | |||
|
|
116 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" | |||
|
|
117 | @echo Finished building: $< | |||
|
|
118 | ||||
|
|
119 | ||||
|
|
120 | ||||
|
|
121 | ||||
|
|
122 | # AVR32/GNU Preprocessing Assembler | |||
|
|
123 | ||||
|
|
124 | ||||
|
|
125 | ||||
|
|
126 | # AVR32/GNU Assembler | |||
|
|
127 | ||||
|
|
128 | ||||
|
|
129 | ||||
|
|
130 | ||||
|
|
131 | ifneq ($(MAKECMDGOALS),clean) | |||
|
|
132 | ifneq ($(strip $(C_DEPS)),) | |||
|
|
133 | -include $(C_DEPS) | |||
|
|
134 | endif | |||
|
|
135 | endif | |||
|
|
136 | ||||
|
|
137 | # Add inputs and outputs from these tool invocations to the build variables | |||
|
|
138 | ||||
|
|
139 | # All Target | |||
|
|
140 | all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) | |||
|
|
141 | ||||
|
|
142 | $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) | |||
|
|
143 | @echo Building target: $@ | |||
|
|
144 | @echo Invoking: AVR/GNU Linker : 4.9.2 | |||
|
|
145 | $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" | |||
|
|
146 | @echo Finished building target: $@ | |||
|
|
147 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex" | |||
|
|
148 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0 | |||
|
|
149 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss" | |||
|
|
150 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec" | |||
|
|
151 | "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf" | |||
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152 | ||||
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153 | ||||
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154 | ||||
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155 | ||||
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156 | ||||
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157 | ||||
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158 | ||||
|
|
159 | # Other Targets | |||
|
|
160 | clean: | |||
|
|
161 | -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) | |||
|
|
162 | -$(RM) $(C_DEPS_AS_ARGS) | |||
|
|
163 | rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures" | |||
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164 | No newline at end of file | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | Ports.d Ports.o: .././Ports.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././Ports.h .././commSPI_ADC.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././Ports.h: | |||
|
|
41 | ||||
|
|
42 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,42 | |||||
|
|
1 | commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././commSPI_ADC.h .././Ports.h | |||
|
|
15 | ||||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
27 | ||||
|
|
28 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
39 | ||||
|
|
40 | .././commSPI_ADC.h: | |||
|
|
41 | ||||
|
|
42 | .././Ports.h: | |||
| @@ -0,0 +1,50 | |||||
|
|
1 | fpga_port.d fpga_port.o: .././fpga_port.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././fpga_port.h \ | |||
|
|
15 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ | |||
|
|
16 | .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
27 | ||||
|
|
28 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
39 | ||||
|
|
40 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
41 | ||||
|
|
42 | .././fpga_port.h: | |||
|
|
43 | ||||
|
|
44 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: | |||
|
|
45 | ||||
|
|
46 | .././ADC_7176_2.h: | |||
|
|
47 | ||||
|
|
48 | .././Ports.h: | |||
|
|
49 | ||||
|
|
50 | .././commSPI_ADC.h: | |||
| @@ -0,0 +1,52 | |||||
|
|
1 | main.d main.o: .././main.c \ | |||
|
|
2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
|
|
3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
|
|
4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
|
|
5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
|
|
6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
|
|
7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
|
|
8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
|
|
9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
|
|
10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
|
|
11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
|
|
12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
|
|
13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ | |||
|
|
14 | .././Ports.h .././sys_clock.h .././ADC_7176_2.h .././commSPI_ADC.h \ | |||
|
|
15 | .././fpga_port.h \ | |||
|
|
16 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h | |||
|
|
17 | ||||
|
|
18 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
|
|
19 | ||||
|
|
20 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
|
|
21 | ||||
|
|
22 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
|
|
23 | ||||
|
|
24 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
|
|
25 | ||||
|
|
26 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
|
|
27 | ||||
|
|
28 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
|
|
29 | ||||
|
|
30 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
|
|
31 | ||||
|
|
32 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
|
|
33 | ||||
|
|
34 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
|
|
35 | ||||
|
|
36 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
|
|
37 | ||||
|
|
38 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
|
|
39 | ||||
|
|
40 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
|
|
41 | ||||
|
|
42 | .././Ports.h: | |||
|
|
43 | ||||
|
|
44 | .././sys_clock.h: | |||
|
|
45 | ||||
|
|
46 | .././ADC_7176_2.h: | |||
|
|
47 | ||||
|
|
48 | .././commSPI_ADC.h: | |||
|
|
49 | ||||
|
|
50 | .././fpga_port.h: | |||
|
|
51 | ||||
|
|
52 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: | |||
| @@ -0,0 +1,16 | |||||
|
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1 | ################################################################################ | |||
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2 | # Automatically-generated file. Do not edit or delete the file | |||
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3 | ################################################################################ | |||
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4 | ||||
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5 | ADC_7176_2.c | |||
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6 | ||||
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7 | commSPI_ADC.c | |||
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8 | ||||
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9 | fpga_port.c | |||
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10 | ||||
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11 | main.c | |||
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12 | ||||
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13 | Ports.c | |||
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14 | ||||
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15 | sys_clock.c | |||
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16 | ||||
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1 | sys_clock.d sys_clock.o: .././sys_clock.c \ | |||
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2 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ | |||
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3 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ | |||
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4 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ | |||
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5 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ | |||
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6 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ | |||
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7 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ | |||
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8 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ | |||
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9 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ | |||
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10 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ | |||
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11 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ | |||
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12 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ | |||
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13 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h | |||
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14 | ||||
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15 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: | |||
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16 | ||||
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17 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: | |||
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18 | ||||
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19 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: | |||
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20 | ||||
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21 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: | |||
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22 | ||||
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23 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: | |||
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24 | ||||
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25 | C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: | |||
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26 | ||||
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27 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: | |||
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28 | ||||
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29 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: | |||
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30 | ||||
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31 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: | |||
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32 | ||||
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33 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: | |||
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34 | ||||
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35 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: | |||
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36 | ||||
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37 | c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: | |||
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1 | /* | |||
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2 | * Ports.c | |||
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3 | * | |||
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4 | * Created: 23/11/15 13:57:48 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | /*! | |||
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9 | * \fn config_puertos | |||
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10 | * \brief Configuraci�n de todos los pines de I/O a usarse | |||
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11 | * para la prueba. Para el firmware final se deben dejar de configurar en este segmento | |||
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12 | * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo. | |||
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13 | * Los criterios de asignaci�n de control: | |||
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14 | * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si | |||
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15 | * Se sabe que la entrada ser� casi siempre alta. | |||
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16 | * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si | |||
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17 | * Se sabe que la entrada ser� casi siempre baja. | |||
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18 | * WiredAndpull: Para evitar cortos de una salida al exterior del board. | |||
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19 | * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board). | |||
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20 | * \ | |||
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21 | */ | |||
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22 | ||||
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23 | #define F_CPU 32000000UL | |||
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24 | #include <avr/io.h> | |||
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25 | ||||
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26 | #include "Ports.h" | |||
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27 | #include "commSPI_ADC.h" | |||
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28 | ||||
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29 | inline void config_puertos(void){ | |||
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30 | //Configuracion pines del puerto A: PA7-PA0 | |||
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31 | //Pines de entrada y totem_pullup | |||
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32 | PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; | |||
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33 | PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
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34 | PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; | |||
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35 | PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; | |||
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36 | PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; | |||
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37 | PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
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38 | PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
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39 | PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
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40 | //Pin de salida A0 | |||
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41 | //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n | |||
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42 | //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta | |||
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43 | //Valor por defecto salida: PA0 = low | |||
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44 | PORTA.DIRSET = PIN0_bm; | |||
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45 | PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
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46 | PORTA.OUTCLR = PIN0_bm; | |||
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47 | ||||
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48 | //Configuracion pines del puerto B: PB3-PB0 | |||
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49 | //Pines de entrada y totem_pullup | |||
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50 | PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; | |||
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51 | PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
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52 | PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
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53 | PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
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54 | PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
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55 | ||||
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56 | //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI | |||
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57 | //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 | |||
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58 | //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. | |||
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59 | PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C | |||
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60 | PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; | |||
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61 | PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
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62 | PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
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63 | PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
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64 | PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
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65 | //Pines de salida wiredand-pull | |||
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66 | //Valor por defecto salida: PC4,PC7 = low | |||
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67 | //Valor por defecto salida: PC5 = set | |||
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68 | PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; | |||
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69 | PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; | |||
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70 | PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; | |||
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71 | PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; | |||
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72 | PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; | |||
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73 | PORTSPI.OUTCLR = SPI_MOSI_bm; | |||
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74 | ||||
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75 | //Configuracion pines del puerto D: PD7-PD0 | |||
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76 | //Pines de entrada y totem_pullup: PIN7 y PIN0 | |||
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77 | //NOTA | |||
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78 | //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO | |||
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79 | //NOTA FIN | |||
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80 | PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
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81 | PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; | |||
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82 | PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
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83 | //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga | |||
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84 | PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; | |||
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85 | PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
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86 | //Pines de salida tipo wired-and-pull | |||
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87 | //Valor por defecto PD6, PD5, PD4, PD3 = low | |||
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88 | PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
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89 | PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
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90 | PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
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91 | PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
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92 | PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; | |||
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93 | PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; | |||
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94 | ||||
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95 | //Configuracion pines del puerto E: PE3-PE0 | |||
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96 | //Pines de entrada y totem_pullup: PIN3 - PIN0 | |||
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97 | PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; | |||
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98 | PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; | |||
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99 | PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; | |||
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100 | PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; | |||
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101 | PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
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102 | ||||
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103 | //Configuracion pines del puerto R: PR1-PR0 | |||
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104 | //Pines de entrada y totem_pulldown: PIN0 | |||
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105 | PORTR.DIRCLR = PIN1_bm| PIN0_bm; | |||
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106 | PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; | |||
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107 | //Pines de entrada y totem_pulldup:PIN1 | |||
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108 | PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; | |||
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109 | ||||
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110 | //Configuraci�n como interrupci�n del pin SPI_MISO_RDY | |||
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111 | ||||
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112 | PORTSPI.INT0MASK = SPI_MISO_bm; | |||
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113 | PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; | |||
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114 | PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
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115 | ||||
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116 | } No newline at end of file | |||
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1 | /* | |||
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2 | * Ports.h | |||
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3 | * | |||
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4 | * Created: 23/11/15 13:55:28 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | ||||
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9 | #ifndef PORTS_H_ | |||
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10 | #define PORTS_H_ | |||
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11 | ||||
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12 | #define F_CPU 32000000UL | |||
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13 | #include <avr/io.h> | |||
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14 | ||||
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15 | #define INT_RDY PORTC_INT0_vect | |||
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16 | ||||
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17 | void config_puertos(void); | |||
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18 | ||||
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19 | ||||
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20 | ||||
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21 | #endif /* PORTS_H_ */ No newline at end of file | |||
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1 | /* | |||
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2 | * commSPI_ADC.c | |||
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3 | * | |||
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4 | * Created: 23/11/15 14:08:25 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | ||||
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9 | #define F_CPU 32000000UL | |||
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10 | #include <avr/io.h> | |||
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11 | #include "commSPI_ADC.h" | |||
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12 | ||||
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13 | /*! | |||
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14 | * \fn config_spiparm | |||
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15 | * \brief Configuraci�n de los par�metros de reloj SPI | |||
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16 | * | |||
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17 | * fspi = fper/2 = fcpu/2 = 16MHz | |||
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18 | * | |||
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19 | * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una | |||
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20 | * nueva evaluaci�n | |||
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21 | * \ | |||
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22 | */ | |||
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23 | inline void config_spiparm(void){ | |||
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24 | // Preescaler: clkper/2 = f_cpu/2. | |||
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25 | // Master | |||
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26 | // Mode 3: CPOL=1,CPHA=1 | |||
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27 | // MSB --- LSB | |||
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28 | SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | | |||
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29 | SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm; | |||
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30 | } | |||
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31 | ||||
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1 | /* | |||
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2 | * commSPI_ADC.h | |||
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3 | * | |||
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4 | * Created: 23/11/15 14:06:45 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | ||||
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9 | #ifndef COMMSPI_ADC_H_ | |||
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10 | #define COMMSPI_ADC_H_ | |||
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11 | ||||
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12 | #define F_CPU 32000000UL | |||
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13 | #include <avr/io.h> | |||
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14 | ||||
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15 | #include "Ports.h" | |||
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16 | ||||
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17 | #define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI | |||
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18 | ||||
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19 | #define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS | |||
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20 | #define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI | |||
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21 | #define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO | |||
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22 | #define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK | |||
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23 | ||||
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24 | #define SPI_SS_bm PIN4_bm // Pin de entrada - Totem | |||
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25 | #define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem | |||
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26 | #define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem | |||
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27 | #define SPI_SCK_bm PIN7_bm // Pin de salida - Totem | |||
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28 | ||||
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29 | void config_spiparm(void); | |||
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30 | ||||
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31 | ||||
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32 | #endif /* COMMSPI_ADC_H_ */ No newline at end of file | |||
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1 | /* | |||
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2 | * fpga_port.c | |||
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3 | * | |||
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4 | * Created: 23/11/15 14:33:16 | |||
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5 | * Author: Francisco | |||
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6 | */ | |||
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7 | ||||
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8 | #define F_CPU 32000000UL | |||
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9 | #include <avr/io.h> | |||
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10 | ||||
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11 | #include "fpga_port.h" | |||
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12 | ||||
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13 | inline void config_fpgaport() | |||
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14 | { | |||
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15 | //Configuracion pines del puerto D: PD6-PA1 | |||
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16 | //Pines de entrada CLK_FPGA, LOCK_FPGA | |||
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17 | //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
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18 | PORT_FPGA.DIRCLR = LOCK_FPGA; | |||
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19 | PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; | |||
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20 | PORT_FPGA.DIRSET = CLK_FPGA; | |||
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21 | PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; | |||
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22 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
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23 | ||||
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24 | //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA | |||
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25 | PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
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26 | PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; | |||
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27 | PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; | |||
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28 | ||||
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29 | //Configuracion pines del puerto B: PPS | |||
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30 | //Pines de entrada PPS_FPGA | |||
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31 | //Pines de entrada en pulldown | |||
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32 | PORT_PPS.DIRCLR = PPS_FPGA; | |||
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33 | PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; | |||
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34 | ||||
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35 | //Configuracion pines del puerto A: LOCKOUT | |||
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36 | //Pines de salida LOCK_OUT | |||
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37 | //Pines de salida en baja | |||
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38 | PORT_LOCKOUT.DIRSET = LOCK_OUT; | |||
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39 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
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40 | ||||
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41 | ||||
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42 | ||||
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43 | //Configuracion de interrupciones de LOCK_FPGA | |||
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44 | ||||
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45 | PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; | |||
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46 | PORT_FPGA.INT0MASK = LOCK_FPGA; | |||
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47 | PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; | |||
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48 | ||||
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49 | //Configuracion de interrupciones de CLK | |||
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|
50 | //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
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51 | //PORT_FPGA.INT1MASK = CLK_FPGA; | |||
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52 | //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; | |||
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53 | ||||
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54 | //Configuracion de interrupciones de PPS | |||
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55 | PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; | |||
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56 | PORT_PPS.INT1MASK = PPS_FPGA; | |||
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57 | PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; | |||
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58 | } | |||
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59 | ||||
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60 | void habilitar_interrupciones( uint8_t level_mask ) | |||
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61 | { | |||
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62 | PMIC.CTRL |= level_mask; | |||
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63 | } | |||
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64 | ||||
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65 | void habilitar_interrupciones_globales( void ) | |||
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66 | { | |||
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67 | sei(); | |||
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68 | } | |||
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69 | ||||
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70 | void deshabilitar_interrupciones_globales( void ) | |||
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71 | { | |||
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72 | cli(); | |||
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73 | } | |||
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74 | ||||
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75 | void envio_nibble(uint8_t fpga_dato) | |||
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76 | { | |||
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77 | //Nibble superior 8 a 4 | |||
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78 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
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79 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) >> fpga_salidas_nibblealto_bp); | |||
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80 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
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81 | //asm("nop"); | |||
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82 | //Nibble inferior 3 a 0 | |||
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83 | PORT_FPGA.OUTCLR = CLK_FPGA; | |||
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84 | PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_nibblebajo_bp); | |||
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85 | PORT_FPGA.OUTSET = CLK_FPGA; | |||
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86 | ||||
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|
87 | } | |||
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|
88 | ||||
|
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89 | void envio_datos_fpga(void) | |||
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90 | { | |||
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91 | uint8_t fpga_dato[ADC_DATASZ] ; | |||
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92 | //uint8_t aux_dato[ADC_DATASZ] ; | |||
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93 | ||||
|
|
94 | adcport_read_data(fpga_dato,ADC_DATASZ); | |||
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95 | //aux_dato[0] = fpga_dato[0]; | |||
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96 | //aux_dato[1] = fpga_dato[1]; | |||
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97 | //aux_dato[2] = fpga_dato[2]; | |||
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98 | //adcport_read_data(fpga_dato,ADC_DATASZ); | |||
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99 | ||||
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100 | //envio_dato_adc(aux_dato); | |||
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101 | envio_dato_adc(fpga_dato); | |||
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102 | } | |||
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103 | ||||
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104 | void envio_dato_adc(uint8_t* dato_adc) | |||
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105 | { | |||
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106 | for(int i=0; i<ADC_DATASZ ; i++) | |||
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107 | envio_nibble(dato_adc[i]); | |||
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108 | } | |||
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109 | /* | |||
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110 | __attribute__((noinline)) void delay_nop(void) | |||
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111 | { | |||
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112 | asm("nop"); | |||
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|
113 | } | |||
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114 | */ | |||
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115 | ||||
| @@ -0,0 +1,69 | |||||
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1 | /* | |||
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|
2 | * fpga_port.h | |||
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|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:20:25 | |||
|
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5 | * Author: Francisco | |||
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|
6 | */ | |||
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|
7 | ||||
|
|
8 | ||||
|
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9 | #ifndef FPGA_PORT_H_ | |||
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10 | #define FPGA_PORT_H_ | |||
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11 | ||||
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12 | #define F_CPU 32000000UL | |||
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13 | #include <avr/io.h> | |||
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14 | #include <avr/interrupt.h> | |||
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15 | #include "ADC_7176_2.h" | |||
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|
16 | ||||
|
|
17 | //Port B | |||
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|
18 | #define PORT_PPS PORTB | |||
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19 | #define PPS_FPGA PIN2_bm | |||
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20 | #define PPS_FPGA_CTRL PIN2CTRL | |||
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21 | #define INT_PPS PORTB_INT1_vect | |||
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22 | ||||
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|
23 | //Port A | |||
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|
24 | #define PORT_LOCKOUT PORTA | |||
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25 | #define LOCK_OUT PIN0_bm | |||
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26 | ||||
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27 | ||||
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28 | //Port D | |||
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|
29 | #define PORT_FPGA PORTD | |||
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|
30 | #define LOCK_FPGA PIN1_bm | |||
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|
31 | #define CLK_FPGA PIN2_bm | |||
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32 | #define CH_BIT0_FPGA PIN3_bm | |||
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33 | #define CH_BIT1_FPGA PIN4_bm | |||
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34 | #define CH_BIT2_FPGA PIN5_bm | |||
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35 | #define CH_BIT3_FPGA PIN6_bm | |||
|
|
36 | #define INT_LOCK_FPGA PORTD_INT0_vect | |||
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|
37 | ||||
|
|
38 | #define LOCK_FPGA_CTRL PIN1CTRL | |||
|
|
39 | #define CLK_FPGA_CTRL PIN2CTRL | |||
|
|
40 | #define CH_BIT0_FPGA_CTRL PIN3CTRL | |||
|
|
41 | #define CH_BIT1_FPGA_CTRL PIN4CTRL | |||
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|
42 | #define CH_BIT2_FPGA_CTRL PIN5CTRL | |||
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43 | #define CH_BIT3_FPGA_CTRL PIN6CTRL | |||
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44 | ||||
|
|
45 | void config_fpgaport(); | |||
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46 | void habilitar_interrupciones( uint8_t level_mask ); | |||
|
|
47 | void habilitar_interrupciones_globales( ); | |||
|
|
48 | void deshabilitar_interrupciones_globales( ); | |||
|
|
49 | ||||
|
|
50 | //Habilitar | |||
|
|
51 | #define hab_prioridad_alta PMIC_HILVLEN_bm | |||
|
|
52 | #define hab_prioridad_media PMIC_MEDLVLEN_bm | |||
|
|
53 | #define hab_prioridad_baja PMIC_LOLVLEN_bm | |||
|
|
54 | ||||
|
|
55 | //M�scara de nibbles | |||
|
|
56 | #define nibble_alto_bm 0xF0 | |||
|
|
57 | #define nibble_bajo_bm 0x0F | |||
|
|
58 | #define fpga_salidas_nibblealto_bp 1 | |||
|
|
59 | #define fpga_salidas_nibblebajo_bp 3 | |||
|
|
60 | #define fpga_salidas_bm 0x87 | |||
|
|
61 | ||||
|
|
62 | //funciones de env�o de datos | |||
|
|
63 | void envio_nibble(uint8_t fpga_dato); | |||
|
|
64 | ||||
|
|
65 | //funcion interrupcion por flanco de subida de RDY | |||
|
|
66 | void envio_datos_fpga(void); | |||
|
|
67 | void envio_dato_adc(uint8_t* dato_adc); | |||
|
|
68 | ||||
|
|
69 | #endif /* FPGA_PORT_H_ */ No newline at end of file | |||
| @@ -0,0 +1,83 | |||||
|
|
1 | /* | |||
|
|
2 | * ADCSPI_ver01.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 26/10/15 12:02:22 | |||
|
|
5 | * Author : Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | #define F_CPU 32000000UL | |||
|
|
9 | #include <avr/io.h> | |||
|
|
10 | #include "Ports.h" | |||
|
|
11 | //#include "commSPI_ADC.h" | |||
|
|
12 | #include "sys_clock.h" | |||
|
|
13 | #include "ADC_7176_2.h" | |||
|
|
14 | #include "fpga_port.h" | |||
|
|
15 | ||||
|
|
16 | ||||
|
|
17 | int main(void) | |||
|
|
18 | { | |||
|
|
19 | //uint8_t datos_adc[3]; | |||
|
|
20 | config_puertos(); | |||
|
|
21 | config_sysclock(); | |||
|
|
22 | config_spiparm(); | |||
|
|
23 | config_fpgaport(); | |||
|
|
24 | config_adc(); | |||
|
|
25 | //datos_adc[0] = 0x00; | |||
|
|
26 | //datos_adc[1] = 0x00; | |||
|
|
27 | //datos_adc[2] = 0x00; | |||
|
|
28 | //PORTD.OUTSET = PIN5_bm; | |||
|
|
29 | ||||
|
|
30 | PMIC.CTRL = hab_prioridad_alta; | |||
|
|
31 | habilitar_interrupciones_globales(); | |||
|
|
32 | ||||
|
|
33 | /* Replace with your application code */ | |||
|
|
34 | while (1) | |||
|
|
35 | { | |||
|
|
36 | if (test_adc() == ADC_ID){ | |||
|
|
37 | PORTD.OUTSET = PIN6_bm | PIN5_bm; | |||
|
|
38 | } | |||
|
|
39 | ||||
|
|
40 | //test_adc_2(datos_adc); | |||
|
|
41 | //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){ | |||
|
|
42 | //PORTD.OUTSET = PIN4_bm; | |||
|
|
43 | //} | |||
|
|
44 | } | |||
|
|
45 | return 0; | |||
|
|
46 | } | |||
|
|
47 | ||||
|
|
48 | ||||
|
|
49 | ISR(INT_LOCK_FPGA) | |||
|
|
50 | { | |||
|
|
51 | if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) | |||
|
|
52 | { | |||
|
|
53 | PMIC.CTRL |= hab_prioridad_media; | |||
|
|
54 | PORT_LOCKOUT.OUTSET = LOCK_OUT; | |||
|
|
55 | PORTD.OUTSET = PIN4_bm; | |||
|
|
56 | } | |||
|
|
57 | else | |||
|
|
58 | { | |||
|
|
59 | PMIC.CTRL &= ~hab_prioridad_media; | |||
|
|
60 | PMIC.CTRL &= ~hab_prioridad_baja; | |||
|
|
61 | PORT_LOCKOUT.OUTCLR = LOCK_OUT; | |||
|
|
62 | PORTSPI.OUTSET = SPI_SS_bm; | |||
|
|
63 | } | |||
|
|
64 | } | |||
|
|
65 | ||||
|
|
66 | //Interrupcion por flanco de subida de PPS | |||
|
|
67 | //Habilito interrupciones de prioridad baja | |||
|
|
68 | //Selecciono el chip del ADC para iniciar comunicaci�n. | |||
|
|
69 | //Al iniciar esta comunicaci�n se indicar� al ADC que use el RDYbar | |||
|
|
70 | //Esta ser� nuestra interrupci�n para lectura del ADC y env�o de dato a la FPGA | |||
|
|
71 | ISR(INT_PPS) | |||
|
|
72 | { | |||
|
|
73 | PMIC.CTRL |= hab_prioridad_baja; | |||
|
|
74 | PORTSPI.OUTCLR = SPI_SS_bm; | |||
|
|
75 | } | |||
|
|
76 | ||||
|
|
77 | ISR(INT_RDY) | |||
|
|
78 | { | |||
|
|
79 | envio_datos_fpga(); | |||
|
|
80 | } | |||
|
|
81 | ||||
|
|
82 | ||||
|
|
83 | ||||
| @@ -0,0 +1,53 | |||||
|
|
1 | /* | |||
|
|
2 | * sys_clock.c | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:04:36 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | /*! | |||
|
|
10 | * \fn config_sysclock | |||
|
|
11 | * \brief Configuraci�n del reloj interno del sistema | |||
|
|
12 | * Reloj interno | |||
|
|
13 | * fsys = 32MHz | |||
|
|
14 | * | |||
|
|
15 | * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL | |||
|
|
16 | * \ | |||
|
|
17 | */ | |||
|
|
18 | ||||
|
|
19 | #define F_CPU 32000000UL | |||
|
|
20 | #include <avr/io.h> | |||
|
|
21 | ||||
|
|
22 | void config_sysclock(void){ | |||
|
|
23 | ||||
|
|
24 | CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1 | |||
|
|
25 | OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; /* Enable the internal 32MHz & 32KHz oscillators */ | |||
|
|
26 | while(!(OSC.STATUS & OSC_RC32KRDY_bm)); /* Wait for 32Khz oscillator to stabilize */ | |||
|
|
27 | while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */ | |||
|
|
28 | DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ | |||
|
|
29 | OSC.DFLLCTRL &= 0xFD; //Habilito calibraci�n interna mediante reloj de 32K | |||
|
|
30 | CCP = CCP_IOREG_gc; /* Disable register security for clock update */ | |||
|
|
31 | CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */ | |||
|
|
32 | OSC.CTRL &= ~OSC_RC2MEN_bm; | |||
|
|
33 | ||||
|
|
34 | /* | |||
|
|
35 | CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1 | |||
|
|
36 | OSC_XOSCCTRL = OSC_XOSCSEL_EXTCLK_gc; //usar external clock | |||
|
|
37 | ||||
|
|
38 | OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | ( 0x02 & OSC_PLLFAC_gm); | |||
|
|
39 | ||||
|
|
40 | OSC_CTRL |= OSC_PLLEN_bm; //usar external clock | |||
|
|
41 | while(!(OSC_STATUS & OSC_XOSCRDY_bm)); | |||
|
|
42 | while(!(OSC_STATUS & OSC_PLLRDY_bm)); | |||
|
|
43 | ||||
|
|
44 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
45 | CLK_CTRL = (CLK_SCLKSEL_PLL_gc) & CLK_SCLKSEL_gm; //CLK usa oscilador externo | |||
|
|
46 | ||||
|
|
47 | OSC_CTRL &= ~OSC_RC2MEN_bm; | |||
|
|
48 | ||||
|
|
49 | CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro | |||
|
|
50 | OSC_XOSCFAIL = (OSC_PLLFDEN_bm)|(OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de | |||
|
|
51 | */ | |||
|
|
52 | ||||
|
|
53 | } No newline at end of file | |||
| @@ -0,0 +1,20 | |||||
|
|
1 | /* | |||
|
|
2 | * sys_clock.h | |||
|
|
3 | * | |||
|
|
4 | * Created: 23/11/15 14:03:16 | |||
|
|
5 | * Author: Francisco | |||
|
|
6 | */ | |||
|
|
7 | ||||
|
|
8 | ||||
|
|
9 | #ifndef SYS_CLOCK_H_ | |||
|
|
10 | #define SYS_CLOCK_H_ | |||
|
|
11 | ||||
|
|
12 | ||||
|
|
13 | #define F_CPU 32000000UL | |||
|
|
14 | #include <avr/io.h> | |||
|
|
15 | ||||
|
|
16 | void config_sysclock(void); | |||
|
|
17 | ||||
|
|
18 | ||||
|
|
19 | ||||
|
|
20 | #endif /* SYS_CLOCK_H_ */ No newline at end of file | |||
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