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1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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2 <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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3
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4 <!-- -->
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5
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6 <!-- For tool use only. Do not edit. -->
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7
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8 <!-- -->
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9
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10 <!-- ProjectNavigator created generated project file. -->
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11
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12 <!-- For use in tracking generated file and other information -->
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13
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14 <!-- allowing preservation of process status. -->
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15
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16 <!-- -->
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17
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18 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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19
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20 <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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21
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22 <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Controlador_Mem_RAM.xise"/>
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23
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24 <files xmlns="http://www.xilinx.com/XMLSchema"/>
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25
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26 <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
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27
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28 </generated_project> No newline at end of file
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1 ----------------------------------------------------------------------------------
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2 -- Company:
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3 -- Engineer:
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4 --
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5 -- Create Date: 16:52:35 12/09/2015
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6 -- Design Name:
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7 -- Module Name: Controlador_Mem_RAM - Behavioral
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8 -- Project Name:
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9 -- Target Devices:
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10 -- Tool versions:
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11 -- Description:
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12 --
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13 -- Dependencies:
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14 --
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15 -- Revision:
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16 -- Revision 0.01 - File Created
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17 -- Additional Comments:
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18 --
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19 ----------------------------------------------------------------------------------
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20 library IEEE;
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21 use IEEE.STD_LOGIC_1164.ALL;
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22
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23 -- Uncomment the following library declaration if using
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24 -- arithmetic functions with Signed or Unsigned values
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25 --use IEEE.NUMERIC_STD.ALL;
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26
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27 -- Uncomment the following library declaration if instantiating
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28 -- any Xilinx primitives in this code.
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29 --library UNISIM;
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30 --use UNISIM.VComponents.all;
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31
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32 entity Controlador_Mem_RAM is
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33 GENERIC(
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34 num_ch: INTEGER :=3;
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35 id_ch_lenght: INTEGER :=3;
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36 data_lenght: INTEGER :=24;
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37 id_data_lenght: INTEGER :=1 --Para 250ksp deben ser 18 bits
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38 );
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39
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40 PORT(
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41 clk: IN STD_LOGIC;
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42 rdy_ch1: IN STD_LOGIC_VECTOR((num_ch-1) downto 0);
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43 start_sender: IN STD_LOGIC;
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44 sum: IN STD_LOGIC_VECTOR(13 downto 0);
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45 serial_output: OUT STD_LOGIC
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46 );
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47 end Controlador_Mem_RAM;
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48
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49 architecture Behavioral of Controlador_Mem_RAM is
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50
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51 begin
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52
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53
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54 end Behavioral;
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55 No newline at end of file
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1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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2 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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3
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4 <header>
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5 <!-- ISE source project file created by Project Navigator. -->
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6 <!-- -->
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7 <!-- This file contains project source information including a list of -->
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8 <!-- project source files, project and process properties. This file, -->
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9 <!-- along with the project source files, is sufficient to open and -->
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10 <!-- implement in ISE Project Navigator. -->
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11 <!-- -->
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12 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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13 </header>
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14
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15 <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
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16
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17 <files>
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18 <file xil_pn:name="Controlador_Mem_RAM.vhd" xil_pn:type="FILE_VHDL">
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19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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20 <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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21 </file>
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22 </files>
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23
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34 <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
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35 <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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36 <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
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37 <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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38 <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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39 <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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40 <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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43 <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
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44 <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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45 <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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46 <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
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47 <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
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48 <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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49 <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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52 <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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53 <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
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54 <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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55 <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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56 <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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57 <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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58 <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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59 <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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60 <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
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61 <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
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62 <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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63 <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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64 <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
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65 <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
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66 <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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67 <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
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68 <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
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69 <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
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70 <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
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71 <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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72 <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
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73 <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
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74 <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
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75 <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
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76 <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
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77 <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
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78 <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
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79 <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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80 <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
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81 <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
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82 <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
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83 <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
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84 <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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85 <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
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86 <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
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87 <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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88 <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
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89 <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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90 <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
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91 <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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92 <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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93 <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
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94 <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
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95 <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
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96 <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
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97 <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
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100 <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
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101 <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
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102 <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
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103 <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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104 <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
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105 <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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109 <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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112 <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
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113 <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
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116 <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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117 <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
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118 <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
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123 <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
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127 <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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128 <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
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133 <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
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134 <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
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136 <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
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138 <property xil_pn:name="Implementation Top File" xil_pn:value="Controlador_Mem_RAM.vhd" xil_pn:valueState="non-default"/>
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175 <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
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181 <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
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185 <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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186 <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
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187 <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
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189 <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
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190 <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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191 <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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192 <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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193 <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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194 <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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195 <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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196 <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
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198 <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
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200 <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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201 <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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202 <property xil_pn:name="Output File Name" xil_pn:value="Controlador_Mem_RAM" xil_pn:valueState="default"/>
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203 <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
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206 <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
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208 <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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211 <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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212 <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
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214 <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
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215 <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_map.vhd" xil_pn:valueState="default"/>
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216 <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_timesim.vhd" xil_pn:valueState="default"/>
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217 <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_synthesis.vhd" xil_pn:valueState="default"/>
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218 <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_translate.vhd" xil_pn:valueState="default"/>
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219 <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
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220 <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
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222 <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
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223 <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
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224 <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
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225 <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
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226 <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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227 <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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228 <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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229 <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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230 <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
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231 <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
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232 <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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235 <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
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236 <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
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239 <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
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240 <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Controlador_Mem_RAM" xil_pn:valueState="default"/>
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241 <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
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252 <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
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253 <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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254 <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
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255 <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
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261 <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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262 <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
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263 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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267 <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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268 <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
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269 <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
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270 <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
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271 <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
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272 <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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273 <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
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279 <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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280 <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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282 <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
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283 <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
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284 <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
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285 <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
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286 <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
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287 <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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288 <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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289 <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
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290 <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
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291 <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
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292 <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
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293 <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
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294 <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
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295 <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
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296 <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
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297 <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
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298 <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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299 <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
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300 <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
No newline at end of file
301 <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
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302 <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
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303 <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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304 <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
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305 <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
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306 <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
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307 <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
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308 <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
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309 <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
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310 <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
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311 <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
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312 <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
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313 <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
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314 <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
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315 <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
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316 <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
No newline at end of file
317 <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
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1 <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
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5 <TD ALIGN=CENTER COLSPAN='4'><B>Controlador_Mem_RAM Project Status</B></TD></TR>
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7 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
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8 <TD>Controlador_Mem_RAM.xise</TD>
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9 <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
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10 <TD> No Errors </TD>
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13 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
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14 <TD>Controlador_Mem_RAM</TD>
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15 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
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16 <TD>New</TD>
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20 <TD>xc6slx9-3tqg144</TD>
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21 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
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22 <TD>&nbsp;</TD>
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25 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
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26 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
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27 <TD>&nbsp;</TD>
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30 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
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31 <TD>Balanced</TD>
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33 <TD>
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34 &nbsp;</TD>
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37 <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
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78 <br><center><b>Date Generated:</b> 12/10/2015 - 08:38:12</center>
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59 <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
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60 <toc-item title="HDL Compilation" target=" HDL Compilation " />
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61 <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
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62 <toc-item title="HDL Analysis" target=" HDL Analysis " />
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63 <toc-item title="HDL Parsing" target=" HDL Parsing " />
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64 <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
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65 <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
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69 <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
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70 <toc-item title="Partition Report" target=" Partition Report " />
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71 <toc-item title="Final Report" target=" Final Report " />
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72 <toc-item title="Design Summary" target=" Design Summary " />
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73 <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
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74 <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
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75 <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
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76 <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
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77 <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
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78 <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
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79 <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
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80 <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
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81 <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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82 </view>
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83 <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="Controlador_Mem_RAM.srr" label="Synplify Report" />
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85 <view inputState="Synthesized" program="ngdbuild" type="Report" file="Controlador_Mem_RAM.bld" label="Translation Report" >
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86 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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87 <toc-item title="Command Line" target="Command Line:" />
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88 <toc-item title="Partition Status" target="Partition Implementation Status" />
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89 <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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90 </view>
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91 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM_map.mrp" label="Map Report" >
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92 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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93 <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
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94 <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
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95 <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
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96 <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
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97 <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
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98 <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
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99 <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
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100 <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
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101 <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
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102 <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
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103 <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
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104 <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
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105 <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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106 </view>
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107 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM.par" label="Place and Route Report" >
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108 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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109 <toc-item title="Device Utilization" target="Device Utilization Summary:" />
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110 <toc-item title="Router Information" target="Starting Router" />
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111 <toc-item title="Partition Status" target="Partition Implementation Status" />
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112 <toc-item title="Clock Report" target="Generating Clock Report" />
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113 <toc-item title="Timing Results" target="Timing Score:" />
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114 <toc-item title="Final Summary" target="Peak Memory Usage:" />
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115 </view>
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116 <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM.twr" label="Post-PAR Static Timing Report" >
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117 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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118 <toc-item title="Timing Report Description" target="Device,package,speed:" />
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119 <toc-item title="Informational Messages" target="INFO:" />
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120 <toc-item title="Warning Messages" target="WARNING:" />
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121 <toc-item title="Timing Constraints" target="Timing constraint:" />
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122 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
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123 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
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124 <toc-item title="Timing Summary" target="Timing summary:" />
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126 </view>
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127 <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Controlador_Mem_RAM.rpt" label="CPLD Fitter Report (Text)" >
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128 <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
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129 <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
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130 <toc-item title="Pin Resources" target="** Pin Resources **" />
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131 <toc-item title="Global Resources" target="** Global Control Resources **" />
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132 </view>
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133 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Controlador_Mem_RAM.tim" label="CPLD Timing Report (Text)" >
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134 <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
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135 <toc-item title="Performance Summary" target="Performance Summary:" />
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136 </view>
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137 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="Controlador_Mem_RAM.pwr" label="Power Report" >
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138 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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139 <toc-item title="Power summary" target="Power summary" />
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140 <toc-item title="Thermal summary" target="Thermal summary" />
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144 <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
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145 <toc-item title="Final Summary" target="DRC detected" />
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146 </view>
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147 </viewgroup>
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148 <viewgroup label="Secondary Reports" >
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151 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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152 </view>
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153 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/Controlador_Mem_RAM_translate.nlf" label="Post-Translate Simulation Model Report" >
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154 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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155 </view>
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156 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
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158 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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159 <toc-item title="Design Information" target="Design Information" />
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160 <toc-item title="Design Summary" target="Design Summary" />
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161 </view>
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164 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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165 <toc-item title="Timing Report Description" target="Device,package,speed:" />
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166 <toc-item title="Informational Messages" target="INFO:" />
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167 <toc-item title="Warning Messages" target="WARNING:" />
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168 <toc-item title="Timing Constraints" target="Timing constraint:" />
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169 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
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170 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
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171 <toc-item title="Timing Summary" target="Timing summary:" />
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172 <toc-item title="Trace Settings" target="Trace Settings:" />
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174 <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/Controlador_Mem_RAM_map.nlf" label="Post-Map Simulation Model Report" />
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175 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_map.psr" label="Physical Synthesis Report" >
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176 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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177 </view>
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178 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="Controlador_Mem_RAM_pad.txt" label="Pad Report" >
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179 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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180 </view>
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181 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Controlador_Mem_RAM.unroutes" label="Unroutes Report" >
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182 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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183 </view>
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184 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_preroute.tsi" label="Post-Map Constraints Interaction Report" >
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185 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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186 </view>
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187 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.grf" label="Guide Results Report" />
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188 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.dly" label="Asynchronous Delay Report" />
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189 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.clk_rgn" label="Clock Region Report" />
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190 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.tsi" label="Post-Place and Route Constraints Interaction Report" >
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191 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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192 </view>
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193 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
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194 <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/Controlador_Mem_RAM_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
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195 <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_sta.nlf" label="Primetime Netlist Report" >
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196 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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197 </view>
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198 <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.ibs" label="IBIS Model" >
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199 <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
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200 <toc-item title="Component" target="Component " />
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201 </view>
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202 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.lck" label="Back-annotate Pin Report" >
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203 <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
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204 <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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205 </view>
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206 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.lpc" label="Locked Pin Constraints" >
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207 <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
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208 <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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209 </view>
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210 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/Controlador_Mem_RAM_timesim.nlf" label="Post-Fit Simulation Model Report" />
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213 </viewgroup>
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214 </body>
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215 </report-views> No newline at end of file
@@ -0,0 +1,37
1 Release 14.7 ngdbuild P.20131013 (nt64)
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2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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3
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4 Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
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5 -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 BloqueRAM_int.ngc
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6 BloqueRAM_int.ngd
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7
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8 Reading NGO file
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9 "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SR
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10 AM_16kb_v02/BloqueRAM_int.ngc" ...
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11 Gathering constraint information from source properties...
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12 Done.
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13
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14 Resolving constraint associations...
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15 Checking Constraint Associations...
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16 Done...
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17
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18 Checking expanded design ...
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19
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20 Partition Implementation Status
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21 -------------------------------
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22
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23 No Partitions were found in this design.
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24
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25 -------------------------------
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26
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27 NGDBUILD Design Results Summary:
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28 Number of errors: 0
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29 Number of warnings: 0
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30
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31 Total memory usage is 173092 kilobytes
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32
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33 Writing NGD file "BloqueRAM_int.ngd" ...
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34 Total REAL time to NGDBUILD completion: 4 sec
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35 Total CPU time to NGDBUILD completion: 3 sec
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36
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37 Writing NGDBUILD log file "BloqueRAM_int.bld"... No newline at end of file
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1 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SRAM_16kb_v02/BloqueRAM_int.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SRAM_16kb_v02/BloqueRAM_int.syr"
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2 ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 BloqueRAM_int.ngc BloqueRAM_int.ngd
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3 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd BloqueRAM_int.pcf
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4 par -w -intstyle ise -ol high -mt off BloqueRAM_int_map.ncd BloqueRAM_int.ncd BloqueRAM_int.pcf
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5 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr BloqueRAM_int.pcf No newline at end of file
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1 work No newline at end of file
@@ -0,0 +1,3
1 XILINX-XDB 0.1 STUB 0.1 ASCII
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2 XILINX-XDM V1.6
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2 XILINX-XDM V1.6e
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1 Release 14.7 - par P.20131013 (nt64)
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2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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3
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4 Mon Dec 14 11:39:10 2015
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5
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6
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7 # NOTE: This file is designed to be imported into a spreadsheet program
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8 # such as Microsoft Excel for viewing, printing and sorting. The |
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9 # character is used as the data field separator. This file is also designed
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10 # to support parsing.
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11 #
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12 INPUT FILE: BloqueRAM_int_map.ncd
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13 OUTPUT FILE: BloqueRAM_int.pad
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14 PART TYPE: xc6slx9
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15 SPEED GRADE: -3
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16 PACKAGE: tqg144
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17
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18 Pinout by Pin Number:
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19
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20 -----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
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21 Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
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22 P1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
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23 P2||IOBM|IO_L83P_3|UNUSED||3|||||||||
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24 P3|||GND||||||||||||
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25 P4|||VCCO_3|||3|||||any******||||
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26 P5||IOBS|IO_L52N_3|UNUSED||3|||||||||
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27 P6||IOBM|IO_L52P_3|UNUSED||3|||||||||
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28 P7||IOBS|IO_L51N_3|UNUSED||3|||||||||
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29 P8||IOBM|IO_L51P_3|UNUSED||3|||||||||
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30 P9||IOBS|IO_L50N_3|UNUSED||3|||||||||
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31 P10||IOBM|IO_L50P_3|UNUSED||3|||||||||
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32 P11||IOBS|IO_L49N_3|UNUSED||3|||||||||
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33 P12||IOBM|IO_L49P_3|UNUSED||3|||||||||
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34 P13|||GND||||||||||||
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35 P14||IOBS|IO_L44N_GCLK20_3|UNUSED||3|||||||||
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36 P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
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37 P16||IOBS|IO_L43N_GCLK22_IRDY2_3|UNUSED||3|||||||||
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38 P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
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39 P18|||VCCO_3|||3|||||any******||||
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40 P19|||VCCINT||||||||1.2||||
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41 P20|||VCCAUX||||||||2.5||||
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42 P21|clk_main|IOB|IO_L42N_GCLK24_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
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43 P22||IOBM|IO_L42P_GCLK25_TRDY2_3|UNUSED||3|||||||||
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44 P23||IOBS|IO_L41N_GCLK26_3|UNUSED||3|||||||||
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45 P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
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46 P25|||GND||||||||||||
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47 P26||IOBS|IO_L37N_3|UNUSED||3|||||||||
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48 P27||IOBM|IO_L37P_3|UNUSED||3|||||||||
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49 P28|||VCCINT||||||||1.2||||
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50 P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
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51 P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
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52 P31|||VCCO_3|||3|||||any******||||
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53 P32||IOBS|IO_L2N_3|UNUSED||3|||||||||
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54 P33||IOBM|IO_L2P_3|UNUSED||3|||||||||
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55 P34||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
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56 P35||IOBM|IO_L1P_3|UNUSED||3|||||||||
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57 P36|||VCCAUX||||||||2.5||||
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58 P37|||PROGRAM_B_2||||||||||||
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59 P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
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60 P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
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61 P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
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62 P41||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
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63 P42|||VCCO_2|||2|||||any******||||
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64 P43||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
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65 P44||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
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66 P45||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
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67 P46||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
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68 P47||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
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69 P48||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
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70 P49|||GND||||||||||||
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71 P50||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
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72 P51||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
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73 P52|||VCCINT||||||||1.2||||
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74 P53|||VCCAUX||||||||2.5||||
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75 P54|||GND||||||||||||
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76 P55||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
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77 P56||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
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78 P57||IOBS|IO_L14N_D12_2|UNUSED||2|||||||||
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79 P58||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
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80 P59||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
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81 P60||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
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82 P61||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
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83 P62||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
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84 P63|||VCCO_2|||2|||||any******||||
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85 P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
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86 P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
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87 P66||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
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88 P67||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
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89 P68|||GND||||||||||||
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90 P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
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91 P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
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92 P71|||DONE_2||||||||||||
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93 P72|||CMPCS_B_2||||||||||||
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94 P73|||SUSPEND||||||||||||
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95 P74||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
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96 P75||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
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97 P76|||VCCO_1|||1|||||any******||||
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98 P77|||GND||||||||||||
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99 P78||IOBS|IO_L47N_1|UNUSED||1|||||||||
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100 P79||IOBM|IO_L47P_1|UNUSED||1|||||||||
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101 P80||IOBS|IO_L46N_1|UNUSED||1|||||||||
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102 P81||IOBM|IO_L46P_1|UNUSED||1|||||||||
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103 P82||IOBS|IO_L45N_1|UNUSED||1|||||||||
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104 P83||IOBM|IO_L45P_1|UNUSED||1|||||||||
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105 P84||IOBS|IO_L43N_GCLK4_1|UNUSED||1|||||||||
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106 P85||IOBM|IO_L43P_GCLK5_1|UNUSED||1|||||||||
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107 P86|||VCCO_1|||1|||||any******||||
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108 P87||IOBS|IO_L42N_GCLK6_TRDY1_1|UNUSED||1|||||||||
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109 P88|OE_bar|IOB|IO_L42P_GCLK7_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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110 P89|||VCCINT||||||||1.2||||
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111 P90|||VCCAUX||||||||2.5||||
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112 P91|||GND||||||||||||
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113 P92||IOBS|IO_L41N_GCLK8_1|UNUSED||1|||||||||
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114 P93||IOBM|IO_L41P_GCLK9_IRDY1_1|UNUSED||1|||||||||
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115 P94||IOBS|IO_L40N_GCLK10_1|UNUSED||1|||||||||
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116 P95|CS_2|IOB|IO_L40P_GCLK11_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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117 P96|||GND||||||||||||
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118 P97|UB_bar|IOB|IO_L34N_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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119 P98|LB_bar|IOB|IO_L34P_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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120 P99|WEA_bar|IOB|IO_L33N_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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121 P100|CS_1_bar|IOB|IO_L33P_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
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122 P101||IOBS|IO_L32N_1|UNUSED||1|||||||||
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123 P102||IOBM|IO_L32P_1|UNUSED||1|||||||||
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124 P103|||VCCO_1|||1|||||any******||||
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125 P104||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
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126 P105||IOBM|IO_L1P_1|UNUSED||1|||||||||
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127 P106|||TDO||||||||||||
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128 P107|||TMS||||||||||||
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129 P108|||GND||||||||||||
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130 P109|||TCK||||||||||||
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131 P110|||TDI||||||||||||
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132 P111|DATA_RAM<15>|IOB|IO_L66N_SCP0_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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133 P112|DATA_RAM<14>|IOB|IO_L66P_SCP1_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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134 P113|||GND||||||||||||
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135 P114|DATA_RAM<13>|IOB|IO_L65N_SCP2_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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136 P115|DATA_RAM<12>|IOB|IO_L65P_SCP3_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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137 P116|DATA_RAM<11>|IOB|IO_L64N_SCP4_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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138 P117|DATA_RAM<10>|IOB|IO_L64P_SCP5_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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139 P118|DATA_RAM<9>|IOB|IO_L63N_SCP6_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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140 P119|DATA_RAM<8>|IOB|IO_L63P_SCP7_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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141 P120|DATA_RAM<7>|IOB|IO_L62N_VREF_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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142 P121|DATA_RAM<6>|IOB|IO_L62P_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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143 P122|||VCCO_0|||0|||||2.50||||
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144 P123|DATA_RAM<5>|IOB|IO_L37N_GCLK12_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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145 P124|DATA_RAM<4>|IOB|IO_L37P_GCLK13_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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146 P125|||VCCO_0|||0|||||2.50||||
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147 P126|DATA_RAM<3>|IOB|IO_L36N_GCLK14_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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148 P127|DATA_RAM<2>|IOB|IO_L36P_GCLK15_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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149 P128|||VCCINT||||||||1.2||||
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150 P129|||VCCAUX||||||||2.5||||
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151 P130|||GND||||||||||||
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152 P131|DATA_RAM<1>|IOB|IO_L35N_GCLK16_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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153 P132|DATA_RAM<0>|IOB|IO_L35P_GCLK17_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
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154 P133|ADDR_RAM<9>|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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155 P134|ADDR_RAM<8>|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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156 P135|||VCCO_0|||0|||||2.50||||
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157 P136|||GND||||||||||||
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158 P137|ADDR_RAM<7>|IOB|IO_L4N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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159 P138|ADDR_RAM<6>|IOB|IO_L4P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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160 P139|ADDR_RAM<5>|IOB|IO_L3N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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161 P140|ADDR_RAM<4>|IOB|IO_L3P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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162 P141|ADDR_RAM<3>|IOB|IO_L2N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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163 P142|ADDR_RAM<2>|IOB|IO_L2P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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164 P143|ADDR_RAM<1>|IOB|IO_L1N_VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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165 P144|ADDR_RAM<0>|IOB|IO_L1P_HSWAPEN_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
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166
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167 -----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
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168
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169 * Default value.
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170 ** This default Pullup/Pulldown value can be overridden in Bitgen.
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171 ****** Special VCCO requirements may apply. Please consult the device
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172 family datasheet for specific guideline on VCCO requirements.
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173
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174 No newline at end of file
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1 Release 14.7 par P.20131013 (nt64)
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2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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3
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4 LENOVO-PC:: Mon Dec 14 11:39:04 2015
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5
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6 par -w -intstyle ise -ol high -mt off BloqueRAM_int_map.ncd BloqueRAM_int.ncd
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7 BloqueRAM_int.pcf
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8
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9
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10 Constraints file: BloqueRAM_int.pcf.
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11 Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
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12 "BloqueRAM_int" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
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13
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14 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
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15 Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
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16
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17 INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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18 -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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19 internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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20 reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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21 Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
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22
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23 Device speed data version: "PRODUCTION 1.23 2013-10-13".
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24
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25
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26
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27 Device Utilization Summary:
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28
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29 Slice Logic Utilization:
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30 Number of Slice Registers: 34 out of 11,440 1%
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31 Number used as Flip Flops: 34
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32 Number used as Latches: 0
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33 Number used as Latch-thrus: 0
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34 Number used as AND/OR logics: 0
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35 Number of Slice LUTs: 5 out of 5,720 1%
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36 Number used as logic: 5 out of 5,720 1%
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37 Number using O6 output only: 3
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38 Number using O5 output only: 0
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39 Number using O5 and O6: 2
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40 Number used as ROM: 0
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41 Number used as Memory: 0 out of 1,440 0%
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42
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43 Slice Logic Distribution:
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44 Number of occupied Slices: 11 out of 1,430 1%
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45 Number of MUXCYs used: 0 out of 2,860 0%
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46 Number of LUT Flip Flop pairs used: 37
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47 Number with an unused Flip Flop: 3 out of 37 8%
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48 Number with an unused LUT: 32 out of 37 86%
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49 Number of fully used LUT-FF pairs: 2 out of 37 5%
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50 Number of slice register sites lost
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51 to control set restrictions: 0 out of 11,440 0%
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52
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53 A LUT Flip Flop pair for this architecture represents one LUT paired with
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54 one Flip Flop within a slice. A control set is a unique combination of
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55 clock, reset, set, and enable signals for a registered element.
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56 The Slice Logic Distribution report is not meaningful if the design is
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57 over-mapped for a non-slice resource or if Placement fails.
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58
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59 IO Utilization:
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60 Number of bonded IOBs: 33 out of 102 32%
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61
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62 Specific Feature Utilization:
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63 Number of RAMB16BWERs: 1 out of 32 3%
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64 Number of RAMB8BWERs: 0 out of 64 0%
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65 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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66 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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67 Number of BUFG/BUFGMUXs: 1 out of 16 6%
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68 Number used as BUFGs: 1
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69 Number used as BUFGMUX: 0
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70 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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71 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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72 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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73 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
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74 Number of BSCANs: 0 out of 4 0%
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75 Number of BUFHs: 0 out of 128 0%
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76 Number of BUFPLLs: 0 out of 8 0%
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77 Number of BUFPLL_MCBs: 0 out of 4 0%
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78 Number of DSP48A1s: 0 out of 16 0%
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79 Number of ICAPs: 0 out of 1 0%
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80 Number of MCBs: 0 out of 2 0%
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81 Number of PCILOGICSEs: 0 out of 2 0%
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82 Number of PLL_ADVs: 0 out of 2 0%
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83 Number of PMVs: 0 out of 1 0%
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84 Number of STARTUPs: 0 out of 1 0%
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85 Number of SUSPEND_SYNCs: 0 out of 1 0%
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86
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87
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88 Overall effort level (-ol): High
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89 Router effort level (-rl): High
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90
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91 Starting initial Timing Analysis. REAL time: 3 secs
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92 Finished initial Timing Analysis. REAL time: 3 secs
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93
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94 Starting Router
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95
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96
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97 Phase 1 : 219 unrouted; REAL time: 3 secs
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98
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99 Phase 2 : 121 unrouted; REAL time: 4 secs
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100
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101 Phase 3 : 51 unrouted; REAL time: 4 secs
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102
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103 Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 5 secs
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104
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105 Updating file: BloqueRAM_int.ncd with current fully routed design.
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106
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107 Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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108
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109 Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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110
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111 Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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112
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113 Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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114
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115 Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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116
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117 Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
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118 Total REAL time to Router completion: 5 secs
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119 Total CPU time to Router completion: 4 secs
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120
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121 Partition Implementation Status
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122 -------------------------------
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123
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124 No Partitions were found in this design.
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125
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126 -------------------------------
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127
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128 Generating "PAR" statistics.
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129 INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
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130 Timing Score: 0 (Setup: 0, Hold: 0)
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131
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132 Asterisk (*) preceding a constraint indicates it was not met.
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133 This may be due to a setup or hold violation.
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134
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135 ----------------------------------------------------------------------------------------------------------
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136 Constraint | Check | Worst Case | Best Case | Timing | Timing
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137 | | Slack | Achievable | Errors | Score
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138 ----------------------------------------------------------------------------------------------------------
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139 Autotimespec constraint for clock net clk | SETUP | N/A| 3.387ns| N/A| 0
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140 _main_BUFGP | HOLD | 0.481ns| | 0| 0
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141 ----------------------------------------------------------------------------------------------------------
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142
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143
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144 All constraints were met.
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145 INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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146 constraint is not analyzed due to the following: No paths covered by this
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147 constraint; Other constraints intersect with this constraint; or This
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148 constraint was disabled by a Path Tracing Control. Please run the Timespec
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149 Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
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150
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151
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152 Generating Pad Report.
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153
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154 All signals are completely routed.
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155
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156 Total REAL time to PAR completion: 5 secs
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157 Total CPU time to PAR completion: 4 secs
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158
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159 Peak Memory Usage: 306 MB
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160
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161 Placer: Placement generated during map.
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162 Routing: Completed - No errors found.
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163
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164 Number of error messages: 0
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165 Number of warning messages: 0
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166 Number of info messages: 2
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167
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168 Writing design to file BloqueRAM_int.ncd
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169
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170
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171
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172 PAR done! No newline at end of file
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1 //! **************************************************************************
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2 // Written by: Map P.20131013 on Mon Dec 14 11:38:57 2015
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3 //! **************************************************************************
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4 No newline at end of file
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1 vhdl work "BloqueRAM_int.vhd" No newline at end of file
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1 <?xml version="1.0" encoding="UTF-8"?>
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2 <!DOCTYPE twReport [
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3 <!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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4 twDebug*, twFoot?, twClientInfo?)>
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5 <!ATTLIST twReport version CDATA "10,4">
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6 <!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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7 <!ELEMENT twExecVer (#PCDATA)>
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8 <!ELEMENT twCopyright (#PCDATA)>
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9 <!ELEMENT twCmdLine (#PCDATA)>
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10 <!ELEMENT twDesign (#PCDATA)>
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11 <!ELEMENT twPCF (#PCDATA)>
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12 <!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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13 <!ELEMENT twDevName (#PCDATA)>
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14 <!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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15 <!ELEMENT twSpeedGrade (#PCDATA)>
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16 <!ELEMENT twSpeedVer (#PCDATA)>
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17 <!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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18 <!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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19 <!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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20 <!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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21 <!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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22 <!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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23 <!ELEMENT twItemLimit (#PCDATA)>
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24 <!ELEMENT twUnconst EMPTY>
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25 <!ELEMENT twUnconstLimit (#PCDATA)>
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26 <!ELEMENT twEnvVar EMPTY>
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27 <!ATTLIST twEnvVar name CDATA #REQUIRED>
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28 <!ATTLIST twEnvVar description CDATA #REQUIRED>
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29 <!ELEMENT twWarn (#PCDATA)>
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30 <!ELEMENT twInfo (#PCDATA)>
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31 <!ELEMENT twDebug (#PCDATA)>
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32 <!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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33 <!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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34 <!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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35 <!ELEMENT twProc (#PCDATA)>
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36 <!ELEMENT twTemp (#PCDATA)>
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37 <!ELEMENT twVolt (#PCDATA)>
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38 <!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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39 <!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
No newline at end of file
40 <!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
No newline at end of file
41 <!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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42 <!ELEMENT twCycles (twSigConn+)>
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43 <!ATTLIST twCycles twNum CDATA #REQUIRED>
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44 <!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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45 <!ELEMENT twSig (#PCDATA)>
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46 <!ELEMENT twDriver (#PCDATA)>
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47 <!ELEMENT twLoad (#PCDATA)>
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48 <!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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49 <!ATTLIST twConst twConstType (NET |
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50 NETDELAY |
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51 NETSKEW |
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52 PATH |
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53 DEFPERIOD |
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54 UNCONSTPATH |
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55 DEFPATH |
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56 PATH2SETUP |
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57 UNCONSTPATH2SETUP |
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58 PATHCLASS |
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59 PATHDELAY |
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60 PERIOD |
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61 FREQUENCY |
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62 PATHBLOCK |
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63 OFFSET |
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64 OFFSETIN |
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65 OFFSETINCLOCK |
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66 UNCONSTOFFSETINCLOCK |
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67 OFFSETINDELAY |
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68 OFFSETINMOD |
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69 OFFSETOUT |
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70 OFFSETOUTCLOCK |
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71 UNCONSTOFFSETOUTCLOCK |
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72 OFFSETOUTDELAY |
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73 OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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74 <!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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75 twEndPtCnt?,
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76 twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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77 <!ELEMENT twConstName (#PCDATA)>
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78 <!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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79 <!ATTLIST twConstHead uID CDATA #IMPLIED>
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80 <!ELEMENT twItemCnt (#PCDATA)>
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81 <!ELEMENT twErrCnt (#PCDATA)>
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82 <!ELEMENT twErrCntEndPt (#PCDATA)>
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83 <!ELEMENT twErrCntSetup (#PCDATA)>
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84 <!ELEMENT twErrCntHold (#PCDATA)>
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85 <!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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86 <!ELEMENT twEndPtCnt (#PCDATA)>
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87 <!ELEMENT twPathErrCnt (#PCDATA)>
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88 <!ELEMENT twMinPer (#PCDATA) >
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89 <!ELEMENT twFootnote EMPTY>
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90 <!ATTLIST twFootnote number CDATA #REQUIRED>
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91 <!ELEMENT twMaxDel (#PCDATA)>
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92 <!ELEMENT twMaxFreq (#PCDATA)>
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93 <!ELEMENT twMinOff (#PCDATA)>
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94 <!ELEMENT twMaxOff (#PCDATA)>
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95 <!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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96 <!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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97 <!ELEMENT twTIGName (#PCDATA)>
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98 <!ELEMENT twInstantiated (#PCDATA)>
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99 <!ELEMENT twBlocked (#PCDATA)>
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100 <!ELEMENT twRacePathRpt (twRacePath+)>
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101 <!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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102 <!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
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103 <!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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104 twSimpleMinPath CDATA #IMPLIED>
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105 <!ELEMENT twTotDel (#PCDATA)>
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106 <!ELEMENT twSrc (#PCDATA)>
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107 <!ATTLIST twSrc BELType CDATA #IMPLIED>
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108 <!ELEMENT twDest (#PCDATA)>
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109 <!ATTLIST twDest BELType CDATA #IMPLIED>
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110 <!ELEMENT twDel (#PCDATA)>
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111 <!ELEMENT twSUTime (#PCDATA)>
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112 <!ELEMENT twTotPathDel (#PCDATA)>
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113 <!ELEMENT twClkSkew (#PCDATA)>
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114 <!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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115 <!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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116 <!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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117 <!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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118 <!ELEMENT twSlack (#PCDATA)>
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119 <!ELEMENT twDelConst (#PCDATA)>
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120 <!ELEMENT tw2Phase EMPTY>
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121 <!ELEMENT twClkUncert (#PCDATA)>
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122 <!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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123 fDCMJit CDATA #IMPLIED
No newline at end of file
124 fPhaseErr CDATA #IMPLIED
No newline at end of file
125 sEqu CDATA #IMPLIED>
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126 <!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
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127 <!ELEMENT twPathRptBanner (#PCDATA)>
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128 <!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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129 <!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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130 <!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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131 <!ELEMENT twOff (#PCDATA)>
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132 <!ELEMENT twGuaranteed EMPTY>
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133 <!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
No newline at end of file
134 <!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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135 <!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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136 <!ELEMENT twClkDel (#PCDATA)>
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137 <!ELEMENT twClkSrc (#PCDATA)>
No newline at end of file
138 <!ELEMENT twClkDest (#PCDATA)>
No newline at end of file
139 <!ELEMENT twGuarInSetup (#PCDATA)>
No newline at end of file
140 <!ELEMENT twOffSrc (#PCDATA)>
No newline at end of file
141 <!ELEMENT twOffDest (#PCDATA)>
No newline at end of file
142 <!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
No newline at end of file
143 <!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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144 <!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
No newline at end of file
145 <!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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146 <!ELEMENT twDataDel (#PCDATA)>
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147 <!ELEMENT twDataSrc (#PCDATA)>
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148 <!ELEMENT twDataDest (#PCDATA)>
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149 <!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
No newline at end of file
150 <!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
151 <!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
No newline at end of file
152 <!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
153 <!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
No newline at end of file
154 <!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
155 <!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
No newline at end of file
156 <!ELEMENT twLogLvls (#PCDATA)>
No newline at end of file
157 <!ELEMENT twSrcSite (#PCDATA)>
No newline at end of file
158 <!ELEMENT twSrcClk (#PCDATA)>
No newline at end of file
159 <!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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160 <!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
No newline at end of file
161 <!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
No newline at end of file
162 <!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
No newline at end of file
163 <!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
No newline at end of file
164 <!ELEMENT twDelInfo (#PCDATA)>
No newline at end of file
165 <!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
No newline at end of file
166 <!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
No newline at end of file
167 <!ELEMENT twSite (#PCDATA)>
No newline at end of file
168 <!ELEMENT twDelType (#PCDATA)>
No newline at end of file
169 <!ELEMENT twFanCnt (#PCDATA)>
No newline at end of file
170 <!ELEMENT twComp (#PCDATA)>
No newline at end of file
171 <!ELEMENT twNet (#PCDATA)>
No newline at end of file
172 <!ELEMENT twBEL (#PCDATA)>
No newline at end of file
173 <!ELEMENT twLogDel (#PCDATA)>
No newline at end of file
174 <!ELEMENT twRouteDel (#PCDATA)>
No newline at end of file
175 <!ELEMENT twDestClk (#PCDATA)>
No newline at end of file
176 <!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
No newline at end of file
177 <!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
No newline at end of file
178 <!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
No newline at end of file
179 <!ELEMENT twPctLog (#PCDATA)>
No newline at end of file
180 <!ELEMENT twPctRoute (#PCDATA)>
No newline at end of file
181 <!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
No newline at end of file
182 <!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
No newline at end of file
183 <!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
No newline at end of file
184 <!ELEMENT twTimeConst (#PCDATA)>
No newline at end of file
185 <!ELEMENT twAbsSlack (#PCDATA)>
No newline at end of file
186 <!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
No newline at end of file
187 <!ELEMENT twSkew (#PCDATA)>
No newline at end of file
188 <!ELEMENT twDetNet (twNetDel*)>
No newline at end of file
189 <!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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190 <!ELEMENT twNetDelInfo (#PCDATA)>
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191 <!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
No newline at end of file
192 <!ELEMENT twDetSkewNet (twNetSkew*)>
No newline at end of file
193 <!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
No newline at end of file
194 <!ELEMENT twClkSkewLimit EMPTY>
No newline at end of file
195 <!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
No newline at end of file
196 arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
No newline at end of file
197 <!ELEMENT twConstRollupTable (twConstRollup*)>
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198 <!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
No newline at end of file
199 <!ELEMENT twConstRollup EMPTY>
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200 <!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
No newline at end of file
201 <!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
No newline at end of file
202 <!ELEMENT twConstList (twConstListItem)*>
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203 <!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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204 <!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
No newline at end of file
205 <!ELEMENT twNotMet EMPTY>
No newline at end of file
206 <!ELEMENT twReqVal (#PCDATA)>
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207 <!ELEMENT twActVal (#PCDATA)>
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208 <!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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209 <!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
No newline at end of file
210 <!ELEMENT twConstStats (twConstName)>
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211 <!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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212 <!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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213 <!ATTLIST twConstStats twActual CDATA #IMPLIED>
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214 <!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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215 <!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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216 <!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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217 <!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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218 <!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
No newline at end of file
219 <!ATTLIST twConstStats twTCType CDATA #IMPLIED>
No newline at end of file
220 <!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
No newline at end of file
221 <!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
No newline at end of file
222 <!ELEMENT twConstData EMPTY>
No newline at end of file
223 <!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
No newline at end of file
224 best CDATA #IMPLIED requested CDATA #IMPLIED
No newline at end of file
225 errors CDATA #IMPLIED
No newline at end of file
226 score CDATA #IMPLIED>
No newline at end of file
227 <!ELEMENT twTimeGrpRpt (twTimeGrp)*>
No newline at end of file
228 <!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
No newline at end of file
229 <!ELEMENT twTimeGrpName (#PCDATA)>
No newline at end of file
230 <!ELEMENT twCompList (twCompName+)>
No newline at end of file
231 <!ELEMENT twCompName (#PCDATA)>
No newline at end of file
232 <!ELEMENT twSigList (twSigName+)>
No newline at end of file
233 <!ELEMENT twSigName (#PCDATA)>
No newline at end of file
234 <!ELEMENT twBELList (twBELName+)>
No newline at end of file
235 <!ELEMENT twBELName (#PCDATA)>
No newline at end of file
236 <!ELEMENT twBlockList (twBlockName+)>
No newline at end of file
237 <!ELEMENT twBlockName (#PCDATA)>
No newline at end of file
238 <!ELEMENT twMacList (twMacName+)>
No newline at end of file
239 <!ELEMENT twMacName (#PCDATA)>
No newline at end of file
240 <!ELEMENT twPinList (twPinName+)>
No newline at end of file
241 <!ELEMENT twPinName (#PCDATA)>
No newline at end of file
242 <!ELEMENT twUnmetConstCnt (#PCDATA)>
No newline at end of file
243 <!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
No newline at end of file
244 <!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
No newline at end of file
245 <!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
No newline at end of file
246 <!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
No newline at end of file
247 <!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
No newline at end of file
248 <!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
No newline at end of file
249 <!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
No newline at end of file
250 <!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
No newline at end of file
251 <!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
No newline at end of file
252 <!ELEMENT twSU2ClkTime (#PCDATA)>
No newline at end of file
253 <!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
No newline at end of file
254 <!ELEMENT twH2ClkTime (#PCDATA)>
No newline at end of file
255 <!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
No newline at end of file
256 <!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
No newline at end of file
257 <!ELEMENT twClk2Pad (twDest, twTime)>
No newline at end of file
258 <!ELEMENT twTime (#PCDATA)>
No newline at end of file
259 <!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
No newline at end of file
260 <!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
No newline at end of file
261 <!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
No newline at end of file
262 <!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
No newline at end of file
263 <!ELEMENT twClk2Out EMPTY>
No newline at end of file
264 <!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
No newline at end of file
265 <!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
No newline at end of file
266 <!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
No newline at end of file
267 <!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
No newline at end of file
268 <!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
No newline at end of file
269 <!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
No newline at end of file
270 <!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
No newline at end of file
271 <!ELEMENT twClk2SUList (twDest, twClk2SU+)>
No newline at end of file
272 <!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
No newline at end of file
273 <!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
No newline at end of file
274 <!ELEMENT twRiseRise (#PCDATA)>
No newline at end of file
275 <!ELEMENT twFallRise (#PCDATA)>
No newline at end of file
276 <!ELEMENT twRiseFall (#PCDATA)>
No newline at end of file
277 <!ELEMENT twFallFall (#PCDATA)>
No newline at end of file
278 <!ELEMENT twPad2PadList (twPad2Pad+)>
No newline at end of file
279 <!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
No newline at end of file
280 <!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
No newline at end of file
281 <!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
No newline at end of file
282 <!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
No newline at end of file
283 <!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
No newline at end of file
284 <!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
No newline at end of file
285 <!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
No newline at end of file
286 <!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
No newline at end of file
287 <!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
No newline at end of file
288 <!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
No newline at end of file
289 <!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
No newline at end of file
290 <!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
No newline at end of file
291 <!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
No newline at end of file
292 <!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
No newline at end of file
293 <!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
No newline at end of file
294 <!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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295 <!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
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296 <!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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297 <!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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298 <!ELEMENT twOffOutTblRow EMPTY>
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299 <!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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300 <!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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301 <!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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302 <!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
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303 <!ELEMENT twNonDedClk (#PCDATA)>
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304 <!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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305 <!ELEMENT twScore (#PCDATA)>
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306 <!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
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307 <!ELEMENT twPathCnt (#PCDATA)>
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308 <!ELEMENT twNetCnt (#PCDATA)>
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309 <!ELEMENT twConnCnt (#PCDATA)>
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310 <!ELEMENT twPct (#PCDATA)>
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311 <!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
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312 <!ELEMENT twMaxCombDel (#PCDATA)>
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313 <!ELEMENT twMaxFromToDel (#PCDATA)>
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314 <!ELEMENT twMaxNetDel (#PCDATA)>
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315 <!ELEMENT twMaxNetSkew (#PCDATA)>
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316 <!ELEMENT twMaxInAfterClk (#PCDATA)>
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317 <!ELEMENT twMinInBeforeClk (#PCDATA)>
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318 <!ELEMENT twMaxOutBeforeClk (#PCDATA)>
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319 <!ELEMENT twMinOutAfterClk (#PCDATA)>
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320 <!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
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321 <!ELEMENT twTimestamp (#PCDATA)>
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322 <!ELEMENT twFootnoteExplanation EMPTY>
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323 <!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
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324 <!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
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325 <!ELEMENT twClientInfo (twClientName, twAttrList?)>
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326 <!ELEMENT twClientName (#PCDATA)>
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327 <!ELEMENT twAttrList (twAttrListItem)*>
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328 <!ELEMENT twAttrListItem (twName, twValue*)>
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329 <!ELEMENT twName (#PCDATA)>
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330 <!ELEMENT twValue (#PCDATA)>
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331 ]>
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332 <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_main_BUFGP</twConstName><twConstData type="SETUP" best="3.387" units="ns" score="0"/><twConstData type="HOLD" slack="0.481" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="4">0</twUnmetConstCnt><twInfo anchorID="5">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport> No newline at end of file
1 NO CONTENT: new file 10644
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@@ -0,0 +1,423
1 Release 14.7 - xst P.20131013 (nt64)
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2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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3 --> Parameter TMPDIR set to xst/projnav.tmp
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4
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5
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6 Total REAL time to Xst completion: 0.00 secs
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7 Total CPU time to Xst completion: 0.12 secs
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8
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9 --> Parameter xsthdpdir set to xst
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10
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11
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12 Total REAL time to Xst completion: 0.00 secs
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13 Total CPU time to Xst completion: 0.12 secs
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14
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15 --> Reading design: BloqueRAM_int.prj
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16
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17 TABLE OF CONTENTS
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18 1) Synthesis Options Summary
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19 2) HDL Parsing
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20 3) HDL Elaboration
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21 4) HDL Synthesis
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22 4.1) HDL Synthesis Report
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23 5) Advanced HDL Synthesis
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24 5.1) Advanced HDL Synthesis Report
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25 6) Low Level Synthesis
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26 7) Partition Report
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27 8) Design Summary
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28 8.1) Primitive and Black Box Usage
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29 8.2) Device utilization summary
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30 8.3) Partition Resource Summary
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31 8.4) Timing Report
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32 8.4.1) Clock Information
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33 8.4.2) Asynchronous Control Signals Information
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34 8.4.3) Timing Summary
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35 8.4.4) Timing Details
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36 8.4.5) Cross Clock Domains Report
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37
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38
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39 =========================================================================
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40 * Synthesis Options Summary *
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41 =========================================================================
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42 ---- Source Parameters
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43 Input File Name : "BloqueRAM_int.prj"
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44 Ignore Synthesis Constraint File : NO
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45
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46 ---- Target Parameters
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47 Output File Name : "BloqueRAM_int"
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48 Output Format : NGC
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49 Target Device : xc6slx9-3-tqg144
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50
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51 ---- Source Options
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52 Top Module Name : BloqueRAM_int
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53 Automatic FSM Extraction : YES
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54 FSM Encoding Algorithm : Auto
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55 Safe Implementation : No
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56 FSM Style : LUT
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57 RAM Extraction : Yes
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58 RAM Style : Auto
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59 ROM Extraction : Yes
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60 Shift Register Extraction : YES
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61 ROM Style : Auto
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62 Resource Sharing : YES
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63 Asynchronous To Synchronous : NO
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64 Shift Register Minimum Size : 2
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65 Use DSP Block : Auto
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66 Automatic Register Balancing : No
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67
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68 ---- Target Options
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69 LUT Combining : Auto
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70 Reduce Control Sets : Auto
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71 Add IO Buffers : YES
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72 Global Maximum Fanout : 100000
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73 Add Generic Clock Buffer(BUFG) : 16
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74 Register Duplication : YES
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75 Optimize Instantiated Primitives : NO
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76 Use Clock Enable : Auto
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77 Use Synchronous Set : Auto
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78 Use Synchronous Reset : Auto
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79 Pack IO Registers into IOBs : Auto
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80 Equivalent register Removal : YES
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81
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82 ---- General Options
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83 Optimization Goal : Speed
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84 Optimization Effort : 1
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85 Power Reduction : NO
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86 Keep Hierarchy : No
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87 Netlist Hierarchy : As_Optimized
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88 RTL Output : Yes
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89 Global Optimization : AllClockNets
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90 Read Cores : YES
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91 Write Timing Constraints : NO
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92 Cross Clock Analysis : NO
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93 Hierarchy Separator : /
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94 Bus Delimiter : <>
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95 Case Specifier : Maintain
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96 Slice Utilization Ratio : 100
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97 BRAM Utilization Ratio : 100
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98 DSP48 Utilization Ratio : 100
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99 Auto BRAM Packing : NO
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100 Slice Utilization Ratio Delta : 5
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101
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102 =========================================================================
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103
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104
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105 =========================================================================
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106 * HDL Parsing *
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107 =========================================================================
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108 Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\Memoria_SRAM_16kb_v02\BloqueRAM_int.vhd" into library work
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109 Parsing entity <BloqueRAM_int>.
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110 Parsing architecture <Behavioral> of entity <bloqueram_int>.
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111
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112 =========================================================================
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113 * HDL Elaboration *
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114 =========================================================================
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115
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116 Elaborating entity <BloqueRAM_int> (architecture <Behavioral>) with generics from library <work>.
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117
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118 =========================================================================
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119 * HDL Synthesis *
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120 =========================================================================
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121
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122 Synthesizing Unit <BloqueRAM_int>.
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123 Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\Memoria_SRAM_16kb_v02\BloqueRAM_int.vhd".
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124 DATA_PRIM_SZ = 32
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125 ADDR_PRIM_SZ = 14
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126 RESUL_SZ = 16
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127 ADDR_SZ = 10
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128 Found 1-bit register for signal <data_ram_aux_out[14]_clk_main_DFF_2_q>.
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129 Found 1-bit register for signal <data_ram_aux_out[13]_clk_main_DFF_3_q>.
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130 Found 1-bit register for signal <data_ram_aux_out[12]_clk_main_DFF_4_q>.
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131 Found 1-bit register for signal <data_ram_aux_out[11]_clk_main_DFF_5_q>.
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132 Found 1-bit register for signal <data_ram_aux_out[10]_clk_main_DFF_6_q>.
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133 Found 1-bit register for signal <data_ram_aux_out[9]_clk_main_DFF_7_q>.
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134 Found 1-bit register for signal <data_ram_aux_out[8]_clk_main_DFF_8_q>.
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135 Found 1-bit register for signal <data_ram_aux_out[7]_clk_main_DFF_9_q>.
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136 Found 1-bit register for signal <data_ram_aux_out[6]_clk_main_DFF_10_q>.
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137 Found 1-bit register for signal <data_ram_aux_out[5]_clk_main_DFF_11_q>.
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138 Found 1-bit register for signal <data_ram_aux_out[4]_clk_main_DFF_12_q>.
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139 Found 1-bit register for signal <data_ram_aux_out[3]_clk_main_DFF_13_q>.
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140 Found 1-bit register for signal <data_ram_aux_out[2]_clk_main_DFF_14_q>.
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141 Found 1-bit register for signal <data_ram_aux_out[1]_clk_main_DFF_15_q>.
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142 Found 1-bit register for signal <data_ram_aux_out[0]_clk_main_DFF_16_q>.
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143 Found 1-bit register for signal <data_ram_aux_in<15>>.
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144 Found 1-bit register for signal <data_ram_aux_in<14>>.
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145 Found 1-bit register for signal <data_ram_aux_in<13>>.
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146 Found 1-bit register for signal <data_ram_aux_in<12>>.
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147 Found 1-bit register for signal <data_ram_aux_in<11>>.
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148 Found 1-bit register for signal <data_ram_aux_in<10>>.
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149 Found 1-bit register for signal <data_ram_aux_in<9>>.
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150 Found 1-bit register for signal <data_ram_aux_in<8>>.
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151 Found 1-bit register for signal <data_ram_aux_in<7>>.
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152 Found 1-bit register for signal <data_ram_aux_in<6>>.
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153 Found 1-bit register for signal <data_ram_aux_in<5>>.
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154 Found 1-bit register for signal <data_ram_aux_in<4>>.
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155 Found 1-bit register for signal <data_ram_aux_in<3>>.
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156 Found 1-bit register for signal <data_ram_aux_in<2>>.
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157 Found 1-bit register for signal <data_ram_aux_in<1>>.
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158 Found 1-bit register for signal <data_ram_aux_in<0>>.
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159 Found 1-bit register for signal <PWR_5_o_clk_main_DFF_33>.
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160 Found 1-bit register for signal <PWR_13_o_clk_main_DFF_41>.
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161 Found 1-bit register for signal <data_ram_aux_out[15]_clk_main_DFF_1_q>.
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162 Found 1-bit tristate buffer for signal <DATA_RAM<15>> created at line 73
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163 Found 1-bit tristate buffer for signal <DATA_RAM<14>> created at line 73
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164 Found 1-bit tristate buffer for signal <DATA_RAM<13>> created at line 73
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165 Found 1-bit tristate buffer for signal <DATA_RAM<12>> created at line 73
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166 Found 1-bit tristate buffer for signal <DATA_RAM<11>> created at line 73
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167 Found 1-bit tristate buffer for signal <DATA_RAM<10>> created at line 73
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168 Found 1-bit tristate buffer for signal <DATA_RAM<9>> created at line 73
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169 Found 1-bit tristate buffer for signal <DATA_RAM<8>> created at line 73
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170 Found 1-bit tristate buffer for signal <DATA_RAM<7>> created at line 73
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171 Found 1-bit tristate buffer for signal <DATA_RAM<6>> created at line 73
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172 Found 1-bit tristate buffer for signal <DATA_RAM<5>> created at line 73
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173 Found 1-bit tristate buffer for signal <DATA_RAM<4>> created at line 73
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174 Found 1-bit tristate buffer for signal <DATA_RAM<3>> created at line 73
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175 Found 1-bit tristate buffer for signal <DATA_RAM<2>> created at line 73
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176 Found 1-bit tristate buffer for signal <DATA_RAM<1>> created at line 73
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177 Found 1-bit tristate buffer for signal <DATA_RAM<0>> created at line 73
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178 Summary:
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179 inferred 34 D-type flip-flop(s).
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180 inferred 16 Tristate(s).
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181 Unit <BloqueRAM_int> synthesized.
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182
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183 =========================================================================
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184 HDL Synthesis Report
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185
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186 Macro Statistics
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187 # Registers : 34
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188 1-bit register : 34
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189 # Tristates : 16
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190 1-bit tristate buffer : 16
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191
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192 =========================================================================
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193
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194 =========================================================================
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195 * Advanced HDL Synthesis *
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196 =========================================================================
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197
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198
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199 =========================================================================
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200 Advanced HDL Synthesis Report
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201
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202 Macro Statistics
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203 # Registers : 34
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204 Flip-Flops : 34
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205
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206 =========================================================================
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207
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208 =========================================================================
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209 * Low Level Synthesis *
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210 =========================================================================
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211
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212 Optimizing unit <BloqueRAM_int> ...
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213
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214 Mapping all equations...
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215 Building and optimizing final netlist ...
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216 Found area constraint ratio of 100 (+ 5) on block BloqueRAM_int, actual ratio is 0.
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217
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218 Final Macro Processing ...
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219
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220 =========================================================================
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221 Final Register Report
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222
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223 Macro Statistics
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224 # Registers : 34
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225 Flip-Flops : 34
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226
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227 =========================================================================
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228
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229 =========================================================================
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230 * Partition Report *
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231 =========================================================================
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232
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233 Partition Implementation Status
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234 -------------------------------
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235
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236 No Partitions were found in this design.
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237
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238 -------------------------------
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239
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240 =========================================================================
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241 * Design Summary *
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242 =========================================================================
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243
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244 Top Level Output File Name : BloqueRAM_int.ngc
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245
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246 Primitive and Black Box Usage:
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247 ------------------------------
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248 # BELS : 10
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249 # GND : 1
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250 # INV : 3
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251 # LUT2 : 1
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252 # LUT4 : 2
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253 # LUT5 : 2
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254 # VCC : 1
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255 # FlipFlops/Latches : 34
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256 # FDC : 18
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257 # FDE : 16
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258 # RAMS : 1
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259 # RAMB16BWER : 1
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260 # Clock Buffers : 1
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261 # BUFGP : 1
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262 # IO Buffers : 32
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263 # IBUF : 16
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264 # IOBUF : 16
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265
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266 Device utilization summary:
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267 ---------------------------
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268
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269 Selected Device : 6slx9tqg144-3
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270
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271
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272 Slice Logic Utilization:
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273 Number of Slice Registers: 34 out of 11440 0%
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274 Number of Slice LUTs: 8 out of 5720 0%
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275 Number used as Logic: 8 out of 5720 0%
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276
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277 Slice Logic Distribution:
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278 Number of LUT Flip Flop pairs used: 42
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279 Number with an unused Flip Flop: 8 out of 42 19%
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280 Number with an unused LUT: 34 out of 42 80%
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281 Number of fully used LUT-FF pairs: 0 out of 42 0%
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282 Number of unique control sets: 4
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283
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284 IO Utilization:
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285 Number of IOs: 33
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286 Number of bonded IOBs: 33 out of 102 32%
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287
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288 Specific Feature Utilization:
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289 Number of Block RAM/FIFO: 1 out of 32 3%
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290 Number using Block RAM only: 1
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291 Number of BUFG/BUFGCTRLs: 1 out of 16 6%
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292
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293 ---------------------------
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294 Partition Resource Summary:
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295 ---------------------------
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296
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297 No Partitions were found in this design.
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298
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299 ---------------------------
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300
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301
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302 =========================================================================
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303 Timing Report
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304
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305 NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
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306 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
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307 GENERATED AFTER PLACE-and-ROUTE.
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308
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309 Clock Information:
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310 ------------------
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311 -----------------------------------+------------------------+-------+
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312 Clock Signal | Clock buffer(FF name) | Load |
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313 -----------------------------------+------------------------+-------+
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314 clk_main | BUFGP | 35 |
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315 data_ram_aux_in<31:16><1> | NONE(RAMB16BWER_inst) | 1 |
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316 -----------------------------------+------------------------+-------+
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317 INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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318
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319 Asynchronous Control Signals Information:
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320 ----------------------------------------
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321 No asynchronous control signals found in this design
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322
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323 Timing Summary:
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324 ---------------
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325 Speed Grade: -3
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326
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327 Minimum period: 2.531ns (Maximum Frequency: 395.124MHz)
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328 Minimum input arrival time before clock: 3.743ns
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329 Maximum output required time after clock: 4.604ns
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330 Maximum combinational path delay: No path found
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331
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332 Timing Details:
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333 ---------------
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334 All values displayed in nanoseconds (ns)
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335
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336 =========================================================================
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337 Timing constraint: Default period analysis for Clock 'clk_main'
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338 Clock period: 2.531ns (frequency: 395.124MHz)
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339 Total number of paths / destination ports: 32 / 32
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340 -------------------------------------------------------------------------
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341 Delay: 2.531ns (Levels of Logic = 0)
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342 Source: RAMB16BWER_inst (RAM)
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343 Destination: DATA_RAM_15 (FF)
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344 Source Clock: clk_main rising
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345 Destination Clock: clk_main rising
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346
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347 Data Path: RAMB16BWER_inst to DATA_RAM_15
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348 Gate Net
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349 Cell:in->out fanout Delay Delay Logical Name (Net Name)
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350 ---------------------------------------- ------------
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351 RAMB16BWER:CLKA->DOA15 1 1.850 0.579 RAMB16BWER_inst (data_ram_aux_out<15>)
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352 FDC:D 0.102 DATA_RAM_15
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353 ----------------------------------------
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354 Total 2.531ns (1.952ns logic, 0.579ns route)
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355 (77.1% logic, 22.9% route)
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356
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357 =========================================================================
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358 Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main'
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359 Total number of paths / destination ports: 186 / 65
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360 -------------------------------------------------------------------------
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361 Offset: 3.743ns (Levels of Logic = 2)
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362 Source: WEA_bar (PAD)
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363 Destination: PWR_5_o_clk_main_DFF_33 (FF)
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364 Destination Clock: clk_main rising
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365
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366 Data Path: WEA_bar to PWR_5_o_clk_main_DFF_33
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367 Gate Net
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368 Cell:in->out fanout Delay Delay Logical Name (Net Name)
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369 ---------------------------------------- ------------
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370 IBUF:I->O 5 1.222 1.059 WEA_bar_IBUF (WEA_bar_IBUF)
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371 LUT5:I0->O 9 0.203 0.829 UB_bar_CS_aux_OR_50_o1 (UB_bar_CS_aux_OR_50_o)
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372 FDC:CLR 0.430 PWR_5_o_clk_main_DFF_33
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373 ----------------------------------------
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374 Total 3.743ns (1.855ns logic, 1.888ns route)
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375 (49.6% logic, 50.4% route)
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376
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377 =========================================================================
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378 Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main'
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379 Total number of paths / destination ports: 32 / 16
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380 -------------------------------------------------------------------------
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381 Offset: 4.604ns (Levels of Logic = 2)
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382 Source: PWR_5_o_clk_main_DFF_33 (FF)
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383 Destination: DATA_RAM<15> (PAD)
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384 Source Clock: clk_main rising
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385
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386 Data Path: PWR_5_o_clk_main_DFF_33 to DATA_RAM<15>
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387 Gate Net
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388 Cell:in->out fanout Delay Delay Logical Name (Net Name)
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389 ---------------------------------------- ------------
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390 FDC:C->Q 1 0.447 0.579 PWR_5_o_clk_main_DFF_33 (PWR_5_o_clk_main_DFF_33)
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391 INV:I->O 8 0.206 0.802 PWR_5_o_clk_main_DFF_33_inv1_INV_0 (PWR_5_o_clk_main_DFF_33_inv)
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392 IOBUF:T->IO 2.571 DATA_RAM_15_IOBUF (DATA_RAM<15>)
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393 ----------------------------------------
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394 Total 4.604ns (3.224ns logic, 1.380ns route)
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395 (70.0% logic, 30.0% route)
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396
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397 =========================================================================
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398
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399 Cross Clock Domains Report:
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400 --------------------------
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401
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402 Clock to Setup on destination clock clk_main
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403 ---------------+---------+---------+---------+---------+
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404 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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405 Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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406 ---------------+---------+---------+---------+---------+
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407 clk_main | 2.531| | | |
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408 ---------------+---------+---------+---------+---------+
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409
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410 =========================================================================
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411
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412
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413 Total REAL time to Xst completion: 6.00 secs
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414 Total CPU time to Xst completion: 6.19 secs
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415
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416 -->
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417
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418 Total memory usage is 249008 kilobytes
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419
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420 Number of errors : 0 ( 0 filtered)
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421 Number of warnings : 0 ( 0 filtered)
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422 Number of infos : 1 ( 0 filtered)
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423 No newline at end of file
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1 --------------------------------------------------------------------------------
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2 Release 14.7 Trace (nt64)
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3 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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4
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5 C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
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6 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr
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7 BloqueRAM_int.pcf
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8
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9 Design file: BloqueRAM_int.ncd
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10 Physical constraint file: BloqueRAM_int.pcf
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11 Device,package,speed: xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13)
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12 Report level: verbose report
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13
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14 Environment Variable Effect
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15 -------------------- ------
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16 NONE No environment variables were set
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17 --------------------------------------------------------------------------------
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18
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19 INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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20 INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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21 INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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22 option. All paths that are not constrained will be reported in the
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23 unconstrained paths section(s) of the report.
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24 INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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25 a 50 Ohm transmission line loading model. For the details of this model,
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26 and for more information on accounting for different loading conditions,
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27 please see the device datasheet.
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28
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29
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30
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31 Data Sheet report:
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32 -----------------
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33 All values displayed in nanoseconds (ns)
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34
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35 Setup/Hold to clock clk_main
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36 ------------+------------+------------+------------+------------+------------------+--------+
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37 |Max Setup to| Process |Max Hold to | Process | | Clock |
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38 Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
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39 ------------+------------+------------+------------+------------+------------------+--------+
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40 ADDR_RAM<0> | 2.801(R)| SLOW | -1.108(R)| FAST |clk_main_BUFGP | 0.000|
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41 ADDR_RAM<1> | 3.246(R)| SLOW | -1.456(R)| FAST |clk_main_BUFGP | 0.000|
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42 ADDR_RAM<2> | 3.279(R)| SLOW | -1.417(R)| FAST |clk_main_BUFGP | 0.000|
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43 ADDR_RAM<3> | 2.472(R)| SLOW | -0.858(R)| FAST |clk_main_BUFGP | 0.000|
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44 ADDR_RAM<4> | 2.592(R)| SLOW | -0.944(R)| FAST |clk_main_BUFGP | 0.000|
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45 ADDR_RAM<5> | 2.575(R)| SLOW | -0.975(R)| FAST |clk_main_BUFGP | 0.000|
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46 ADDR_RAM<6> | 2.784(R)| SLOW | -1.124(R)| FAST |clk_main_BUFGP | 0.000|
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47 ADDR_RAM<7> | 2.323(R)| SLOW | -0.758(R)| FAST |clk_main_BUFGP | 0.000|
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48 ADDR_RAM<8> | 2.837(R)| SLOW | -1.172(R)| FAST |clk_main_BUFGP | 0.000|
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49 ADDR_RAM<9> | 2.986(R)| SLOW | -1.256(R)| FAST |clk_main_BUFGP | 0.000|
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50 CS_1_bar | 4.345(R)| SLOW | -1.617(R)| FAST |clk_main_BUFGP | 0.000|
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51 CS_2 | 3.532(R)| SLOW | -1.117(R)| FAST |clk_main_BUFGP | 0.000|
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52 DATA_RAM<0> | 2.070(R)| SLOW | -0.953(R)| FAST |clk_main_BUFGP | 0.000|
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53 DATA_RAM<1> | 2.467(R)| SLOW | -1.234(R)| FAST |clk_main_BUFGP | 0.000|
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54 DATA_RAM<2> | 2.583(R)| SLOW | -1.331(R)| FAST |clk_main_BUFGP | 0.000|
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55 DATA_RAM<3> | 2.402(R)| SLOW | -1.216(R)| FAST |clk_main_BUFGP | 0.000|
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56 DATA_RAM<4> | 3.146(R)| SLOW | -1.732(R)| FAST |clk_main_BUFGP | 0.000|
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57 DATA_RAM<5> | 2.409(R)| SLOW | -1.177(R)| FAST |clk_main_BUFGP | 0.000|
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58 DATA_RAM<6> | 2.535(R)| SLOW | -1.272(R)| FAST |clk_main_BUFGP | 0.000|
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59 DATA_RAM<7> | 2.494(R)| SLOW | -1.234(R)| FAST |clk_main_BUFGP | 0.000|
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60 DATA_RAM<8> | 2.834(R)| SLOW | -1.499(R)| FAST |clk_main_BUFGP | 0.000|
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61 DATA_RAM<9> | 2.770(R)| SLOW | -1.457(R)| FAST |clk_main_BUFGP | 0.000|
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62 DATA_RAM<10>| 2.773(R)| SLOW | -1.436(R)| FAST |clk_main_BUFGP | 0.000|
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63 DATA_RAM<11>| 2.636(R)| SLOW | -1.363(R)| FAST |clk_main_BUFGP | 0.000|
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64 DATA_RAM<12>| 3.878(R)| SLOW | -2.273(R)| FAST |clk_main_BUFGP | 0.000|
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65 DATA_RAM<13>| 2.808(R)| SLOW | -1.448(R)| FAST |clk_main_BUFGP | 0.000|
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66 DATA_RAM<14>| 2.982(R)| SLOW | -1.557(R)| FAST |clk_main_BUFGP | 0.000|
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67 DATA_RAM<15>| 2.769(R)| SLOW | -1.433(R)| FAST |clk_main_BUFGP | 0.000|
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68 LB_bar | 4.122(R)| SLOW | -1.890(R)| FAST |clk_main_BUFGP | 0.000|
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69 OE_bar | 2.665(R)| SLOW | -1.074(R)| FAST |clk_main_BUFGP | 0.000|
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70 UB_bar | 4.479(R)| SLOW | -1.697(R)| FAST |clk_main_BUFGP | 0.000|
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71 WEA_bar | 4.813(R)| SLOW | -1.442(R)| FAST |clk_main_BUFGP | 0.000|
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72 ------------+------------+------------+------------+------------+------------------+--------+
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73
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74 Clock clk_main to Pad
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75 ------------+-----------------+------------+-----------------+------------+------------------+--------+
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76 |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
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77 Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
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78 ------------+-----------------+------------+-----------------+------------+------------------+--------+
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79 DATA_RAM<0> | 9.844(R)| SLOW | 4.721(R)| FAST |clk_main_BUFGP | 0.000|
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80 DATA_RAM<1> | 10.026(R)| SLOW | 4.710(R)| FAST |clk_main_BUFGP | 0.000|
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81 DATA_RAM<2> | 10.364(R)| SLOW | 5.006(R)| FAST |clk_main_BUFGP | 0.000|
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82 DATA_RAM<3> | 10.364(R)| SLOW | 4.968(R)| FAST |clk_main_BUFGP | 0.000|
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83 DATA_RAM<4> | 10.240(R)| SLOW | 4.959(R)| FAST |clk_main_BUFGP | 0.000|
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84 DATA_RAM<5> | 10.240(R)| SLOW | 4.857(R)| FAST |clk_main_BUFGP | 0.000|
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85 DATA_RAM<6> | 10.886(R)| SLOW | 5.091(R)| FAST |clk_main_BUFGP | 0.000|
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86 DATA_RAM<7> | 10.886(R)| SLOW | 5.131(R)| FAST |clk_main_BUFGP | 0.000|
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87 DATA_RAM<8> | 10.064(R)| SLOW | 5.049(R)| FAST |clk_main_BUFGP | 0.000|
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88 DATA_RAM<9> | 10.064(R)| SLOW | 5.049(R)| FAST |clk_main_BUFGP | 0.000|
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89 DATA_RAM<10>| 9.947(R)| SLOW | 5.039(R)| FAST |clk_main_BUFGP | 0.000|
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90 DATA_RAM<11>| 9.947(R)| SLOW | 4.995(R)| FAST |clk_main_BUFGP | 0.000|
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91 DATA_RAM<12>| 10.119(R)| SLOW | 5.097(R)| FAST |clk_main_BUFGP | 0.000|
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92 DATA_RAM<13>| 10.119(R)| SLOW | 5.025(R)| FAST |clk_main_BUFGP | 0.000|
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93 DATA_RAM<14>| 10.418(R)| SLOW | 5.153(R)| FAST |clk_main_BUFGP | 0.000|
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94 DATA_RAM<15>| 10.418(R)| SLOW | 5.135(R)| FAST |clk_main_BUFGP | 0.000|
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95 ------------+-----------------+------------+-----------------+------------+------------------+--------+
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96
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97 Clock to Setup on destination clock clk_main
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98 ---------------+---------+---------+---------+---------+
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99 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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100 Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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101 ---------------+---------+---------+---------+---------+
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102 clk_main | 3.387| | | |
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103 ---------------+---------+---------+---------+---------+
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104
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105
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106 Analysis completed Mon Dec 14 11:39:17 2015
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107 --------------------------------------------------------------------------------
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108
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109 Trace Settings:
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110 -------------------------
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111 Trace Settings
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112
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113 Peak Memory Usage: 213 MB
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114
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115
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116 No newline at end of file
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1 <?xml version="1.0" encoding="UTF-8"?>
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2 <!DOCTYPE twReport [
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3 <!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
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4 twDebug*, twFoot?, twClientInfo?)>
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5 <!ATTLIST twReport version CDATA "10,4">
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6 <!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
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7 <!ELEMENT twExecVer (#PCDATA)>
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8 <!ELEMENT twCopyright (#PCDATA)>
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9 <!ELEMENT twCmdLine (#PCDATA)>
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10 <!ELEMENT twDesign (#PCDATA)>
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11 <!ELEMENT twPCF (#PCDATA)>
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12 <!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
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13 <!ELEMENT twDevName (#PCDATA)>
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14 <!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
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15 <!ELEMENT twSpeedGrade (#PCDATA)>
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16 <!ELEMENT twSpeedVer (#PCDATA)>
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17 <!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
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18 <!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
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19 <!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
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20 <!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
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21 <!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
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22 <!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
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23 <!ELEMENT twItemLimit (#PCDATA)>
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24 <!ELEMENT twUnconst EMPTY>
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25 <!ELEMENT twUnconstLimit (#PCDATA)>
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26 <!ELEMENT twEnvVar EMPTY>
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27 <!ATTLIST twEnvVar name CDATA #REQUIRED>
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28 <!ATTLIST twEnvVar description CDATA #REQUIRED>
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29 <!ELEMENT twWarn (#PCDATA)>
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30 <!ELEMENT twInfo (#PCDATA)>
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31 <!ELEMENT twDebug (#PCDATA)>
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32 <!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
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33 <!ATTLIST twBody twFastPaths CDATA #IMPLIED>
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34 <!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
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35 <!ELEMENT twProc (#PCDATA)>
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36 <!ELEMENT twTemp (#PCDATA)>
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37 <!ELEMENT twVolt (#PCDATA)>
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38 <!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
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39 <!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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40 <!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
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41 <!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
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42 <!ELEMENT twCycles (twSigConn+)>
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43 <!ATTLIST twCycles twNum CDATA #REQUIRED>
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44 <!ELEMENT twSigConn (twSig, twDriver, twLoad)>
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45 <!ELEMENT twSig (#PCDATA)>
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46 <!ELEMENT twDriver (#PCDATA)>
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47 <!ELEMENT twLoad (#PCDATA)>
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48 <!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
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49 <!ATTLIST twConst twConstType (NET |
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50 NETDELAY |
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51 NETSKEW |
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52 PATH |
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53 DEFPERIOD |
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54 UNCONSTPATH |
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55 DEFPATH |
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56 PATH2SETUP |
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57 UNCONSTPATH2SETUP |
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58 PATHCLASS |
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59 PATHDELAY |
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60 PERIOD |
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61 FREQUENCY |
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62 PATHBLOCK |
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63 OFFSET |
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64 OFFSETIN |
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65 OFFSETINCLOCK |
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66 UNCONSTOFFSETINCLOCK |
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67 OFFSETINDELAY |
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68 OFFSETINMOD |
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69 OFFSETOUT |
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70 OFFSETOUTCLOCK |
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71 UNCONSTOFFSETOUTCLOCK |
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72 OFFSETOUTDELAY |
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73 OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
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74 <!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
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75 twEndPtCnt?,
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76 twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
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77 <!ELEMENT twConstName (#PCDATA)>
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78 <!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
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79 <!ATTLIST twConstHead uID CDATA #IMPLIED>
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80 <!ELEMENT twItemCnt (#PCDATA)>
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81 <!ELEMENT twErrCnt (#PCDATA)>
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82 <!ELEMENT twErrCntEndPt (#PCDATA)>
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83 <!ELEMENT twErrCntSetup (#PCDATA)>
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84 <!ELEMENT twErrCntHold (#PCDATA)>
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85 <!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
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86 <!ELEMENT twEndPtCnt (#PCDATA)>
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87 <!ELEMENT twPathErrCnt (#PCDATA)>
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88 <!ELEMENT twMinPer (#PCDATA) >
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89 <!ELEMENT twFootnote EMPTY>
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90 <!ATTLIST twFootnote number CDATA #REQUIRED>
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91 <!ELEMENT twMaxDel (#PCDATA)>
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92 <!ELEMENT twMaxFreq (#PCDATA)>
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93 <!ELEMENT twMinOff (#PCDATA)>
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94 <!ELEMENT twMaxOff (#PCDATA)>
No newline at end of file
95 <!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
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96 <!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
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97 <!ELEMENT twTIGName (#PCDATA)>
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98 <!ELEMENT twInstantiated (#PCDATA)>
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99 <!ELEMENT twBlocked (#PCDATA)>
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100 <!ELEMENT twRacePathRpt (twRacePath+)>
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101 <!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
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102 <!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
No newline at end of file
103 <!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
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104 twSimpleMinPath CDATA #IMPLIED>
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105 <!ELEMENT twTotDel (#PCDATA)>
No newline at end of file
106 <!ELEMENT twSrc (#PCDATA)>
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107 <!ATTLIST twSrc BELType CDATA #IMPLIED>
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108 <!ELEMENT twDest (#PCDATA)>
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109 <!ATTLIST twDest BELType CDATA #IMPLIED>
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110 <!ELEMENT twDel (#PCDATA)>
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111 <!ELEMENT twSUTime (#PCDATA)>
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112 <!ELEMENT twTotPathDel (#PCDATA)>
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113 <!ELEMENT twClkSkew (#PCDATA)>
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114 <!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
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115 <!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
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116 <!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
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117 <!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
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118 <!ELEMENT twSlack (#PCDATA)>
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119 <!ELEMENT twDelConst (#PCDATA)>
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120 <!ELEMENT tw2Phase EMPTY>
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121 <!ELEMENT twClkUncert (#PCDATA)>
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122 <!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
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123 fDCMJit CDATA #IMPLIED
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124 fPhaseErr CDATA #IMPLIED
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125 sEqu CDATA #IMPLIED>
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126 <!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
No newline at end of file
127 <!ELEMENT twPathRptBanner (#PCDATA)>
No newline at end of file
128 <!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
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129 <!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
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130 <!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
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131 <!ELEMENT twOff (#PCDATA)>
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132 <!ELEMENT twGuaranteed EMPTY>
No newline at end of file
133 <!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
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134 <!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
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135 <!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
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136 <!ELEMENT twClkDel (#PCDATA)>
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137 <!ELEMENT twClkSrc (#PCDATA)>
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138 <!ELEMENT twClkDest (#PCDATA)>
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139 <!ELEMENT twGuarInSetup (#PCDATA)>
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140 <!ELEMENT twOffSrc (#PCDATA)>
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141 <!ELEMENT twOffDest (#PCDATA)>
No newline at end of file
142 <!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
No newline at end of file
143 <!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
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144 <!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
No newline at end of file
145 <!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
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146 <!ELEMENT twDataDel (#PCDATA)>
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147 <!ELEMENT twDataSrc (#PCDATA)>
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148 <!ELEMENT twDataDest (#PCDATA)>
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149 <!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
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150 <!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
151 <!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
No newline at end of file
152 <!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
153 <!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
No newline at end of file
154 <!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
No newline at end of file
155 <!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
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156 <!ELEMENT twLogLvls (#PCDATA)>
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157 <!ELEMENT twSrcSite (#PCDATA)>
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158 <!ELEMENT twSrcClk (#PCDATA)>
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159 <!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
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160 <!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
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161 <!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
No newline at end of file
162 <!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
No newline at end of file
163 <!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
No newline at end of file
164 <!ELEMENT twDelInfo (#PCDATA)>
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165 <!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
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166 <!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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167 <!ELEMENT twSite (#PCDATA)>
No newline at end of file
168 <!ELEMENT twDelType (#PCDATA)>
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169 <!ELEMENT twFanCnt (#PCDATA)>
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170 <!ELEMENT twComp (#PCDATA)>
No newline at end of file
171 <!ELEMENT twNet (#PCDATA)>
No newline at end of file
172 <!ELEMENT twBEL (#PCDATA)>
No newline at end of file
173 <!ELEMENT twLogDel (#PCDATA)>
No newline at end of file
174 <!ELEMENT twRouteDel (#PCDATA)>
No newline at end of file
175 <!ELEMENT twDestClk (#PCDATA)>
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176 <!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
No newline at end of file
177 <!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
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178 <!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
No newline at end of file
179 <!ELEMENT twPctLog (#PCDATA)>
No newline at end of file
180 <!ELEMENT twPctRoute (#PCDATA)>
No newline at end of file
181 <!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
No newline at end of file
182 <!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
No newline at end of file
183 <!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
No newline at end of file
184 <!ELEMENT twTimeConst (#PCDATA)>
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185 <!ELEMENT twAbsSlack (#PCDATA)>
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186 <!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
No newline at end of file
187 <!ELEMENT twSkew (#PCDATA)>
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188 <!ELEMENT twDetNet (twNetDel*)>
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189 <!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
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190 <!ELEMENT twNetDelInfo (#PCDATA)>
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191 <!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
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192 <!ELEMENT twDetSkewNet (twNetSkew*)>
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193 <!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
No newline at end of file
194 <!ELEMENT twClkSkewLimit EMPTY>
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195 <!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
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196 arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
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197 <!ELEMENT twConstRollupTable (twConstRollup*)>
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198 <!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
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199 <!ELEMENT twConstRollup EMPTY>
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200 <!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
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201 <!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
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202 <!ELEMENT twConstList (twConstListItem)*>
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203 <!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
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204 <!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
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205 <!ELEMENT twNotMet EMPTY>
No newline at end of file
206 <!ELEMENT twReqVal (#PCDATA)>
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207 <!ELEMENT twActVal (#PCDATA)>
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208 <!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
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209 <!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
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210 <!ELEMENT twConstStats (twConstName)>
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211 <!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
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212 <!ATTLIST twConstStats twRequired CDATA #IMPLIED>
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213 <!ATTLIST twConstStats twActual CDATA #IMPLIED>
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214 <!ATTLIST twConstStats twSlack CDATA #IMPLIED>
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215 <!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
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216 <!ATTLIST twConstStats twErrors CDATA #IMPLIED>
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217 <!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
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218 <!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
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219 <!ATTLIST twConstStats twTCType CDATA #IMPLIED>
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220 <!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
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221 <!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
No newline at end of file
222 <!ELEMENT twConstData EMPTY>
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223 <!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
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224 best CDATA #IMPLIED requested CDATA #IMPLIED
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225 errors CDATA #IMPLIED
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226 score CDATA #IMPLIED>
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227 <!ELEMENT twTimeGrpRpt (twTimeGrp)*>
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228 <!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
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229 <!ELEMENT twTimeGrpName (#PCDATA)>
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230 <!ELEMENT twCompList (twCompName+)>
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231 <!ELEMENT twCompName (#PCDATA)>
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232 <!ELEMENT twSigList (twSigName+)>
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233 <!ELEMENT twSigName (#PCDATA)>
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234 <!ELEMENT twBELList (twBELName+)>
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235 <!ELEMENT twBELName (#PCDATA)>
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236 <!ELEMENT twBlockList (twBlockName+)>
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237 <!ELEMENT twBlockName (#PCDATA)>
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238 <!ELEMENT twMacList (twMacName+)>
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239 <!ELEMENT twMacName (#PCDATA)>
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240 <!ELEMENT twPinList (twPinName+)>
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241 <!ELEMENT twPinName (#PCDATA)>
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242 <!ELEMENT twUnmetConstCnt (#PCDATA)>
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243 <!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
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244 <!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
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245 <!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
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246 <!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
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247 <!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
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248 <!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
No newline at end of file
249 <!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
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250 <!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
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251 <!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
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252 <!ELEMENT twSU2ClkTime (#PCDATA)>
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253 <!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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254 <!ELEMENT twH2ClkTime (#PCDATA)>
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255 <!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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256 <!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
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257 <!ELEMENT twClk2Pad (twDest, twTime)>
No newline at end of file
258 <!ELEMENT twTime (#PCDATA)>
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259 <!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
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260 <!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
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261 <!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
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262 <!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
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263 <!ELEMENT twClk2Out EMPTY>
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264 <!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
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265 <!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
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266 <!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
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267 <!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
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268 <!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
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269 <!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
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270 <!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
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271 <!ELEMENT twClk2SUList (twDest, twClk2SU+)>
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272 <!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
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273 <!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
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274 <!ELEMENT twRiseRise (#PCDATA)>
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275 <!ELEMENT twFallRise (#PCDATA)>
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276 <!ELEMENT twRiseFall (#PCDATA)>
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277 <!ELEMENT twFallFall (#PCDATA)>
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278 <!ELEMENT twPad2PadList (twPad2Pad+)>
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279 <!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
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280 <!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
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281 <!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
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282 <!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
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283 <!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
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284 <!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
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285 <!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
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286 <!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
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287 <!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
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288 <!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
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289 <!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
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290 <!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
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291 <!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
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292 <!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
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293 <!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
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294 <!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
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295 <!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
No newline at end of file
296 <!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
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297 <!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
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298 <!ELEMENT twOffOutTblRow EMPTY>
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299 <!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
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300 <!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
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301 <!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
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302 <!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
No newline at end of file
303 <!ELEMENT twNonDedClk (#PCDATA)>
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304 <!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
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305 <!ELEMENT twScore (#PCDATA)>
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306 <!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
No newline at end of file
307 <!ELEMENT twPathCnt (#PCDATA)>
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308 <!ELEMENT twNetCnt (#PCDATA)>
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309 <!ELEMENT twConnCnt (#PCDATA)>
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310 <!ELEMENT twPct (#PCDATA)>
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311 <!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
No newline at end of file
312 <!ELEMENT twMaxCombDel (#PCDATA)>
No newline at end of file
313 <!ELEMENT twMaxFromToDel (#PCDATA)>
No newline at end of file
314 <!ELEMENT twMaxNetDel (#PCDATA)>
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315 <!ELEMENT twMaxNetSkew (#PCDATA)>
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316 <!ELEMENT twMaxInAfterClk (#PCDATA)>
No newline at end of file
317 <!ELEMENT twMinInBeforeClk (#PCDATA)>
No newline at end of file
318 <!ELEMENT twMaxOutBeforeClk (#PCDATA)>
No newline at end of file
319 <!ELEMENT twMinOutAfterClk (#PCDATA)>
No newline at end of file
320 <!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
No newline at end of file
321 <!ELEMENT twTimestamp (#PCDATA)>
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322 <!ELEMENT twFootnoteExplanation EMPTY>
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323 <!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
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324 <!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
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325 <!ELEMENT twClientInfo (twClientName, twAttrList?)>
No newline at end of file
326 <!ELEMENT twClientName (#PCDATA)>
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327 <!ELEMENT twAttrList (twAttrListItem)*>
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328 <!ELEMENT twAttrListItem (twName, twValue*)>
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329 <!ELEMENT twName (#PCDATA)>
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330 <!ELEMENT twValue (#PCDATA)>
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331 ]>
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332 <twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
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333 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr
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334 BloqueRAM_int.pcf
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335
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336 </twCmdLine><twDesign>BloqueRAM_int.ncd</twDesign><twDesignPath>BloqueRAM_int.ncd</twDesignPath><twPCF>BloqueRAM_int.pcf</twPCF><twPcfPath>BloqueRAM_int.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="tqg144"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twSUH2ClkList anchorID="7" twDestWidth="12" twPhaseWidth="14"><twDest>clk_main</twDest><twSUH2Clk ><twSrc>ADDR_RAM&lt;0&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.801</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.108</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;1&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.246</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.456</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;2&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.279</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.417</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;3&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.472</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.858</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;4&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.592</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.944</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;5&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.575</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.975</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;6&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.784</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.124</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;7&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.323</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.758</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;8&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.837</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.172</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;9&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.986</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.256</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>CS_1_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.345</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.617</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>CS_2</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.532</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.117</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;0&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.070</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.953</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;1&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.467</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.234</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;2&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.583</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.331</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;3&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.402</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.216</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;4&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.146</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.732</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;5&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.409</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.177</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;6&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.535</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.272</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;7&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.494</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.234</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;8&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.834</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.499</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;9&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.770</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.457</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;10&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.773</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.436</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;11&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.636</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.363</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;12&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.878</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-2.273</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;13&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.808</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.448</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;14&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.982</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.557</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;15&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.769</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.433</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>LB_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.122</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.890</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>OE_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.665</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.074</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>UB_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.479</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.697</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>WEA_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.813</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.442</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="8" twDestWidth="12" twPhaseWidth="14"><twSrc>clk_main</twSrc><twClk2Out twOutPad = "DATA_RAM&lt;0&gt;" twMinTime = "4.721" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.844" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;1&gt;" twMinTime = "4.710" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.026" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;2&gt;" twMinTime = "5.006" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.364" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;3&gt;" twMinTime = "4.968" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.364" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;4&gt;" twMinTime = "4.959" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.240" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;5&gt;" twMinTime = "4.857" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.240" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;6&gt;" twMinTime = "5.091" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.886" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;7&gt;" twMinTime = "5.131" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.886" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;8&gt;" twMinTime = "5.049" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.064" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;9&gt;" twMinTime = "5.049" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.064" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;10&gt;" twMinTime = "5.039" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.947" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;11&gt;" twMinTime = "4.995" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.947" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;12&gt;" twMinTime = "5.097" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.119" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;13&gt;" twMinTime = "5.025" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.119" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;14&gt;" twMinTime = "5.153" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.418" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;15&gt;" twMinTime = "5.135" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.418" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="9" twDestWidth="8"><twDest>clk_main</twDest><twClk2SU><twSrc>clk_main</twSrc><twRiseRise>3.387</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Mon Dec 14 11:39:17 2015 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
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337
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338 Peak Memory Usage: 213 MB
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339 </twValue></twAttrListItem></twAttrList></twClientInfo></twReport> No newline at end of file
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1 Release 14.7 - par P.20131013 (nt64)
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2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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3
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4 Mon Dec 14 11:39:10 2015
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5
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6 All signals are completely routed.
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7
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8
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1 ----------------------------------------------------------------------------------
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2 -- Company:
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3 -- Engineer:
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4 --
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5 -- Create Date: 08:20:52 12/14/2015
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6 -- Design Name:
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7 -- Module Name: BloqueRAM_int - Behavioral
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8 -- Project Name:
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9 -- Target Devices:
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10 -- Tool versions:
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11 -- Description:
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12 --
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13 -- Dependencies:
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14 --
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15 -- Revision:
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16 -- Revision 0.01 - File Created
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17 -- Additional Comments:
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18 --
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19 ----------------------------------------------------------------------------------
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20 library IEEE;
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21 use IEEE.STD_LOGIC_1164.ALL;
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22
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23 -- Uncomment the following library declaration if using
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24 -- arithmetic functions with Signed or Unsigned values
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25 --use IEEE.NUMERIC_STD.ALL;
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26
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27 -- Uncomment the following library declaration if instantiating
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28 -- any Xilinx primitives in this code.
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29 library UNISIM;
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30 use UNISIM.VComponents.all;
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31
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32 entity BloqueRAM_int is
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33 GENERIC(
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34 DATA_PRIM_SZ: INTEGER:=32;
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35 ADDR_PRIM_SZ: INTEGER:=14;
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36 RESUL_SZ: INTEGER:= 16;
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37 ADDR_SZ: INTEGER:= 10
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38 );
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39 PORT(
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40 clk_main: IN std_logic; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n o PLL
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41 --o m�dulo de divisi�n de relojes internos
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42 CS_1_bar: IN std_logic;
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43 CS_2: IN std_logic;
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44 OE_bar: IN std_logic;
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45 WEA_bar: IN std_logic; --Se�al de habilitador proveniente del controlador de memoria
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46 UB_bar: IN std_logic;
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47 LB_bar: IN std_logic;
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48
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49 ADDR_RAM: IN std_logic_vector((ADDR_SZ-1) downto 0);
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50 DATA_RAM: INOUT std_logic_vector((RESUL_SZ-1) downto 0) --Entrada Salida de datos a escribir/leer en/de la RAM
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51
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52 );
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53 end BloqueRAM_int;
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54
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55 architecture Behavioral of BloqueRAM_int is
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56
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57 SIGNAL addr_ram_aux: std_logic_vector((ADDR_PRIM_SZ-1) downto 0) := (OTHERS => '0'); --14 bits de bus de direcci�n
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58 SIGNAL data_ram_aux_in: std_logic_vector((DATA_PRIM_SZ-1) downto 0) := (OTHERS => '0'); --32 bits de bus de direcci�n
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59 SIGNAL data_ram_aux_out: std_logic_vector((DATA_PRIM_SZ-1) downto 0); --32 bits de bus de direcci�n
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60 SIGNAL CS_aux: std_logic;
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61 signal WE_AUX: std_logic_vector(3 downto 0);
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62
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63 begin
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64
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65 addr_ram_aux <= ADDR_RAM & "0000";
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66 data_ram_aux_in((DATA_PRIM_SZ-1) downto RESUL_SZ) <= "0000000000000000";
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67
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68 PROCESS(OE_bar,UB_bar,LB_bar)
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69 BEGIN
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70
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71 END PROCESS;
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72
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73 PROCESS (CS_aux,WEA_bar,clk_main,UB_bar,LB_bar,OE_bar)
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74 BEGIN
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75 IF(CS_aux /= '1') THEN
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76 DATA_RAM <= (OTHERS=>'Z');
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77
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78 ELSIF((UB_bar AND LB_bar) = '1') THEN
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79 DATA_RAM <= (OTHERS=>'Z');
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80
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81 ELSIF(WEA_bar = '1') THEN
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82 IF(OE_BAR = '1') THEN
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83 DATA_RAM <= (OTHERS=>'Z');
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84 ELSE
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85
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86 IF(UB_bar='0') THEN
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87 IF(rising_edge(clk_main)) THEN
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88 DATA_RAM(15 downto 8) <= data_ram_aux_out(15 downto 8);
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89 END IF;
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90 ELSE
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91 DATA_RAM(15 downto 8) <= (OTHERS=>'Z');
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92 END IF;
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93
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94 IF(LB_bar='0') THEN
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95 IF(rising_edge(clk_main)) THEN
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96 DATA_RAM(7 downto 0) <= data_ram_aux_out(7 downto 0);
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97 END IF;
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98 ELSE
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99 DATA_RAM(7 downto 0) <= (OTHERS=>'Z');
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100 END IF;
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101
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102 END IF;
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103
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104 ELSE
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105 DATA_RAM <= (OTHERS=>'Z');
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106
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107 IF(UB_bar='0') THEN
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108 IF(rising_edge(clk_main)) THEN
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109 data_ram_aux_in((RESUL_SZ-1) downto 8) <= DATA_RAM(15 downto 8);
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110 END IF;
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111 --ELSE
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112 -- data_ram_aux_in((RESUL_SZ-1) downto 8) <= (OTHERS=>'Z');
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113 END IF;
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114
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115 IF(LB_bar='0') THEN
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116 IF(rising_edge(clk_main)) THEN
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117 data_ram_aux_in(7 downto 0) <= DATA_RAM(7 downto 0);
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118 END IF;
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119 --ELSE
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120 -- data_ram_aux_in(7 downto 0) <= (OTHERS=>'Z');
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121 END IF;
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122
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123 END IF;
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124
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125 END PROCESS;
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126
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127
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128
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129 CS_aux <=((NOT(CS_1_bar)) AND CS_2);
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130 WE_aux <= (NOT(WEA_bar))&(NOT(WEA_bar))&(NOT(WEA_bar))&(NOT(WEA_bar)) ;
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131
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132 RAMB16BWER_inst : RAMB16BWER
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133 generic map (
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134 -- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
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135 DATA_WIDTH_A => 18,
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136 DATA_WIDTH_B => 18,
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137 -- DOA_REG/DOB_REG: Optional output register (0 or 1)
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138 DOA_REG => 0, --Que no cambie la data mostrada en escritura hasta el flanco de reloj,
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139 DOB_REG => 0,
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140 -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
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141 EN_RSTRAM_A => TRUE,
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142 EN_RSTRAM_B => TRUE,
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143 -- INITP_00 to INITP_07: Initial memory contents.
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144 INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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145 INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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146 INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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147 INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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148 INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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149 INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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150 INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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151 INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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152 -- INIT_00 to INIT_3F: Initial memory contents.
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153 INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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154 INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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155 INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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156 INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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157 INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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158 INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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159 INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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160 INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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161 INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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162 INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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163 INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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164 INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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165 INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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166 INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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167 INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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168 INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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169 INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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170 INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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171 INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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172 INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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173 INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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174 INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
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175 INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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176 INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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177 INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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178 INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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179 INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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180 INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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181 INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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182 INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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183 INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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184 INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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185 INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
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186 INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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187 INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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188 INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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189 INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
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190 INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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191 INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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192 INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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193 INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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194 INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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195 INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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196 INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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197 INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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198 INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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199 INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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200 INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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201 INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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202 INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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203 INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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204 INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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205 INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
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206 INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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207 INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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208 INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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209 INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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210 INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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211 INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
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212 INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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213 INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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214 INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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215 INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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216 INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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217 -- INIT_A/INIT_B: Initial values on output port
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218 INIT_A => X"000000000",
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219 INIT_B => X"000000000",
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220 -- INIT_FILE: Optional file used to specify initial RAM contents
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221 INIT_FILE => "NONE",
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222 -- RSTTYPE: "SYNC" or "ASYNC"
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223 RSTTYPE => "SYNC",
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224 -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
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225 RST_PRIORITY_A => "CE",
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226 RST_PRIORITY_B => "CE",
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227 -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
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228 SIM_COLLISION_CHECK => "ALL",
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229 -- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
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230 SIM_DEVICE => "SPARTAN6",
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231 -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
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232 SRVAL_A => X"000000000",
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233 SRVAL_B => X"000000000",
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234 -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
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235 WRITE_MODE_A => "NO_CHANGE",
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236 WRITE_MODE_B => "NO_CHANGE"
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237 )
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238 port map (
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239 -- Port A Data: 32-bit (each) output: Port A data
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240 DOA => data_ram_aux_out, -- 32-bit output: A port data output
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241 DOPA => open, -- 4-bit output: A port parity output
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242 -- Port B Data: 32-bit (each) output: Port B data
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243 DOB => open, -- 32-bit output: B port data output
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244 DOPB => open, -- 4-bit output: B port parity output
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245 -- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
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246 ADDRA => addr_ram_aux, -- 14-bit input: A port address input
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247 CLKA => clk_main, -- 1-bit input: A port clock input
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248 ENA => CS_AUX, -- 1-bit input: A port enable input
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249 REGCEA => '1', -- 1-bit input: A port register clock enable input
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250 RSTA => '0', -- 1-bit input: A port register set/reset input
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251 WEA => WE_aux, -- 4-bit input: Port A byte-wide write enable input
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252 -- Port A Data: 32-bit (each) input: Port A data
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253 DIA => data_ram_aux_in, -- 32-bit input: A port data input
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254 DIPA => "0000", -- 4-bit input: A port parity input
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255 -- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
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256 ADDRB => "00000000000000", -- 14-bit input: B port address input
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257 CLKB => '0', -- 1-bit input: B port clock input
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258 ENB => '0', -- 1-bit input: B port enable input
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259 REGCEB => '0', -- 1-bit input: B port register clock enable input
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260 RSTB => '0', -- 1-bit input: B port register set/reset input
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261 WEB => "0000", -- 4-bit input: Port B byte-wide write enable input
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262 -- Port B Data: 32-bit (each) input: Port B data
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263 DIB => X"00000000", -- 32-bit input: B port data input
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264 DIPB => "0000" -- 4-bit input: B port parity input
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265 );
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266
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267 end Behavioral; No newline at end of file
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1 PROGRAM=PAR
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2 STATE=ROUTED
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3 TIMESPECS_MET=OFF No newline at end of file
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1 set -tmpdir "xst/projnav.tmp"
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2 set -xsthdpdir "xst"
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3 run
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4 -ifn BloqueRAM_int.prj
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5 -ofn BloqueRAM_int
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6 -ofmt NGC
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7 -p xc6slx9-3-tqg144
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8 -top BloqueRAM_int
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9 -opt_mode Speed
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10 -opt_level 1
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11 -power NO
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12 -iuc NO
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13 -keep_hierarchy No
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14 -netlist_hierarchy As_Optimized
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15 -rtlview Yes
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16 -glob_opt AllClockNets
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17 -read_cores YES
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18 -write_timing_constraints NO
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19 -cross_clock_analysis NO
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20 -hierarchy_separator /
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21 -bus_delimiter <>
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22 -case Maintain
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23 -slice_utilization_ratio 100
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24 -bram_utilization_ratio 100
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25 -dsp_utilization_ratio 100
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26 -lc Auto
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27 -reduce_control_sets Auto
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28 -fsm_extract YES -fsm_encoding Auto
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29 -safe_implementation No
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30 -fsm_style LUT
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31 -ram_extract Yes
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32 -ram_style Auto
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33 -rom_extract Yes
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34 -shreg_extract YES
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35 -rom_style Auto
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36 -auto_bram_packing NO
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37 -resource_sharing YES
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38 -async_to_sync NO
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39 -shreg_min_size 2
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40 -use_dsp48 Auto
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41 -iobuf YES
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42 -max_fanout 100000
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43 -bufg 16
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44 -register_duplication YES
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45 -register_balancing No
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46 -optimize_primitives NO
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47 -use_clock_enable Auto
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48 -use_sync_set Auto
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49 -use_sync_reset Auto
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50 -iob Auto
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51 -equivalent_register_removal YES
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52 -slice_utilization_ratio_maxmargin 5 No newline at end of file
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1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
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2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
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3 <center><big><big><b>System Settings</b></big></big></center><br>
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4 <A NAME="Environment Settings"></A>
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5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
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8 </tr>
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9 <tr bgcolor='#ffff99'>
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10 <td><b>Environment Variable</b></td>
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11 <td><b>xst</b></td>
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12 <td><b>ngdbuild</b></td>
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13 <td><b>map</b></td>
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14 <td><b>par</b></td>
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15 </tr>
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16 <tr>
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17 <td>PATHEXT</td>
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18 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
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19 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
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20 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
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21 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
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22 </tr>
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23 <tr>
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24 <td>Path</td>
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25 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
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26 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
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27 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
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28 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
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29 </tr>
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30 <tr>
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31 <td>XILINX</td>
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32 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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33 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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34 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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35 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
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36 </tr>
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37 <tr>
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38 <td>XILINX_DSP</td>
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39 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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40 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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41 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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42 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
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43 </tr>
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44 <tr>
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45 <td>XILINX_EDK</td>
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46 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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47 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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48 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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49 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
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50 </tr>
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51 <tr>
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52 <td>XILINX_PLANAHEAD</td>
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53 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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54 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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55 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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56 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
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57 </tr>
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58 </TABLE>
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59 <A NAME="Synthesis Property Settings"></A>
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60 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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61 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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62 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
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63 </tr>
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64 <tr bgcolor='#ffff99'>
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65 <td><b>Switch Name</b></td>
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66 <td><b>Property Name</b></td>
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67 <td><b>Value</b></td>
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68 <td><b>Default Value</b></td>
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69 </tr>
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70 <tr>
No newline at end of file
71 <td>-ifn</td>
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72 <td>&nbsp;</td>
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73 <td>BloqueRAM_int.prj</td>
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74 <td>&nbsp;</td>
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75 </tr>
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76 <tr>
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77 <td>-ofn</td>
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78 <td>&nbsp;</td>
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79 <td>BloqueRAM_int</td>
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80 <td>&nbsp;</td>
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81 </tr>
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82 <tr>
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83 <td>-ofmt</td>
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84 <td>&nbsp;</td>
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85 <td>NGC</td>
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86 <td>NGC</td>
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87 </tr>
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88 <tr>
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89 <td>-p</td>
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90 <td>&nbsp;</td>
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91 <td>xc6slx9-3-tqg144</td>
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92 <td>&nbsp;</td>
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93 </tr>
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94 <tr>
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95 <td>-top</td>
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96 <td>&nbsp;</td>
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97 <td>BloqueRAM_int</td>
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98 <td>&nbsp;</td>
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99 </tr>
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100 <tr>
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101 <td>-opt_mode</td>
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102 <td>Optimization Goal</td>
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103 <td>Speed</td>
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104 <td>Speed</td>
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105 </tr>
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106 <tr>
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107 <td>-opt_level</td>
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108 <td>Optimization Effort</td>
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109 <td>1</td>
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110 <td>1</td>
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111 </tr>
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112 <tr>
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113 <td>-power</td>
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114 <td>Power Reduction</td>
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115 <td>NO</td>
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116 <td>No</td>
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117 </tr>
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118 <tr>
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119 <td>-iuc</td>
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120 <td>Use synthesis Constraints File</td>
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121 <td>NO</td>
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122 <td>No</td>
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123 </tr>
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124 <tr>
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125 <td>-keep_hierarchy</td>
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126 <td>Keep Hierarchy</td>
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127 <td>No</td>
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128 <td>No</td>
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129 </tr>
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130 <tr>
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131 <td>-netlist_hierarchy</td>
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132 <td>Netlist Hierarchy</td>
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133 <td>As_Optimized</td>
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134 <td>As_Optimized</td>
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135 </tr>
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136 <tr>
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137 <td>-rtlview</td>
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138 <td>Generate RTL Schematic</td>
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139 <td>Yes</td>
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140 <td>No</td>
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141 </tr>
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142 <tr>
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143 <td>-glob_opt</td>
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144 <td>Global Optimization Goal</td>
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145 <td>AllClockNets</td>
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146 <td>AllClockNets</td>
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147 </tr>
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148 <tr>
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149 <td>-read_cores</td>
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150 <td>Read Cores</td>
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151 <td>YES</td>
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152 <td>Yes</td>
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153 </tr>
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154 <tr>
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155 <td>-write_timing_constraints</td>
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156 <td>Write Timing Constraints</td>
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157 <td>NO</td>
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158 <td>No</td>
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159 </tr>
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160 <tr>
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161 <td>-cross_clock_analysis</td>
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162 <td>Cross Clock Analysis</td>
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163 <td>NO</td>
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164 <td>No</td>
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165 </tr>
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166 <tr>
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167 <td>-bus_delimiter</td>
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168 <td>Bus Delimiter</td>
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169 <td>&lt;&gt;</td>
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170 <td>&lt;&gt;</td>
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171 </tr>
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172 <tr>
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173 <td>-slice_utilization_ratio</td>
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174 <td>Slice Utilization Ratio</td>
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175 <td>100</td>
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176 <td>100</td>
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177 </tr>
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178 <tr>
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179 <td>-bram_utilization_ratio</td>
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180 <td>BRAM Utilization Ratio</td>
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181 <td>100</td>
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182 <td>100</td>
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183 </tr>
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184 <tr>
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185 <td>-dsp_utilization_ratio</td>
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186 <td>DSP Utilization Ratio</td>
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187 <td>100</td>
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188 <td>100</td>
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189 </tr>
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190 <tr>
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191 <td>-reduce_control_sets</td>
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192 <td>&nbsp;</td>
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193 <td>Auto</td>
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194 <td>Auto</td>
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195 </tr>
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196 <tr>
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197 <td>-fsm_extract</td>
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198 <td>&nbsp;</td>
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199 <td>YES</td>
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200 <td>Yes</td>
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201 </tr>
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202 <tr>
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203 <td>-fsm_encoding</td>
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204 <td>&nbsp;</td>
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205 <td>Auto</td>
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206 <td>Auto</td>
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207 </tr>
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208 <tr>
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209 <td>-safe_implementation</td>
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210 <td>&nbsp;</td>
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211 <td>No</td>
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212 <td>No</td>
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213 </tr>
No newline at end of file
214 <tr>
No newline at end of file
215 <td>-fsm_style</td>
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216 <td>&nbsp;</td>
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217 <td>LUT</td>
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218 <td>LUT</td>
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219 </tr>
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220 <tr>
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221 <td>-ram_extract</td>
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222 <td>&nbsp;</td>
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223 <td>Yes</td>
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224 <td>Yes</td>
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225 </tr>
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226 <tr>
No newline at end of file
227 <td>-ram_style</td>
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228 <td>&nbsp;</td>
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229 <td>Auto</td>
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230 <td>Auto</td>
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231 </tr>
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232 <tr>
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233 <td>-rom_extract</td>
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234 <td>&nbsp;</td>
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235 <td>Yes</td>
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236 <td>Yes</td>
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237 </tr>
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238 <tr>
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239 <td>-shreg_extract</td>
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240 <td>&nbsp;</td>
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241 <td>YES</td>
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242 <td>Yes</td>
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243 </tr>
No newline at end of file
244 <tr>
No newline at end of file
245 <td>-rom_style</td>
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246 <td>&nbsp;</td>
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247 <td>Auto</td>
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248 <td>Auto</td>
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249 </tr>
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250 <tr>
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251 <td>-auto_bram_packing</td>
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252 <td>&nbsp;</td>
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253 <td>NO</td>
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254 <td>No</td>
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255 </tr>
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256 <tr>
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257 <td>-resource_sharing</td>
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258 <td>&nbsp;</td>
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259 <td>YES</td>
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260 <td>Yes</td>
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261 </tr>
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262 <tr>
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263 <td>-async_to_sync</td>
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264 <td>&nbsp;</td>
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265 <td>NO</td>
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266 <td>No</td>
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267 </tr>
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268 <tr>
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269 <td>-use_dsp48</td>
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270 <td>&nbsp;</td>
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271 <td>Auto</td>
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272 <td>Auto</td>
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273 </tr>
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274 <tr>
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275 <td>-iobuf</td>
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276 <td>&nbsp;</td>
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277 <td>YES</td>
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278 <td>Yes</td>
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279 </tr>
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280 <tr>
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281 <td>-max_fanout</td>
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282 <td>&nbsp;</td>
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283 <td>100000</td>
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284 <td>100000</td>
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285 </tr>
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286 <tr>
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287 <td>-bufg</td>
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288 <td>&nbsp;</td>
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289 <td>16</td>
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290 <td>16</td>
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291 </tr>
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292 <tr>
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293 <td>-register_duplication</td>
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294 <td>&nbsp;</td>
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295 <td>YES</td>
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296 <td>Yes</td>
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297 </tr>
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298 <tr>
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299 <td>-register_balancing</td>
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300 <td>&nbsp;</td>
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301 <td>No</td>
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302 <td>No</td>
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303 </tr>
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304 <tr>
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305 <td>-optimize_primitives</td>
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306 <td>&nbsp;</td>
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307 <td>NO</td>
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308 <td>No</td>
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309 </tr>
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310 <tr>
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311 <td>-use_clock_enable</td>
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312 <td>&nbsp;</td>
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313 <td>Auto</td>
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314 <td>Auto</td>
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315 </tr>
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316 <tr>
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317 <td>-use_sync_set</td>
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318 <td>&nbsp;</td>
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319 <td>Auto</td>
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320 <td>Auto</td>
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321 </tr>
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322 <tr>
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323 <td>-use_sync_reset</td>
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324 <td>&nbsp;</td>
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325 <td>Auto</td>
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326 <td>Auto</td>
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327 </tr>
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328 <tr>
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329 <td>-iob</td>
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330 <td>&nbsp;</td>
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331 <td>Auto</td>
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332 <td>Auto</td>
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333 </tr>
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334 <tr>
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335 <td>-equivalent_register_removal</td>
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336 <td>&nbsp;</td>
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337 <td>YES</td>
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338 <td>Yes</td>
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339 </tr>
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340 <tr>
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341 <td>-slice_utilization_ratio_maxmargin</td>
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342 <td>&nbsp;</td>
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343 <td>5</td>
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344 <td>0</td>
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345 </tr>
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346 </TABLE>
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347 <A NAME="Translation Property Settings"></A>
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348 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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349 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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350 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
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351 </tr>
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352 <tr bgcolor='#ffff99'>
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353 <td><b>Switch Name</b></td>
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354 <td><b>Property Name</b></td>
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355 <td><b>Value</b></td>
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356 <td><b>Default Value</b></td>
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357 </tr>
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358 <tr>
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359 <td>-intstyle</td>
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360 <td>&nbsp;</td>
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361 <td>ise</td>
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362 <td>None</td>
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363 </tr>
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364 <tr>
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365 <td>-dd</td>
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366 <td>&nbsp;</td>
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367 <td>_ngo</td>
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368 <td>None</td>
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369 </tr>
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370 <tr>
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371 <td>-p</td>
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372 <td>&nbsp;</td>
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373 <td>xc6slx9-tqg144-3</td>
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374 <td>None</td>
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375 </tr>
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376 </TABLE>
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377 <A NAME="Map Property Settings"></A>
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378 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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379 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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380 <TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
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381 </tr>
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382 <tr bgcolor='#ffff99'>
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383 <td><b>Switch Name</b></td>
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384 <td><b>Property Name</b></td>
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385 <td><b>Value</b></td>
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386 <td><b>Default Value</b></td>
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387 </tr>
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388 <tr>
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389 <td>-ol</td>
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390 <td>Place & Route Effort Level (Overall)</td>
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391 <td>high</td>
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392 <td>high</td>
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393 </tr>
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394 <tr>
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395 <td>-xt</td>
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396 <td>Extra Cost Tables</td>
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397 <td>0</td>
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398 <td>0</td>
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399 </tr>
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400 <tr>
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401 <td>-ir</td>
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402 <td>Use RLOC Constraints</td>
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403 <td>OFF</td>
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404 <td>OFF</td>
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405 </tr>
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406 <tr>
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407 <td>-t</td>
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408 <td>Starting Placer Cost Table (1-100) Map</td>
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409 <td>1</td>
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410 <td>0</td>
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411 </tr>
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412 <tr>
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413 <td>-r</td>
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414 <td>Register Ordering</td>
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415 <td>4</td>
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416 <td>4</td>
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417 </tr>
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418 <tr>
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419 <td>-intstyle</td>
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420 <td>&nbsp;</td>
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421 <td>ise</td>
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422 <td>None</td>
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423 </tr>
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424 <tr>
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425 <td>-lc</td>
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426 <td>LUT Combining</td>
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427 <td>off</td>
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428 <td>off</td>
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429 </tr>
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430 <tr>
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431 <td>-o</td>
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432 <td>&nbsp;</td>
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433 <td>BloqueRAM_int_map.ncd</td>
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434 <td>None</td>
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435 </tr>
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436 <tr>
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438 <td>&nbsp;</td>
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440 <td>false</td>
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441 </tr>
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442 <tr>
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445 <td>off</td>
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446 <td>off</td>
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447 </tr>
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448 <tr>
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450 <td>&nbsp;</td>
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451 <td>xc6slx9-tqg144-3</td>
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452 <td>None</td>
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453 </tr>
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454 </TABLE>
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455 <A NAME="Place and Route Property Settings"></A>
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456 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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457 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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458 <TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
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459 </tr>
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460 <tr bgcolor='#ffff99'>
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461 <td><b>Switch Name</b></td>
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462 <td><b>Property Name</b></td>
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463 <td><b>Value</b></td>
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464 <td><b>Default Value</b></td>
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465 </tr>
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466 <tr>
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467 <td>-intstyle</td>
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468 <td>&nbsp;</td>
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469 <td>ise</td>
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470 <td>&nbsp;</td>
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471 </tr>
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472 <tr>
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473 <td>-mt</td>
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474 <td>Enable Multi-Threading</td>
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475 <td>off</td>
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476 <td>off</td>
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477 </tr>
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478 <tr>
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479 <td>-ol</td>
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480 <td>Place & Route Effort Level (Overall)</td>
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481 <td>high</td>
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482 <td>std</td>
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483 </tr>
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484 <tr>
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486 <td>&nbsp;</td>
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488 <td>false</td>
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489 </tr>
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491 <A NAME="Operating System Information"></A>
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492 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
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493 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
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494 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
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495 </tr>
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496 <tr bgcolor='#ffff99'>
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497 <td><b>Operating System Information</b></td>
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498 <td><b>xst</b></td>
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499 <td><b>ngdbuild</b></td>
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500 <td><b>map</b></td>
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501 <td><b>par</b></td>
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502 </tr>
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503 <tr>
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504 <td>CPU Architecture/Speed</td>
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505 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
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506 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
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507 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
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508 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
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509 </tr>
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510 <tr>
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511 <td>Host</td>
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512 <td>Lenovo-PC</td>
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513 <td>Lenovo-PC</td>
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514 <td>Lenovo-PC</td>
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515 <td>Lenovo-PC</td>
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516 </tr>
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517 <tr>
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518 <td>OS Name</td>
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519 <td>Microsoft , 64-bit</td>
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520 <td>Microsoft , 64-bit</td>
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521 <td>Microsoft , 64-bit</td>
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522 <td>Microsoft , 64-bit</td>
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523 </tr>
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524 <tr>
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525 <td>OS Release</td>
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526 <td>major release (build 9200)</td>
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527 <td>major release (build 9200)</td>
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528 <td>major release (build 9200)</td>
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530 </tr>
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531 </TABLE>
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1 Release 14.7 Map P.20131013 (nt64)
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2 Xilinx Map Application Log File for Design 'BloqueRAM_int'
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3
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4 Design Information
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5 ------------------
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6 Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
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7 high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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8 -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd
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9 BloqueRAM_int.pcf
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10 Target Device : xc6slx9
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11 Target Package : tqg144
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12 Target Speed : -3
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13 Mapper Version : spartan6 -- $Revision: 1.55 $
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14 Mapped Date : Mon Dec 14 11:38:44 2015
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15
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16 Mapping design into LUTs...
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17 Running directed packing...
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18 Running delay-based LUT packing...
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19 Updating timing models...
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20 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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21 (.mrp).
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22 Running timing-driven placement...
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23 Total REAL time at the beginning of Placer: 7 secs
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24 Total CPU time at the beginning of Placer: 4 secs
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25
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26 Phase 1.1 Initial Placement Analysis
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27 Phase 1.1 Initial Placement Analysis (Checksum:c0e) REAL time: 9 secs
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28
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29 Phase 2.7 Design Feasibility Check
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30 Phase 2.7 Design Feasibility Check (Checksum:c0e) REAL time: 9 secs
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31
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32 Phase 3.31 Local Placement Optimization
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33 Phase 3.31 Local Placement Optimization (Checksum:c0e) REAL time: 9 secs
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34
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35 Phase 4.2 Initial Placement for Architecture Specific Features
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36 ...
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37 .....
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38 Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:ecc6) REAL time: 11 secs
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39
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40 Phase 5.36 Local Placement Optimization
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41 Phase 5.36 Local Placement Optimization (Checksum:ecc6) REAL time: 11 secs
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42
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43 Phase 6.30 Global Clock Region Assignment
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44 Phase 6.30 Global Clock Region Assignment (Checksum:ecc6) REAL time: 11 secs
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45
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46 Phase 7.3 Local Placement Optimization
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47 ...
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48 .....
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49 Phase 7.3 Local Placement Optimization (Checksum:1e558ea8) REAL time: 12 secs
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50
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51 Phase 8.5 Local Placement Optimization
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52 Phase 8.5 Local Placement Optimization (Checksum:1e558ea8) REAL time: 12 secs
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53
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54 Phase 9.8 Global Placement
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55 .................
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56 ....................
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57 Phase 9.8 Global Placement (Checksum:dadb6f42) REAL time: 12 secs
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58
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59 Phase 10.5 Local Placement Optimization
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60 Phase 10.5 Local Placement Optimization (Checksum:dadb6f42) REAL time: 12 secs
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61
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62 Phase 11.18 Placement Optimization
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63 Phase 11.18 Placement Optimization (Checksum:686ff5d2) REAL time: 13 secs
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64
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65 Phase 12.5 Local Placement Optimization
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66 Phase 12.5 Local Placement Optimization (Checksum:686ff5d2) REAL time: 13 secs
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67
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68 Phase 13.34 Placement Validation
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69 Phase 13.34 Placement Validation (Checksum:685119d3) REAL time: 13 secs
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70
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71 Total REAL time to Placer completion: 13 secs
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72 Total CPU time to Placer completion: 7 secs
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73 Running post-placement packing...
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74 Writing output files...
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75
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76 Design Summary
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77 --------------
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78
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79 Design Summary:
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80 Number of errors: 0
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81 Number of warnings: 0
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82 Slice Logic Utilization:
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83 Number of Slice Registers: 34 out of 11,440 1%
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84 Number used as Flip Flops: 34
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85 Number used as Latches: 0
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86 Number used as Latch-thrus: 0
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87 Number used as AND/OR logics: 0
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88 Number of Slice LUTs: 5 out of 5,720 1%
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89 Number used as logic: 5 out of 5,720 1%
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90 Number using O6 output only: 3
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91 Number using O5 output only: 0
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92 Number using O5 and O6: 2
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93 Number used as ROM: 0
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94 Number used as Memory: 0 out of 1,440 0%
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95
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96 Slice Logic Distribution:
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97 Number of occupied Slices: 11 out of 1,430 1%
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98 Number of MUXCYs used: 0 out of 2,860 0%
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99 Number of LUT Flip Flop pairs used: 37
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100 Number with an unused Flip Flop: 3 out of 37 8%
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101 Number with an unused LUT: 32 out of 37 86%
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102 Number of fully used LUT-FF pairs: 2 out of 37 5%
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103 Number of unique control sets: 4
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104 Number of slice register sites lost
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105 to control set restrictions: 14 out of 11,440 1%
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106
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107 A LUT Flip Flop pair for this architecture represents one LUT paired with
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108 one Flip Flop within a slice. A control set is a unique combination of
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109 clock, reset, set, and enable signals for a registered element.
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110 The Slice Logic Distribution report is not meaningful if the design is
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111 over-mapped for a non-slice resource or if Placement fails.
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112
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113 IO Utilization:
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114 Number of bonded IOBs: 33 out of 102 32%
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115
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116 Specific Feature Utilization:
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117 Number of RAMB16BWERs: 1 out of 32 3%
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118 Number of RAMB8BWERs: 0 out of 64 0%
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119 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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120 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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121 Number of BUFG/BUFGMUXs: 1 out of 16 6%
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122 Number used as BUFGs: 1
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123 Number used as BUFGMUX: 0
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124 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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125 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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126 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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127 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
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128 Number of BSCANs: 0 out of 4 0%
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129 Number of BUFHs: 0 out of 128 0%
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130 Number of BUFPLLs: 0 out of 8 0%
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131 Number of BUFPLL_MCBs: 0 out of 4 0%
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132 Number of DSP48A1s: 0 out of 16 0%
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133 Number of ICAPs: 0 out of 1 0%
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134 Number of MCBs: 0 out of 2 0%
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135 Number of PCILOGICSEs: 0 out of 2 0%
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136 Number of PLL_ADVs: 0 out of 2 0%
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137 Number of PMVs: 0 out of 1 0%
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138 Number of STARTUPs: 0 out of 1 0%
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139 Number of SUSPEND_SYNCs: 0 out of 1 0%
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140
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141 Average Fanout of Non-Clock Nets: 1.60
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142
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143 Peak Memory Usage: 330 MB
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144 Total REAL time to MAP completion: 13 secs
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145 Total CPU time to MAP completion: 8 secs
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146
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147 Mapping completed.
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148 See MAP report file "BloqueRAM_int_map.mrp" for details. No newline at end of file
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1 Release 14.7 Map P.20131013 (nt64)
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2 Xilinx Mapping Report File for Design 'BloqueRAM_int'
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3
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4 Design Information
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5 ------------------
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6 Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
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7 high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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8 -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd
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9 BloqueRAM_int.pcf
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10 Target Device : xc6slx9
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11 Target Package : tqg144
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12 Target Speed : -3
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13 Mapper Version : spartan6 -- $Revision: 1.55 $
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14 Mapped Date : Mon Dec 14 11:38:44 2015
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15
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16 Design Summary
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17 --------------
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18 Number of errors: 0
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19 Number of warnings: 0
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20 Slice Logic Utilization:
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21 Number of Slice Registers: 34 out of 11,440 1%
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22 Number used as Flip Flops: 34
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23 Number used as Latches: 0
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24 Number used as Latch-thrus: 0
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25 Number used as AND/OR logics: 0
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26 Number of Slice LUTs: 5 out of 5,720 1%
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27 Number used as logic: 5 out of 5,720 1%
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28 Number using O6 output only: 3
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29 Number using O5 output only: 0
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30 Number using O5 and O6: 2
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31 Number used as ROM: 0
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32 Number used as Memory: 0 out of 1,440 0%
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33
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34 Slice Logic Distribution:
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35 Number of occupied Slices: 11 out of 1,430 1%
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36 Number of MUXCYs used: 0 out of 2,860 0%
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37 Number of LUT Flip Flop pairs used: 37
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38 Number with an unused Flip Flop: 3 out of 37 8%
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39 Number with an unused LUT: 32 out of 37 86%
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40 Number of fully used LUT-FF pairs: 2 out of 37 5%
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41 Number of unique control sets: 4
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42 Number of slice register sites lost
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43 to control set restrictions: 14 out of 11,440 1%
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44
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45 A LUT Flip Flop pair for this architecture represents one LUT paired with
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46 one Flip Flop within a slice. A control set is a unique combination of
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47 clock, reset, set, and enable signals for a registered element.
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48 The Slice Logic Distribution report is not meaningful if the design is
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49 over-mapped for a non-slice resource or if Placement fails.
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50
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51 IO Utilization:
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52 Number of bonded IOBs: 33 out of 102 32%
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53
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54 Specific Feature Utilization:
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55 Number of RAMB16BWERs: 1 out of 32 3%
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56 Number of RAMB8BWERs: 0 out of 64 0%
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57 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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58 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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59 Number of BUFG/BUFGMUXs: 1 out of 16 6%
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60 Number used as BUFGs: 1
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61 Number used as BUFGMUX: 0
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62 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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63 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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64 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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65 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
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66 Number of BSCANs: 0 out of 4 0%
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67 Number of BUFHs: 0 out of 128 0%
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68 Number of BUFPLLs: 0 out of 8 0%
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69 Number of BUFPLL_MCBs: 0 out of 4 0%
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70 Number of DSP48A1s: 0 out of 16 0%
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71 Number of ICAPs: 0 out of 1 0%
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72 Number of MCBs: 0 out of 2 0%
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73 Number of PCILOGICSEs: 0 out of 2 0%
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74 Number of PLL_ADVs: 0 out of 2 0%
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75 Number of PMVs: 0 out of 1 0%
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76 Number of STARTUPs: 0 out of 1 0%
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77 Number of SUSPEND_SYNCs: 0 out of 1 0%
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78
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79 Average Fanout of Non-Clock Nets: 1.60
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80
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81 Peak Memory Usage: 330 MB
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82 Total REAL time to MAP completion: 13 secs
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83 Total CPU time to MAP completion: 8 secs
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84
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85 Table of Contents
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86 -----------------
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87 Section 1 - Errors
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88 Section 2 - Warnings
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89 Section 3 - Informational
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90 Section 4 - Removed Logic Summary
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91 Section 5 - Removed Logic
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92 Section 6 - IOB Properties
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93 Section 7 - RPMs
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94 Section 8 - Guide Report
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95 Section 9 - Area Group and Partition Summary
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96 Section 10 - Timing Report
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97 Section 11 - Configuration String Information
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98 Section 12 - Control Set Information
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99 Section 13 - Utilization by Hierarchy
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100
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101 Section 1 - Errors
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102 ------------------
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103
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104 Section 2 - Warnings
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105 --------------------
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106
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107 Section 3 - Informational
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108 -------------------------
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109 INFO:MapLib:562 - No environment variables are currently set.
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110 INFO:LIT:244 - All of the single ended outputs in this design are using slew
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111 rate limited output drivers. The delay on speed critical single ended outputs
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112 can be dramatically reduced by designating them as fast outputs.
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113 INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
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114 0.000 to 85.000 Celsius)
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115 INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
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116 1.260 Volts)
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117 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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118 (.mrp).
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119 INFO:Pack:1650 - Map created a placed design.
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120
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121 Section 4 - Removed Logic Summary
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122 ---------------------------------
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123 2 block(s) optimized away
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124
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125 Section 5 - Removed Logic
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126 -------------------------
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127
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128 Optimized Block(s):
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129 TYPE BLOCK
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130 GND XST_GND
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131 VCC XST_VCC
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132
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133 To enable printing of redundant blocks removed and signals merged, set the
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134 detailed map report option and rerun map.
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135
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136 Section 6 - IOB Properties
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137 --------------------------
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138
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139 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
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140 | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
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141 | | | | | Term | Strength | Rate | | | Delay |
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142 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
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143 | ADDR_RAM<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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144 | ADDR_RAM<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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145 | ADDR_RAM<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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146 | ADDR_RAM<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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147 | ADDR_RAM<4> | IOB | INPUT | LVCMOS25 | | | | | | |
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148 | ADDR_RAM<5> | IOB | INPUT | LVCMOS25 | | | | | | |
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149 | ADDR_RAM<6> | IOB | INPUT | LVCMOS25 | | | | | | |
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150 | ADDR_RAM<7> | IOB | INPUT | LVCMOS25 | | | | | | |
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151 | ADDR_RAM<8> | IOB | INPUT | LVCMOS25 | | | | | | |
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152 | ADDR_RAM<9> | IOB | INPUT | LVCMOS25 | | | | | | |
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153 | CS_2 | IOB | INPUT | LVCMOS25 | | | | | | |
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154 | CS_1_bar | IOB | INPUT | LVCMOS25 | | | | | | |
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155 | DATA_RAM<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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156 | DATA_RAM<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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157 | DATA_RAM<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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158 | DATA_RAM<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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159 | DATA_RAM<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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160 | DATA_RAM<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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161 | DATA_RAM<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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162 | DATA_RAM<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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163 | DATA_RAM<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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164 | DATA_RAM<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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165 | DATA_RAM<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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166 | DATA_RAM<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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167 | DATA_RAM<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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168 | DATA_RAM<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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169 | DATA_RAM<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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170 | DATA_RAM<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
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171 | LB_bar | IOB | INPUT | LVCMOS25 | | | | | | |
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172 | OE_bar | IOB | INPUT | LVCMOS25 | | | | | | |
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173 | UB_bar | IOB | INPUT | LVCMOS25 | | | | | | |
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174 | WEA_bar | IOB | INPUT | LVCMOS25 | | | | | | |
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175 | clk_main | IOB | INPUT | LVCMOS25 | | | | | | |
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176 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
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177
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178 Section 7 - RPMs
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179 ----------------
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180
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181 Section 8 - Guide Report
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182 ------------------------
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183 Guide not run on this design.
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184
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185 Section 9 - Area Group and Partition Summary
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186 --------------------------------------------
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187
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188 Partition Implementation Status
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189 -------------------------------
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190
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191 No Partitions were found in this design.
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192
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193 -------------------------------
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194
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195 Area Group Information
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196 ----------------------
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197
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198 No area groups were found in this design.
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199
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200 ----------------------
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201
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202 Section 10 - Timing Report
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203 --------------------------
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204 A logic-level (pre-route) timing report can be generated by using Xilinx static
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205 timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
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206 mapped NCD and PCF files. Please note that this timing report will be generated
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207 using estimated delay information. For accurate numbers, please generate a
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208 timing report with the post Place and Route NCD file.
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209
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210 For more information about the Timing Analyzer, consult the Xilinx Timing
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211 Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
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212 Command Line Tools User Guide "TRACE" chapter.
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213
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214 Section 11 - Configuration String Details
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215 -----------------------------------------
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216 Use the "-detail" map option to print out Configuration Strings
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217
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218 Section 12 - Control Set Information
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219 ------------------------------------
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220 Use the "-detail" map option to print out Control Set Information.
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221
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222 Section 13 - Utilization by Hierarchy
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223 -------------------------------------
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224 Use the "-detail" map option to print out the Utilization by Hierarchy section. No newline at end of file
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1 XILINX-XDB 0.1 STUB 0.1 ASCII
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2 XILINX-XDM V1.6
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3 ###4848:XlxV32DM 3fff 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The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
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The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
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The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
1 NO CONTENT: new file 10644
NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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