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Versión inicial de los bloques de comunicación para el módulo de procesamiento.
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1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2 <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4 <!-- -->
5
6 <!-- For tool use only. Do not edit. -->
7
8 <!-- -->
9
10 <!-- ProjectNavigator created generated project file. -->
11
12 <!-- For use in tracking generated file and other information -->
13
14 <!-- allowing preservation of process status. -->
15
16 <!-- -->
17
18 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
19
20 <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
21
22 <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="Controlador_Mem_RAM.xise"/>
23
24 <files xmlns="http://www.xilinx.com/XMLSchema"/>
25
26 <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
27
28 </generated_project>
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 16:52:35 12/09/2015
6 -- Design Name:
7 -- Module Name: Controlador_Mem_RAM - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity Controlador_Mem_RAM is
33 GENERIC(
34 num_ch: INTEGER :=3;
35 id_ch_lenght: INTEGER :=3;
36 data_lenght: INTEGER :=24;
37 id_data_lenght: INTEGER :=1 --Para 250ksp deben ser 18 bits
38 );
39
40 PORT(
41 clk: IN STD_LOGIC;
42 rdy_ch1: IN STD_LOGIC_VECTOR((num_ch-1) downto 0);
43 start_sender: IN STD_LOGIC;
44 sum: IN STD_LOGIC_VECTOR(13 downto 0);
45 serial_output: OUT STD_LOGIC
46 );
47 end Controlador_Mem_RAM;
48
49 architecture Behavioral of Controlador_Mem_RAM is
50
51 begin
52
53
54 end Behavioral;
55
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@@ -0,0 +1,359
1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
3
4 <header>
5 <!-- ISE source project file created by Project Navigator. -->
6 <!-- -->
7 <!-- This file contains project source information including a list of -->
8 <!-- project source files, project and process properties. This file, -->
9 <!-- along with the project source files, is sufficient to open and -->
10 <!-- implement in ISE Project Navigator. -->
11 <!-- -->
12 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
13 </header>
14
15 <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
16
17 <files>
18 <file xil_pn:name="Controlador_Mem_RAM.vhd" xil_pn:type="FILE_VHDL">
19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
21 </file>
22 </files>
23
24 <properties>
25 <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
26 <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
27 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
28 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
29 <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
30 <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
31 <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
32 <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
33 <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
34 <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
35 <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
36 <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
37 <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
38 <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
39 <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
40 <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
41 <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
42 <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
43 <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
44 <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
45 <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
46 <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
47 <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
48 <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
49 <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
50 <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
51 <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
52 <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
53 <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
54 <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
55 <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
56 <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
57 <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
58 <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
59 <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
60 <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
61 <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
62 <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
63 <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
64 <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
65 <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
66 <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
67 <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
68 <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
69 <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
70 <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
71 <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
72 <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
73 <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
74 <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
75 <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
76 <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
77 <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
78 <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
79 <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
80 <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
81 <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
82 <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
83 <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
84 <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
85 <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
86 <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
87 <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
88 <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
89 <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
90 <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
91 <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
92 <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
93 <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
94 <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
95 <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
96 <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
97 <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
98 <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
99 <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
100 <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
101 <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
102 <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
103 <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
104 <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
105 <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
106 <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
107 <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
108 <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
109 <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
110 <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
111 <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
112 <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
113 <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
114 <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
115 <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
116 <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
117 <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
118 <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
119 <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
120 <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
121 <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
122 <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
123 <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
124 <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
125 <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
126 <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
127 <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
128 <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
129 <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
130 <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
131 <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
132 <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
133 <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
134 <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
135 <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
136 <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
137 <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Controlador_Mem_RAM|Behavioral" xil_pn:valueState="non-default"/>
138 <property xil_pn:name="Implementation Top File" xil_pn:value="Controlador_Mem_RAM.vhd" xil_pn:valueState="non-default"/>
139 <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Controlador_Mem_RAM" xil_pn:valueState="non-default"/>
140 <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
141 <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
142 <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
143 <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
144 <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
145 <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
146 <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
147 <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
148 <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
149 <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
150 <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
151 <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
152 <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
153 <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
154 <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
155 <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
156 <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
157 <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
158 <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
159 <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
160 <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
161 <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
162 <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
163 <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
164 <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
165 <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
166 <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
167 <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
168 <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
169 <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
170 <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
171 <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
172 <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
173 <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
174 <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
175 <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
176 <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
177 <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
178 <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
179 <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
180 <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
181 <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
182 <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
183 <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
184 <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
185 <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
186 <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
187 <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
188 <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
189 <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
190 <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
191 <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
192 <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
193 <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
194 <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
195 <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
196 <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
197 <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
198 <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
199 <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
200 <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
201 <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
202 <property xil_pn:name="Output File Name" xil_pn:value="Controlador_Mem_RAM" xil_pn:valueState="default"/>
203 <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
204 <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
205 <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
206 <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
207 <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
208 <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
209 <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
210 <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
211 <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
212 <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
213 <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
214 <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
215 <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_map.vhd" xil_pn:valueState="default"/>
216 <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_timesim.vhd" xil_pn:valueState="default"/>
217 <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_synthesis.vhd" xil_pn:valueState="default"/>
218 <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Controlador_Mem_RAM_translate.vhd" xil_pn:valueState="default"/>
219 <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
220 <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
221 <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
222 <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
223 <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
224 <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
225 <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
226 <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
227 <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
228 <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
229 <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
230 <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
231 <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
232 <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
233 <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
234 <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
235 <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
236 <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
237 <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
238 <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
239 <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
240 <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="Controlador_Mem_RAM" xil_pn:valueState="default"/>
241 <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
242 <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
243 <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
244 <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
245 <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
246 <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
247 <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
248 <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
249 <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
250 <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
251 <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
252 <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
253 <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
254 <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
255 <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
256 <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
257 <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
258 <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
259 <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
260 <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
261 <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
262 <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
263 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
264 <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
265 <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
266 <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
267 <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
268 <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
269 <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
270 <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
271 <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
272 <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
273 <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
274 <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
275 <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
276 <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
277 <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
278 <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
279 <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
280 <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
281 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
282 <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
283 <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
284 <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
285 <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
286 <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
287 <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
288 <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
289 <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
290 <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
291 <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
292 <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
293 <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
294 <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
295 <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
296 <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
297 <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
298 <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
299 <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
300 <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
301 <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
302 <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
303 <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
304 <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
305 <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
306 <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
307 <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
308 <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
309 <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
310 <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
311 <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
312 <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
313 <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
314 <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
315 <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
316 <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
317 <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
318 <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
319 <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
320 <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
321 <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
322 <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
323 <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
324 <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
325 <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
326 <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
327 <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
328 <!-- -->
329 <!-- The following properties are for internal use only. These should not be modified.-->
330 <!-- -->
331 <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
332 <property xil_pn:name="PROP_DesignName" xil_pn:value="Controlador_Mem_RAM" xil_pn:valueState="non-default"/>
333 <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
334 <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
335 <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
336 <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
337 <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
338 <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
339 <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
340 <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2015-12-09T16:52:03" xil_pn:valueState="non-default"/>
341 <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E173BA5612214290878C33D973D2EB48" xil_pn:valueState="non-default"/>
342 <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
343 <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
344 </properties>
345
346 <bindings/>
347
348 <libraries/>
349
350 <autoManagedFiles>
351 <!-- The following files are identified by `include statements in verilog -->
352 <!-- source files and are automatically managed by Project Navigator. -->
353 <!-- -->
354 <!-- Do not hand-edit this section, as it will be overwritten when the -->
355 <!-- project is analyzed based on files automatically identified as -->
356 <!-- include files. -->
357 </autoManagedFiles>
358
359 </project>
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1 <HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
4 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
5 <TD ALIGN=CENTER COLSPAN='4'><B>Controlador_Mem_RAM Project Status</B></TD></TR>
6 <TR ALIGN=LEFT>
7 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
8 <TD>Controlador_Mem_RAM.xise</TD>
9 <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
10 <TD> No Errors </TD>
11 </TR>
12 <TR ALIGN=LEFT>
13 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
14 <TD>Controlador_Mem_RAM</TD>
15 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
16 <TD>New</TD>
17 </TR>
18 <TR ALIGN=LEFT>
19 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
20 <TD>xc6slx9-3tqg144</TD>
21 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
22 <TD>&nbsp;</TD>
23 </TR>
24 <TR ALIGN=LEFT>
25 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
26 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
27 <TD>&nbsp;</TD>
28 </TR>
29 <TR ALIGN=LEFT>
30 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
31 <TD>Balanced</TD>
32 <TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
33 <TD>
34 &nbsp;</TD>
35 </TR>
36 <TR ALIGN=LEFT>
37 <TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
38 <TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
39 <TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
40 <TD>&nbsp;</TD>
41 </TR>
42 <TR ALIGN=LEFT>
43 <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
44 <TD>&nbsp;</TD>
45 <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
46 <TD>&nbsp;&nbsp;</TD>
47 </TR>
48 </TABLE>
49
50
51
52
53
54
55
56
57
58
59
60 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
61 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
62 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
63 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
64 <TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
65 <TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
66 <TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
67 <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
68 <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
69 <TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
70 <TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
71 </TABLE>
72 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
73 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
74 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
75 </TABLE>
76
77
78 <br><center><b>Date Generated:</b> 12/10/2015 - 08:38:12</center>
79 </BODY></HTML> No newline at end of file
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1 <?xml version="1.0" encoding="UTF-8"?>
2 <!-- IMPORTANT: This is an internal file that has been generated -->
3 <!-- by the Xilinx ISE software. Any direct editing or -->
4 <!-- changes made to this file may result in unpredictable -->
5 <!-- behavior or data corruption. It is strongly advised that -->
6 <!-- users do not edit the contents of this file. -->
7 <!-- -->
8 <!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
9
10 <messages>
11 <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Controlador_Mem_RAM/Controlador_Mem_RAM.vhd&quot; into library work</arg>
12 </msg>
13
14 </messages>
15
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@@ -0,0 +1,78
1 <?xml version='1.0' encoding='utf-8'?>
2 <!--This is an ISE project configuration file.-->
3 <!--It holds project specific layout data for the projectmgr plugin.-->
4 <!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
5 <Project version="2" owner="projectmgr" name="Controlador_Mem_RAM" >
6 <!--This is an ISE project configuration file.-->
7 <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
8 <ClosedNodes>
9 <ClosedNodesVersion>2</ClosedNodesVersion>
10 </ClosedNodes>
11 <SelectedItems>
12 <SelectedItem>Controlador_Mem_RAM - Behavioral (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Controlador_Mem_RAM/Controlador_Mem_RAM.vhd)</SelectedItem>
13 </SelectedItems>
14 <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
15 <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
16 <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001b8000000020000000000000000000000000200000064ffffffff000000810000000300000002000001b80000000100000003000000000000000100000003</ViewHeaderState>
17 <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
18 <CurrentItem>Controlador_Mem_RAM - Behavioral (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Controlador_Mem_RAM/Controlador_Mem_RAM.vhd)</CurrentItem>
19 </ItemView>
20 <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
21 <ClosedNodes>
22 <ClosedNodesVersion>1</ClosedNodesVersion>
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1 <?xml version='1.0' encoding='UTF-8'?>
2 <report-views version="2.0" >
3 <header>
4 <DateModified>2015-12-10T08:38:12</DateModified>
5 <ModuleName>Controlador_Mem_RAM</ModuleName>
6 <SummaryTimeStamp>Unknown</SummaryTimeStamp>
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17 <toc-item title="Performance Summary" target="Performance Summary" />
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59 <toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
60 <toc-item title="HDL Compilation" target=" HDL Compilation " />
61 <toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
62 <toc-item title="HDL Analysis" target=" HDL Analysis " />
63 <toc-item title="HDL Parsing" target=" HDL Parsing " />
64 <toc-item title="HDL Elaboration" target=" HDL Elaboration " />
65 <toc-item title="HDL Synthesis" target=" HDL Synthesis " />
66 <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
67 <toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
68 <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
69 <toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
70 <toc-item title="Partition Report" target=" Partition Report " />
71 <toc-item title="Final Report" target=" Final Report " />
72 <toc-item title="Design Summary" target=" Design Summary " />
73 <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
74 <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
75 <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
76 <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
77 <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
78 <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
79 <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
80 <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
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85 <view inputState="Synthesized" program="ngdbuild" type="Report" file="Controlador_Mem_RAM.bld" label="Translation Report" >
86 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
87 <toc-item title="Command Line" target="Command Line:" />
88 <toc-item title="Partition Status" target="Partition Implementation Status" />
89 <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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91 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM_map.mrp" label="Map Report" >
92 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
93 <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
94 <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
95 <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
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97 <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
98 <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
99 <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
100 <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
101 <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
102 <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
103 <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
104 <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
105 <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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107 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM.par" label="Place and Route Report" >
108 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
109 <toc-item title="Device Utilization" target="Device Utilization Summary:" />
110 <toc-item title="Router Information" target="Starting Router" />
111 <toc-item title="Partition Status" target="Partition Implementation Status" />
112 <toc-item title="Clock Report" target="Generating Clock Report" />
113 <toc-item title="Timing Results" target="Timing Score:" />
114 <toc-item title="Final Summary" target="Peak Memory Usage:" />
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118 <toc-item title="Timing Report Description" target="Device,package,speed:" />
119 <toc-item title="Informational Messages" target="INFO:" />
120 <toc-item title="Warning Messages" target="WARNING:" />
121 <toc-item title="Timing Constraints" target="Timing constraint:" />
122 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
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124 <toc-item title="Timing Summary" target="Timing summary:" />
125 <toc-item title="Trace Settings" target="Trace Settings:" />
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128 <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
129 <toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
130 <toc-item title="Pin Resources" target="** Pin Resources **" />
131 <toc-item title="Global Resources" target="** Global Control Resources **" />
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133 <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="Controlador_Mem_RAM.tim" label="CPLD Timing Report (Text)" >
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135 <toc-item title="Performance Summary" target="Performance Summary:" />
136 </view>
137 <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="Controlador_Mem_RAM.pwr" label="Power Report" >
138 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
139 <toc-item title="Power summary" target="Power summary" />
140 <toc-item title="Thermal summary" target="Thermal summary" />
141 </view>
142 <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="Controlador_Mem_RAM.bgn" label="Bitgen Report" >
143 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
144 <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
145 <toc-item title="Final Summary" target="DRC detected" />
146 </view>
147 </viewgroup>
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149 <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
150 <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/Controlador_Mem_RAM_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
151 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
152 </view>
153 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/Controlador_Mem_RAM_translate.nlf" label="Post-Translate Simulation Model Report" >
154 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
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156 <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
157 <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Controlador_Mem_RAM_map.map" label="Map Log File" >
158 <toc-item title="Top of Report" target="Release" searchDir="Forward" />
159 <toc-item title="Design Information" target="Design Information" />
160 <toc-item title="Design Summary" target="Design Summary" />
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162 <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
163 <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_preroute.twr" label="Post-Map Static Timing Report" >
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165 <toc-item title="Timing Report Description" target="Device,package,speed:" />
166 <toc-item title="Informational Messages" target="INFO:" />
167 <toc-item title="Warning Messages" target="WARNING:" />
168 <toc-item title="Timing Constraints" target="Timing constraint:" />
169 <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
170 <toc-item title="Data Sheet Report" target="Data Sheet report:" />
171 <toc-item title="Timing Summary" target="Timing summary:" />
172 <toc-item title="Trace Settings" target="Trace Settings:" />
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176 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
177 </view>
178 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="Controlador_Mem_RAM_pad.txt" label="Pad Report" >
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181 <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="Controlador_Mem_RAM.unroutes" label="Unroutes Report" >
182 <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
183 </view>
184 <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM_preroute.tsi" label="Post-Map Constraints Interaction Report" >
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188 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.dly" label="Asynchronous Delay Report" />
189 <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.clk_rgn" label="Clock Region Report" />
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200 <toc-item title="Component" target="Component " />
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202 <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="Controlador_Mem_RAM.lck" label="Back-annotate Pin Report" >
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204 <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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208 <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
209 </view>
210 <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/Controlador_Mem_RAM_timesim.nlf" label="Post-Fit Simulation Model Report" />
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213 </viewgroup>
214 </body>
215 </report-views>
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1 Release 14.7 ngdbuild P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
5 -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 BloqueRAM_int.ngc
6 BloqueRAM_int.ngd
7
8 Reading NGO file
9 "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SR
10 AM_16kb_v02/BloqueRAM_int.ngc" ...
11 Gathering constraint information from source properties...
12 Done.
13
14 Resolving constraint associations...
15 Checking Constraint Associations...
16 Done...
17
18 Checking expanded design ...
19
20 Partition Implementation Status
21 -------------------------------
22
23 No Partitions were found in this design.
24
25 -------------------------------
26
27 NGDBUILD Design Results Summary:
28 Number of errors: 0
29 Number of warnings: 0
30
31 Total memory usage is 173092 kilobytes
32
33 Writing NGD file "BloqueRAM_int.ngd" ...
34 Total REAL time to NGDBUILD completion: 4 sec
35 Total CPU time to NGDBUILD completion: 3 sec
36
37 Writing NGDBUILD log file "BloqueRAM_int.bld"...
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1 xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SRAM_16kb_v02/BloqueRAM_int.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/Memoria_SRAM_16kb_v02/BloqueRAM_int.syr"
2 ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc6slx9-tqg144-3 BloqueRAM_int.ngc BloqueRAM_int.ngd
3 map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd BloqueRAM_int.pcf
4 par -w -intstyle ise -ol high -mt off BloqueRAM_int_map.ncd BloqueRAM_int.ncd BloqueRAM_int.pcf
5 trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr BloqueRAM_int.pcf
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1 work
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1 XILINX-XDB 0.1 STUB 0.1 ASCII
2 XILINX-XDM V1.6
3 ###4956:XlxV32DM 3fff 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3fff 10e0eNrtmruu5DgOhl+ms0lE6mKrCp3vUzRgyxbQyW5wsNFBv/uKFO2h7JJhxzsYoDTNI5vS95O6sMrF938h4wvN+/07pJd5/YAcX4N5/xvy+HLvf6FruszHLv7UZTp2Cacu8dhlOHUZj13GU5fh2CUeuyB7Ohjj/MG2nG2wpLMRffhgdJ8en+3J+NfstzHPro7ZvI9d7LELnLrgsQueusCxiz11MccuR7n/mvKxiz+9ZT12Cacuy7HLcOqSjl3GU5f52CWeukzHLtOpSzx2mU9dxmOXdOoyHLsspy7h2GU90T2hy4cuM3LC4Qte+F16TC8M+P4B61C6/kCHr8mWSJtc6fT+Dyw0ub8fKvp+c98RyuvX/MJYHxrD6aE/X8jpj98/6fHy1/cv+ih245V9icVePv78mRHLv1+j44/vH2jNa0jFgS2DtWV4MIXSf3zzuGFa6rgtyMD9+7ejcZYm1WapzVqbzI03tYHaYG1sbVxtfG1CbYbajLWJtZlqU/356s9Xf77689VfqP5C9Reqv1D9heovVH+h+ov1X7H+a61vyfUtub4l17fk+pZc35Lrc7k+l+uocx11rqPOddS5jjrXUec66lxHnas/MEZakBaltdI6ab20QdpB2lHaKO0k7SxtknaRdpVW/IP4B/EP4h/EP4h/EP8g/kH8g/gH8Q/iH8Q/iH8Q/yD+Qfyj+Efxj+IfxT+KfxT/KP5R/KP4R/GP4h/FP4p/FP8o/lH8W/Fvxb8V/1b8W/Fvxb8NNfnsKG2UdpJ2ljZJu0i7Sptr64y0IC1Ka6WVJHdeWvHrZN6SgSApiLi1i7SrtHWeKHmIkogomYiSiigZhpJiKDmGNcl4yTC0ZOxLE+JU1ybPS0dnCSldyx7nvSxfyz9Lxz9Lxz9Lx//T0vHnC+Iq55BCtljfv+iD7Iu2L2Rf2J60PZE9sX3W9pnsM51zONN3uyM7n394IdjtluyW7aO2I9mR7YO2A9mB/er3YC728kF2/R6keWGdl34P0ryQ5zUZbad5Ic0LR8WhqFTOaeWD7EnbA9kD22dt92T3bJ+0nc6BjjmMUdst2ZnDOGo7kp05jIO2A9mB7UHbDdkN252yl9X/F32Q3Wr7SvaV7ajtC9kXtoO2J7JXPkbbZ7Kz7kPW9onsE/f32k7n3vJB/VdtH8k+sl7NvMivI79Rv96RWzdz9+b1JIsNbG8wkCzWs73BQLJYx/YGA8liLdsbDCSLJVlgbKZLslgOz7GZFsliDdt1WFHYQg3bJqwobKGGbRNWFLZQw7YJKwpb4LCFJqyQ+CDzacIKSRac2K7DCkkWjGzX+JFkQZalCSuktMCB7ZonEn9k/k1YIfFH5t+EFRJ/ZP5NWCHxR+bfhBUSf2T+Tfgg8UfmPzSciT8y/0FzBuIPzH/QnIH4A/MfNE8g/sD8B80TiD8w/0HzBOIPzH/QPIH4A/MfdNwC8QfmP2jOQPyB+Q+aMxB/YP6D5gzEH5j/oDkD8QfmP2jOQPyB+QfNE4g/MP+geQLxB+YfGp7EH5h/aHgSf2D+QcetIf6Gl6VGL0P8DS9LjV6G+Btelhq9DPE3vCwNzfuJv6nLktbREH/Dy1KjoyH+hvmHpj/xN8w/NP2Jv+FtodHdEH/D/ENjJ/6G+QcdD4b4m8pfx4Mh/qby17ob4m8qf627If6m8te6G+JvKn+ley74M0e/V9mVC/zMse9VLOSCPnPke6VULuBz5a7mkwv2zFHvlXq5QM8c815plwvyzMT1gSEX4Jl562NBLrhzpa0o5QI78xascyYX1Jk3YJ0xuYDOvP3qfMkFc+bNV2dLLpAzb706V3JBnHnjDZpZAZx529X5sxa+a+WroiCW8UYer86FWMYbOTK8IhlK38Bx5NWMQ+kbal8141DmFjiGvJpxKHMLHEFezTiUuQWOH69mHMrcAkePVzMOZW6BY8epGfsyN18PXNpaYkeOkWpudIqUQ6R6L50h6xFSHw3oBOnriqnfUGLHc+xo6r7EjqfY0cnnS+h4Ch0dkb5EjqfI0YHjC1xPcHXclFvxL09sddjQ8ZVPrzpq6Ozqa27q5wtZX8mqFYTOrXxs1cuWL2A9gdUzdYWrI656wXIFqyOserVyhapjqk7FHJ2U+KAETuUpHZTonPRnrmV4fNmX/ZZS4lpLibjVQF25lkx8nfgLVlsrDXxNVTVQmAapHgxU/JRLzlIvF8XJcuw+Ss3USPUhJnl+3J/7Ld62QYJ+XuoawySPpX1wJZFg099QgYM2j4mFWRZlL6afZKEO9DdyYb+raeW/Jf6fX/RBBdm6BWhSuZICuCI1PCElZeJPpMY7pOogP5EKyzWpQZP6u1pNdiJFlkqqurDf1bTy32JDqu5xCtRsBJS5ApWfgKqZ94ETLHc48RA/BtRwjSlrTHv6k5koFUOFxO8vjMhAiMq/G0LjkRAIIbwgxLWc+4Rsj1C6RWjsEQqXhMogNSGrzEzIboRGIWSF0NgSOibbLN/MlOPzBSF4RMj1CM23CPVSbfDXhKAh5JSZCbmNkOQZGZjQIcumIyErC/fVcgT4iJDvEZpuEZp6hNw1IWwIeWVmQn4jNAkhL4SmltB8JOSE0HBFyD4iFHqE4i1Cc4+QvSZkG0JBmZlQ2AjNQigIobkldNz8Zy+E0hUh94jQ0CN0a0cL3a0frwm5hpA2M6FhIyT7/jAIoXbXr/dcTSgIofWKkH9EaOwRGm4RWnqE4JqQbwiNysyExo3QIoRGIbS0hNYjoUG+i77a7eHRAbIefj8RCrcIrT1C5ppQc3zcT+Agp8diEEKrEIpCaG0J5SOhUfYye3UeGh8RmnqE/C1CuXdszNfnobEhNCkzE5o2QlkITUIoN4TqPVsTikLIXRGKjwjNPULuDiEe4kdC6zWh2BCalZkJzUKI30+E6gr9s/xbE+Jfs7jyn98ITULInwj9ll+dbMP5jfVbqJJ1j2IqmQ4xf2tvSzwj/XiUx/fDw3ZQiuTda+9lzKm+Zuolb5g/gIcsl9/iHenyi/y1SMVXrKbSTfUM9nPSmfo15/3ZMhz5Kc4XpO0+DRLWyWx3IRzVn3aZyz2sVm10RM+yb8SriJ4eXRZ9b2tFuHVZ5EF+XBfn65iemsui13a+LPptd60u6LLoZX8liw5s/iVXE9hJAjs8CexHS8HSO9b6W9vJEnqBPTwJ7LlHP0xXgV28q8Cu+IpVjsBL3bJ+zpryV8L92Sawt3oIyGq0+HNgxyaw+bd5jVzyyzMYHsiFj26yS+985O0tuWJPLvdIrl7JIMRLuWIj1yByyVlqiSKXrg98LcP+bCPXXj2Xy/QynuRC08o1HuWS6h4dvu/L9ehavfQ2Wn+r2FcLcZ/kgkdy9eoXYbyUKzVyjSKXbMpLErnGRq5pf7aRa6/tys1+mc9yQStXPMq1lRjjE7ke3fGXtSOXu1VJW3JHLrc+kqtbtxwu5cqNXFHkWkWuLHLFRq5lf7aRa6+6S5mB3nKUCxu54rHAkKTQiePVJj8/kSf2CsKw3pEndgsM4/UWP+stfv+xD5mJTdyqwVEKDFFqwbEtMPBvxnVAp63QOT0J6EclmRV6AX2raLViL6DnRwHdq32FcBXQxbsO6KkG9FovA/TXGtC60PW1mv3ZJqD3b4ykKrTCOaBte2x1x3JHkrIrXpVdTXp2bO3dKxBvHVtdt+CRrmM6tcdWo+z12Lqf692yHVvlwkCW5j6Wj4G9VV/Nk8B+VElLvXq1vVWvTr4T2DY9uo91SwUfy01Gjp7Fu76PZbmPSW07ebmP5ebYavdndWAv+/erUsxL7hzYrt1Y56NcUgqG9ESuR2W9tSeXu1XWW3tyufHROtTbAIK/XIcauSq+YhW5VpFrnpt1yO7PNuvQrolUFtcPcvlWLnOUa6tL4xO5HtUYU+8ybW/VqXmWH7MrPpLL9OQyl9k1NnIZyS65c6dR5DJNdoX92Sa79h86SJkzDWe5QitXOsolRXJYnsj16JvytSeXu1XOW3tyOf9Irt63E8FdZlcrV5LsErnWTa7UZFfYn22ya/+ti3xTv36Qa2jlgqNcUrFH+6Tk8qhWlXr1aXurPs13qY/ZFR7J1Svi+nyZXXMjF0h2SS07zSIXNNkV92eb7Np+MgBSK0vTueQytXItR7m2rw/WJ3I9unWsPbncrcri2pPL4SO5ege9YK/kWlu5FskukWvd5Fqa7Ir7s41c+zercvFZP8g1t3LhUS75LgPdE7keHalT7/dV9taJmgvcH7PLPpILe9m1XmbX2siFkl3yM6y0ilzYZFfan23k2n69CHKkT8tZrtTKdfxiJW1frOQnci0f5PofM7y8Ww==###5088:XlxV32DM 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1 XILINX-XDB 0.1 STUB 0.1 ASCII
2 XILINX-XDM V1.6e
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1 XILINX-XDB 0.1 STUB 0.1 ASCII
2 XILINX-XDM V1.6e
3 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1 XILINX-XDB 0.1 STUB 0.1 ASCII
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4g>28287E?mf:k26=<722c:>44?::m2<4<722wi=h>50;194?6|,8k26<6<;I3ab>o6:10;66g>2883>>i6080;66sm1e494?5=83:p(<o6:0:7?M7en2c:>54?::k26<<722e:4<4?::a5`2=8391<7>t$0c:>4>33A;ij6g>2983>>o6:00;66a>8083>>{e90:1<7<50;2x 4g>28=27E?mf:k262<722e:4<4?::a5=b=8381<7>t$0c:>41>3A;ij6g>2683>>i6080;66sm1e:94?4=83:p(<o6:05:?M7en2c:>:4?::m2<4<722wi=h850;094?6|,8k26<96;I3ab>o6:>0;66a>8083>>{e9hi1<7850;2x 4g>282>7E?mf:k26=<722c:>44?::k26d<722c:>o4?::k26f<722e:4<4?::a52e=83<1<7>t$0c:>4>23A;ij6g>2983>>o6:00;66g>2`83>>o6:k0;66g>2b83>>i6080;66s|3d83>7}Y;l16=4=51c9O5f7=9r.:>i4?;|&2=`<4l2d:5i4?;|q0g?6=:rT8o63>9282=>J6k80:w)?=d;28y!7>m39o7c?6d;38yv5e2909wS=m;<3:7?7?3E;h=7?t$00g>5=z,83n6>j4n0;g>7=z{:k1<7<t^2c894?428=0@<m>:0y'57b=82w/=4k53e9m5<b=;2wx?44?:3y]7<=:9091>95C1b395~"6:m0;7p*>9d80`>h61m0?7p}<8;296~X4027:5>4=3:N2g4<6s-;9h7>4}%3:a?5c3g;2h7;4}r14>5<5sW9<70?63;01?I7d93;p(<<k:19~ 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1 Release 14.7 - par P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 Mon Dec 14 11:39:10 2015
5
6
7 # NOTE: This file is designed to be imported into a spreadsheet program
8 # such as Microsoft Excel for viewing, printing and sorting. The |
9 # character is used as the data field separator. This file is also designed
10 # to support parsing.
11 #
12 INPUT FILE: BloqueRAM_int_map.ncd
13 OUTPUT FILE: BloqueRAM_int.pad
14 PART TYPE: xc6slx9
15 SPEED GRADE: -3
16 PACKAGE: tqg144
17
18 Pinout by Pin Number:
19
20 -----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
21 Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
22 P1||IOBS|IO_L83N_VREF_3|UNUSED||3|||||||||
23 P2||IOBM|IO_L83P_3|UNUSED||3|||||||||
24 P3|||GND||||||||||||
25 P4|||VCCO_3|||3|||||any******||||
26 P5||IOBS|IO_L52N_3|UNUSED||3|||||||||
27 P6||IOBM|IO_L52P_3|UNUSED||3|||||||||
28 P7||IOBS|IO_L51N_3|UNUSED||3|||||||||
29 P8||IOBM|IO_L51P_3|UNUSED||3|||||||||
30 P9||IOBS|IO_L50N_3|UNUSED||3|||||||||
31 P10||IOBM|IO_L50P_3|UNUSED||3|||||||||
32 P11||IOBS|IO_L49N_3|UNUSED||3|||||||||
33 P12||IOBM|IO_L49P_3|UNUSED||3|||||||||
34 P13|||GND||||||||||||
35 P14||IOBS|IO_L44N_GCLK20_3|UNUSED||3|||||||||
36 P15||IOBM|IO_L44P_GCLK21_3|UNUSED||3|||||||||
37 P16||IOBS|IO_L43N_GCLK22_IRDY2_3|UNUSED||3|||||||||
38 P17||IOBM|IO_L43P_GCLK23_3|UNUSED||3|||||||||
39 P18|||VCCO_3|||3|||||any******||||
40 P19|||VCCINT||||||||1.2||||
41 P20|||VCCAUX||||||||2.5||||
42 P21|clk_main|IOB|IO_L42N_GCLK24_3|INPUT|LVCMOS25*|3||||NONE||UNLOCATED|NO|NONE|
43 P22||IOBM|IO_L42P_GCLK25_TRDY2_3|UNUSED||3|||||||||
44 P23||IOBS|IO_L41N_GCLK26_3|UNUSED||3|||||||||
45 P24||IOBM|IO_L41P_GCLK27_3|UNUSED||3|||||||||
46 P25|||GND||||||||||||
47 P26||IOBS|IO_L37N_3|UNUSED||3|||||||||
48 P27||IOBM|IO_L37P_3|UNUSED||3|||||||||
49 P28|||VCCINT||||||||1.2||||
50 P29||IOBS|IO_L36N_3|UNUSED||3|||||||||
51 P30||IOBM|IO_L36P_3|UNUSED||3|||||||||
52 P31|||VCCO_3|||3|||||any******||||
53 P32||IOBS|IO_L2N_3|UNUSED||3|||||||||
54 P33||IOBM|IO_L2P_3|UNUSED||3|||||||||
55 P34||IOBS|IO_L1N_VREF_3|UNUSED||3|||||||||
56 P35||IOBM|IO_L1P_3|UNUSED||3|||||||||
57 P36|||VCCAUX||||||||2.5||||
58 P37|||PROGRAM_B_2||||||||||||
59 P38||IOBS|IO_L65N_CSO_B_2|UNUSED||2|||||||||
60 P39||IOBM|IO_L65P_INIT_B_2|UNUSED||2|||||||||
61 P40||IOBS|IO_L64N_D9_2|UNUSED||2|||||||||
62 P41||IOBM|IO_L64P_D8_2|UNUSED||2|||||||||
63 P42|||VCCO_2|||2|||||any******||||
64 P43||IOBS|IO_L62N_D6_2|UNUSED||2|||||||||
65 P44||IOBM|IO_L62P_D5_2|UNUSED||2|||||||||
66 P45||IOBS|IO_L49N_D4_2|UNUSED||2|||||||||
67 P46||IOBM|IO_L49P_D3_2|UNUSED||2|||||||||
68 P47||IOBS|IO_L48N_RDWR_B_VREF_2|UNUSED||2|||||||||
69 P48||IOBM|IO_L48P_D7_2|UNUSED||2|||||||||
70 P49|||GND||||||||||||
71 P50||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2|||||||||
72 P51||IOBM|IO_L31P_GCLK31_D14_2|UNUSED||2|||||||||
73 P52|||VCCINT||||||||1.2||||
74 P53|||VCCAUX||||||||2.5||||
75 P54|||GND||||||||||||
76 P55||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2|||||||||
77 P56||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2|||||||||
78 P57||IOBS|IO_L14N_D12_2|UNUSED||2|||||||||
79 P58||IOBM|IO_L14P_D11_2|UNUSED||2|||||||||
80 P59||IOBS|IO_L13N_D10_2|UNUSED||2|||||||||
81 P60||IOBM|IO_L13P_M1_2|UNUSED||2|||||||||
82 P61||IOBS|IO_L12N_D2_MISO3_2|UNUSED||2|||||||||
83 P62||IOBM|IO_L12P_D1_MISO2_2|UNUSED||2|||||||||
84 P63|||VCCO_2|||2|||||any******||||
85 P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2|||||||||
86 P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2|||||||||
87 P66||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2|||||||||
88 P67||IOBM|IO_L2P_CMPCLK_2|UNUSED||2|||||||||
89 P68|||GND||||||||||||
90 P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2|||||||||
91 P70||IOBM|IO_L1P_CCLK_2|UNUSED||2|||||||||
92 P71|||DONE_2||||||||||||
93 P72|||CMPCS_B_2||||||||||||
94 P73|||SUSPEND||||||||||||
95 P74||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1|||||||||
96 P75||IOBM|IO_L74P_AWAKE_1|UNUSED||1|||||||||
97 P76|||VCCO_1|||1|||||any******||||
98 P77|||GND||||||||||||
99 P78||IOBS|IO_L47N_1|UNUSED||1|||||||||
100 P79||IOBM|IO_L47P_1|UNUSED||1|||||||||
101 P80||IOBS|IO_L46N_1|UNUSED||1|||||||||
102 P81||IOBM|IO_L46P_1|UNUSED||1|||||||||
103 P82||IOBS|IO_L45N_1|UNUSED||1|||||||||
104 P83||IOBM|IO_L45P_1|UNUSED||1|||||||||
105 P84||IOBS|IO_L43N_GCLK4_1|UNUSED||1|||||||||
106 P85||IOBM|IO_L43P_GCLK5_1|UNUSED||1|||||||||
107 P86|||VCCO_1|||1|||||any******||||
108 P87||IOBS|IO_L42N_GCLK6_TRDY1_1|UNUSED||1|||||||||
109 P88|OE_bar|IOB|IO_L42P_GCLK7_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
110 P89|||VCCINT||||||||1.2||||
111 P90|||VCCAUX||||||||2.5||||
112 P91|||GND||||||||||||
113 P92||IOBS|IO_L41N_GCLK8_1|UNUSED||1|||||||||
114 P93||IOBM|IO_L41P_GCLK9_IRDY1_1|UNUSED||1|||||||||
115 P94||IOBS|IO_L40N_GCLK10_1|UNUSED||1|||||||||
116 P95|CS_2|IOB|IO_L40P_GCLK11_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
117 P96|||GND||||||||||||
118 P97|UB_bar|IOB|IO_L34N_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
119 P98|LB_bar|IOB|IO_L34P_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
120 P99|WEA_bar|IOB|IO_L33N_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
121 P100|CS_1_bar|IOB|IO_L33P_1|INPUT|LVCMOS25*|1||||NONE||UNLOCATED|NO|NONE|
122 P101||IOBS|IO_L32N_1|UNUSED||1|||||||||
123 P102||IOBM|IO_L32P_1|UNUSED||1|||||||||
124 P103|||VCCO_1|||1|||||any******||||
125 P104||IOBS|IO_L1N_VREF_1|UNUSED||1|||||||||
126 P105||IOBM|IO_L1P_1|UNUSED||1|||||||||
127 P106|||TDO||||||||||||
128 P107|||TMS||||||||||||
129 P108|||GND||||||||||||
130 P109|||TCK||||||||||||
131 P110|||TDI||||||||||||
132 P111|DATA_RAM<15>|IOB|IO_L66N_SCP0_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
133 P112|DATA_RAM<14>|IOB|IO_L66P_SCP1_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
134 P113|||GND||||||||||||
135 P114|DATA_RAM<13>|IOB|IO_L65N_SCP2_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
136 P115|DATA_RAM<12>|IOB|IO_L65P_SCP3_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
137 P116|DATA_RAM<11>|IOB|IO_L64N_SCP4_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
138 P117|DATA_RAM<10>|IOB|IO_L64P_SCP5_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
139 P118|DATA_RAM<9>|IOB|IO_L63N_SCP6_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
140 P119|DATA_RAM<8>|IOB|IO_L63P_SCP7_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
141 P120|DATA_RAM<7>|IOB|IO_L62N_VREF_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
142 P121|DATA_RAM<6>|IOB|IO_L62P_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
143 P122|||VCCO_0|||0|||||2.50||||
144 P123|DATA_RAM<5>|IOB|IO_L37N_GCLK12_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
145 P124|DATA_RAM<4>|IOB|IO_L37P_GCLK13_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
146 P125|||VCCO_0|||0|||||2.50||||
147 P126|DATA_RAM<3>|IOB|IO_L36N_GCLK14_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
148 P127|DATA_RAM<2>|IOB|IO_L36P_GCLK15_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
149 P128|||VCCINT||||||||1.2||||
150 P129|||VCCAUX||||||||2.5||||
151 P130|||GND||||||||||||
152 P131|DATA_RAM<1>|IOB|IO_L35N_GCLK16_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
153 P132|DATA_RAM<0>|IOB|IO_L35P_GCLK17_0|BIDIR|LVCMOS25*|0|12|SLOW||NONE||UNLOCATED|NO|NONE|
154 P133|ADDR_RAM<9>|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
155 P134|ADDR_RAM<8>|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
156 P135|||VCCO_0|||0|||||2.50||||
157 P136|||GND||||||||||||
158 P137|ADDR_RAM<7>|IOB|IO_L4N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
159 P138|ADDR_RAM<6>|IOB|IO_L4P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
160 P139|ADDR_RAM<5>|IOB|IO_L3N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
161 P140|ADDR_RAM<4>|IOB|IO_L3P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
162 P141|ADDR_RAM<3>|IOB|IO_L2N_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
163 P142|ADDR_RAM<2>|IOB|IO_L2P_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
164 P143|ADDR_RAM<1>|IOB|IO_L1N_VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
165 P144|ADDR_RAM<0>|IOB|IO_L1P_HSWAPEN_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
166
167 -----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
168
169 * Default value.
170 ** This default Pullup/Pulldown value can be overridden in Bitgen.
171 ****** Special VCCO requirements may apply. Please consult the device
172 family datasheet for specific guideline on VCCO requirements.
173
174
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1 Release 14.7 par P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 LENOVO-PC:: Mon Dec 14 11:39:04 2015
5
6 par -w -intstyle ise -ol high -mt off BloqueRAM_int_map.ncd BloqueRAM_int.ncd
7 BloqueRAM_int.pcf
8
9
10 Constraints file: BloqueRAM_int.pcf.
11 Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\.
12 "BloqueRAM_int" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3
13
14 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
15 Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
16
17 INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
18 -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
19 internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
20 reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
21 Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
22
23 Device speed data version: "PRODUCTION 1.23 2013-10-13".
24
25
26
27 Device Utilization Summary:
28
29 Slice Logic Utilization:
30 Number of Slice Registers: 34 out of 11,440 1%
31 Number used as Flip Flops: 34
32 Number used as Latches: 0
33 Number used as Latch-thrus: 0
34 Number used as AND/OR logics: 0
35 Number of Slice LUTs: 5 out of 5,720 1%
36 Number used as logic: 5 out of 5,720 1%
37 Number using O6 output only: 3
38 Number using O5 output only: 0
39 Number using O5 and O6: 2
40 Number used as ROM: 0
41 Number used as Memory: 0 out of 1,440 0%
42
43 Slice Logic Distribution:
44 Number of occupied Slices: 11 out of 1,430 1%
45 Number of MUXCYs used: 0 out of 2,860 0%
46 Number of LUT Flip Flop pairs used: 37
47 Number with an unused Flip Flop: 3 out of 37 8%
48 Number with an unused LUT: 32 out of 37 86%
49 Number of fully used LUT-FF pairs: 2 out of 37 5%
50 Number of slice register sites lost
51 to control set restrictions: 0 out of 11,440 0%
52
53 A LUT Flip Flop pair for this architecture represents one LUT paired with
54 one Flip Flop within a slice. A control set is a unique combination of
55 clock, reset, set, and enable signals for a registered element.
56 The Slice Logic Distribution report is not meaningful if the design is
57 over-mapped for a non-slice resource or if Placement fails.
58
59 IO Utilization:
60 Number of bonded IOBs: 33 out of 102 32%
61
62 Specific Feature Utilization:
63 Number of RAMB16BWERs: 1 out of 32 3%
64 Number of RAMB8BWERs: 0 out of 64 0%
65 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
66 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
67 Number of BUFG/BUFGMUXs: 1 out of 16 6%
68 Number used as BUFGs: 1
69 Number used as BUFGMUX: 0
70 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
71 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
72 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
73 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
74 Number of BSCANs: 0 out of 4 0%
75 Number of BUFHs: 0 out of 128 0%
76 Number of BUFPLLs: 0 out of 8 0%
77 Number of BUFPLL_MCBs: 0 out of 4 0%
78 Number of DSP48A1s: 0 out of 16 0%
79 Number of ICAPs: 0 out of 1 0%
80 Number of MCBs: 0 out of 2 0%
81 Number of PCILOGICSEs: 0 out of 2 0%
82 Number of PLL_ADVs: 0 out of 2 0%
83 Number of PMVs: 0 out of 1 0%
84 Number of STARTUPs: 0 out of 1 0%
85 Number of SUSPEND_SYNCs: 0 out of 1 0%
86
87
88 Overall effort level (-ol): High
89 Router effort level (-rl): High
90
91 Starting initial Timing Analysis. REAL time: 3 secs
92 Finished initial Timing Analysis. REAL time: 3 secs
93
94 Starting Router
95
96
97 Phase 1 : 219 unrouted; REAL time: 3 secs
98
99 Phase 2 : 121 unrouted; REAL time: 4 secs
100
101 Phase 3 : 51 unrouted; REAL time: 4 secs
102
103 Phase 4 : 51 unrouted; (Par is working to improve performance) REAL time: 5 secs
104
105 Updating file: BloqueRAM_int.ncd with current fully routed design.
106
107 Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
108
109 Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
110
111 Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
112
113 Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
114
115 Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
116
117 Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 5 secs
118 Total REAL time to Router completion: 5 secs
119 Total CPU time to Router completion: 4 secs
120
121 Partition Implementation Status
122 -------------------------------
123
124 No Partitions were found in this design.
125
126 -------------------------------
127
128 Generating "PAR" statistics.
129 INFO:Par:459 - The Clock Report is not displayed in the non timing-driven mode.
130 Timing Score: 0 (Setup: 0, Hold: 0)
131
132 Asterisk (*) preceding a constraint indicates it was not met.
133 This may be due to a setup or hold violation.
134
135 ----------------------------------------------------------------------------------------------------------
136 Constraint | Check | Worst Case | Best Case | Timing | Timing
137 | | Slack | Achievable | Errors | Score
138 ----------------------------------------------------------------------------------------------------------
139 Autotimespec constraint for clock net clk | SETUP | N/A| 3.387ns| N/A| 0
140 _main_BUFGP | HOLD | 0.481ns| | 0| 0
141 ----------------------------------------------------------------------------------------------------------
142
143
144 All constraints were met.
145 INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
146 constraint is not analyzed due to the following: No paths covered by this
147 constraint; Other constraints intersect with this constraint; or This
148 constraint was disabled by a Path Tracing Control. Please run the Timespec
149 Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
150
151
152 Generating Pad Report.
153
154 All signals are completely routed.
155
156 Total REAL time to PAR completion: 5 secs
157 Total CPU time to PAR completion: 4 secs
158
159 Peak Memory Usage: 306 MB
160
161 Placer: Placement generated during map.
162 Routing: Completed - No errors found.
163
164 Number of error messages: 0
165 Number of warning messages: 0
166 Number of info messages: 2
167
168 Writing design to file BloqueRAM_int.ncd
169
170
171
172 PAR done!
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1 //! **************************************************************************
2 // Written by: Map P.20131013 on Mon Dec 14 11:38:57 2015
3 //! **************************************************************************
4
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1 vhdl work "BloqueRAM_int.vhd"
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1 <?xml version="1.0" encoding="UTF-8"?>
2 <!DOCTYPE twReport [
3 <!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
4 twDebug*, twFoot?, twClientInfo?)>
5 <!ATTLIST twReport version CDATA "10,4">
6 <!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
7 <!ELEMENT twExecVer (#PCDATA)>
8 <!ELEMENT twCopyright (#PCDATA)>
9 <!ELEMENT twCmdLine (#PCDATA)>
10 <!ELEMENT twDesign (#PCDATA)>
11 <!ELEMENT twPCF (#PCDATA)>
12 <!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
13 <!ELEMENT twDevName (#PCDATA)>
14 <!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
15 <!ELEMENT twSpeedGrade (#PCDATA)>
16 <!ELEMENT twSpeedVer (#PCDATA)>
17 <!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
18 <!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
19 <!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
20 <!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
21 <!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
22 <!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
23 <!ELEMENT twItemLimit (#PCDATA)>
24 <!ELEMENT twUnconst EMPTY>
25 <!ELEMENT twUnconstLimit (#PCDATA)>
26 <!ELEMENT twEnvVar EMPTY>
27 <!ATTLIST twEnvVar name CDATA #REQUIRED>
28 <!ATTLIST twEnvVar description CDATA #REQUIRED>
29 <!ELEMENT twWarn (#PCDATA)>
30 <!ELEMENT twInfo (#PCDATA)>
31 <!ELEMENT twDebug (#PCDATA)>
32 <!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
33 <!ATTLIST twBody twFastPaths CDATA #IMPLIED>
34 <!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
35 <!ELEMENT twProc (#PCDATA)>
36 <!ELEMENT twTemp (#PCDATA)>
37 <!ELEMENT twVolt (#PCDATA)>
38 <!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
39 <!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
40 <!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
41 <!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
42 <!ELEMENT twCycles (twSigConn+)>
43 <!ATTLIST twCycles twNum CDATA #REQUIRED>
44 <!ELEMENT twSigConn (twSig, twDriver, twLoad)>
45 <!ELEMENT twSig (#PCDATA)>
46 <!ELEMENT twDriver (#PCDATA)>
47 <!ELEMENT twLoad (#PCDATA)>
48 <!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
49 <!ATTLIST twConst twConstType (NET |
50 NETDELAY |
51 NETSKEW |
52 PATH |
53 DEFPERIOD |
54 UNCONSTPATH |
55 DEFPATH |
56 PATH2SETUP |
57 UNCONSTPATH2SETUP |
58 PATHCLASS |
59 PATHDELAY |
60 PERIOD |
61 FREQUENCY |
62 PATHBLOCK |
63 OFFSET |
64 OFFSETIN |
65 OFFSETINCLOCK |
66 UNCONSTOFFSETINCLOCK |
67 OFFSETINDELAY |
68 OFFSETINMOD |
69 OFFSETOUT |
70 OFFSETOUTCLOCK |
71 UNCONSTOFFSETOUTCLOCK |
72 OFFSETOUTDELAY |
73 OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
74 <!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
75 twEndPtCnt?,
76 twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
77 <!ELEMENT twConstName (#PCDATA)>
78 <!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
79 <!ATTLIST twConstHead uID CDATA #IMPLIED>
80 <!ELEMENT twItemCnt (#PCDATA)>
81 <!ELEMENT twErrCnt (#PCDATA)>
82 <!ELEMENT twErrCntEndPt (#PCDATA)>
83 <!ELEMENT twErrCntSetup (#PCDATA)>
84 <!ELEMENT twErrCntHold (#PCDATA)>
85 <!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
86 <!ELEMENT twEndPtCnt (#PCDATA)>
87 <!ELEMENT twPathErrCnt (#PCDATA)>
88 <!ELEMENT twMinPer (#PCDATA) >
89 <!ELEMENT twFootnote EMPTY>
90 <!ATTLIST twFootnote number CDATA #REQUIRED>
91 <!ELEMENT twMaxDel (#PCDATA)>
92 <!ELEMENT twMaxFreq (#PCDATA)>
93 <!ELEMENT twMinOff (#PCDATA)>
94 <!ELEMENT twMaxOff (#PCDATA)>
95 <!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
96 <!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
97 <!ELEMENT twTIGName (#PCDATA)>
98 <!ELEMENT twInstantiated (#PCDATA)>
99 <!ELEMENT twBlocked (#PCDATA)>
100 <!ELEMENT twRacePathRpt (twRacePath+)>
101 <!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
102 <!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
103 <!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
104 twSimpleMinPath CDATA #IMPLIED>
105 <!ELEMENT twTotDel (#PCDATA)>
106 <!ELEMENT twSrc (#PCDATA)>
107 <!ATTLIST twSrc BELType CDATA #IMPLIED>
108 <!ELEMENT twDest (#PCDATA)>
109 <!ATTLIST twDest BELType CDATA #IMPLIED>
110 <!ELEMENT twDel (#PCDATA)>
111 <!ELEMENT twSUTime (#PCDATA)>
112 <!ELEMENT twTotPathDel (#PCDATA)>
113 <!ELEMENT twClkSkew (#PCDATA)>
114 <!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
115 <!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
116 <!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
117 <!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
118 <!ELEMENT twSlack (#PCDATA)>
119 <!ELEMENT twDelConst (#PCDATA)>
120 <!ELEMENT tw2Phase EMPTY>
121 <!ELEMENT twClkUncert (#PCDATA)>
122 <!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
123 fDCMJit CDATA #IMPLIED
124 fPhaseErr CDATA #IMPLIED
125 sEqu CDATA #IMPLIED>
126 <!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
127 <!ELEMENT twPathRptBanner (#PCDATA)>
128 <!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
129 <!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
130 <!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
131 <!ELEMENT twOff (#PCDATA)>
132 <!ELEMENT twGuaranteed EMPTY>
133 <!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
134 <!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
135 <!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
136 <!ELEMENT twClkDel (#PCDATA)>
137 <!ELEMENT twClkSrc (#PCDATA)>
138 <!ELEMENT twClkDest (#PCDATA)>
139 <!ELEMENT twGuarInSetup (#PCDATA)>
140 <!ELEMENT twOffSrc (#PCDATA)>
141 <!ELEMENT twOffDest (#PCDATA)>
142 <!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
143 <!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
144 <!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
145 <!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
146 <!ELEMENT twDataDel (#PCDATA)>
147 <!ELEMENT twDataSrc (#PCDATA)>
148 <!ELEMENT twDataDest (#PCDATA)>
149 <!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
150 <!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
151 <!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
152 <!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
153 <!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
154 <!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
155 <!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
156 <!ELEMENT twLogLvls (#PCDATA)>
157 <!ELEMENT twSrcSite (#PCDATA)>
158 <!ELEMENT twSrcClk (#PCDATA)>
159 <!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
160 <!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
161 <!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
162 <!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
163 <!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
164 <!ELEMENT twDelInfo (#PCDATA)>
165 <!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
166 <!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
167 <!ELEMENT twSite (#PCDATA)>
168 <!ELEMENT twDelType (#PCDATA)>
169 <!ELEMENT twFanCnt (#PCDATA)>
170 <!ELEMENT twComp (#PCDATA)>
171 <!ELEMENT twNet (#PCDATA)>
172 <!ELEMENT twBEL (#PCDATA)>
173 <!ELEMENT twLogDel (#PCDATA)>
174 <!ELEMENT twRouteDel (#PCDATA)>
175 <!ELEMENT twDestClk (#PCDATA)>
176 <!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
177 <!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
178 <!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
179 <!ELEMENT twPctLog (#PCDATA)>
180 <!ELEMENT twPctRoute (#PCDATA)>
181 <!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
182 <!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
183 <!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
184 <!ELEMENT twTimeConst (#PCDATA)>
185 <!ELEMENT twAbsSlack (#PCDATA)>
186 <!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
187 <!ELEMENT twSkew (#PCDATA)>
188 <!ELEMENT twDetNet (twNetDel*)>
189 <!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
190 <!ELEMENT twNetDelInfo (#PCDATA)>
191 <!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
192 <!ELEMENT twDetSkewNet (twNetSkew*)>
193 <!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
194 <!ELEMENT twClkSkewLimit EMPTY>
195 <!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
196 arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
197 <!ELEMENT twConstRollupTable (twConstRollup*)>
198 <!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
199 <!ELEMENT twConstRollup EMPTY>
200 <!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
201 <!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
202 <!ELEMENT twConstList (twConstListItem)*>
203 <!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
204 <!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
205 <!ELEMENT twNotMet EMPTY>
206 <!ELEMENT twReqVal (#PCDATA)>
207 <!ELEMENT twActVal (#PCDATA)>
208 <!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
209 <!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
210 <!ELEMENT twConstStats (twConstName)>
211 <!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
212 <!ATTLIST twConstStats twRequired CDATA #IMPLIED>
213 <!ATTLIST twConstStats twActual CDATA #IMPLIED>
214 <!ATTLIST twConstStats twSlack CDATA #IMPLIED>
215 <!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
216 <!ATTLIST twConstStats twErrors CDATA #IMPLIED>
217 <!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
218 <!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
219 <!ATTLIST twConstStats twTCType CDATA #IMPLIED>
220 <!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
221 <!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
222 <!ELEMENT twConstData EMPTY>
223 <!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
224 best CDATA #IMPLIED requested CDATA #IMPLIED
225 errors CDATA #IMPLIED
226 score CDATA #IMPLIED>
227 <!ELEMENT twTimeGrpRpt (twTimeGrp)*>
228 <!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
229 <!ELEMENT twTimeGrpName (#PCDATA)>
230 <!ELEMENT twCompList (twCompName+)>
231 <!ELEMENT twCompName (#PCDATA)>
232 <!ELEMENT twSigList (twSigName+)>
233 <!ELEMENT twSigName (#PCDATA)>
234 <!ELEMENT twBELList (twBELName+)>
235 <!ELEMENT twBELName (#PCDATA)>
236 <!ELEMENT twBlockList (twBlockName+)>
237 <!ELEMENT twBlockName (#PCDATA)>
238 <!ELEMENT twMacList (twMacName+)>
239 <!ELEMENT twMacName (#PCDATA)>
240 <!ELEMENT twPinList (twPinName+)>
241 <!ELEMENT twPinName (#PCDATA)>
242 <!ELEMENT twUnmetConstCnt (#PCDATA)>
243 <!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
244 <!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
245 <!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
246 <!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
247 <!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
248 <!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
249 <!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
250 <!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
251 <!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
252 <!ELEMENT twSU2ClkTime (#PCDATA)>
253 <!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
254 <!ELEMENT twH2ClkTime (#PCDATA)>
255 <!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
256 <!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
257 <!ELEMENT twClk2Pad (twDest, twTime)>
258 <!ELEMENT twTime (#PCDATA)>
259 <!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
260 <!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
261 <!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
262 <!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
263 <!ELEMENT twClk2Out EMPTY>
264 <!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
265 <!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
266 <!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
267 <!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
268 <!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
269 <!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
270 <!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
271 <!ELEMENT twClk2SUList (twDest, twClk2SU+)>
272 <!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
273 <!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
274 <!ELEMENT twRiseRise (#PCDATA)>
275 <!ELEMENT twFallRise (#PCDATA)>
276 <!ELEMENT twRiseFall (#PCDATA)>
277 <!ELEMENT twFallFall (#PCDATA)>
278 <!ELEMENT twPad2PadList (twPad2Pad+)>
279 <!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
280 <!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
281 <!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
282 <!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
283 <!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
284 <!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
285 <!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
286 <!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
287 <!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
288 <!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
289 <!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
290 <!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
291 <!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
292 <!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
293 <!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
294 <!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
295 <!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
296 <!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
297 <!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
298 <!ELEMENT twOffOutTblRow EMPTY>
299 <!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
300 <!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
301 <!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
302 <!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
303 <!ELEMENT twNonDedClk (#PCDATA)>
304 <!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
305 <!ELEMENT twScore (#PCDATA)>
306 <!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
307 <!ELEMENT twPathCnt (#PCDATA)>
308 <!ELEMENT twNetCnt (#PCDATA)>
309 <!ELEMENT twConnCnt (#PCDATA)>
310 <!ELEMENT twPct (#PCDATA)>
311 <!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
312 <!ELEMENT twMaxCombDel (#PCDATA)>
313 <!ELEMENT twMaxFromToDel (#PCDATA)>
314 <!ELEMENT twMaxNetDel (#PCDATA)>
315 <!ELEMENT twMaxNetSkew (#PCDATA)>
316 <!ELEMENT twMaxInAfterClk (#PCDATA)>
317 <!ELEMENT twMinInBeforeClk (#PCDATA)>
318 <!ELEMENT twMaxOutBeforeClk (#PCDATA)>
319 <!ELEMENT twMinOutAfterClk (#PCDATA)>
320 <!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
321 <!ELEMENT twTimestamp (#PCDATA)>
322 <!ELEMENT twFootnoteExplanation EMPTY>
323 <!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
324 <!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
325 <!ELEMENT twClientInfo (twClientName, twAttrList?)>
326 <!ELEMENT twClientName (#PCDATA)>
327 <!ELEMENT twAttrList (twAttrListItem)*>
328 <!ELEMENT twAttrListItem (twName, twValue*)>
329 <!ELEMENT twName (#PCDATA)>
330 <!ELEMENT twValue (#PCDATA)>
331 ]>
332 <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net clk_main_BUFGP</twConstName><twConstData type="SETUP" best="3.387" units="ns" score="0"/><twConstData type="HOLD" slack="0.481" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="4">0</twUnmetConstCnt><twInfo anchorID="5">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
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1 NO CONTENT: new file 10644
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1 Release 14.7 - xst P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 --> Parameter TMPDIR set to xst/projnav.tmp
4
5
6 Total REAL time to Xst completion: 0.00 secs
7 Total CPU time to Xst completion: 0.12 secs
8
9 --> Parameter xsthdpdir set to xst
10
11
12 Total REAL time to Xst completion: 0.00 secs
13 Total CPU time to Xst completion: 0.12 secs
14
15 --> Reading design: BloqueRAM_int.prj
16
17 TABLE OF CONTENTS
18 1) Synthesis Options Summary
19 2) HDL Parsing
20 3) HDL Elaboration
21 4) HDL Synthesis
22 4.1) HDL Synthesis Report
23 5) Advanced HDL Synthesis
24 5.1) Advanced HDL Synthesis Report
25 6) Low Level Synthesis
26 7) Partition Report
27 8) Design Summary
28 8.1) Primitive and Black Box Usage
29 8.2) Device utilization summary
30 8.3) Partition Resource Summary
31 8.4) Timing Report
32 8.4.1) Clock Information
33 8.4.2) Asynchronous Control Signals Information
34 8.4.3) Timing Summary
35 8.4.4) Timing Details
36 8.4.5) Cross Clock Domains Report
37
38
39 =========================================================================
40 * Synthesis Options Summary *
41 =========================================================================
42 ---- Source Parameters
43 Input File Name : "BloqueRAM_int.prj"
44 Ignore Synthesis Constraint File : NO
45
46 ---- Target Parameters
47 Output File Name : "BloqueRAM_int"
48 Output Format : NGC
49 Target Device : xc6slx9-3-tqg144
50
51 ---- Source Options
52 Top Module Name : BloqueRAM_int
53 Automatic FSM Extraction : YES
54 FSM Encoding Algorithm : Auto
55 Safe Implementation : No
56 FSM Style : LUT
57 RAM Extraction : Yes
58 RAM Style : Auto
59 ROM Extraction : Yes
60 Shift Register Extraction : YES
61 ROM Style : Auto
62 Resource Sharing : YES
63 Asynchronous To Synchronous : NO
64 Shift Register Minimum Size : 2
65 Use DSP Block : Auto
66 Automatic Register Balancing : No
67
68 ---- Target Options
69 LUT Combining : Auto
70 Reduce Control Sets : Auto
71 Add IO Buffers : YES
72 Global Maximum Fanout : 100000
73 Add Generic Clock Buffer(BUFG) : 16
74 Register Duplication : YES
75 Optimize Instantiated Primitives : NO
76 Use Clock Enable : Auto
77 Use Synchronous Set : Auto
78 Use Synchronous Reset : Auto
79 Pack IO Registers into IOBs : Auto
80 Equivalent register Removal : YES
81
82 ---- General Options
83 Optimization Goal : Speed
84 Optimization Effort : 1
85 Power Reduction : NO
86 Keep Hierarchy : No
87 Netlist Hierarchy : As_Optimized
88 RTL Output : Yes
89 Global Optimization : AllClockNets
90 Read Cores : YES
91 Write Timing Constraints : NO
92 Cross Clock Analysis : NO
93 Hierarchy Separator : /
94 Bus Delimiter : <>
95 Case Specifier : Maintain
96 Slice Utilization Ratio : 100
97 BRAM Utilization Ratio : 100
98 DSP48 Utilization Ratio : 100
99 Auto BRAM Packing : NO
100 Slice Utilization Ratio Delta : 5
101
102 =========================================================================
103
104
105 =========================================================================
106 * HDL Parsing *
107 =========================================================================
108 Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\Memoria_SRAM_16kb_v02\BloqueRAM_int.vhd" into library work
109 Parsing entity <BloqueRAM_int>.
110 Parsing architecture <Behavioral> of entity <bloqueram_int>.
111
112 =========================================================================
113 * HDL Elaboration *
114 =========================================================================
115
116 Elaborating entity <BloqueRAM_int> (architecture <Behavioral>) with generics from library <work>.
117
118 =========================================================================
119 * HDL Synthesis *
120 =========================================================================
121
122 Synthesizing Unit <BloqueRAM_int>.
123 Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\Memoria_SRAM_16kb_v02\BloqueRAM_int.vhd".
124 DATA_PRIM_SZ = 32
125 ADDR_PRIM_SZ = 14
126 RESUL_SZ = 16
127 ADDR_SZ = 10
128 Found 1-bit register for signal <data_ram_aux_out[14]_clk_main_DFF_2_q>.
129 Found 1-bit register for signal <data_ram_aux_out[13]_clk_main_DFF_3_q>.
130 Found 1-bit register for signal <data_ram_aux_out[12]_clk_main_DFF_4_q>.
131 Found 1-bit register for signal <data_ram_aux_out[11]_clk_main_DFF_5_q>.
132 Found 1-bit register for signal <data_ram_aux_out[10]_clk_main_DFF_6_q>.
133 Found 1-bit register for signal <data_ram_aux_out[9]_clk_main_DFF_7_q>.
134 Found 1-bit register for signal <data_ram_aux_out[8]_clk_main_DFF_8_q>.
135 Found 1-bit register for signal <data_ram_aux_out[7]_clk_main_DFF_9_q>.
136 Found 1-bit register for signal <data_ram_aux_out[6]_clk_main_DFF_10_q>.
137 Found 1-bit register for signal <data_ram_aux_out[5]_clk_main_DFF_11_q>.
138 Found 1-bit register for signal <data_ram_aux_out[4]_clk_main_DFF_12_q>.
139 Found 1-bit register for signal <data_ram_aux_out[3]_clk_main_DFF_13_q>.
140 Found 1-bit register for signal <data_ram_aux_out[2]_clk_main_DFF_14_q>.
141 Found 1-bit register for signal <data_ram_aux_out[1]_clk_main_DFF_15_q>.
142 Found 1-bit register for signal <data_ram_aux_out[0]_clk_main_DFF_16_q>.
143 Found 1-bit register for signal <data_ram_aux_in<15>>.
144 Found 1-bit register for signal <data_ram_aux_in<14>>.
145 Found 1-bit register for signal <data_ram_aux_in<13>>.
146 Found 1-bit register for signal <data_ram_aux_in<12>>.
147 Found 1-bit register for signal <data_ram_aux_in<11>>.
148 Found 1-bit register for signal <data_ram_aux_in<10>>.
149 Found 1-bit register for signal <data_ram_aux_in<9>>.
150 Found 1-bit register for signal <data_ram_aux_in<8>>.
151 Found 1-bit register for signal <data_ram_aux_in<7>>.
152 Found 1-bit register for signal <data_ram_aux_in<6>>.
153 Found 1-bit register for signal <data_ram_aux_in<5>>.
154 Found 1-bit register for signal <data_ram_aux_in<4>>.
155 Found 1-bit register for signal <data_ram_aux_in<3>>.
156 Found 1-bit register for signal <data_ram_aux_in<2>>.
157 Found 1-bit register for signal <data_ram_aux_in<1>>.
158 Found 1-bit register for signal <data_ram_aux_in<0>>.
159 Found 1-bit register for signal <PWR_5_o_clk_main_DFF_33>.
160 Found 1-bit register for signal <PWR_13_o_clk_main_DFF_41>.
161 Found 1-bit register for signal <data_ram_aux_out[15]_clk_main_DFF_1_q>.
162 Found 1-bit tristate buffer for signal <DATA_RAM<15>> created at line 73
163 Found 1-bit tristate buffer for signal <DATA_RAM<14>> created at line 73
164 Found 1-bit tristate buffer for signal <DATA_RAM<13>> created at line 73
165 Found 1-bit tristate buffer for signal <DATA_RAM<12>> created at line 73
166 Found 1-bit tristate buffer for signal <DATA_RAM<11>> created at line 73
167 Found 1-bit tristate buffer for signal <DATA_RAM<10>> created at line 73
168 Found 1-bit tristate buffer for signal <DATA_RAM<9>> created at line 73
169 Found 1-bit tristate buffer for signal <DATA_RAM<8>> created at line 73
170 Found 1-bit tristate buffer for signal <DATA_RAM<7>> created at line 73
171 Found 1-bit tristate buffer for signal <DATA_RAM<6>> created at line 73
172 Found 1-bit tristate buffer for signal <DATA_RAM<5>> created at line 73
173 Found 1-bit tristate buffer for signal <DATA_RAM<4>> created at line 73
174 Found 1-bit tristate buffer for signal <DATA_RAM<3>> created at line 73
175 Found 1-bit tristate buffer for signal <DATA_RAM<2>> created at line 73
176 Found 1-bit tristate buffer for signal <DATA_RAM<1>> created at line 73
177 Found 1-bit tristate buffer for signal <DATA_RAM<0>> created at line 73
178 Summary:
179 inferred 34 D-type flip-flop(s).
180 inferred 16 Tristate(s).
181 Unit <BloqueRAM_int> synthesized.
182
183 =========================================================================
184 HDL Synthesis Report
185
186 Macro Statistics
187 # Registers : 34
188 1-bit register : 34
189 # Tristates : 16
190 1-bit tristate buffer : 16
191
192 =========================================================================
193
194 =========================================================================
195 * Advanced HDL Synthesis *
196 =========================================================================
197
198
199 =========================================================================
200 Advanced HDL Synthesis Report
201
202 Macro Statistics
203 # Registers : 34
204 Flip-Flops : 34
205
206 =========================================================================
207
208 =========================================================================
209 * Low Level Synthesis *
210 =========================================================================
211
212 Optimizing unit <BloqueRAM_int> ...
213
214 Mapping all equations...
215 Building and optimizing final netlist ...
216 Found area constraint ratio of 100 (+ 5) on block BloqueRAM_int, actual ratio is 0.
217
218 Final Macro Processing ...
219
220 =========================================================================
221 Final Register Report
222
223 Macro Statistics
224 # Registers : 34
225 Flip-Flops : 34
226
227 =========================================================================
228
229 =========================================================================
230 * Partition Report *
231 =========================================================================
232
233 Partition Implementation Status
234 -------------------------------
235
236 No Partitions were found in this design.
237
238 -------------------------------
239
240 =========================================================================
241 * Design Summary *
242 =========================================================================
243
244 Top Level Output File Name : BloqueRAM_int.ngc
245
246 Primitive and Black Box Usage:
247 ------------------------------
248 # BELS : 10
249 # GND : 1
250 # INV : 3
251 # LUT2 : 1
252 # LUT4 : 2
253 # LUT5 : 2
254 # VCC : 1
255 # FlipFlops/Latches : 34
256 # FDC : 18
257 # FDE : 16
258 # RAMS : 1
259 # RAMB16BWER : 1
260 # Clock Buffers : 1
261 # BUFGP : 1
262 # IO Buffers : 32
263 # IBUF : 16
264 # IOBUF : 16
265
266 Device utilization summary:
267 ---------------------------
268
269 Selected Device : 6slx9tqg144-3
270
271
272 Slice Logic Utilization:
273 Number of Slice Registers: 34 out of 11440 0%
274 Number of Slice LUTs: 8 out of 5720 0%
275 Number used as Logic: 8 out of 5720 0%
276
277 Slice Logic Distribution:
278 Number of LUT Flip Flop pairs used: 42
279 Number with an unused Flip Flop: 8 out of 42 19%
280 Number with an unused LUT: 34 out of 42 80%
281 Number of fully used LUT-FF pairs: 0 out of 42 0%
282 Number of unique control sets: 4
283
284 IO Utilization:
285 Number of IOs: 33
286 Number of bonded IOBs: 33 out of 102 32%
287
288 Specific Feature Utilization:
289 Number of Block RAM/FIFO: 1 out of 32 3%
290 Number using Block RAM only: 1
291 Number of BUFG/BUFGCTRLs: 1 out of 16 6%
292
293 ---------------------------
294 Partition Resource Summary:
295 ---------------------------
296
297 No Partitions were found in this design.
298
299 ---------------------------
300
301
302 =========================================================================
303 Timing Report
304
305 NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
306 FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
307 GENERATED AFTER PLACE-and-ROUTE.
308
309 Clock Information:
310 ------------------
311 -----------------------------------+------------------------+-------+
312 Clock Signal | Clock buffer(FF name) | Load |
313 -----------------------------------+------------------------+-------+
314 clk_main | BUFGP | 35 |
315 data_ram_aux_in<31:16><1> | NONE(RAMB16BWER_inst) | 1 |
316 -----------------------------------+------------------------+-------+
317 INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
318
319 Asynchronous Control Signals Information:
320 ----------------------------------------
321 No asynchronous control signals found in this design
322
323 Timing Summary:
324 ---------------
325 Speed Grade: -3
326
327 Minimum period: 2.531ns (Maximum Frequency: 395.124MHz)
328 Minimum input arrival time before clock: 3.743ns
329 Maximum output required time after clock: 4.604ns
330 Maximum combinational path delay: No path found
331
332 Timing Details:
333 ---------------
334 All values displayed in nanoseconds (ns)
335
336 =========================================================================
337 Timing constraint: Default period analysis for Clock 'clk_main'
338 Clock period: 2.531ns (frequency: 395.124MHz)
339 Total number of paths / destination ports: 32 / 32
340 -------------------------------------------------------------------------
341 Delay: 2.531ns (Levels of Logic = 0)
342 Source: RAMB16BWER_inst (RAM)
343 Destination: DATA_RAM_15 (FF)
344 Source Clock: clk_main rising
345 Destination Clock: clk_main rising
346
347 Data Path: RAMB16BWER_inst to DATA_RAM_15
348 Gate Net
349 Cell:in->out fanout Delay Delay Logical Name (Net Name)
350 ---------------------------------------- ------------
351 RAMB16BWER:CLKA->DOA15 1 1.850 0.579 RAMB16BWER_inst (data_ram_aux_out<15>)
352 FDC:D 0.102 DATA_RAM_15
353 ----------------------------------------
354 Total 2.531ns (1.952ns logic, 0.579ns route)
355 (77.1% logic, 22.9% route)
356
357 =========================================================================
358 Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main'
359 Total number of paths / destination ports: 186 / 65
360 -------------------------------------------------------------------------
361 Offset: 3.743ns (Levels of Logic = 2)
362 Source: WEA_bar (PAD)
363 Destination: PWR_5_o_clk_main_DFF_33 (FF)
364 Destination Clock: clk_main rising
365
366 Data Path: WEA_bar to PWR_5_o_clk_main_DFF_33
367 Gate Net
368 Cell:in->out fanout Delay Delay Logical Name (Net Name)
369 ---------------------------------------- ------------
370 IBUF:I->O 5 1.222 1.059 WEA_bar_IBUF (WEA_bar_IBUF)
371 LUT5:I0->O 9 0.203 0.829 UB_bar_CS_aux_OR_50_o1 (UB_bar_CS_aux_OR_50_o)
372 FDC:CLR 0.430 PWR_5_o_clk_main_DFF_33
373 ----------------------------------------
374 Total 3.743ns (1.855ns logic, 1.888ns route)
375 (49.6% logic, 50.4% route)
376
377 =========================================================================
378 Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main'
379 Total number of paths / destination ports: 32 / 16
380 -------------------------------------------------------------------------
381 Offset: 4.604ns (Levels of Logic = 2)
382 Source: PWR_5_o_clk_main_DFF_33 (FF)
383 Destination: DATA_RAM<15> (PAD)
384 Source Clock: clk_main rising
385
386 Data Path: PWR_5_o_clk_main_DFF_33 to DATA_RAM<15>
387 Gate Net
388 Cell:in->out fanout Delay Delay Logical Name (Net Name)
389 ---------------------------------------- ------------
390 FDC:C->Q 1 0.447 0.579 PWR_5_o_clk_main_DFF_33 (PWR_5_o_clk_main_DFF_33)
391 INV:I->O 8 0.206 0.802 PWR_5_o_clk_main_DFF_33_inv1_INV_0 (PWR_5_o_clk_main_DFF_33_inv)
392 IOBUF:T->IO 2.571 DATA_RAM_15_IOBUF (DATA_RAM<15>)
393 ----------------------------------------
394 Total 4.604ns (3.224ns logic, 1.380ns route)
395 (70.0% logic, 30.0% route)
396
397 =========================================================================
398
399 Cross Clock Domains Report:
400 --------------------------
401
402 Clock to Setup on destination clock clk_main
403 ---------------+---------+---------+---------+---------+
404 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
405 Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
406 ---------------+---------+---------+---------+---------+
407 clk_main | 2.531| | | |
408 ---------------+---------+---------+---------+---------+
409
410 =========================================================================
411
412
413 Total REAL time to Xst completion: 6.00 secs
414 Total CPU time to Xst completion: 6.19 secs
415
416 -->
417
418 Total memory usage is 249008 kilobytes
419
420 Number of errors : 0 ( 0 filtered)
421 Number of warnings : 0 ( 0 filtered)
422 Number of infos : 1 ( 0 filtered)
423
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1 --------------------------------------------------------------------------------
2 Release 14.7 Trace (nt64)
3 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
4
5 C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
6 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr
7 BloqueRAM_int.pcf
8
9 Design file: BloqueRAM_int.ncd
10 Physical constraint file: BloqueRAM_int.pcf
11 Device,package,speed: xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13)
12 Report level: verbose report
13
14 Environment Variable Effect
15 -------------------- ------
16 NONE No environment variables were set
17 --------------------------------------------------------------------------------
18
19 INFO:Timing:2698 - No timing constraints found, doing default enumeration.
20 INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
21 INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
22 option. All paths that are not constrained will be reported in the
23 unconstrained paths section(s) of the report.
24 INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
25 a 50 Ohm transmission line loading model. For the details of this model,
26 and for more information on accounting for different loading conditions,
27 please see the device datasheet.
28
29
30
31 Data Sheet report:
32 -----------------
33 All values displayed in nanoseconds (ns)
34
35 Setup/Hold to clock clk_main
36 ------------+------------+------------+------------+------------+------------------+--------+
37 |Max Setup to| Process |Max Hold to | Process | | Clock |
38 Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase |
39 ------------+------------+------------+------------+------------+------------------+--------+
40 ADDR_RAM<0> | 2.801(R)| SLOW | -1.108(R)| FAST |clk_main_BUFGP | 0.000|
41 ADDR_RAM<1> | 3.246(R)| SLOW | -1.456(R)| FAST |clk_main_BUFGP | 0.000|
42 ADDR_RAM<2> | 3.279(R)| SLOW | -1.417(R)| FAST |clk_main_BUFGP | 0.000|
43 ADDR_RAM<3> | 2.472(R)| SLOW | -0.858(R)| FAST |clk_main_BUFGP | 0.000|
44 ADDR_RAM<4> | 2.592(R)| SLOW | -0.944(R)| FAST |clk_main_BUFGP | 0.000|
45 ADDR_RAM<5> | 2.575(R)| SLOW | -0.975(R)| FAST |clk_main_BUFGP | 0.000|
46 ADDR_RAM<6> | 2.784(R)| SLOW | -1.124(R)| FAST |clk_main_BUFGP | 0.000|
47 ADDR_RAM<7> | 2.323(R)| SLOW | -0.758(R)| FAST |clk_main_BUFGP | 0.000|
48 ADDR_RAM<8> | 2.837(R)| SLOW | -1.172(R)| FAST |clk_main_BUFGP | 0.000|
49 ADDR_RAM<9> | 2.986(R)| SLOW | -1.256(R)| FAST |clk_main_BUFGP | 0.000|
50 CS_1_bar | 4.345(R)| SLOW | -1.617(R)| FAST |clk_main_BUFGP | 0.000|
51 CS_2 | 3.532(R)| SLOW | -1.117(R)| FAST |clk_main_BUFGP | 0.000|
52 DATA_RAM<0> | 2.070(R)| SLOW | -0.953(R)| FAST |clk_main_BUFGP | 0.000|
53 DATA_RAM<1> | 2.467(R)| SLOW | -1.234(R)| FAST |clk_main_BUFGP | 0.000|
54 DATA_RAM<2> | 2.583(R)| SLOW | -1.331(R)| FAST |clk_main_BUFGP | 0.000|
55 DATA_RAM<3> | 2.402(R)| SLOW | -1.216(R)| FAST |clk_main_BUFGP | 0.000|
56 DATA_RAM<4> | 3.146(R)| SLOW | -1.732(R)| FAST |clk_main_BUFGP | 0.000|
57 DATA_RAM<5> | 2.409(R)| SLOW | -1.177(R)| FAST |clk_main_BUFGP | 0.000|
58 DATA_RAM<6> | 2.535(R)| SLOW | -1.272(R)| FAST |clk_main_BUFGP | 0.000|
59 DATA_RAM<7> | 2.494(R)| SLOW | -1.234(R)| FAST |clk_main_BUFGP | 0.000|
60 DATA_RAM<8> | 2.834(R)| SLOW | -1.499(R)| FAST |clk_main_BUFGP | 0.000|
61 DATA_RAM<9> | 2.770(R)| SLOW | -1.457(R)| FAST |clk_main_BUFGP | 0.000|
62 DATA_RAM<10>| 2.773(R)| SLOW | -1.436(R)| FAST |clk_main_BUFGP | 0.000|
63 DATA_RAM<11>| 2.636(R)| SLOW | -1.363(R)| FAST |clk_main_BUFGP | 0.000|
64 DATA_RAM<12>| 3.878(R)| SLOW | -2.273(R)| FAST |clk_main_BUFGP | 0.000|
65 DATA_RAM<13>| 2.808(R)| SLOW | -1.448(R)| FAST |clk_main_BUFGP | 0.000|
66 DATA_RAM<14>| 2.982(R)| SLOW | -1.557(R)| FAST |clk_main_BUFGP | 0.000|
67 DATA_RAM<15>| 2.769(R)| SLOW | -1.433(R)| FAST |clk_main_BUFGP | 0.000|
68 LB_bar | 4.122(R)| SLOW | -1.890(R)| FAST |clk_main_BUFGP | 0.000|
69 OE_bar | 2.665(R)| SLOW | -1.074(R)| FAST |clk_main_BUFGP | 0.000|
70 UB_bar | 4.479(R)| SLOW | -1.697(R)| FAST |clk_main_BUFGP | 0.000|
71 WEA_bar | 4.813(R)| SLOW | -1.442(R)| FAST |clk_main_BUFGP | 0.000|
72 ------------+------------+------------+------------+------------+------------------+--------+
73
74 Clock clk_main to Pad
75 ------------+-----------------+------------+-----------------+------------+------------------+--------+
76 |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock |
77 Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase |
78 ------------+-----------------+------------+-----------------+------------+------------------+--------+
79 DATA_RAM<0> | 9.844(R)| SLOW | 4.721(R)| FAST |clk_main_BUFGP | 0.000|
80 DATA_RAM<1> | 10.026(R)| SLOW | 4.710(R)| FAST |clk_main_BUFGP | 0.000|
81 DATA_RAM<2> | 10.364(R)| SLOW | 5.006(R)| FAST |clk_main_BUFGP | 0.000|
82 DATA_RAM<3> | 10.364(R)| SLOW | 4.968(R)| FAST |clk_main_BUFGP | 0.000|
83 DATA_RAM<4> | 10.240(R)| SLOW | 4.959(R)| FAST |clk_main_BUFGP | 0.000|
84 DATA_RAM<5> | 10.240(R)| SLOW | 4.857(R)| FAST |clk_main_BUFGP | 0.000|
85 DATA_RAM<6> | 10.886(R)| SLOW | 5.091(R)| FAST |clk_main_BUFGP | 0.000|
86 DATA_RAM<7> | 10.886(R)| SLOW | 5.131(R)| FAST |clk_main_BUFGP | 0.000|
87 DATA_RAM<8> | 10.064(R)| SLOW | 5.049(R)| FAST |clk_main_BUFGP | 0.000|
88 DATA_RAM<9> | 10.064(R)| SLOW | 5.049(R)| FAST |clk_main_BUFGP | 0.000|
89 DATA_RAM<10>| 9.947(R)| SLOW | 5.039(R)| FAST |clk_main_BUFGP | 0.000|
90 DATA_RAM<11>| 9.947(R)| SLOW | 4.995(R)| FAST |clk_main_BUFGP | 0.000|
91 DATA_RAM<12>| 10.119(R)| SLOW | 5.097(R)| FAST |clk_main_BUFGP | 0.000|
92 DATA_RAM<13>| 10.119(R)| SLOW | 5.025(R)| FAST |clk_main_BUFGP | 0.000|
93 DATA_RAM<14>| 10.418(R)| SLOW | 5.153(R)| FAST |clk_main_BUFGP | 0.000|
94 DATA_RAM<15>| 10.418(R)| SLOW | 5.135(R)| FAST |clk_main_BUFGP | 0.000|
95 ------------+-----------------+------------+-----------------+------------+------------------+--------+
96
97 Clock to Setup on destination clock clk_main
98 ---------------+---------+---------+---------+---------+
99 | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
100 Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
101 ---------------+---------+---------+---------+---------+
102 clk_main | 3.387| | | |
103 ---------------+---------+---------+---------+---------+
104
105
106 Analysis completed Mon Dec 14 11:39:17 2015
107 --------------------------------------------------------------------------------
108
109 Trace Settings:
110 -------------------------
111 Trace Settings
112
113 Peak Memory Usage: 213 MB
114
115
116
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1 <?xml version="1.0" encoding="UTF-8"?>
2 <!DOCTYPE twReport [
3 <!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
4 twDebug*, twFoot?, twClientInfo?)>
5 <!ATTLIST twReport version CDATA "10,4">
6 <!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
7 <!ELEMENT twExecVer (#PCDATA)>
8 <!ELEMENT twCopyright (#PCDATA)>
9 <!ELEMENT twCmdLine (#PCDATA)>
10 <!ELEMENT twDesign (#PCDATA)>
11 <!ELEMENT twPCF (#PCDATA)>
12 <!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
13 <!ELEMENT twDevName (#PCDATA)>
14 <!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
15 <!ELEMENT twSpeedGrade (#PCDATA)>
16 <!ELEMENT twSpeedVer (#PCDATA)>
17 <!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
18 <!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
19 <!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
20 <!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
21 <!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
22 <!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
23 <!ELEMENT twItemLimit (#PCDATA)>
24 <!ELEMENT twUnconst EMPTY>
25 <!ELEMENT twUnconstLimit (#PCDATA)>
26 <!ELEMENT twEnvVar EMPTY>
27 <!ATTLIST twEnvVar name CDATA #REQUIRED>
28 <!ATTLIST twEnvVar description CDATA #REQUIRED>
29 <!ELEMENT twWarn (#PCDATA)>
30 <!ELEMENT twInfo (#PCDATA)>
31 <!ELEMENT twDebug (#PCDATA)>
32 <!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
33 <!ATTLIST twBody twFastPaths CDATA #IMPLIED>
34 <!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
35 <!ELEMENT twProc (#PCDATA)>
36 <!ELEMENT twTemp (#PCDATA)>
37 <!ELEMENT twVolt (#PCDATA)>
38 <!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
39 <!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
40 <!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
41 <!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
42 <!ELEMENT twCycles (twSigConn+)>
43 <!ATTLIST twCycles twNum CDATA #REQUIRED>
44 <!ELEMENT twSigConn (twSig, twDriver, twLoad)>
45 <!ELEMENT twSig (#PCDATA)>
46 <!ELEMENT twDriver (#PCDATA)>
47 <!ELEMENT twLoad (#PCDATA)>
48 <!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
49 <!ATTLIST twConst twConstType (NET |
50 NETDELAY |
51 NETSKEW |
52 PATH |
53 DEFPERIOD |
54 UNCONSTPATH |
55 DEFPATH |
56 PATH2SETUP |
57 UNCONSTPATH2SETUP |
58 PATHCLASS |
59 PATHDELAY |
60 PERIOD |
61 FREQUENCY |
62 PATHBLOCK |
63 OFFSET |
64 OFFSETIN |
65 OFFSETINCLOCK |
66 UNCONSTOFFSETINCLOCK |
67 OFFSETINDELAY |
68 OFFSETINMOD |
69 OFFSETOUT |
70 OFFSETOUTCLOCK |
71 UNCONSTOFFSETOUTCLOCK |
72 OFFSETOUTDELAY |
73 OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
74 <!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
75 twEndPtCnt?,
76 twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
77 <!ELEMENT twConstName (#PCDATA)>
78 <!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
79 <!ATTLIST twConstHead uID CDATA #IMPLIED>
80 <!ELEMENT twItemCnt (#PCDATA)>
81 <!ELEMENT twErrCnt (#PCDATA)>
82 <!ELEMENT twErrCntEndPt (#PCDATA)>
83 <!ELEMENT twErrCntSetup (#PCDATA)>
84 <!ELEMENT twErrCntHold (#PCDATA)>
85 <!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
86 <!ELEMENT twEndPtCnt (#PCDATA)>
87 <!ELEMENT twPathErrCnt (#PCDATA)>
88 <!ELEMENT twMinPer (#PCDATA) >
89 <!ELEMENT twFootnote EMPTY>
90 <!ATTLIST twFootnote number CDATA #REQUIRED>
91 <!ELEMENT twMaxDel (#PCDATA)>
92 <!ELEMENT twMaxFreq (#PCDATA)>
93 <!ELEMENT twMinOff (#PCDATA)>
94 <!ELEMENT twMaxOff (#PCDATA)>
95 <!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
96 <!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
97 <!ELEMENT twTIGName (#PCDATA)>
98 <!ELEMENT twInstantiated (#PCDATA)>
99 <!ELEMENT twBlocked (#PCDATA)>
100 <!ELEMENT twRacePathRpt (twRacePath+)>
101 <!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
102 <!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
103 <!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
104 twSimpleMinPath CDATA #IMPLIED>
105 <!ELEMENT twTotDel (#PCDATA)>
106 <!ELEMENT twSrc (#PCDATA)>
107 <!ATTLIST twSrc BELType CDATA #IMPLIED>
108 <!ELEMENT twDest (#PCDATA)>
109 <!ATTLIST twDest BELType CDATA #IMPLIED>
110 <!ELEMENT twDel (#PCDATA)>
111 <!ELEMENT twSUTime (#PCDATA)>
112 <!ELEMENT twTotPathDel (#PCDATA)>
113 <!ELEMENT twClkSkew (#PCDATA)>
114 <!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
115 <!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
116 <!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
117 <!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
118 <!ELEMENT twSlack (#PCDATA)>
119 <!ELEMENT twDelConst (#PCDATA)>
120 <!ELEMENT tw2Phase EMPTY>
121 <!ELEMENT twClkUncert (#PCDATA)>
122 <!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
123 fDCMJit CDATA #IMPLIED
124 fPhaseErr CDATA #IMPLIED
125 sEqu CDATA #IMPLIED>
126 <!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
127 <!ELEMENT twPathRptBanner (#PCDATA)>
128 <!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
129 <!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
130 <!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
131 <!ELEMENT twOff (#PCDATA)>
132 <!ELEMENT twGuaranteed EMPTY>
133 <!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
134 <!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
135 <!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
136 <!ELEMENT twClkDel (#PCDATA)>
137 <!ELEMENT twClkSrc (#PCDATA)>
138 <!ELEMENT twClkDest (#PCDATA)>
139 <!ELEMENT twGuarInSetup (#PCDATA)>
140 <!ELEMENT twOffSrc (#PCDATA)>
141 <!ELEMENT twOffDest (#PCDATA)>
142 <!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
143 <!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
144 <!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
145 <!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
146 <!ELEMENT twDataDel (#PCDATA)>
147 <!ELEMENT twDataSrc (#PCDATA)>
148 <!ELEMENT twDataDest (#PCDATA)>
149 <!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
150 <!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
151 <!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
152 <!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
153 <!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
154 <!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
155 <!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
156 <!ELEMENT twLogLvls (#PCDATA)>
157 <!ELEMENT twSrcSite (#PCDATA)>
158 <!ELEMENT twSrcClk (#PCDATA)>
159 <!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
160 <!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
161 <!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
162 <!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
163 <!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
164 <!ELEMENT twDelInfo (#PCDATA)>
165 <!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
166 <!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
167 <!ELEMENT twSite (#PCDATA)>
168 <!ELEMENT twDelType (#PCDATA)>
169 <!ELEMENT twFanCnt (#PCDATA)>
170 <!ELEMENT twComp (#PCDATA)>
171 <!ELEMENT twNet (#PCDATA)>
172 <!ELEMENT twBEL (#PCDATA)>
173 <!ELEMENT twLogDel (#PCDATA)>
174 <!ELEMENT twRouteDel (#PCDATA)>
175 <!ELEMENT twDestClk (#PCDATA)>
176 <!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
177 <!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
178 <!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
179 <!ELEMENT twPctLog (#PCDATA)>
180 <!ELEMENT twPctRoute (#PCDATA)>
181 <!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
182 <!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
183 <!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
184 <!ELEMENT twTimeConst (#PCDATA)>
185 <!ELEMENT twAbsSlack (#PCDATA)>
186 <!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
187 <!ELEMENT twSkew (#PCDATA)>
188 <!ELEMENT twDetNet (twNetDel*)>
189 <!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
190 <!ELEMENT twNetDelInfo (#PCDATA)>
191 <!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
192 <!ELEMENT twDetSkewNet (twNetSkew*)>
193 <!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
194 <!ELEMENT twClkSkewLimit EMPTY>
195 <!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
196 arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
197 <!ELEMENT twConstRollupTable (twConstRollup*)>
198 <!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
199 <!ELEMENT twConstRollup EMPTY>
200 <!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
201 <!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
202 <!ELEMENT twConstList (twConstListItem)*>
203 <!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
204 <!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
205 <!ELEMENT twNotMet EMPTY>
206 <!ELEMENT twReqVal (#PCDATA)>
207 <!ELEMENT twActVal (#PCDATA)>
208 <!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
209 <!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
210 <!ELEMENT twConstStats (twConstName)>
211 <!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
212 <!ATTLIST twConstStats twRequired CDATA #IMPLIED>
213 <!ATTLIST twConstStats twActual CDATA #IMPLIED>
214 <!ATTLIST twConstStats twSlack CDATA #IMPLIED>
215 <!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
216 <!ATTLIST twConstStats twErrors CDATA #IMPLIED>
217 <!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
218 <!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
219 <!ATTLIST twConstStats twTCType CDATA #IMPLIED>
220 <!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
221 <!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
222 <!ELEMENT twConstData EMPTY>
223 <!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
224 best CDATA #IMPLIED requested CDATA #IMPLIED
225 errors CDATA #IMPLIED
226 score CDATA #IMPLIED>
227 <!ELEMENT twTimeGrpRpt (twTimeGrp)*>
228 <!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
229 <!ELEMENT twTimeGrpName (#PCDATA)>
230 <!ELEMENT twCompList (twCompName+)>
231 <!ELEMENT twCompName (#PCDATA)>
232 <!ELEMENT twSigList (twSigName+)>
233 <!ELEMENT twSigName (#PCDATA)>
234 <!ELEMENT twBELList (twBELName+)>
235 <!ELEMENT twBELName (#PCDATA)>
236 <!ELEMENT twBlockList (twBlockName+)>
237 <!ELEMENT twBlockName (#PCDATA)>
238 <!ELEMENT twMacList (twMacName+)>
239 <!ELEMENT twMacName (#PCDATA)>
240 <!ELEMENT twPinList (twPinName+)>
241 <!ELEMENT twPinName (#PCDATA)>
242 <!ELEMENT twUnmetConstCnt (#PCDATA)>
243 <!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
244 <!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
245 <!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
246 <!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
247 <!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
248 <!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
249 <!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
250 <!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
251 <!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
252 <!ELEMENT twSU2ClkTime (#PCDATA)>
253 <!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
254 <!ELEMENT twH2ClkTime (#PCDATA)>
255 <!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
256 <!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
257 <!ELEMENT twClk2Pad (twDest, twTime)>
258 <!ELEMENT twTime (#PCDATA)>
259 <!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
260 <!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
261 <!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
262 <!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
263 <!ELEMENT twClk2Out EMPTY>
264 <!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
265 <!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
266 <!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
267 <!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
268 <!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
269 <!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
270 <!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
271 <!ELEMENT twClk2SUList (twDest, twClk2SU+)>
272 <!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
273 <!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
274 <!ELEMENT twRiseRise (#PCDATA)>
275 <!ELEMENT twFallRise (#PCDATA)>
276 <!ELEMENT twRiseFall (#PCDATA)>
277 <!ELEMENT twFallFall (#PCDATA)>
278 <!ELEMENT twPad2PadList (twPad2Pad+)>
279 <!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
280 <!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
281 <!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
282 <!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
283 <!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
284 <!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
285 <!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
286 <!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
287 <!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
288 <!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
289 <!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
290 <!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
291 <!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
292 <!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
293 <!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
294 <!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
295 <!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
296 <!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
297 <!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
298 <!ELEMENT twOffOutTblRow EMPTY>
299 <!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
300 <!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
301 <!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
302 <!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
303 <!ELEMENT twNonDedClk (#PCDATA)>
304 <!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
305 <!ELEMENT twScore (#PCDATA)>
306 <!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
307 <!ELEMENT twPathCnt (#PCDATA)>
308 <!ELEMENT twNetCnt (#PCDATA)>
309 <!ELEMENT twConnCnt (#PCDATA)>
310 <!ELEMENT twPct (#PCDATA)>
311 <!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
312 <!ELEMENT twMaxCombDel (#PCDATA)>
313 <!ELEMENT twMaxFromToDel (#PCDATA)>
314 <!ELEMENT twMaxNetDel (#PCDATA)>
315 <!ELEMENT twMaxNetSkew (#PCDATA)>
316 <!ELEMENT twMaxInAfterClk (#PCDATA)>
317 <!ELEMENT twMinInBeforeClk (#PCDATA)>
318 <!ELEMENT twMaxOutBeforeClk (#PCDATA)>
319 <!ELEMENT twMinOutAfterClk (#PCDATA)>
320 <!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
321 <!ELEMENT twTimestamp (#PCDATA)>
322 <!ELEMENT twFootnoteExplanation EMPTY>
323 <!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
324 <!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
325 <!ELEMENT twClientInfo (twClientName, twAttrList?)>
326 <!ELEMENT twClientName (#PCDATA)>
327 <!ELEMENT twAttrList (twAttrListItem)*>
328 <!ELEMENT twAttrListItem (twName, twValue*)>
329 <!ELEMENT twName (#PCDATA)>
330 <!ELEMENT twValue (#PCDATA)>
331 ]>
332 <twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3
333 -n 3 -fastpaths -xml BloqueRAM_int.twx BloqueRAM_int.ncd -o BloqueRAM_int.twr
334 BloqueRAM_int.pcf
335
336 </twCmdLine><twDesign>BloqueRAM_int.ncd</twDesign><twDesignPath>BloqueRAM_int.ncd</twDesignPath><twPCF>BloqueRAM_int.pcf</twPCF><twPcfPath>BloqueRAM_int.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="tqg144"><twDevName>xc6slx9</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-3</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-10-13</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="6" twNameLen="15"><twSUH2ClkList anchorID="7" twDestWidth="12" twPhaseWidth="14"><twDest>clk_main</twDest><twSUH2Clk ><twSrc>ADDR_RAM&lt;0&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.801</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.108</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;1&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.246</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.456</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;2&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.279</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.417</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;3&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.472</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.858</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;4&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.592</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.944</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;5&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.575</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.975</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;6&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.784</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.124</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;7&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.323</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.758</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;8&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.837</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.172</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>ADDR_RAM&lt;9&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.986</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.256</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>CS_1_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.345</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.617</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>CS_2</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.532</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.117</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;0&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.070</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-0.953</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;1&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.467</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.234</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;2&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.583</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.331</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;3&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.402</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.216</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;4&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.146</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.732</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;5&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.409</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.177</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;6&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.535</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.272</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;7&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.494</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.234</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;8&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.834</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.499</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;9&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.770</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.457</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;10&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.773</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.436</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;11&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.636</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.363</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;12&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">3.878</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-2.273</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;13&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.808</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.448</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;14&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.982</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.557</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>DATA_RAM&lt;15&gt;</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.769</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.433</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>LB_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.122</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.890</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>OE_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">2.665</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.074</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>UB_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.479</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.697</twH2ClkTime></twSUHTime></twSUH2Clk><twSUH2Clk ><twSrc>WEA_bar</twSrc><twSUHTime twInternalClk ="clk_main_BUFGP" twClkPhase ="0.000" ><twSU2ClkTime twEdge="twRising" twCrnrFst="f">4.813</twSU2ClkTime><twH2ClkTime twEdge="twRising" twCrnrFst="t">-1.442</twH2ClkTime></twSUHTime></twSUH2Clk></twSUH2ClkList><twClk2OutList anchorID="8" twDestWidth="12" twPhaseWidth="14"><twSrc>clk_main</twSrc><twClk2Out twOutPad = "DATA_RAM&lt;0&gt;" twMinTime = "4.721" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.844" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;1&gt;" twMinTime = "4.710" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.026" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;2&gt;" twMinTime = "5.006" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.364" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;3&gt;" twMinTime = "4.968" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.364" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;4&gt;" twMinTime = "4.959" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.240" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;5&gt;" twMinTime = "4.857" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.240" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;6&gt;" twMinTime = "5.091" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.886" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;7&gt;" twMinTime = "5.131" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.886" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;8&gt;" twMinTime = "5.049" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.064" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;9&gt;" twMinTime = "5.049" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.064" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;10&gt;" twMinTime = "5.039" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.947" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;11&gt;" twMinTime = "4.995" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "9.947" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;12&gt;" twMinTime = "5.097" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.119" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;13&gt;" twMinTime = "5.025" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.119" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;14&gt;" twMinTime = "5.153" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.418" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "DATA_RAM&lt;15&gt;" twMinTime = "5.135" twMinCrnr="t" twMinEdge ="twRising" twMaxTime = "10.418" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="clk_main_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="9" twDestWidth="8"><twDest>clk_main</twDest><twClk2SU><twSrc>clk_main</twSrc><twRiseRise>3.387</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Mon Dec 14 11:39:17 2015 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
337
338 Peak Memory Usage: 213 MB
339 </twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
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1 Release 14.7 - par P.20131013 (nt64)
2 Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3
4 Mon Dec 14 11:39:10 2015
5
6 All signals are completely routed.
7
8
9
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 08:20:52 12/14/2015
6 -- Design Name:
7 -- Module Name: BloqueRAM_int - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 library UNISIM;
30 use UNISIM.VComponents.all;
31
32 entity BloqueRAM_int is
33 GENERIC(
34 DATA_PRIM_SZ: INTEGER:=32;
35 ADDR_PRIM_SZ: INTEGER:=14;
36 RESUL_SZ: INTEGER:= 16;
37 ADDR_SZ: INTEGER:= 10
38 );
39 PORT(
40 clk_main: IN std_logic; --Reloj externo de por lo menos 32MHz proveniente del m�dulo de sincronizaci�n o PLL
41 --o m�dulo de divisi�n de relojes internos
42 CS_1_bar: IN std_logic;
43 CS_2: IN std_logic;
44 OE_bar: IN std_logic;
45 WEA_bar: IN std_logic; --Se�al de habilitador proveniente del controlador de memoria
46 UB_bar: IN std_logic;
47 LB_bar: IN std_logic;
48
49 ADDR_RAM: IN std_logic_vector((ADDR_SZ-1) downto 0);
50 DATA_RAM: INOUT std_logic_vector((RESUL_SZ-1) downto 0) --Entrada Salida de datos a escribir/leer en/de la RAM
51
52 );
53 end BloqueRAM_int;
54
55 architecture Behavioral of BloqueRAM_int is
56
57 SIGNAL addr_ram_aux: std_logic_vector((ADDR_PRIM_SZ-1) downto 0) := (OTHERS => '0'); --14 bits de bus de direcci�n
58 SIGNAL data_ram_aux_in: std_logic_vector((DATA_PRIM_SZ-1) downto 0) := (OTHERS => '0'); --32 bits de bus de direcci�n
59 SIGNAL data_ram_aux_out: std_logic_vector((DATA_PRIM_SZ-1) downto 0); --32 bits de bus de direcci�n
60 SIGNAL CS_aux: std_logic;
61 signal WE_AUX: std_logic_vector(3 downto 0);
62
63 begin
64
65 addr_ram_aux <= ADDR_RAM & "0000";
66 data_ram_aux_in((DATA_PRIM_SZ-1) downto RESUL_SZ) <= "0000000000000000";
67
68 PROCESS(OE_bar,UB_bar,LB_bar)
69 BEGIN
70
71 END PROCESS;
72
73 PROCESS (CS_aux,WEA_bar,clk_main,UB_bar,LB_bar,OE_bar)
74 BEGIN
75 IF(CS_aux /= '1') THEN
76 DATA_RAM <= (OTHERS=>'Z');
77
78 ELSIF((UB_bar AND LB_bar) = '1') THEN
79 DATA_RAM <= (OTHERS=>'Z');
80
81 ELSIF(WEA_bar = '1') THEN
82 IF(OE_BAR = '1') THEN
83 DATA_RAM <= (OTHERS=>'Z');
84 ELSE
85
86 IF(UB_bar='0') THEN
87 IF(rising_edge(clk_main)) THEN
88 DATA_RAM(15 downto 8) <= data_ram_aux_out(15 downto 8);
89 END IF;
90 ELSE
91 DATA_RAM(15 downto 8) <= (OTHERS=>'Z');
92 END IF;
93
94 IF(LB_bar='0') THEN
95 IF(rising_edge(clk_main)) THEN
96 DATA_RAM(7 downto 0) <= data_ram_aux_out(7 downto 0);
97 END IF;
98 ELSE
99 DATA_RAM(7 downto 0) <= (OTHERS=>'Z');
100 END IF;
101
102 END IF;
103
104 ELSE
105 DATA_RAM <= (OTHERS=>'Z');
106
107 IF(UB_bar='0') THEN
108 IF(rising_edge(clk_main)) THEN
109 data_ram_aux_in((RESUL_SZ-1) downto 8) <= DATA_RAM(15 downto 8);
110 END IF;
111 --ELSE
112 -- data_ram_aux_in((RESUL_SZ-1) downto 8) <= (OTHERS=>'Z');
113 END IF;
114
115 IF(LB_bar='0') THEN
116 IF(rising_edge(clk_main)) THEN
117 data_ram_aux_in(7 downto 0) <= DATA_RAM(7 downto 0);
118 END IF;
119 --ELSE
120 -- data_ram_aux_in(7 downto 0) <= (OTHERS=>'Z');
121 END IF;
122
123 END IF;
124
125 END PROCESS;
126
127
128
129 CS_aux <=((NOT(CS_1_bar)) AND CS_2);
130 WE_aux <= (NOT(WEA_bar))&(NOT(WEA_bar))&(NOT(WEA_bar))&(NOT(WEA_bar)) ;
131
132 RAMB16BWER_inst : RAMB16BWER
133 generic map (
134 -- DATA_WIDTH_A/DATA_WIDTH_B: 0, 1, 2, 4, 9, 18, or 36
135 DATA_WIDTH_A => 18,
136 DATA_WIDTH_B => 18,
137 -- DOA_REG/DOB_REG: Optional output register (0 or 1)
138 DOA_REG => 0, --Que no cambie la data mostrada en escritura hasta el flanco de reloj,
139 DOB_REG => 0,
140 -- EN_RSTRAM_A/EN_RSTRAM_B: Enable/disable RST
141 EN_RSTRAM_A => TRUE,
142 EN_RSTRAM_B => TRUE,
143 -- INITP_00 to INITP_07: Initial memory contents.
144 INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
145 INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
146 INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
147 INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
148 INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
149 INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
150 INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
151 INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
152 -- INIT_00 to INIT_3F: Initial memory contents.
153 INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
154 INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
155 INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
156 INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
157 INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
158 INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
159 INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
160 INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
161 INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
162 INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
163 INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
164 INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
165 INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
166 INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
167 INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
168 INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
169 INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
170 INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
171 INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
172 INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
173 INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
174 INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
175 INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
176 INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
177 INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
178 INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
179 INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
180 INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
181 INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
182 INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
183 INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
184 INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
185 INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
186 INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
187 INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
188 INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
189 INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
190 INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
191 INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
192 INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
193 INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
194 INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
195 INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
196 INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
197 INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
198 INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
199 INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
200 INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
201 INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
202 INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
203 INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
204 INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
205 INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
206 INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
207 INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
208 INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
209 INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
210 INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
211 INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
212 INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
213 INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
214 INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
215 INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
216 INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
217 -- INIT_A/INIT_B: Initial values on output port
218 INIT_A => X"000000000",
219 INIT_B => X"000000000",
220 -- INIT_FILE: Optional file used to specify initial RAM contents
221 INIT_FILE => "NONE",
222 -- RSTTYPE: "SYNC" or "ASYNC"
223 RSTTYPE => "SYNC",
224 -- RST_PRIORITY_A/RST_PRIORITY_B: "CE" or "SR"
225 RST_PRIORITY_A => "CE",
226 RST_PRIORITY_B => "CE",
227 -- SIM_COLLISION_CHECK: Collision check enable "ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE"
228 SIM_COLLISION_CHECK => "ALL",
229 -- SIM_DEVICE: Must be set to "SPARTAN6" for proper simulation behavior
230 SIM_DEVICE => "SPARTAN6",
231 -- SRVAL_A/SRVAL_B: Set/Reset value for RAM output
232 SRVAL_A => X"000000000",
233 SRVAL_B => X"000000000",
234 -- WRITE_MODE_A/WRITE_MODE_B: "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"
235 WRITE_MODE_A => "NO_CHANGE",
236 WRITE_MODE_B => "NO_CHANGE"
237 )
238 port map (
239 -- Port A Data: 32-bit (each) output: Port A data
240 DOA => data_ram_aux_out, -- 32-bit output: A port data output
241 DOPA => open, -- 4-bit output: A port parity output
242 -- Port B Data: 32-bit (each) output: Port B data
243 DOB => open, -- 32-bit output: B port data output
244 DOPB => open, -- 4-bit output: B port parity output
245 -- Port A Address/Control Signals: 14-bit (each) input: Port A address and control signals
246 ADDRA => addr_ram_aux, -- 14-bit input: A port address input
247 CLKA => clk_main, -- 1-bit input: A port clock input
248 ENA => CS_AUX, -- 1-bit input: A port enable input
249 REGCEA => '1', -- 1-bit input: A port register clock enable input
250 RSTA => '0', -- 1-bit input: A port register set/reset input
251 WEA => WE_aux, -- 4-bit input: Port A byte-wide write enable input
252 -- Port A Data: 32-bit (each) input: Port A data
253 DIA => data_ram_aux_in, -- 32-bit input: A port data input
254 DIPA => "0000", -- 4-bit input: A port parity input
255 -- Port B Address/Control Signals: 14-bit (each) input: Port B address and control signals
256 ADDRB => "00000000000000", -- 14-bit input: B port address input
257 CLKB => '0', -- 1-bit input: B port clock input
258 ENB => '0', -- 1-bit input: B port enable input
259 REGCEB => '0', -- 1-bit input: B port register clock enable input
260 RSTB => '0', -- 1-bit input: B port register set/reset input
261 WEB => "0000", -- 4-bit input: Port B byte-wide write enable input
262 -- Port B Data: 32-bit (each) input: Port B data
263 DIB => X"00000000", -- 32-bit input: B port data input
264 DIPB => "0000" -- 4-bit input: B port parity input
265 );
266
267 end Behavioral;
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1 PROGRAM=PAR
2 STATE=ROUTED
3 TIMESPECS_MET=OFF
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1 set -tmpdir "xst/projnav.tmp"
2 set -xsthdpdir "xst"
3 run
4 -ifn BloqueRAM_int.prj
5 -ofn BloqueRAM_int
6 -ofmt NGC
7 -p xc6slx9-3-tqg144
8 -top BloqueRAM_int
9 -opt_mode Speed
10 -opt_level 1
11 -power NO
12 -iuc NO
13 -keep_hierarchy No
14 -netlist_hierarchy As_Optimized
15 -rtlview Yes
16 -glob_opt AllClockNets
17 -read_cores YES
18 -write_timing_constraints NO
19 -cross_clock_analysis NO
20 -hierarchy_separator /
21 -bus_delimiter <>
22 -case Maintain
23 -slice_utilization_ratio 100
24 -bram_utilization_ratio 100
25 -dsp_utilization_ratio 100
26 -lc Auto
27 -reduce_control_sets Auto
28 -fsm_extract YES -fsm_encoding Auto
29 -safe_implementation No
30 -fsm_style LUT
31 -ram_extract Yes
32 -ram_style Auto
33 -rom_extract Yes
34 -shreg_extract YES
35 -rom_style Auto
36 -auto_bram_packing NO
37 -resource_sharing YES
38 -async_to_sync NO
39 -shreg_min_size 2
40 -use_dsp48 Auto
41 -iobuf YES
42 -max_fanout 100000
43 -bufg 16
44 -register_duplication YES
45 -register_balancing No
46 -optimize_primitives NO
47 -use_clock_enable Auto
48 -use_sync_set Auto
49 -use_sync_reset Auto
50 -iob Auto
51 -equivalent_register_removal YES
52 -slice_utilization_ratio_maxmargin 5
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1 <HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
2 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
3 <center><big><big><b>System Settings</b></big></big></center><br>
4 <A NAME="Environment Settings"></A>
5 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
6 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
7 <TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
8 </tr>
9 <tr bgcolor='#ffff99'>
10 <td><b>Environment Variable</b></td>
11 <td><b>xst</b></td>
12 <td><b>ngdbuild</b></td>
13 <td><b>map</b></td>
14 <td><b>par</b></td>
15 </tr>
16 <tr>
17 <td>PATHEXT</td>
18 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
19 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
20 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
21 <td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC;<br>.PY;<br>.PYW</td>
22 </tr>
23 <tr>
24 <td>Path</td>
25 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
26 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
27 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
28 <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\WinAVR\bin;<br>C:\WinAVR\utils\bin;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files\doxygen\bin;<br>C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;<br>C:\Program Files (x86)\Microchip\xc8\v1.35\bin;<br>C:\Program Files (x86)\Microchip\xc16\v1.24\bin;<br>c:\MinGW\bin;<br>c:\MinGW\MSYS\1.0\bin</td>
29 </tr>
30 <tr>
31 <td>XILINX</td>
32 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
33 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
34 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
35 <td>C:\Xilinx\14.7\ISE_DS\ISE\</td>
36 </tr>
37 <tr>
38 <td>XILINX_DSP</td>
39 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
40 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
41 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
42 <td>C:\Xilinx\14.7\ISE_DS\ISE</td>
43 </tr>
44 <tr>
45 <td>XILINX_EDK</td>
46 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
47 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
48 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
49 <td>C:\Xilinx\14.7\ISE_DS\EDK</td>
50 </tr>
51 <tr>
52 <td>XILINX_PLANAHEAD</td>
53 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
54 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
55 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
56 <td>C:\Xilinx\14.7\ISE_DS\PlanAhead</td>
57 </tr>
58 </TABLE>
59 <A NAME="Synthesis Property Settings"></A>
60 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
61 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
62 <TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
63 </tr>
64 <tr bgcolor='#ffff99'>
65 <td><b>Switch Name</b></td>
66 <td><b>Property Name</b></td>
67 <td><b>Value</b></td>
68 <td><b>Default Value</b></td>
69 </tr>
70 <tr>
71 <td>-ifn</td>
72 <td>&nbsp;</td>
73 <td>BloqueRAM_int.prj</td>
74 <td>&nbsp;</td>
75 </tr>
76 <tr>
77 <td>-ofn</td>
78 <td>&nbsp;</td>
79 <td>BloqueRAM_int</td>
80 <td>&nbsp;</td>
81 </tr>
82 <tr>
83 <td>-ofmt</td>
84 <td>&nbsp;</td>
85 <td>NGC</td>
86 <td>NGC</td>
87 </tr>
88 <tr>
89 <td>-p</td>
90 <td>&nbsp;</td>
91 <td>xc6slx9-3-tqg144</td>
92 <td>&nbsp;</td>
93 </tr>
94 <tr>
95 <td>-top</td>
96 <td>&nbsp;</td>
97 <td>BloqueRAM_int</td>
98 <td>&nbsp;</td>
99 </tr>
100 <tr>
101 <td>-opt_mode</td>
102 <td>Optimization Goal</td>
103 <td>Speed</td>
104 <td>Speed</td>
105 </tr>
106 <tr>
107 <td>-opt_level</td>
108 <td>Optimization Effort</td>
109 <td>1</td>
110 <td>1</td>
111 </tr>
112 <tr>
113 <td>-power</td>
114 <td>Power Reduction</td>
115 <td>NO</td>
116 <td>No</td>
117 </tr>
118 <tr>
119 <td>-iuc</td>
120 <td>Use synthesis Constraints File</td>
121 <td>NO</td>
122 <td>No</td>
123 </tr>
124 <tr>
125 <td>-keep_hierarchy</td>
126 <td>Keep Hierarchy</td>
127 <td>No</td>
128 <td>No</td>
129 </tr>
130 <tr>
131 <td>-netlist_hierarchy</td>
132 <td>Netlist Hierarchy</td>
133 <td>As_Optimized</td>
134 <td>As_Optimized</td>
135 </tr>
136 <tr>
137 <td>-rtlview</td>
138 <td>Generate RTL Schematic</td>
139 <td>Yes</td>
140 <td>No</td>
141 </tr>
142 <tr>
143 <td>-glob_opt</td>
144 <td>Global Optimization Goal</td>
145 <td>AllClockNets</td>
146 <td>AllClockNets</td>
147 </tr>
148 <tr>
149 <td>-read_cores</td>
150 <td>Read Cores</td>
151 <td>YES</td>
152 <td>Yes</td>
153 </tr>
154 <tr>
155 <td>-write_timing_constraints</td>
156 <td>Write Timing Constraints</td>
157 <td>NO</td>
158 <td>No</td>
159 </tr>
160 <tr>
161 <td>-cross_clock_analysis</td>
162 <td>Cross Clock Analysis</td>
163 <td>NO</td>
164 <td>No</td>
165 </tr>
166 <tr>
167 <td>-bus_delimiter</td>
168 <td>Bus Delimiter</td>
169 <td>&lt;&gt;</td>
170 <td>&lt;&gt;</td>
171 </tr>
172 <tr>
173 <td>-slice_utilization_ratio</td>
174 <td>Slice Utilization Ratio</td>
175 <td>100</td>
176 <td>100</td>
177 </tr>
178 <tr>
179 <td>-bram_utilization_ratio</td>
180 <td>BRAM Utilization Ratio</td>
181 <td>100</td>
182 <td>100</td>
183 </tr>
184 <tr>
185 <td>-dsp_utilization_ratio</td>
186 <td>DSP Utilization Ratio</td>
187 <td>100</td>
188 <td>100</td>
189 </tr>
190 <tr>
191 <td>-reduce_control_sets</td>
192 <td>&nbsp;</td>
193 <td>Auto</td>
194 <td>Auto</td>
195 </tr>
196 <tr>
197 <td>-fsm_extract</td>
198 <td>&nbsp;</td>
199 <td>YES</td>
200 <td>Yes</td>
201 </tr>
202 <tr>
203 <td>-fsm_encoding</td>
204 <td>&nbsp;</td>
205 <td>Auto</td>
206 <td>Auto</td>
207 </tr>
208 <tr>
209 <td>-safe_implementation</td>
210 <td>&nbsp;</td>
211 <td>No</td>
212 <td>No</td>
213 </tr>
214 <tr>
215 <td>-fsm_style</td>
216 <td>&nbsp;</td>
217 <td>LUT</td>
218 <td>LUT</td>
219 </tr>
220 <tr>
221 <td>-ram_extract</td>
222 <td>&nbsp;</td>
223 <td>Yes</td>
224 <td>Yes</td>
225 </tr>
226 <tr>
227 <td>-ram_style</td>
228 <td>&nbsp;</td>
229 <td>Auto</td>
230 <td>Auto</td>
231 </tr>
232 <tr>
233 <td>-rom_extract</td>
234 <td>&nbsp;</td>
235 <td>Yes</td>
236 <td>Yes</td>
237 </tr>
238 <tr>
239 <td>-shreg_extract</td>
240 <td>&nbsp;</td>
241 <td>YES</td>
242 <td>Yes</td>
243 </tr>
244 <tr>
245 <td>-rom_style</td>
246 <td>&nbsp;</td>
247 <td>Auto</td>
248 <td>Auto</td>
249 </tr>
250 <tr>
251 <td>-auto_bram_packing</td>
252 <td>&nbsp;</td>
253 <td>NO</td>
254 <td>No</td>
255 </tr>
256 <tr>
257 <td>-resource_sharing</td>
258 <td>&nbsp;</td>
259 <td>YES</td>
260 <td>Yes</td>
261 </tr>
262 <tr>
263 <td>-async_to_sync</td>
264 <td>&nbsp;</td>
265 <td>NO</td>
266 <td>No</td>
267 </tr>
268 <tr>
269 <td>-use_dsp48</td>
270 <td>&nbsp;</td>
271 <td>Auto</td>
272 <td>Auto</td>
273 </tr>
274 <tr>
275 <td>-iobuf</td>
276 <td>&nbsp;</td>
277 <td>YES</td>
278 <td>Yes</td>
279 </tr>
280 <tr>
281 <td>-max_fanout</td>
282 <td>&nbsp;</td>
283 <td>100000</td>
284 <td>100000</td>
285 </tr>
286 <tr>
287 <td>-bufg</td>
288 <td>&nbsp;</td>
289 <td>16</td>
290 <td>16</td>
291 </tr>
292 <tr>
293 <td>-register_duplication</td>
294 <td>&nbsp;</td>
295 <td>YES</td>
296 <td>Yes</td>
297 </tr>
298 <tr>
299 <td>-register_balancing</td>
300 <td>&nbsp;</td>
301 <td>No</td>
302 <td>No</td>
303 </tr>
304 <tr>
305 <td>-optimize_primitives</td>
306 <td>&nbsp;</td>
307 <td>NO</td>
308 <td>No</td>
309 </tr>
310 <tr>
311 <td>-use_clock_enable</td>
312 <td>&nbsp;</td>
313 <td>Auto</td>
314 <td>Auto</td>
315 </tr>
316 <tr>
317 <td>-use_sync_set</td>
318 <td>&nbsp;</td>
319 <td>Auto</td>
320 <td>Auto</td>
321 </tr>
322 <tr>
323 <td>-use_sync_reset</td>
324 <td>&nbsp;</td>
325 <td>Auto</td>
326 <td>Auto</td>
327 </tr>
328 <tr>
329 <td>-iob</td>
330 <td>&nbsp;</td>
331 <td>Auto</td>
332 <td>Auto</td>
333 </tr>
334 <tr>
335 <td>-equivalent_register_removal</td>
336 <td>&nbsp;</td>
337 <td>YES</td>
338 <td>Yes</td>
339 </tr>
340 <tr>
341 <td>-slice_utilization_ratio_maxmargin</td>
342 <td>&nbsp;</td>
343 <td>5</td>
344 <td>0</td>
345 </tr>
346 </TABLE>
347 <A NAME="Translation Property Settings"></A>
348 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
349 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
350 <TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
351 </tr>
352 <tr bgcolor='#ffff99'>
353 <td><b>Switch Name</b></td>
354 <td><b>Property Name</b></td>
355 <td><b>Value</b></td>
356 <td><b>Default Value</b></td>
357 </tr>
358 <tr>
359 <td>-intstyle</td>
360 <td>&nbsp;</td>
361 <td>ise</td>
362 <td>None</td>
363 </tr>
364 <tr>
365 <td>-dd</td>
366 <td>&nbsp;</td>
367 <td>_ngo</td>
368 <td>None</td>
369 </tr>
370 <tr>
371 <td>-p</td>
372 <td>&nbsp;</td>
373 <td>xc6slx9-tqg144-3</td>
374 <td>None</td>
375 </tr>
376 </TABLE>
377 <A NAME="Map Property Settings"></A>
378 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
379 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
380 <TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
381 </tr>
382 <tr bgcolor='#ffff99'>
383 <td><b>Switch Name</b></td>
384 <td><b>Property Name</b></td>
385 <td><b>Value</b></td>
386 <td><b>Default Value</b></td>
387 </tr>
388 <tr>
389 <td>-ol</td>
390 <td>Place & Route Effort Level (Overall)</td>
391 <td>high</td>
392 <td>high</td>
393 </tr>
394 <tr>
395 <td>-xt</td>
396 <td>Extra Cost Tables</td>
397 <td>0</td>
398 <td>0</td>
399 </tr>
400 <tr>
401 <td>-ir</td>
402 <td>Use RLOC Constraints</td>
403 <td>OFF</td>
404 <td>OFF</td>
405 </tr>
406 <tr>
407 <td>-t</td>
408 <td>Starting Placer Cost Table (1-100) Map</td>
409 <td>1</td>
410 <td>0</td>
411 </tr>
412 <tr>
413 <td>-r</td>
414 <td>Register Ordering</td>
415 <td>4</td>
416 <td>4</td>
417 </tr>
418 <tr>
419 <td>-intstyle</td>
420 <td>&nbsp;</td>
421 <td>ise</td>
422 <td>None</td>
423 </tr>
424 <tr>
425 <td>-lc</td>
426 <td>LUT Combining</td>
427 <td>off</td>
428 <td>off</td>
429 </tr>
430 <tr>
431 <td>-o</td>
432 <td>&nbsp;</td>
433 <td>BloqueRAM_int_map.ncd</td>
434 <td>None</td>
435 </tr>
436 <tr>
437 <td>-w</td>
438 <td>&nbsp;</td>
439 <td>true</td>
440 <td>false</td>
441 </tr>
442 <tr>
443 <td>-pr</td>
444 <td>Pack I/O Registers/Latches into IOBs</td>
445 <td>off</td>
446 <td>off</td>
447 </tr>
448 <tr>
449 <td>-p</td>
450 <td>&nbsp;</td>
451 <td>xc6slx9-tqg144-3</td>
452 <td>None</td>
453 </tr>
454 </TABLE>
455 <A NAME="Place and Route Property Settings"></A>
456 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
457 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
458 <TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
459 </tr>
460 <tr bgcolor='#ffff99'>
461 <td><b>Switch Name</b></td>
462 <td><b>Property Name</b></td>
463 <td><b>Value</b></td>
464 <td><b>Default Value</b></td>
465 </tr>
466 <tr>
467 <td>-intstyle</td>
468 <td>&nbsp;</td>
469 <td>ise</td>
470 <td>&nbsp;</td>
471 </tr>
472 <tr>
473 <td>-mt</td>
474 <td>Enable Multi-Threading</td>
475 <td>off</td>
476 <td>off</td>
477 </tr>
478 <tr>
479 <td>-ol</td>
480 <td>Place & Route Effort Level (Overall)</td>
481 <td>high</td>
482 <td>std</td>
483 </tr>
484 <tr>
485 <td>-w</td>
486 <td>&nbsp;</td>
487 <td>true</td>
488 <td>false</td>
489 </tr>
490 </TABLE>
491 <A NAME="Operating System Information"></A>
492 &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
493 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
494 <TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
495 </tr>
496 <tr bgcolor='#ffff99'>
497 <td><b>Operating System Information</b></td>
498 <td><b>xst</b></td>
499 <td><b>ngdbuild</b></td>
500 <td><b>map</b></td>
501 <td><b>par</b></td>
502 </tr>
503 <tr>
504 <td>CPU Architecture/Speed</td>
505 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
506 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
507 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
508 <td>Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz</td>
509 </tr>
510 <tr>
511 <td>Host</td>
512 <td>Lenovo-PC</td>
513 <td>Lenovo-PC</td>
514 <td>Lenovo-PC</td>
515 <td>Lenovo-PC</td>
516 </tr>
517 <tr>
518 <td>OS Name</td>
519 <td>Microsoft , 64-bit</td>
520 <td>Microsoft , 64-bit</td>
521 <td>Microsoft , 64-bit</td>
522 <td>Microsoft , 64-bit</td>
523 </tr>
524 <tr>
525 <td>OS Release</td>
526 <td>major release (build 9200)</td>
527 <td>major release (build 9200)</td>
528 <td>major release (build 9200)</td>
529 <td>major release (build 9200)</td>
530 </tr>
531 </TABLE>
532 </BODY> </HTML> No newline at end of file
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2 XILINX-XDM V1.6
3 ###4956:XlxV32DM 3fff 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1 Release 14.7 Map P.20131013 (nt64)
2 Xilinx Map Application Log File for Design 'BloqueRAM_int'
3
4 Design Information
5 ------------------
6 Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
7 high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
8 -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd
9 BloqueRAM_int.pcf
10 Target Device : xc6slx9
11 Target Package : tqg144
12 Target Speed : -3
13 Mapper Version : spartan6 -- $Revision: 1.55 $
14 Mapped Date : Mon Dec 14 11:38:44 2015
15
16 Mapping design into LUTs...
17 Running directed packing...
18 Running delay-based LUT packing...
19 Updating timing models...
20 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
21 (.mrp).
22 Running timing-driven placement...
23 Total REAL time at the beginning of Placer: 7 secs
24 Total CPU time at the beginning of Placer: 4 secs
25
26 Phase 1.1 Initial Placement Analysis
27 Phase 1.1 Initial Placement Analysis (Checksum:c0e) REAL time: 9 secs
28
29 Phase 2.7 Design Feasibility Check
30 Phase 2.7 Design Feasibility Check (Checksum:c0e) REAL time: 9 secs
31
32 Phase 3.31 Local Placement Optimization
33 Phase 3.31 Local Placement Optimization (Checksum:c0e) REAL time: 9 secs
34
35 Phase 4.2 Initial Placement for Architecture Specific Features
36 ...
37 .....
38 Phase 4.2 Initial Placement for Architecture Specific Features (Checksum:ecc6) REAL time: 11 secs
39
40 Phase 5.36 Local Placement Optimization
41 Phase 5.36 Local Placement Optimization (Checksum:ecc6) REAL time: 11 secs
42
43 Phase 6.30 Global Clock Region Assignment
44 Phase 6.30 Global Clock Region Assignment (Checksum:ecc6) REAL time: 11 secs
45
46 Phase 7.3 Local Placement Optimization
47 ...
48 .....
49 Phase 7.3 Local Placement Optimization (Checksum:1e558ea8) REAL time: 12 secs
50
51 Phase 8.5 Local Placement Optimization
52 Phase 8.5 Local Placement Optimization (Checksum:1e558ea8) REAL time: 12 secs
53
54 Phase 9.8 Global Placement
55 .................
56 ....................
57 Phase 9.8 Global Placement (Checksum:dadb6f42) REAL time: 12 secs
58
59 Phase 10.5 Local Placement Optimization
60 Phase 10.5 Local Placement Optimization (Checksum:dadb6f42) REAL time: 12 secs
61
62 Phase 11.18 Placement Optimization
63 Phase 11.18 Placement Optimization (Checksum:686ff5d2) REAL time: 13 secs
64
65 Phase 12.5 Local Placement Optimization
66 Phase 12.5 Local Placement Optimization (Checksum:686ff5d2) REAL time: 13 secs
67
68 Phase 13.34 Placement Validation
69 Phase 13.34 Placement Validation (Checksum:685119d3) REAL time: 13 secs
70
71 Total REAL time to Placer completion: 13 secs
72 Total CPU time to Placer completion: 7 secs
73 Running post-placement packing...
74 Writing output files...
75
76 Design Summary
77 --------------
78
79 Design Summary:
80 Number of errors: 0
81 Number of warnings: 0
82 Slice Logic Utilization:
83 Number of Slice Registers: 34 out of 11,440 1%
84 Number used as Flip Flops: 34
85 Number used as Latches: 0
86 Number used as Latch-thrus: 0
87 Number used as AND/OR logics: 0
88 Number of Slice LUTs: 5 out of 5,720 1%
89 Number used as logic: 5 out of 5,720 1%
90 Number using O6 output only: 3
91 Number using O5 output only: 0
92 Number using O5 and O6: 2
93 Number used as ROM: 0
94 Number used as Memory: 0 out of 1,440 0%
95
96 Slice Logic Distribution:
97 Number of occupied Slices: 11 out of 1,430 1%
98 Number of MUXCYs used: 0 out of 2,860 0%
99 Number of LUT Flip Flop pairs used: 37
100 Number with an unused Flip Flop: 3 out of 37 8%
101 Number with an unused LUT: 32 out of 37 86%
102 Number of fully used LUT-FF pairs: 2 out of 37 5%
103 Number of unique control sets: 4
104 Number of slice register sites lost
105 to control set restrictions: 14 out of 11,440 1%
106
107 A LUT Flip Flop pair for this architecture represents one LUT paired with
108 one Flip Flop within a slice. A control set is a unique combination of
109 clock, reset, set, and enable signals for a registered element.
110 The Slice Logic Distribution report is not meaningful if the design is
111 over-mapped for a non-slice resource or if Placement fails.
112
113 IO Utilization:
114 Number of bonded IOBs: 33 out of 102 32%
115
116 Specific Feature Utilization:
117 Number of RAMB16BWERs: 1 out of 32 3%
118 Number of RAMB8BWERs: 0 out of 64 0%
119 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
120 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
121 Number of BUFG/BUFGMUXs: 1 out of 16 6%
122 Number used as BUFGs: 1
123 Number used as BUFGMUX: 0
124 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
125 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
126 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
127 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
128 Number of BSCANs: 0 out of 4 0%
129 Number of BUFHs: 0 out of 128 0%
130 Number of BUFPLLs: 0 out of 8 0%
131 Number of BUFPLL_MCBs: 0 out of 4 0%
132 Number of DSP48A1s: 0 out of 16 0%
133 Number of ICAPs: 0 out of 1 0%
134 Number of MCBs: 0 out of 2 0%
135 Number of PCILOGICSEs: 0 out of 2 0%
136 Number of PLL_ADVs: 0 out of 2 0%
137 Number of PMVs: 0 out of 1 0%
138 Number of STARTUPs: 0 out of 1 0%
139 Number of SUSPEND_SYNCs: 0 out of 1 0%
140
141 Average Fanout of Non-Clock Nets: 1.60
142
143 Peak Memory Usage: 330 MB
144 Total REAL time to MAP completion: 13 secs
145 Total CPU time to MAP completion: 8 secs
146
147 Mapping completed.
148 See MAP report file "BloqueRAM_int_map.mrp" for details.
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1 Release 14.7 Map P.20131013 (nt64)
2 Xilinx Mapping Report File for Design 'BloqueRAM_int'
3
4 Design Information
5 ------------------
6 Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol
7 high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
8 -pr off -lc off -power off -o BloqueRAM_int_map.ncd BloqueRAM_int.ngd
9 BloqueRAM_int.pcf
10 Target Device : xc6slx9
11 Target Package : tqg144
12 Target Speed : -3
13 Mapper Version : spartan6 -- $Revision: 1.55 $
14 Mapped Date : Mon Dec 14 11:38:44 2015
15
16 Design Summary
17 --------------
18 Number of errors: 0
19 Number of warnings: 0
20 Slice Logic Utilization:
21 Number of Slice Registers: 34 out of 11,440 1%
22 Number used as Flip Flops: 34
23 Number used as Latches: 0
24 Number used as Latch-thrus: 0
25 Number used as AND/OR logics: 0
26 Number of Slice LUTs: 5 out of 5,720 1%
27 Number used as logic: 5 out of 5,720 1%
28 Number using O6 output only: 3
29 Number using O5 output only: 0
30 Number using O5 and O6: 2
31 Number used as ROM: 0
32 Number used as Memory: 0 out of 1,440 0%
33
34 Slice Logic Distribution:
35 Number of occupied Slices: 11 out of 1,430 1%
36 Number of MUXCYs used: 0 out of 2,860 0%
37 Number of LUT Flip Flop pairs used: 37
38 Number with an unused Flip Flop: 3 out of 37 8%
39 Number with an unused LUT: 32 out of 37 86%
40 Number of fully used LUT-FF pairs: 2 out of 37 5%
41 Number of unique control sets: 4
42 Number of slice register sites lost
43 to control set restrictions: 14 out of 11,440 1%
44
45 A LUT Flip Flop pair for this architecture represents one LUT paired with
46 one Flip Flop within a slice. A control set is a unique combination of
47 clock, reset, set, and enable signals for a registered element.
48 The Slice Logic Distribution report is not meaningful if the design is
49 over-mapped for a non-slice resource or if Placement fails.
50
51 IO Utilization:
52 Number of bonded IOBs: 33 out of 102 32%
53
54 Specific Feature Utilization:
55 Number of RAMB16BWERs: 1 out of 32 3%
56 Number of RAMB8BWERs: 0 out of 64 0%
57 Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
58 Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
59 Number of BUFG/BUFGMUXs: 1 out of 16 6%
60 Number used as BUFGs: 1
61 Number used as BUFGMUX: 0
62 Number of DCM/DCM_CLKGENs: 0 out of 4 0%
63 Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
64 Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
65 Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
66 Number of BSCANs: 0 out of 4 0%
67 Number of BUFHs: 0 out of 128 0%
68 Number of BUFPLLs: 0 out of 8 0%
69 Number of BUFPLL_MCBs: 0 out of 4 0%
70 Number of DSP48A1s: 0 out of 16 0%
71 Number of ICAPs: 0 out of 1 0%
72 Number of MCBs: 0 out of 2 0%
73 Number of PCILOGICSEs: 0 out of 2 0%
74 Number of PLL_ADVs: 0 out of 2 0%
75 Number of PMVs: 0 out of 1 0%
76 Number of STARTUPs: 0 out of 1 0%
77 Number of SUSPEND_SYNCs: 0 out of 1 0%
78
79 Average Fanout of Non-Clock Nets: 1.60
80
81 Peak Memory Usage: 330 MB
82 Total REAL time to MAP completion: 13 secs
83 Total CPU time to MAP completion: 8 secs
84
85 Table of Contents
86 -----------------
87 Section 1 - Errors
88 Section 2 - Warnings
89 Section 3 - Informational
90 Section 4 - Removed Logic Summary
91 Section 5 - Removed Logic
92 Section 6 - IOB Properties
93 Section 7 - RPMs
94 Section 8 - Guide Report
95 Section 9 - Area Group and Partition Summary
96 Section 10 - Timing Report
97 Section 11 - Configuration String Information
98 Section 12 - Control Set Information
99 Section 13 - Utilization by Hierarchy
100
101 Section 1 - Errors
102 ------------------
103
104 Section 2 - Warnings
105 --------------------
106
107 Section 3 - Informational
108 -------------------------
109 INFO:MapLib:562 - No environment variables are currently set.
110 INFO:LIT:244 - All of the single ended outputs in this design are using slew
111 rate limited output drivers. The delay on speed critical single ended outputs
112 can be dramatically reduced by designating them as fast outputs.
113 INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
114 0.000 to 85.000 Celsius)
115 INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
116 1.260 Volts)
117 INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
118 (.mrp).
119 INFO:Pack:1650 - Map created a placed design.
120
121 Section 4 - Removed Logic Summary
122 ---------------------------------
123 2 block(s) optimized away
124
125 Section 5 - Removed Logic
126 -------------------------
127
128 Optimized Block(s):
129 TYPE BLOCK
130 GND XST_GND
131 VCC XST_VCC
132
133 To enable printing of redundant blocks removed and signals merged, set the
134 detailed map report option and rerun map.
135
136 Section 6 - IOB Properties
137 --------------------------
138
139 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
140 | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
141 | | | | | Term | Strength | Rate | | | Delay |
142 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
143 | ADDR_RAM<0> | IOB | INPUT | LVCMOS25 | | | | | | |
144 | ADDR_RAM<1> | IOB | INPUT | LVCMOS25 | | | | | | |
145 | ADDR_RAM<2> | IOB | INPUT | LVCMOS25 | | | | | | |
146 | ADDR_RAM<3> | IOB | INPUT | LVCMOS25 | | | | | | |
147 | ADDR_RAM<4> | IOB | INPUT | LVCMOS25 | | | | | | |
148 | ADDR_RAM<5> | IOB | INPUT | LVCMOS25 | | | | | | |
149 | ADDR_RAM<6> | IOB | INPUT | LVCMOS25 | | | | | | |
150 | ADDR_RAM<7> | IOB | INPUT | LVCMOS25 | | | | | | |
151 | ADDR_RAM<8> | IOB | INPUT | LVCMOS25 | | | | | | |
152 | ADDR_RAM<9> | IOB | INPUT | LVCMOS25 | | | | | | |
153 | CS_2 | IOB | INPUT | LVCMOS25 | | | | | | |
154 | CS_1_bar | IOB | INPUT | LVCMOS25 | | | | | | |
155 | DATA_RAM<0> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
156 | DATA_RAM<1> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
157 | DATA_RAM<2> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
158 | DATA_RAM<3> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
159 | DATA_RAM<4> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
160 | DATA_RAM<5> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
161 | DATA_RAM<6> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
162 | DATA_RAM<7> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
163 | DATA_RAM<8> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
164 | DATA_RAM<9> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
165 | DATA_RAM<10> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
166 | DATA_RAM<11> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
167 | DATA_RAM<12> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
168 | DATA_RAM<13> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
169 | DATA_RAM<14> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
170 | DATA_RAM<15> | IOB | BIDIR | LVCMOS25 | | 12 | SLOW | | | |
171 | LB_bar | IOB | INPUT | LVCMOS25 | | | | | | |
172 | OE_bar | IOB | INPUT | LVCMOS25 | | | | | | |
173 | UB_bar | IOB | INPUT | LVCMOS25 | | | | | | |
174 | WEA_bar | IOB | INPUT | LVCMOS25 | | | | | | |
175 | clk_main | IOB | INPUT | LVCMOS25 | | | | | | |
176 +---------------------------------------------------------------------------------------------------------------------------------------------------------+
177
178 Section 7 - RPMs
179 ----------------
180
181 Section 8 - Guide Report
182 ------------------------
183 Guide not run on this design.
184
185 Section 9 - Area Group and Partition Summary
186 --------------------------------------------
187
188 Partition Implementation Status
189 -------------------------------
190
191 No Partitions were found in this design.
192
193 -------------------------------
194
195 Area Group Information
196 ----------------------
197
198 No area groups were found in this design.
199
200 ----------------------
201
202 Section 10 - Timing Report
203 --------------------------
204 A logic-level (pre-route) timing report can be generated by using Xilinx static
205 timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
206 mapped NCD and PCF files. Please note that this timing report will be generated
207 using estimated delay information. For accurate numbers, please generate a
208 timing report with the post Place and Route NCD file.
209
210 For more information about the Timing Analyzer, consult the Xilinx Timing
211 Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
212 Command Line Tools User Guide "TRACE" chapter.
213
214 Section 11 - Configuration String Details
215 -----------------------------------------
216 Use the "-detail" map option to print out Configuration Strings
217
218 Section 12 - Control Set Information
219 ------------------------------------
220 Use the "-detail" map option to print out Control Set Information.
221
222 Section 13 - Utilization by Hierarchy
223 -------------------------------------
224 Use the "-detail" map option to print out the Utilization by Hierarchy section.
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1 XILINX-XDB 0.1 STUB 0.1 ASCII
2 XILINX-XDM V1.6
3 ###4848:XlxV32DM 3fff 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1 XILINX-XDB 0.1 STUB 0.1 ASCII
2 XILINX-XDM V1.6e
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1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
2 <document OS="nt64" product="ISE" version="14.7">
3
4 <!--The data in this file is primarily intended for consumption by Xilinx tools.
5 The structure and the elements are likely to change over the next few releases.
6 This means code written to parse this file will need to be revisited each subsequent release.-->
7
8 <application stringID="Map" timeStamp="Mon Dec 14 11:38:58 2015">
9 <section stringID="User_Env">
10 <table stringID="User_EnvVar">
11 <column stringID="variable"/>
12 <column stringID="value"/>
13 <row stringID="row" value="0">
14 <item stringID="variable" value="Path"/>
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27 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
28 </row>
29 <row stringID="row" value="4">
30 <item stringID="variable" value="XILINX_EDK"/>
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36 </row>
37 </table>
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40 <item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
41 </item>
42 <item stringID="User_EnvHost" value="Lenovo-PC"/>
43 <table stringID="User_EnvCpu">
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45 <column stringID="speed"/>
46 <row stringID="row" value="0">
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48 <item stringID="speed" value="2394 MHz"/>
49 </row>
50 </table>
51 </section>
52 <section stringID="MAP_OPTION_SUMMARY">
53 <item DEFAULT="high" label="-ol" stringID="MAP_EFFORTLEVEL" value="high"/>
54 <item DEFAULT="0" label="-xt" stringID="MAP_EXTRA_COST_TABLE" value="0"/>
55 <item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
56 <item DEFAULT="OFF" stringID="MAP_LUTCOMPRESSIONMODE" value="OFF"/>
57 <item DEFAULT="0" label="-t" stringID="MAP_PLACERCOSTTABLE" value="1"/>
58 <item DEFAULT="4" label="-r" stringID="MAP_REGORDERING" value="4"/>
59 <item DEFAULT="FALSE" stringID="MAP_REPLICATELUTS" value="TRUE"/>
60 <item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
61 <item DEFAULT="off" label="-lc" stringID="MAP_LUT_COMBINING" value="off"/>
62 <item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="BloqueRAM_int_map.ncd"/>
63 <item DEFAULT="false" label="-w" stringID="MAP_OVERWRITE_OUTPUT" value="true"/>
64 <item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
65 <item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc6slx9-tqg144-3"/>
66 </section>
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77 <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
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86 <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
87 <item dataType="int" stringID="MAP_NUM_SRL_O5ONLY" value="0"/>
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89 <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
90 <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
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94 <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
95 <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
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98 <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
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102 <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBM" value="0"/>
103 <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBS" value="0"/>
104 <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
105 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
106 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_IPAD" value="0"/>
107 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_BONDED_OPAD" value="0"/>
108 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
109 <section stringID="MAP_DESIGN_INFORMATION">
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111 <item stringID="MAP_DEVICE" value="xc6slx9"/>
112 <item stringID="MAP_ARCHITECTURE" value="spartan6"/>
113 <item stringID="MAP_PACKAGE" value="tqg144"/>
114 <item stringID="MAP_SPEED" value="-3"/>
115 </section>
116 <section stringID="MAP_DESIGN_SUMMARY">
117 <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
118 <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
119 <item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
120 <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="338216"/>
121 <item stringID="MAP_TOTAL_REAL_TIME" value="13 secs "/>
122 <item stringID="MAP_TOTAL_CPU_TIME" value="8 secs "/>
123 </section>
124 <section stringID="MAP_SLICE_REPORTING">
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126 <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="34"/>
127 <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="0"/>
128 <item dataType="int" stringID="MAP_NUM_SLICE_LATCHTHRU" value="0"/>
129 <item dataType="int" stringID="MAP_NUM_SLICE_LATCHLOGIC" value="0"/>
130 </item>
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133 <item dataType="int" label="Number using O6 output only" stringID="MAP_NUM_LOGIC_O6ONLY" value="3"/>
134 <item dataType="int" label="Number using O5 and O6" stringID="MAP_NUM_LOGIC_O5ANDO6" value="2"/>
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136 <item dataType="int" stringID="MAP_NUM_ROM_O6ONLY" value="0"/>
137 <item dataType="int" stringID="MAP_NUM_ROM_O5ANDO6" value="0"/>
138 <item dataType="int" stringID="MAP_NUM_DPRAM_O5ONLY" value="0"/>
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143 <item dataType="int" stringID="MAP_NUM_SPRAM_O5ANDO6" value="0"/>
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146 <item dataType="int" stringID="MAP_NUM_SRL_O5ANDO6" value="0"/>
147 <item dataType="int" stringID="MAP_NUM_LUT_RT_EXO6" value="0"/>
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150 <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_FLOP" value="0"/>
151 <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_CARRY4" value="0"/>
152 <item dataType="int" stringID="MAP_NUM_LUT_RT_DRIVES_OTHERS" value="0"/>
153 </item>
154 <item AVAILABLE="1430" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="11">
155 <item AVAILABLE="355" dataType="int" stringID="MAP_NUM_SLICEL" value="0"/>
156 <item AVAILABLE="360" dataType="int" stringID="MAP_NUM_SLICEM" value="0"/>
157 <item AVAILABLE="715" dataType="int" stringID="MAP_NUM_SLICEX" value="11"/>
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159 <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="MAP_OCCUPIED_LUT_AND_FF" value="37">
160 <item dataType="int" stringID="MAP_OCCUPIED_LUT_ONLY" value="3"/>
161 <item dataType="int" label="Number with an unused LUT" stringID="MAP_OCCUPIED_FF_ONLY" value="32"/>
162 <item dataType="int" label="Number of fully used LUT-FF pairs" stringID="MAP_OCCUPIED_FF_AND_LUT" value="2"/>
163 </item>
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167 <item AVAILABLE="98" dataType="int" stringID="MAP_AGG_UNBONDED_IO" value="0"/>
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169 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IOB_LATCH" value="0"/>
170 <item AVAILABLE="49" dataType="int" stringID="MAP_NUM_IOBM" value="0"/>
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173 <item AVAILABLE="51" dataType="int" stringID="MAP_NUM_BONDED_IOBS" value="0"/>
174 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_IPAD" value="0"/>
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177 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_OPAD" value="0"/>
178 </section>
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180 <section stringID="MAP_RAM_FIFO_DATA">
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182 <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
183 </section>
184 <section stringID="MAP_IP_DATA">
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186 <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
187 <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
188 <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
189 <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
190 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
191 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
192 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
193 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
194 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
195 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
196 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
197 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
198 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
199 </section>
200 <section stringID="MAP_BUFG_DATA">
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202 <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
203 <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
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207 <item dataType="int" stringID="MAP_RPMS" value="0"/>
208 </section>
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212 <column stringID="Type"/>
213 <column stringID="Direction"/>
214 <column label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD"/>
215 <column label="Diff&#xA;Term" stringID="DIFF_TERM"/>
216 <column label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH"/>
217 <column label="Slew&#xA;Rate" stringID="SLEW_RATE"/>
218 <column label="Reg&#xA;(s)" stringID="REGS"/>
219 <column stringID="Resistor"/>
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226 </row>
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244 </row>
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250 </row>
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256 </row>
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262 </row>
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268 </row>
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271 <item stringID="Type" value="IOB"/>
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274 </row>
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277 <item stringID="Type" value="IOB"/>
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279 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
280 </row>
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283 <item stringID="Type" value="IOB"/>
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286 </row>
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292 </row>
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295 <item stringID="Type" value="IOB"/>
296 <item stringID="Direction" value="BIDIR"/>
297 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
298 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
299 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
300 </row>
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302 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DATA_RAM&lt;1>"/>
303 <item stringID="Type" value="IOB"/>
304 <item stringID="Direction" value="BIDIR"/>
305 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
306 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
307 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
308 </row>
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311 <item stringID="Type" value="IOB"/>
312 <item stringID="Direction" value="BIDIR"/>
313 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
314 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
315 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
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318 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DATA_RAM&lt;3>"/>
319 <item stringID="Type" value="IOB"/>
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321 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
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323 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
324 </row>
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327 <item stringID="Type" value="IOB"/>
328 <item stringID="Direction" value="BIDIR"/>
329 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
330 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
331 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
332 </row>
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335 <item stringID="Type" value="IOB"/>
336 <item stringID="Direction" value="BIDIR"/>
337 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
338 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
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340 </row>
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358 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DATA_RAM&lt;8>"/>
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361 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
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391 <item stringID="Type" value="IOB"/>
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407 <item stringID="Type" value="IOB"/>
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409 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
410 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
411 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
412 </row>
413 <row stringID="row" value="28">
414 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="DATA_RAM&lt;15>"/>
415 <item stringID="Type" value="IOB"/>
416 <item stringID="Direction" value="BIDIR"/>
417 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
418 <item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
419 <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
420 </row>
421 <row stringID="row" value="29">
422 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="LB_bar"/>
423 <item stringID="Type" value="IOB"/>
424 <item stringID="Direction" value="INPUT"/>
425 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
426 </row>
427 <row stringID="row" value="30">
428 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="OE_bar"/>
429 <item stringID="Type" value="IOB"/>
430 <item stringID="Direction" value="INPUT"/>
431 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
432 </row>
433 <row stringID="row" value="31">
434 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="UB_bar"/>
435 <item stringID="Type" value="IOB"/>
436 <item stringID="Direction" value="INPUT"/>
437 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
438 </row>
439 <row stringID="row" value="32">
440 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="WEA_bar"/>
441 <item stringID="Type" value="IOB"/>
442 <item stringID="Direction" value="INPUT"/>
443 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
444 </row>
445 <row stringID="row" value="33">
446 <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="clk_main"/>
447 <item stringID="Type" value="IOB"/>
448 <item stringID="Direction" value="INPUT"/>
449 <item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
450 </row>
451 </table>
452 </section>
453 <section stringID="MAP_RPM_MACROS">
454 <section stringID="MAP_SHAPE_SECTION">
455 <item dataType="int" stringID="MAP_NUM_SHAPE" value="0"/>
456 </section>
457 </section>
458 <section stringID="MAP_GUIDE_REPORT"/>
459 <section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
460 <section stringID="MAP_TIMING_REPORT"/>
461 <section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
462 <section stringID="MAP_GENERAL_CONFIG_DATA"/>
463 <section stringID="MAP_CONTROL_SET_INFORMATION">
464 <item dataType="int" label="Number of unique control sets" stringID="MAP_NUM_CONTROL_SETS" value="4"/>
465 <tree stringID="MAP_CONTROL_SET_HIERARCHY">
466 <property stringID="MAP_CLOCK_SIGNAL"/>
467 <property stringID="MAP_RESET_SIGNAL"/>
468 <property stringID="MAP_SET_SIGNAL"/>
469 <property stringID="MAP_ENABLE_SIGNAL"/>
470 <property label="Slice&#xA;Load Count" stringID="MAP_SLICE_LOAD_COUNT"/>
471 <property label="Bel&#xA;Load Count" stringID="MAP_BEL_LOAD_COUNT"/>
472 </tree>
473 </section>
474 </task>
475 <section stringID="MAP_RAM_FIFO_DATA">
476 <item AVAILABLE="32" dataType="int" stringID="MAP_NUM_RAMB16BWER" value="1"/>
477 <item AVAILABLE="64" dataType="int" stringID="MAP_NUM_RAMB8BWER" value="0"/>
478 </section>
479 <section stringID="MAP_IP_DATA">
480 <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BSCAN" value="0"/>
481 <item AVAILABLE="128" dataType="int" stringID="MAP_NUM_BUFH" value="0"/>
482 <item AVAILABLE="8" dataType="int" stringID="MAP_NUM_BUFPLL" value="0"/>
483 <item AVAILABLE="4" dataType="int" stringID="MAP_NUM_BUFPLL_MCB" value="0"/>
484 <item AVAILABLE="16" dataType="int" stringID="MAP_NUM_DSP48A1" value="0"/>
485 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_GTPA1_DUAL" value="0"/>
486 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_ICAP" value="0"/>
487 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_MCB" value="0"/>
488 <item AVAILABLE="0" dataType="int" stringID="MAP_NUM_PCIE_A1" value="0"/>
489 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PCILOGICSE" value="0"/>
490 <item AVAILABLE="2" dataType="int" stringID="MAP_NUM_PLL_ADV" value="0"/>
491 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_PMV" value="0"/>
492 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_STARTUP" value="0"/>
493 <item AVAILABLE="1" dataType="int" stringID="MAP_NUM_SUSPEND_SYNC" value="0"/>
494 </section>
495 <section stringID="MAP_BUFG_DATA">
496 <item dataType="int" label="Number used as BUFGs" stringID="MAP_NUM_BUFG" value="1"/>
497 <item dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="0"/>
498 <item dataType="int" stringID="MAP_AVAILABLE" value="16"/>
499 <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
500 <item dataType="int" stringID="MAP_RPMS" value="0"/>
501 </section>
502 </application>
503
504 </document>
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1 <?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
2 <document OS="nt64" product="ISE" version="14.7">
3
4 <!--The data in this file is primarily intended for consumption by Xilinx tools.
5 The structure and the elements are likely to change over the next few releases.
6 This means code written to parse this file will need to be revisited each subsequent release.-->
7
8 <application stringID="NgdBuild" timeStamp="Mon Dec 14 11:38:38 2015">
9 <section stringID="User_Env">
10 <table stringID="User_EnvVar">
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12 <column stringID="value"/>
13 <row stringID="row" value="0">
14 <item stringID="variable" value="Path"/>
15 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;C:\Xilinx\14.7\ISE_DS\common\bin\nt64;C:\Xilinx\14.7\ISE_DS\common\lib\nt64;C:\WinAVR\bin;C:\WinAVR\utils\bin;C:\Program Files\TortoiseSVN\bin;C:\Program Files\doxygen\bin;C:\Program Files (x86)\MiKTeX 2.9\miktex\bin\;C:\Program Files (x86)\Microchip\xc8\v1.35\bin;C:\Program Files (x86)\Microchip\xc16\v1.24\bin;c:\MinGW\bin;c:\MinGW\MSYS\1.0\bin"/>
16 </row>
17 <row stringID="row" value="1">
18 <item stringID="variable" value="PATHEXT"/>
19 <item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC;.PY;.PYW"/>
20 </row>
21 <row stringID="row" value="2">
22 <item stringID="variable" value="XILINX"/>
23 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE\"/>
24 </row>
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26 <item stringID="variable" value="XILINX_DSP"/>
27 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\ISE"/>
28 </row>
29 <row stringID="row" value="4">
30 <item stringID="variable" value="XILINX_EDK"/>
31 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\EDK"/>
32 </row>
33 <row stringID="row" value="5">
34 <item stringID="variable" value="XILINX_PLANAHEAD"/>
35 <item stringID="value" value="C:\Xilinx\14.7\ISE_DS\PlanAhead"/>
36 </row>
37 </table>
38 <item stringID="User_EnvOs" value="OS Information">
39 <item stringID="User_EnvOsname" value="Microsoft , 64-bit"/>
40 <item stringID="User_EnvOsrelease" value="major release (build 9200)"/>
41 </item>
42 <item stringID="User_EnvHost" value="Lenovo-PC"/>
43 <table stringID="User_EnvCpu">
44 <column stringID="arch"/>
45 <column stringID="speed"/>
46 <row stringID="row" value="0">
47 <item stringID="arch" value="Intel(R) Core(TM) i5-4210U CPU @ 1.70GHz"/>
48 <item stringID="speed" value="2394 MHz"/>
49 </row>
50 </table>
51 </section>
52 <task stringID="NGDBUILD_OPTION_SUMMARY">
53 <section stringID="NGDBUILD_OPTION_SUMMARY">
54 <item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
55 <item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
56 <item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc6slx9-tqg144-3"/>
57 </section>
58 </task>
59 <task stringID="NGDBUILD_REPORT">
60 <section stringID="NGDBUILD_DESIGN_SUMMARY">
61 <item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
62 <item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
63 <item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
64 <item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
65 <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
66 </section>
67 <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
68 <item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
69 <item dataType="int" stringID="NGDBUILD_NUM_FDC" value="18"/>
70 <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="16"/>
71 <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
72 <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="16"/>
73 <item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
74 <item dataType="int" stringID="NGDBUILD_NUM_IOBUF" value="16"/>
75 <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
76 <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
77 <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
78 <item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="1"/>
79 <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
80 </section>
81 <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
82 <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
83 <item dataType="int" stringID="NGDBUILD_NUM_FDC" value="18"/>
84 <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="16"/>
85 <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
86 <item dataType="int" stringID="NGDBUILD_NUM_IBUF" value="32"/>
87 <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
88 <item dataType="int" stringID="NGDBUILD_NUM_INV" value="3"/>
89 <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
90 <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="2"/>
91 <item dataType="int" stringID="NGDBUILD_NUM_LUT5" value="2"/>
92 <item dataType="int" stringID="NGDBUILD_NUM_OBUFT" value="16"/>
93 <item dataType="int" stringID="NGDBUILD_NUM_RAMB16BWER" value="1"/>
94 <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
95 </section>
96 <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
97 <section stringID="NGDBUILD_CORE_INSTANCES"/>
98 </section>
99 </task>
100 </application>
101
102 </document>
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The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
Show file before | Show file after | Hide comments
1 NO CONTENT: new file 10644
The requested commit or file is too big and content was truncated. Show full diff
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1 NO CONTENT: new file 10644
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1 NO CONTENT: new file 10644
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