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Se añade primera versión del módulo del módulo de adquisición. Revisar las notas de versión. Posiblemente tenga bugs de sincronización en casos de PPS cercal LOCK.
lgonzales -
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1 
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2 Microsoft Visual Studio Solution File, Format Version 12.00
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1 /*
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2 * ADC_7176_2.c
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3 *
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4 * Created: 23/11/15 14:01:02
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5 * Author: Francisco
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6 */
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7
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8 /*!
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9 * \fn test_adc
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10 * \brief Lectura de ID del adc
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11 *
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12 * Lectura esperada: 0x0C94
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13 *
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14 * Esta funci�n tiene como fin probar la comunicaci�n on el ADC
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15 *
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16 #define ADC_WENbar_bm (1<<7)
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17 #define ADC_RWbar_bm (1<<6)
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18 #define ADC_ADDR_READ_ID 0x07
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19 * \
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20 */
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21
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22 #define F_CPU 32000000UL
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23 #include <avr/io.h>
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24 #include "ADC_7176_2.h"
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25
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26 inline uint16_t test_adc(void){
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27 uint16_t aux;
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28 PORTSPI.OUTCLR = SPI_SS_bm;
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29 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
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30 aux = adcport_tranceiv(0);
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31 aux = (aux << 8) | adcport_tranceiv(0);
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32 PORTSPI.OUTSET = SPI_SS_bm;
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33 return aux;
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34 }
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35
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36 inline void test_adc_2(uint8_t* dato){
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37 PORTSPI.OUTCLR = SPI_SS_bm;
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38 adcport_read_data(dato,ADC_DATASZ);
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39 PORTSPI.OUTSET = SPI_SS_bm;
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40 }
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41 /*!
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42 * \fn adcport_tranceiv
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43 * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y
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44 * el microcontrolador.
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45 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
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46 * transmision genera clock en el pin "sclk"
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47 * \param El dato a transmitir
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48 * \return El dato leido del ADC
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49 */
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50 inline uint8_t adcport_tranceiv(uint8_t data){
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51 //
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52 SPIC.DATA = data;
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53
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54 //Wait until transmission complete
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55 while( !(SPIC.STATUS & SPI_IF_bm));
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56
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57 // Return received data
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58
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59 return SPIC.DATA;
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60 }
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61
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62 /*!
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63 * \fn adcport_readdata
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64 * \brief Realiza la lectura de datos en modo de conversi�n continua
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65 * el microcontrolador.
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66 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
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67 * transmision genera clock en el pin "sclk"
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68 * \param La direcci�n del puntero a dato
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69 * \return Ninguno s�lo se llena el puntero al dato
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70 */
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71 inline void adcport_read_data(uint8_t* dato,int j)
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72 {
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73
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74 //Env�o del comando de lectura de datos 0x44
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75 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
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76
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77 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
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78
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79 // Save received data
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80 for(int i=0; i<j ; i++)
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81 dato[j-i-1] = adcport_tranceiv(0);
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82 }
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83
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84 void config_adc(void)
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85 {
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86 adcport_write_filtcon0();
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87 //adcport_write_interfmode();
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88
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89 }
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90
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91 void adcport_write_filtcon0(void)
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92 {
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93 adcport_tranceiv((ADC_FILTCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
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94 adcport_tranceiv(0);
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95 adcport_tranceiv((0b00<<ADC_FILT0_ORDER0_bp)|(0b01010<<ADC_FILT0_ODR0_bp));
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96 }
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97
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98 void adcport_write_interfmode(void)
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99 {
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100 adcport_tranceiv((ADC_INTERFMODE) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
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101 adcport_tranceiv(0);
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102 adcport_tranceiv((1<<ADC_CONTREAD_bp)|(1<<ADC_WL16_bp));
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103 } No newline at end of file
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1 /*
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2 * ADC_7176_2.h
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3 *
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4 * Created: 23/11/15 13:59:46
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5 * Author: Francisco
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6 */
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7
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8
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9 #ifndef ADC_7176_2_H_
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10 #define ADC_7176_2_H_
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11
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12 #define F_CPU 32000000UL
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13 #include <avr/io.h>
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14 #include "Ports.h"
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15 #include "commSPI_ADC.h"
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16
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17 //ID esperada
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18 //tama�o 16 bits
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19 //Valor 0x0C94
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20 #define ADC_ID 0x0C94
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21 #define ADC_RD 0x04
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22 #define ADC_FILTCON0 0x28
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23 #define ADC_INTERFMODE 0x02
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24 #define ADC_DATASZ 3
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25
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26 //Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n
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27 #define ADC_WENbar_bm (1<<7)
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28 #define ADC_RWbar_bm (1<<6)
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29 #define ADC_ADDR_READ_ID (0x07)
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30 #define ADC_FILT0_ORDER0_bp 5
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31 #define ADC_FILT0_ODR0_bp 0
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32 #define ADC_CONTREAD_bp 7
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33 #define ADC_WL16_bp 0
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34
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35 uint8_t adcport_tranceiv(uint8_t data);
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36 void adcport_read_data(uint8_t* dato,int j);
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37
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38 void adcport_write_filtcon0(void);
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39 void adcport_write_interfmode(void);
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40
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41 uint16_t test_adc(void);
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42 void test_adc_2(uint8_t* dato);
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43 void config_adc(void);
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44
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45 #endif /* ADC_7176_2_H_ */ No newline at end of file
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1 NO CONTENT: new file 10644
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1
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2 ADCSPI_ver01.elf: file format elf32-avr
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3
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4 Sections:
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5 Idx Name Size VMA LMA File off Algn
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6 0 .text 0000055e 00000000 00000000 00000054 2**1
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7 CONTENTS, ALLOC, LOAD, READONLY, CODE
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8 1 .data 00000000 00802000 00802000 000005b2 2**0
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9 CONTENTS, ALLOC, LOAD, DATA
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10 2 .comment 00000030 00000000 00000000 000005b2 2**0
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11 CONTENTS, READONLY
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12 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 000005e4 2**2
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13 CONTENTS, READONLY
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14 4 .debug_aranges 00000138 00000000 00000000 00000624 2**0
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15 CONTENTS, READONLY, DEBUGGING
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16 5 .debug_info 000014b5 00000000 00000000 0000075c 2**0
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17 CONTENTS, READONLY, DEBUGGING
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18 6 .debug_abbrev 00000644 00000000 00000000 00001c11 2**0
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19 CONTENTS, READONLY, DEBUGGING
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20 7 .debug_line 00000827 00000000 00000000 00002255 2**0
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21 CONTENTS, READONLY, DEBUGGING
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22 8 .debug_frame 00000278 00000000 00000000 00002a7c 2**2
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23 CONTENTS, READONLY, DEBUGGING
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24 9 .debug_str 000007d6 00000000 00000000 00002cf4 2**0
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25 CONTENTS, READONLY, DEBUGGING
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26 10 .debug_loc 000003d0 00000000 00000000 000034ca 2**0
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27 CONTENTS, READONLY, DEBUGGING
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28 11 .debug_ranges 000000d8 00000000 00000000 0000389a 2**0
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29 CONTENTS, READONLY, DEBUGGING
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30
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31 Disassembly of section .text:
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32
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33 00000000 <__vectors>:
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34 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end>
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35 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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36 8: 0c 94 f1 01 jmp 0x3e2 ; 0x3e2 <__vector_2>
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37 c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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38 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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39 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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40 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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41 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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42 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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43 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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44 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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47 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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48 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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49 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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50 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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55 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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56 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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57 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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60 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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61 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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62 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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63 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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64 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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65 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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66 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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67 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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68 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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69 8c: 0c 94 d2 01 jmp 0x3a4 ; 0x3a4 <__vector_35>
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70 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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71 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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72 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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73 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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74 a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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75 a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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76 a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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77 ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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78 b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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79 b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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80 b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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81 bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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82 c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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83 c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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84 c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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85 cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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86 d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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87 d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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88 d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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89 dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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90 e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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92 e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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93 ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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94 f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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95 f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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96 f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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97 fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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98 100: 0c 94 ad 01 jmp 0x35a ; 0x35a <__vector_64>
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99 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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100 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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101 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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102 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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103 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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104 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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105 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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106 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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107 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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108 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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109 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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110 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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111 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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112 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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113 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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114 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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115 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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116 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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117 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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118 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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119 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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120 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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121 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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122 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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123 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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124 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
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125
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126 0000016c <__ctors_end>:
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127 16c: 11 24 eor r1, r1
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128 16e: 1f be out 0x3f, r1 ; 63
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129 170: cf ef ldi r28, 0xFF ; 255
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130 172: cd bf out 0x3d, r28 ; 61
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131 174: df e2 ldi r29, 0x2F ; 47
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132 176: de bf out 0x3e, r29 ; 62
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133 178: 0e 94 95 01 call 0x32a ; 0x32a <main>
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134 17c: 0c 94 ad 02 jmp 0x55a ; 0x55a <_exit>
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135
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136 00000180 <__bad_interrupt>:
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137 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
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138
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139 00000184 <test_adc>:
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140 #include <avr/io.h>
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141 #include "ADC_7176_2.h"
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142
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143 inline uint16_t test_adc(void){
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144 uint16_t aux;
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145 PORTSPI.OUTCLR = SPI_SS_bm;
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146 184: 80 e1 ldi r24, 0x10 ; 16
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147 186: 80 93 46 06 sts 0x0646, r24
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148 * \param El dato a transmitir
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149 * \return El dato leido del ADC
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150 */
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151 inline uint8_t adcport_tranceiv(uint8_t data){
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152 //
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153 SPIC.DATA = data;
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154 18a: 87 e4 ldi r24, 0x47 ; 71
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155 18c: 80 93 c3 08 sts 0x08C3, r24
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156
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157 //Wait until transmission complete
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158 while( !(SPIC.STATUS & SPI_IF_bm));
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159 190: e0 ec ldi r30, 0xC0 ; 192
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160 192: f8 e0 ldi r31, 0x08 ; 8
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161 194: 82 81 ldd r24, Z+2 ; 0x02
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162 196: 88 23 and r24, r24
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163 198: ec f7 brge .-6 ; 0x194 <test_adc+0x10>
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164
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165 // Return received data
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166
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167 return SPIC.DATA;
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168 19a: e0 ec ldi r30, 0xC0 ; 192
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169 19c: f8 e0 ldi r31, 0x08 ; 8
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170 19e: 83 81 ldd r24, Z+3 ; 0x03
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171 * \param El dato a transmitir
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172 * \return El dato leido del ADC
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173 */
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174 inline uint8_t adcport_tranceiv(uint8_t data){
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175 //
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176 SPIC.DATA = data;
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177 1a0: 13 82 std Z+3, r1 ; 0x03
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178
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179 //Wait until transmission complete
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180 while( !(SPIC.STATUS & SPI_IF_bm));
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181 1a2: 82 81 ldd r24, Z+2 ; 0x02
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182 1a4: 88 23 and r24, r24
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183 1a6: ec f7 brge .-6 ; 0x1a2 <test_adc+0x1e>
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184
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185 // Return received data
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186
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187 return SPIC.DATA;
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188 1a8: e0 ec ldi r30, 0xC0 ; 192
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189 1aa: f8 e0 ldi r31, 0x08 ; 8
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190 1ac: 23 81 ldd r18, Z+3 ; 0x03
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191
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192 inline uint16_t test_adc(void){
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193 uint16_t aux;
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194 PORTSPI.OUTCLR = SPI_SS_bm;
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195 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
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196 aux = adcport_tranceiv(0);
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197 1ae: 30 e0 ldi r19, 0x00 ; 0
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198 aux = (aux << 8) | adcport_tranceiv(0);
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199 1b0: 32 2f mov r19, r18
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200 1b2: 22 27 eor r18, r18
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201 * \param El dato a transmitir
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202 * \return El dato leido del ADC
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203 */
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204 inline uint8_t adcport_tranceiv(uint8_t data){
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205 //
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206 SPIC.DATA = data;
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207 1b4: 13 82 std Z+3, r1 ; 0x03
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208
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209 //Wait until transmission complete
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210 while( !(SPIC.STATUS & SPI_IF_bm));
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211 1b6: 92 81 ldd r25, Z+2 ; 0x02
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212 1b8: 99 23 and r25, r25
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213 1ba: ec f7 brge .-6 ; 0x1b6 <test_adc+0x32>
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214
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215 // Return received data
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216
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217 return SPIC.DATA;
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218 1bc: 80 91 c3 08 lds r24, 0x08C3
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219 uint16_t aux;
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220 PORTSPI.OUTCLR = SPI_SS_bm;
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221 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
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222 aux = adcport_tranceiv(0);
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223 aux = (aux << 8) | adcport_tranceiv(0);
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224 PORTSPI.OUTSET = SPI_SS_bm;
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225 1c0: 90 e1 ldi r25, 0x10 ; 16
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226 1c2: 90 93 45 06 sts 0x0645, r25
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227 return aux;
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228 }
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229 1c6: a9 01 movw r20, r18
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230 1c8: 48 2b or r20, r24
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231 1ca: ca 01 movw r24, r20
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232 1cc: 08 95 ret
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233
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234 000001ce <adcport_read_data>:
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235 * transmision genera clock en el pin "sclk"
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236 * \param La direcci�n del puntero a dato
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237 * \return Ninguno s�lo se llena el puntero al dato
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238 */
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239 inline void adcport_read_data(uint8_t* dato,int j)
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240 {
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241 1ce: 9c 01 movw r18, r24
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242 * \param El dato a transmitir
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243 * \return El dato leido del ADC
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244 */
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245 inline uint8_t adcport_tranceiv(uint8_t data){
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246 //
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247 SPIC.DATA = data;
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248 1d0: 84 e4 ldi r24, 0x44 ; 68
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249 1d2: 80 93 c3 08 sts 0x08C3, r24
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250
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251 //Wait until transmission complete
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252 while( !(SPIC.STATUS & SPI_IF_bm));
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253 1d6: e0 ec ldi r30, 0xC0 ; 192
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254 1d8: f8 e0 ldi r31, 0x08 ; 8
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255 1da: 92 81 ldd r25, Z+2 ; 0x02
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256 1dc: 99 23 and r25, r25
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257 1de: ec f7 brge .-6 ; 0x1da <adcport_read_data+0xc>
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258
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259 // Return received data
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260
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261 return SPIC.DATA;
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262 1e0: 80 91 c3 08 lds r24, 0x08C3
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263 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
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264
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265 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
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266
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267 // Save received data
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268 for(int i=0; i<j ; i++)
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269 1e4: 16 16 cp r1, r22
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270 1e6: 17 06 cpc r1, r23
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271 1e8: 74 f4 brge .+28 ; 0x206 <adcport_read_data+0x38>
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272 1ea: d9 01 movw r26, r18
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273 1ec: a6 0f add r26, r22
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274 1ee: b7 1f adc r27, r23
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275 * \param El dato a transmitir
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276 * \return El dato leido del ADC
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277 */
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278 inline uint8_t adcport_tranceiv(uint8_t data){
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279 //
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280 SPIC.DATA = data;
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281 1f0: e0 ec ldi r30, 0xC0 ; 192
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282 1f2: f8 e0 ldi r31, 0x08 ; 8
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283 1f4: 13 82 std Z+3, r1 ; 0x03
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284
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285 //Wait until transmission complete
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286 while( !(SPIC.STATUS & SPI_IF_bm));
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287 1f6: 92 81 ldd r25, Z+2 ; 0x02
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288 1f8: 99 23 and r25, r25
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289 1fa: ec f7 brge .-6 ; 0x1f6 <adcport_read_data+0x28>
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290
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291 // Return received data
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292
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293 return SPIC.DATA;
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294 1fc: 93 81 ldd r25, Z+3 ; 0x03
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295
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296 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
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297
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298 // Save received data
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299 for(int i=0; i<j ; i++)
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300 dato[j-i-1] = adcport_tranceiv(0);
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301 1fe: 9e 93 st -X, r25
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302 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
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303
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304 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
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305
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306 // Save received data
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307 for(int i=0; i<j ; i++)
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308 200: a2 17 cp r26, r18
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309 202: b3 07 cpc r27, r19
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310 204: b9 f7 brne .-18 ; 0x1f4 <adcport_read_data+0x26>
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311 206: 08 95 ret
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312
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313 00000208 <config_spiparm>:
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314 inline void config_spiparm(void){
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315 // Preescaler: clkper/2 = f_cpu/2.
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316 // Master
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317 // Mode 3: CPOL=1,CPHA=1
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318 // MSB --- LSB
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319 SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm |
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320 208: 8c ed ldi r24, 0xDC ; 220
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321 20a: 80 93 c0 08 sts 0x08C0, r24
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322 20e: 08 95 ret
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323
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324 00000210 <config_fpgaport>:
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325 #include <avr/io.h>
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326
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327 #include "fpga_port.h"
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328
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329 inline void config_fpgaport()
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330 {
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331 210: cf 93 push r28
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332 212: df 93 push r29
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333 //Configuracion pines del puerto D: PD6-PA1
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334 //Pines de entrada CLK_FPGA, LOCK_FPGA
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335 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
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336 PORT_FPGA.DIRCLR = LOCK_FPGA;
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337 214: e0 e6 ldi r30, 0x60 ; 96
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338 216: f6 e0 ldi r31, 0x06 ; 6
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339 218: 22 e0 ldi r18, 0x02 ; 2
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340 21a: 22 83 std Z+2, r18 ; 0x02
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341 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
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342 21c: 80 e1 ldi r24, 0x10 ; 16
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343 21e: 81 8b std Z+17, r24 ; 0x11
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344 PORT_FPGA.DIRSET = CLK_FPGA;
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345 220: 94 e0 ldi r25, 0x04 ; 4
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346 222: 91 83 std Z+1, r25 ; 0x01
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347 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc;
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348 224: 38 e1 ldi r19, 0x18 ; 24
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349 226: 32 8b std Z+18, r19 ; 0x12
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350 PORT_FPGA.OUTSET = CLK_FPGA;
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351 228: 95 83 std Z+5, r25 ; 0x05
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352
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353 //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
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354 PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
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355 22a: 38 e7 ldi r19, 0x78 ; 120
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356 22c: 31 83 std Z+1, r19 ; 0x01
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357 PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc;
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358 22e: 13 8a std Z+19, r1 ; 0x13
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359 PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
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360 230: 35 83 std Z+5, r19 ; 0x05
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361
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362 //Configuracion pines del puerto B: PPS
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363 //Pines de entrada PPS_FPGA
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364 //Pines de entrada en pulldown
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365 PORT_PPS.DIRCLR = PPS_FPGA;
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366 232: a0 e2 ldi r26, 0x20 ; 32
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367 234: b6 e0 ldi r27, 0x06 ; 6
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368 236: 12 96 adiw r26, 0x02 ; 2
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369 238: 9c 93 st X, r25
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370 23a: 12 97 sbiw r26, 0x02 ; 2
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371 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
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372 23c: 52 96 adiw r26, 0x12 ; 18
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373 23e: 8c 93 st X, r24
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374 240: 52 97 sbiw r26, 0x12 ; 18
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375
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376 //Configuracion pines del puerto A: LOCKOUT
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377 //Pines de salida LOCK_OUT
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378 //Pines de salida en baja
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379 PORT_LOCKOUT.DIRSET = LOCK_OUT;
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380 242: c0 e0 ldi r28, 0x00 ; 0
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381 244: d6 e0 ldi r29, 0x06 ; 6
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382 246: 81 e0 ldi r24, 0x01 ; 1
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383 248: 89 83 std Y+1, r24 ; 0x01
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384 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
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385 24a: 8e 83 std Y+6, r24 ; 0x06
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386
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387
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388
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389 //Configuracion de interrupciones de LOCK_FPGA
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390
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391 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
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392 24c: 81 85 ldd r24, Z+9 ; 0x09
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393 24e: 83 60 ori r24, 0x03 ; 3
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394 250: 81 87 std Z+9, r24 ; 0x09
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395 PORT_FPGA.INT0MASK = LOCK_FPGA;
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396 252: 22 87 std Z+10, r18 ; 0x0a
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397 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
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398 254: 81 89 ldd r24, Z+17 ; 0x11
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399 256: 88 7f andi r24, 0xF8 ; 248
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400 258: 81 8b std Z+17, r24 ; 0x11
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401 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
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402 //PORT_FPGA.INT1MASK = CLK_FPGA;
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403 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
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404
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405 //Configuracion de interrupciones de PPS
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406 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
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407 25a: 81 85 ldd r24, Z+9 ; 0x09
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408 25c: 83 7f andi r24, 0xF3 ; 243
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409 25e: 88 60 ori r24, 0x08 ; 8
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410 260: 19 96 adiw r26, 0x09 ; 9
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411 262: 8c 93 st X, r24
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412 264: 19 97 sbiw r26, 0x09 ; 9
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413 PORT_PPS.INT1MASK = PPS_FPGA;
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414 266: 1b 96 adiw r26, 0x0b ; 11
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415 268: 9c 93 st X, r25
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416 26a: 1b 97 sbiw r26, 0x0b ; 11
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417 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
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418 26c: 52 96 adiw r26, 0x12 ; 18
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419 26e: 8c 91 ld r24, X
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420 270: 52 97 sbiw r26, 0x12 ; 18
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421 272: 88 7f andi r24, 0xF8 ; 248
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422 274: 81 60 ori r24, 0x01 ; 1
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423 276: 52 96 adiw r26, 0x12 ; 18
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424 278: 8c 93 st X, r24
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425 }
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426 27a: df 91 pop r29
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427 27c: cf 91 pop r28
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428 27e: 08 95 ret
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429
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430 00000280 <habilitar_interrupciones_globales>:
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431 PMIC.CTRL = level_mask;
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432 }
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433
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434 void habilitar_interrupciones_globales( void )
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435 {
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436 sei();
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437 280: 78 94 sei
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438 282: 08 95 ret
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439
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440 00000284 <envio_nibble>:
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441 cli();
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442 }
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443
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444 void envio_nibble(uint8_t fpga_dato)
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445 {
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446 PORT_FPGA.OUTCLR = CLK_FPGA;
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447 284: e0 e6 ldi r30, 0x60 ; 96
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448 286: f6 e0 ldi r31, 0x06 ; 6
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449 288: 24 e0 ldi r18, 0x04 ; 4
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450 28a: 26 83 std Z+6, r18 ; 0x06
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451 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp);
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452 28c: 94 81 ldd r25, Z+4 ; 0x04
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453 28e: 38 2f mov r19, r24
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454 290: 30 7f andi r19, 0xF0 ; 240
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455 292: 33 0f add r19, r19
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456 294: 33 0f add r19, r19
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457 296: 33 0f add r19, r19
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458 298: 98 73 andi r25, 0x38 ; 56
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459 29a: 93 2b or r25, r19
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460 29c: 94 83 std Z+4, r25 ; 0x04
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461 PORT_FPGA.OUTSET = CLK_FPGA;
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462 29e: 25 83 std Z+5, r18 ; 0x05
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463 //asm("nop");
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464 PORT_FPGA.OUTCLR = CLK_FPGA;
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465 2a0: 26 83 std Z+6, r18 ; 0x06
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466 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp);
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467 2a2: 94 81 ldd r25, Z+4 ; 0x04
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468 2a4: 8f 70 andi r24, 0x0F ; 15
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469 2a6: 88 0f add r24, r24
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470 2a8: 88 0f add r24, r24
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471 2aa: 88 0f add r24, r24
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472 2ac: 98 73 andi r25, 0x38 ; 56
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473 2ae: 89 2b or r24, r25
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474 2b0: 84 83 std Z+4, r24 ; 0x04
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475 PORT_FPGA.OUTSET = CLK_FPGA;
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476 2b2: 25 83 std Z+5, r18 ; 0x05
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477 2b4: 08 95 ret
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478
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479 000002b6 <envio_dato_adc>:
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480 envio_dato_adc(aux_dato);
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481 envio_dato_adc(fpga_dato);
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482 }
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483
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484 void envio_dato_adc(uint8_t* dato_adc)
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485 {
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486 2b6: 0f 93 push r16
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487 2b8: 1f 93 push r17
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488 2ba: cf 93 push r28
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489 2bc: df 93 push r29
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490 2be: ec 01 movw r28, r24
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491 2c0: 8c 01 movw r16, r24
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492 2c2: 0d 5f subi r16, 0xFD ; 253
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493 2c4: 1f 4f sbci r17, 0xFF ; 255
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494 for(int i=0; i<3 ; i++)
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495 envio_nibble(dato_adc[i]);
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496 2c6: 89 91 ld r24, Y+
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497 2c8: 0e 94 42 01 call 0x284 ; 0x284 <envio_nibble>
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498 envio_dato_adc(fpga_dato);
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499 }
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500
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501 void envio_dato_adc(uint8_t* dato_adc)
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502 {
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503 for(int i=0; i<3 ; i++)
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504 2cc: c0 17 cp r28, r16
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505 2ce: d1 07 cpc r29, r17
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506 2d0: d1 f7 brne .-12 ; 0x2c6 <envio_dato_adc+0x10>
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507 envio_nibble(dato_adc[i]);
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508 }
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509 2d2: df 91 pop r29
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510 2d4: cf 91 pop r28
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511 2d6: 1f 91 pop r17
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512 2d8: 0f 91 pop r16
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513 2da: 08 95 ret
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514
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515 000002dc <envio_datos_fpga>:
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516 PORT_FPGA.OUTSET = CLK_FPGA;
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517
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518 }
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519
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520 void envio_datos_fpga(void)
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521 {
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522 2dc: cf 93 push r28
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523 2de: df 93 push r29
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524 2e0: cd b7 in r28, 0x3d ; 61
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525 2e2: de b7 in r29, 0x3e ; 62
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526 2e4: 26 97 sbiw r28, 0x06 ; 6
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527 2e6: cd bf out 0x3d, r28 ; 61
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528 2e8: de bf out 0x3e, r29 ; 62
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529 uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ;
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530 adcport_read_data(fpga_dato,ADC_DATASZ);
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531 2ea: 63 e0 ldi r22, 0x03 ; 3
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532 2ec: 70 e0 ldi r23, 0x00 ; 0
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533 2ee: ce 01 movw r24, r28
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534 2f0: 01 96 adiw r24, 0x01 ; 1
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535 2f2: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data>
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536 aux_dato[0] = fpga_dato[0];
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537 2f6: 89 81 ldd r24, Y+1 ; 0x01
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538 2f8: 8c 83 std Y+4, r24 ; 0x04
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539 aux_dato[1] = fpga_dato[1];
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540 2fa: 8a 81 ldd r24, Y+2 ; 0x02
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541 2fc: 8d 83 std Y+5, r24 ; 0x05
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542 aux_dato[2] = fpga_dato[2];
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543 2fe: 8b 81 ldd r24, Y+3 ; 0x03
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544 300: 8e 83 std Y+6, r24 ; 0x06
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545 adcport_read_data(fpga_dato,ADC_DATASZ);
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546 302: 63 e0 ldi r22, 0x03 ; 3
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547 304: 70 e0 ldi r23, 0x00 ; 0
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548 306: ce 01 movw r24, r28
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549 308: 01 96 adiw r24, 0x01 ; 1
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550 30a: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data>
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551
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552 envio_dato_adc(aux_dato);
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553 30e: ce 01 movw r24, r28
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554 310: 04 96 adiw r24, 0x04 ; 4
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555 312: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc>
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556 envio_dato_adc(fpga_dato);
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557 316: ce 01 movw r24, r28
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558 318: 01 96 adiw r24, 0x01 ; 1
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559 31a: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc>
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560 }
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561 31e: 26 96 adiw r28, 0x06 ; 6
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562 320: cd bf out 0x3d, r28 ; 61
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563 322: de bf out 0x3e, r29 ; 62
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564 324: df 91 pop r29
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565 326: cf 91 pop r28
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566 328: 08 95 ret
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567
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568 0000032a <main>:
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569
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570
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571 int main(void)
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572 {
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573 //uint8_t datos_adc[3];
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574 config_puertos();
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575 32a: 0e 94 15 02 call 0x42a ; 0x42a <config_puertos>
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576 config_sysclock();
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577 32e: 0e 94 8b 02 call 0x516 ; 0x516 <config_sysclock>
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578 config_spiparm();
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579 332: 0e 94 04 01 call 0x208 ; 0x208 <config_spiparm>
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580 config_fpgaport();
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581 336: 0e 94 08 01 call 0x210 ; 0x210 <config_fpgaport>
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582 //datos_adc[0] = 0x00;
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583 //datos_adc[1] = 0x00;
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584 //datos_adc[2] = 0x00;
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585 //PORTD.OUTSET = PIN5_bm;
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586
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587 PMIC.CTRL = hab_prioridad_alta;
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588 33a: 84 e0 ldi r24, 0x04 ; 4
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589 33c: 80 93 a2 00 sts 0x00A2, r24
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590 habilitar_interrupciones_globales();
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591 340: 0e 94 40 01 call 0x280 ; 0x280 <habilitar_interrupciones_globales>
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592
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593 /* Replace with your application code */
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594 while (1)
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595 {
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596 if (test_adc() == ADC_ID){
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597 PORTD.OUTSET = PIN6_bm | PIN5_bm;
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598 344: 00 e6 ldi r16, 0x60 ; 96
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599 346: 16 e0 ldi r17, 0x06 ; 6
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600 348: c0 e6 ldi r28, 0x60 ; 96
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601 habilitar_interrupciones_globales();
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602
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603 /* Replace with your application code */
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604 while (1)
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605 {
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606 if (test_adc() == ADC_ID){
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607 34a: 0e 94 c2 00 call 0x184 ; 0x184 <test_adc>
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608 34e: 84 39 cpi r24, 0x94 ; 148
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609 350: 9c 40 sbci r25, 0x0C ; 12
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610 352: d9 f7 brne .-10 ; 0x34a <main+0x20>
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611 PORTD.OUTSET = PIN6_bm | PIN5_bm;
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612 354: f8 01 movw r30, r16
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613 356: c5 83 std Z+5, r28 ; 0x05
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614 358: f8 cf rjmp .-16 ; 0x34a <main+0x20>
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615
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616 0000035a <__vector_64>:
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617 return 0;
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618 }
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619
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620
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621 ISR(INT_LOCK_FPGA)
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622 {
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623 35a: 1f 92 push r1
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624 35c: 0f 92 push r0
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625 35e: 0f b6 in r0, 0x3f ; 63
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626 360: 0f 92 push r0
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627 362: 11 24 eor r1, r1
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628 364: 8f 93 push r24
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629 366: ef 93 push r30
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630 368: ff 93 push r31
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631 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
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632 36a: 80 91 68 06 lds r24, 0x0668
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633 36e: 81 ff sbrs r24, 1
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634 370: 09 c0 rjmp .+18 ; 0x384 <__vector_64+0x2a>
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635 {
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636 PMIC.CTRL |= hab_prioridad_media;
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637 372: e0 ea ldi r30, 0xA0 ; 160
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638 374: f0 e0 ldi r31, 0x00 ; 0
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639 376: 82 81 ldd r24, Z+2 ; 0x02
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640 378: 82 60 ori r24, 0x02 ; 2
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641 37a: 82 83 std Z+2, r24 ; 0x02
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642 PORT_LOCKOUT.OUTSET = LOCK_OUT;
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643 37c: 81 e0 ldi r24, 0x01 ; 1
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644 37e: 80 93 05 06 sts 0x0605, r24
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645 382: 08 c0 rjmp .+16 ; 0x394 <__vector_64+0x3a>
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646 }
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647 else
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648 {
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649 PMIC.CTRL &= ~hab_prioridad_media;
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650 384: e0 ea ldi r30, 0xA0 ; 160
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651 386: f0 e0 ldi r31, 0x00 ; 0
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652 388: 82 81 ldd r24, Z+2 ; 0x02
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653 38a: 8d 7f andi r24, 0xFD ; 253
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654 38c: 82 83 std Z+2, r24 ; 0x02
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655 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
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656 38e: 81 e0 ldi r24, 0x01 ; 1
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657 390: 80 93 06 06 sts 0x0606, r24
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658 }
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659 }
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660 394: ff 91 pop r31
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661 396: ef 91 pop r30
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662 398: 8f 91 pop r24
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663 39a: 0f 90 pop r0
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664 39c: 0f be out 0x3f, r0 ; 63
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665 39e: 0f 90 pop r0
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666 3a0: 1f 90 pop r1
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667 3a2: 18 95 reti
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668
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669 000003a4 <__vector_35>:
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670
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671 ISR(INT_PPS)
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672 {
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673 3a4: 1f 92 push r1
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674 3a6: 0f 92 push r0
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675 3a8: 0f b6 in r0, 0x3f ; 63
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676 3aa: 0f 92 push r0
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677 3ac: 11 24 eor r1, r1
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678 3ae: 8f 93 push r24
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679 3b0: ef 93 push r30
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680 3b2: ff 93 push r31
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681 if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA)
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682 3b4: 80 91 28 06 lds r24, 0x0628
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683 3b8: 82 ff sbrs r24, 2
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684 3ba: 06 c0 rjmp .+12 ; 0x3c8 <__vector_35+0x24>
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685 PMIC.CTRL |= hab_prioridad_baja;
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686 3bc: e0 ea ldi r30, 0xA0 ; 160
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687 3be: f0 e0 ldi r31, 0x00 ; 0
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688 3c0: 82 81 ldd r24, Z+2 ; 0x02
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689 3c2: 81 60 ori r24, 0x01 ; 1
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690 3c4: 82 83 std Z+2, r24 ; 0x02
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691 3c6: 05 c0 rjmp .+10 ; 0x3d2 <__vector_35+0x2e>
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692 else
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693 PMIC.CTRL &= ~hab_prioridad_baja;
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694 3c8: e0 ea ldi r30, 0xA0 ; 160
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695 3ca: f0 e0 ldi r31, 0x00 ; 0
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696 3cc: 82 81 ldd r24, Z+2 ; 0x02
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697 3ce: 8e 7f andi r24, 0xFE ; 254
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698 3d0: 82 83 std Z+2, r24 ; 0x02
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699 }
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700 3d2: ff 91 pop r31
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701 3d4: ef 91 pop r30
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702 3d6: 8f 91 pop r24
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703 3d8: 0f 90 pop r0
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704 3da: 0f be out 0x3f, r0 ; 63
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705 3dc: 0f 90 pop r0
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706 3de: 1f 90 pop r1
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707 3e0: 18 95 reti
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708
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709 000003e2 <__vector_2>:
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710
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711 ISR(INT_RDY)
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712 {
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713 3e2: 1f 92 push r1
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714 3e4: 0f 92 push r0
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715 3e6: 0f b6 in r0, 0x3f ; 63
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716 3e8: 0f 92 push r0
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717 3ea: 11 24 eor r1, r1
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718 3ec: 2f 93 push r18
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719 3ee: 3f 93 push r19
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720 3f0: 4f 93 push r20
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721 3f2: 5f 93 push r21
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722 3f4: 6f 93 push r22
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723 3f6: 7f 93 push r23
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724 3f8: 8f 93 push r24
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725 3fa: 9f 93 push r25
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726 3fc: af 93 push r26
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727 3fe: bf 93 push r27
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728 400: ef 93 push r30
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729 402: ff 93 push r31
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730 envio_datos_fpga();
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731 404: 0e 94 6e 01 call 0x2dc ; 0x2dc <envio_datos_fpga>
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732 }
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733 408: ff 91 pop r31
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734 40a: ef 91 pop r30
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735 40c: bf 91 pop r27
No newline at end of file
736 40e: af 91 pop r26
No newline at end of file
737 410: 9f 91 pop r25
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738 412: 8f 91 pop r24
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739 414: 7f 91 pop r23
No newline at end of file
740 416: 6f 91 pop r22
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741 418: 5f 91 pop r21
No newline at end of file
742 41a: 4f 91 pop r20
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743 41c: 3f 91 pop r19
No newline at end of file
744 41e: 2f 91 pop r18
No newline at end of file
745 420: 0f 90 pop r0
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746 422: 0f be out 0x3f, r0 ; 63
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747 424: 0f 90 pop r0
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748 426: 1f 90 pop r1
No newline at end of file
749 428: 18 95 reti
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750
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751 0000042a <config_puertos>:
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752 #include "commSPI_ADC.h"
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753
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754 inline void config_puertos(void){
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755 //Configuracion pines del puerto A: PA7-PA0
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756 //Pines de entrada y totem_pullup
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757 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
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758 42a: e0 e0 ldi r30, 0x00 ; 0
No newline at end of file
759 42c: f6 e0 ldi r31, 0x06 ; 6
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760 42e: 8e ef ldi r24, 0xFE ; 254
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761 430: 82 83 std Z+2, r24 ; 0x02
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762 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
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763 432: 88 e1 ldi r24, 0x18 ; 24
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764 434: 87 8b std Z+23, r24 ; 0x17
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765 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
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766 436: 86 8b std Z+22, r24 ; 0x16
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767 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
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768 438: 85 8b std Z+21, r24 ; 0x15
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769 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
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770 43a: 84 8b std Z+20, r24 ; 0x14
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771 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
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772 43c: 83 8b std Z+19, r24 ; 0x13
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773 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
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774 43e: 82 8b std Z+18, r24 ; 0x12
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775 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
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776 440: 81 8b std Z+17, r24 ; 0x11
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777 //Pin de salida A0
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778 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
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779 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
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780 //Valor por defecto salida: PA0 = low
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781 PORTA.DIRSET = PIN0_bm;
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782 442: 21 e0 ldi r18, 0x01 ; 1
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783 444: 21 83 std Z+1, r18 ; 0x01
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784 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
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785 446: 98 e3 ldi r25, 0x38 ; 56
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786 448: 90 8b std Z+16, r25 ; 0x10
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787 PORTA.OUTCLR = PIN0_bm;
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788 44a: 26 83 std Z+6, r18 ; 0x06
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789
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790 //Configuracion pines del puerto B: PB3-PB0
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791 //Pines de entrada y totem_pullup
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792 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
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793 44c: e0 e2 ldi r30, 0x20 ; 32
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794 44e: f6 e0 ldi r31, 0x06 ; 6
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795 450: 3f e0 ldi r19, 0x0F ; 15
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796 452: 32 83 std Z+2, r19 ; 0x02
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797 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
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798 454: 83 8b std Z+19, r24 ; 0x13
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799 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
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800 456: 82 8b std Z+18, r24 ; 0x12
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801 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
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802 458: 81 8b std Z+17, r24 ; 0x11
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803 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
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804 45a: 80 8b std Z+16, r24 ; 0x10
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805
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806 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
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807 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
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808 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
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809 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
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810 45c: e0 e4 ldi r30, 0x40 ; 64
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811 45e: f6 e0 ldi r31, 0x06 ; 6
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812 460: 2f e4 ldi r18, 0x4F ; 79
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813 462: 22 83 std Z+2, r18 ; 0x02
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814 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
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815 464: 86 8b std Z+22, r24 ; 0x16
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816 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
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817 466: 83 8b std Z+19, r24 ; 0x13
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818 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
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819 468: 82 8b std Z+18, r24 ; 0x12
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820 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
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821 46a: 81 8b std Z+17, r24 ; 0x11
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822 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
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823 46c: 80 8b std Z+16, r24 ; 0x10
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824 //Pines de salida wiredand-pull
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825 //Valor por defecto salida: PC4,PC7 = low
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826 //Valor por defecto salida: PC5 = set
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827 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
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828 46e: 20 eb ldi r18, 0xB0 ; 176
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829 470: 21 83 std Z+1, r18 ; 0x01
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830 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
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831 472: 15 8a std Z+21, r1 ; 0x15
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832 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
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833 474: 17 8a std Z+23, r1 ; 0x17
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834 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
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835 476: 14 8a std Z+20, r1 ; 0x14
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836 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
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837 478: 20 e9 ldi r18, 0x90 ; 144
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838 47a: 25 83 std Z+5, r18 ; 0x05
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839 PORTSPI.OUTCLR = SPI_MOSI_bm;
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840 47c: 20 e2 ldi r18, 0x20 ; 32
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841 47e: 26 83 std Z+6, r18 ; 0x06
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842 //Configuracion pines del puerto D: PD7-PD0
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843 //Pines de entrada y totem_pullup: PIN7 y PIN0
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844 //NOTA
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845 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
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846 //NOTA FIN
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847 PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm;
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848 480: a0 e6 ldi r26, 0x60 ; 96
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849 482: b6 e0 ldi r27, 0x06 ; 6
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850 484: 27 e8 ldi r18, 0x87 ; 135
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851 486: 12 96 adiw r26, 0x02 ; 2
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852 488: 2c 93 st X, r18
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853 48a: 12 97 sbiw r26, 0x02 ; 2
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854 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
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855 48c: 57 96 adiw r26, 0x17 ; 23
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856 48e: 8c 93 st X, r24
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857 490: 57 97 sbiw r26, 0x17 ; 23
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858 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
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859 492: 50 96 adiw r26, 0x10 ; 16
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860 494: 8c 93 st X, r24
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861 496: 50 97 sbiw r26, 0x10 ; 16
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862 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
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863 PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
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864 498: 20 e1 ldi r18, 0x10 ; 16
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865 49a: 52 96 adiw r26, 0x12 ; 18
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866 49c: 2c 93 st X, r18
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867 49e: 52 97 sbiw r26, 0x12 ; 18
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868 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
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869 4a0: 51 96 adiw r26, 0x11 ; 17
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870 4a2: 2c 93 st X, r18
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871 4a4: 51 97 sbiw r26, 0x11 ; 17
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872 //Pines de salida tipo wired-and-pull
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873 //Valor por defecto PD6, PD5, PD4, PD3 = low
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874 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
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875 4a6: 48 e7 ldi r20, 0x78 ; 120
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876 4a8: 11 96 adiw r26, 0x01 ; 1
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877 4aa: 4c 93 st X, r20
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878 4ac: 11 97 sbiw r26, 0x01 ; 1
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879 PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc;
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880 4ae: 56 96 adiw r26, 0x16 ; 22
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881 4b0: 9c 93 st X, r25
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882 4b2: 56 97 sbiw r26, 0x16 ; 22
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883 PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc;
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884 4b4: 55 96 adiw r26, 0x15 ; 21
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885 4b6: 9c 93 st X, r25
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886 4b8: 55 97 sbiw r26, 0x15 ; 21
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887 PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc;
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888 4ba: 54 96 adiw r26, 0x14 ; 20
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889 4bc: 9c 93 st X, r25
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890 4be: 54 97 sbiw r26, 0x14 ; 20
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891 PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc;
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892 4c0: 53 96 adiw r26, 0x13 ; 19
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893 4c2: 9c 93 st X, r25
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894 4c4: 53 97 sbiw r26, 0x13 ; 19
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895 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
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896 4c6: 16 96 adiw r26, 0x06 ; 6
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897 4c8: 4c 93 st X, r20
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898
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899 //Configuracion pines del puerto E: PE3-PE0
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900 //Pines de entrada y totem_pullup: PIN3 - PIN0
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901 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
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902 4ca: a0 e8 ldi r26, 0x80 ; 128
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903 4cc: b6 e0 ldi r27, 0x06 ; 6
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904 4ce: 12 96 adiw r26, 0x02 ; 2
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905 4d0: 3c 93 st X, r19
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906 4d2: 12 97 sbiw r26, 0x02 ; 2
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907 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
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908 4d4: 53 96 adiw r26, 0x13 ; 19
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909 4d6: 8c 93 st X, r24
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910 4d8: 53 97 sbiw r26, 0x13 ; 19
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911 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
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912 4da: 52 96 adiw r26, 0x12 ; 18
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913 4dc: 8c 93 st X, r24
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914 4de: 52 97 sbiw r26, 0x12 ; 18
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915 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
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916 4e0: 51 96 adiw r26, 0x11 ; 17
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917 4e2: 8c 93 st X, r24
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918 4e4: 51 97 sbiw r26, 0x11 ; 17
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919 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
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920 4e6: 50 96 adiw r26, 0x10 ; 16
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921 4e8: 8c 93 st X, r24
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922
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923 //Configuracion pines del puerto R: PR1-PR0
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924 //Pines de entrada y totem_pulldown: PIN0
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925 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
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926 4ea: a0 ee ldi r26, 0xE0 ; 224
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927 4ec: b7 e0 ldi r27, 0x07 ; 7
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928 4ee: 93 e0 ldi r25, 0x03 ; 3
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929 4f0: 12 96 adiw r26, 0x02 ; 2
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930 4f2: 9c 93 st X, r25
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931 4f4: 12 97 sbiw r26, 0x02 ; 2
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932 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
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933 4f6: 51 96 adiw r26, 0x11 ; 17
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934 4f8: 2c 93 st X, r18
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935 4fa: 51 97 sbiw r26, 0x11 ; 17
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936 //Pines de entrada y totem_pulldup:PIN1
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937 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
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938 4fc: 50 96 adiw r26, 0x10 ; 16
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939 4fe: 8c 93 st X, r24
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940
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941 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
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942
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943 PORTSPI.INT0MASK = SPI_MISO_bm;
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944 500: 80 e4 ldi r24, 0x40 ; 64
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945 502: 82 87 std Z+10, r24 ; 0x0a
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946 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
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947 504: 81 85 ldd r24, Z+9 ; 0x09
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948 506: 8c 7f andi r24, 0xFC ; 252
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949 508: 81 60 ori r24, 0x01 ; 1
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950 50a: 81 87 std Z+9, r24 ; 0x09
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951 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
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952 50c: 86 89 ldd r24, Z+22 ; 0x16
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953 50e: 88 7f andi r24, 0xF8 ; 248
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954 510: 82 60 ori r24, 0x02 ; 2
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955 512: 86 8b std Z+22, r24 ; 0x16
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956 514: 08 95 ret
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957
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958 00000516 <config_sysclock>:
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959 #define F_CPU 32000000UL
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960 #include <avr/io.h>
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961
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962 void config_sysclock(void){
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963
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964 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz
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965 516: e0 e5 ldi r30, 0x50 ; 80
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966 518: f0 e0 ldi r31, 0x00 ; 0
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967 51a: 80 81 ld r24, Z
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968 51c: 86 60 ori r24, 0x06 ; 6
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969 51e: 80 83 st Z, r24
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970 do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj
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971 520: 81 81 ldd r24, Z+1 ; 0x01
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972 522: 81 ff sbrs r24, 1
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973 524: fd cf rjmp .-6 ; 0x520 <config_sysclock+0xa>
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974 do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj
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975 526: e0 e5 ldi r30, 0x50 ; 80
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976 528: f0 e0 ldi r31, 0x00 ; 0
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977 52a: 81 81 ldd r24, Z+1 ; 0x01
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978 52c: 82 ff sbrs r24, 2
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979 52e: fd cf rjmp .-6 ; 0x52a <config_sysclock+0x14>
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980 CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla
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981 530: 28 ed ldi r18, 0xD8 ; 216
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982 532: 24 bf out 0x34, r18 ; 52
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983 //con instrucciones en assembler
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984 CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler
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985 534: e0 e4 ldi r30, 0x40 ; 64
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986 536: f0 e0 ldi r31, 0x00 ; 0
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987 538: 80 81 ld r24, Z
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988 53a: 81 60 ori r24, 0x01 ; 1
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989 53c: 80 83 st Z, r24
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990 DFLLRC32M.CTRL = DFLL_ENABLE_bm;
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991 53e: 91 e0 ldi r25, 0x01 ; 1
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992 540: 90 93 60 00 sts 0x0060, r25
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993 OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K
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994 544: e0 e5 ldi r30, 0x50 ; 80
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995 546: f0 e0 ldi r31, 0x00 ; 0
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996 548: 86 81 ldd r24, Z+6 ; 0x06
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997 54a: 16 82 std Z+6, r1 ; 0x06
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998 OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno
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999 54c: 80 81 ld r24, Z
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1000 54e: 8e 7f andi r24, 0xFE ; 254
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1001 550: 80 83 st Z, r24
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1002 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
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1003 552: 24 bf out 0x34, r18 ; 52
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1004 OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
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1005 554: 90 93 53 00 sts 0x0053, r25
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1006 558: 08 95 ret
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1007
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1008 0000055a <_exit>:
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1009 55a: f8 94 cli
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1010
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1011 0000055c <__stop_program>:
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1012 55c: ff cf rjmp .-2 ; 0x55c <__stop_program> No newline at end of file
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1 Archive member included to satisfy reference by file (symbol)
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2
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3 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o)
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4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o (exit)
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5
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6 Discarded input sections
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7
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8 .data 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o
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9 .bss 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o
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10 .text 0x00000000 0x0 ADC_7176_2.o
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11 .data 0x00000000 0x0 ADC_7176_2.o
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12 .bss 0x00000000 0x0 ADC_7176_2.o
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13 .text.test_adc_2
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14 0x00000000 0x3e ADC_7176_2.o
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15 .text.adcport_tranceiv
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16 0x00000000 0x14 ADC_7176_2.o
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17 .text.adcport_write_filtcon0
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18 0x00000000 0x34 ADC_7176_2.o
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19 .text.config_adc
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20 0x00000000 0x6 ADC_7176_2.o
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21 .text.adcport_write_interfmode
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22 0x00000000 0x34 ADC_7176_2.o
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23 .text 0x00000000 0x0 commSPI_ADC.o
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24 .data 0x00000000 0x0 commSPI_ADC.o
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25 .bss 0x00000000 0x0 commSPI_ADC.o
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
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14 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h
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15
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16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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17
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18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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19
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20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
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21
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22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
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23
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24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
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25
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26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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27
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28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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29
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30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
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31
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32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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33
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34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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35
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36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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37
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38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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39
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40 .././ADC_7176_2.h:
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41
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42 .././Ports.h:
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43
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44 .././commSPI_ADC.h: No newline at end of file
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1 ################################################################################
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2 # Automatically-generated file. Do not edit!
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3 ################################################################################
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4
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5 SHELL := cmd.exe
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6 RM := rm -rf
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7
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8 USER_OBJS :=
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9
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10 LIBS :=
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11 PROJ :=
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12
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13 O_SRCS :=
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14 C_SRCS :=
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15 S_SRCS :=
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16 S_UPPER_SRCS :=
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17 OBJ_SRCS :=
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18 ASM_SRCS :=
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19 PREPROCESSING_SRCS :=
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20 OBJS :=
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21 OBJS_AS_ARGS :=
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22 C_DEPS :=
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23 C_DEPS_AS_ARGS :=
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24 EXECUTABLES :=
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25 OUTPUT_FILE_PATH :=
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26 OUTPUT_FILE_PATH_AS_ARGS :=
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27 AVR_APP_PATH :=$$$AVR_APP_PATH$$$
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28 QUOTE := "
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29 ADDITIONAL_DEPENDENCIES:=
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30 OUTPUT_FILE_DEP:=
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31 LIB_DEP:=
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32 LINKER_SCRIPT_DEP:=
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33
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34 # Every subdirectory with source files must be described here
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35 SUBDIRS :=
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36
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37
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38 # Add inputs and outputs from these tool invocations to the build variables
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39 C_SRCS += \
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40 ../ADC_7176_2.c \
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41 ../commSPI_ADC.c \
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42 ../fpga_port.c \
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43 ../main.c \
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44 ../Ports.c \
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45 ../sys_clock.c
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46
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47
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48 PREPROCESSING_SRCS +=
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49
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50
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51 ASM_SRCS +=
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52
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53
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54 OBJS += \
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55 ADC_7176_2.o \
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56 commSPI_ADC.o \
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57 fpga_port.o \
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58 main.o \
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59 Ports.o \
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60 sys_clock.o
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61
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62 OBJS_AS_ARGS += \
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63 ADC_7176_2.o \
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64 commSPI_ADC.o \
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65 fpga_port.o \
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66 main.o \
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67 Ports.o \
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68 sys_clock.o
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69
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70 C_DEPS += \
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71 ADC_7176_2.d \
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72 commSPI_ADC.d \
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73 fpga_port.d \
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74 main.d \
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75 Ports.d \
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76 sys_clock.d
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77
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78 C_DEPS_AS_ARGS += \
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79 ADC_7176_2.d \
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80 commSPI_ADC.d \
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81 fpga_port.d \
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82 main.d \
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83 Ports.d \
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84 sys_clock.d
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85
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86 OUTPUT_FILE_PATH +=ADCSPI_ver01.elf
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87
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88 OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf
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89
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90 ADDITIONAL_DEPENDENCIES:=
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91
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92 OUTPUT_FILE_DEP:= ./makedep.mk
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93
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94 LIB_DEP+=
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95
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96 LINKER_SCRIPT_DEP+=
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97
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98
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99 # AVR32/GNU C Compiler
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100
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101
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102
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103
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104
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105
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106
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107
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108
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109
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110
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111
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112
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113 ./%.o: .././%.c
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114 @echo Building file: $<
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115 @echo Invoking: AVR/GNU C Compiler : 4.9.2
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116 $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
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117 @echo Finished building: $<
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118
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119
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120
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121
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122 # AVR32/GNU Preprocessing Assembler
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123
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124
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125
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126 # AVR32/GNU Assembler
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127
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128
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129
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130
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131 ifneq ($(MAKECMDGOALS),clean)
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132 ifneq ($(strip $(C_DEPS)),)
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133 -include $(C_DEPS)
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134 endif
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135 endif
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136
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137 # Add inputs and outputs from these tool invocations to the build variables
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138
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139 # All Target
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140 all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
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141
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142 $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
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143 @echo Building target: $@
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144 @echo Invoking: AVR/GNU Linker : 4.9.2
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145 $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4"
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146 @echo Finished building target: $@
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147 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex"
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148 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0
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149 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss"
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150 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec"
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151 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf"
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152
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153
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154
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155
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156
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157
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158
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159 # Other Targets
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160 clean:
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161 -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
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162 -$(RM) $(C_DEPS_AS_ARGS)
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163 rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures"
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164 No newline at end of file
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1 Ports.d Ports.o: .././Ports.c \
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2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
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3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
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4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
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5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
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6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
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7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
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8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
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9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
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14 .././Ports.h .././commSPI_ADC.h
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15
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16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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17
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18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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19
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20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
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21
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22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
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23
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24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
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25
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26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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27
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28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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29
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30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
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31
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32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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33
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34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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35
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36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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37
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38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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39
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40 .././Ports.h:
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41
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42 .././commSPI_ADC.h: No newline at end of file
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1 commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \
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2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
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3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
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4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
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5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
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6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
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7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
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8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
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9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
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14 .././commSPI_ADC.h .././Ports.h
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15
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16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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17
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18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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19
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20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
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21
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22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
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23
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24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
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25
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26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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27
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28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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29
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30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
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31
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32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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33
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34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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35
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36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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39
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40 .././commSPI_ADC.h:
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41
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42 .././Ports.h: No newline at end of file
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1 fpga_port.d fpga_port.o: .././fpga_port.c \
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2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
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3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
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4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
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5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
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6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
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7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
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8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
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9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
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14 .././fpga_port.h \
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15 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \
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16 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h
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17
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18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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19
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20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
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24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
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26 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
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27
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28 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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29
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30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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31
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32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
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33
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34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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35
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36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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37
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38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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39
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40 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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41
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42 .././fpga_port.h:
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43
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44 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
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45
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46 .././ADC_7176_2.h:
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47
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48 .././Ports.h:
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49
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50 .././commSPI_ADC.h: No newline at end of file
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1 main.d main.o: .././main.c \
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2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
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3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
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4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
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5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
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6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
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7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
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8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
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9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
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14 .././Ports.h .././commSPI_ADC.h .././sys_clock.h .././ADC_7176_2.h \
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15 .././fpga_port.h \
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16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h
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17
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18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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19
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20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
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28 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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31
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32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
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33
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34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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35
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36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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40 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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41
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42 .././Ports.h:
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43
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44 .././commSPI_ADC.h:
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45
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46 .././sys_clock.h:
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47
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48 .././ADC_7176_2.h:
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49
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50 .././fpga_port.h:
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51
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52 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: No newline at end of file
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1 ################################################################################
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2 # Automatically-generated file. Do not edit or delete the file
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3 ################################################################################
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4
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5 ADC_7176_2.c
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6
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7 commSPI_ADC.c
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8
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9 fpga_port.c
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10
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11 main.c
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12
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13 Ports.c
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14
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15 sys_clock.c
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1 sys_clock.d sys_clock.o: .././sys_clock.c \
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2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
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3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
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5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
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6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
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7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
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8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
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9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
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10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
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11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
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12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
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13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h
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15 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
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17 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
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25 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
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27 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
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31 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
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33 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
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35 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
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1 /*
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2 * Ports.c
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3 *
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4 * Created: 23/11/15 13:57:48
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5 * Author: Francisco
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6 */
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7
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8 /*!
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9 * \fn config_puertos
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10 * \brief Configuraci�n de todos los pines de I/O a usarse
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11 * para la prueba. Para el firmware final se deben dejar de configurar en este segmento
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12 * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo.
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13 * Los criterios de asignaci�n de control:
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14 * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
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15 * Se sabe que la entrada ser� casi siempre alta.
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16 * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
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17 * Se sabe que la entrada ser� casi siempre baja.
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18 * WiredAndpull: Para evitar cortos de una salida al exterior del board.
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19 * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board).
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20 * \
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21 */
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22
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23 #define F_CPU 32000000UL
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24 #include <avr/io.h>
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25
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26 #include "Ports.h"
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27 #include "commSPI_ADC.h"
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28
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29 inline void config_puertos(void){
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30 //Configuracion pines del puerto A: PA7-PA0
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31 //Pines de entrada y totem_pullup
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32 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
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33 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
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34 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
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35 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
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36 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
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37 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
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38 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
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39 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
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40 //Pin de salida A0
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41 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
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42 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
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43 //Valor por defecto salida: PA0 = low
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44 PORTA.DIRSET = PIN0_bm;
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45 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
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46 PORTA.OUTCLR = PIN0_bm;
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47
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48 //Configuracion pines del puerto B: PB3-PB0
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49 //Pines de entrada y totem_pullup
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50 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
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51 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
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52 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
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53 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
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54 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
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55
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56 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
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57 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
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58 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
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59 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
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60 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
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61 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
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62 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
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63 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
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64 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
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65 //Pines de salida wiredand-pull
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66 //Valor por defecto salida: PC4,PC7 = low
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67 //Valor por defecto salida: PC5 = set
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68 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
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69 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
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70 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
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71 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
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72 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
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73 PORTSPI.OUTCLR = SPI_MOSI_bm;
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74
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75 //Configuracion pines del puerto D: PD7-PD0
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76 //Pines de entrada y totem_pullup: PIN7 y PIN0
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77 //NOTA
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78 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
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79 //NOTA FIN
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80 PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm;
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81 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
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82 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
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83 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
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84 PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
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85 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
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86 //Pines de salida tipo wired-and-pull
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87 //Valor por defecto PD6, PD5, PD4, PD3 = low
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88 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
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89 PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc;
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90 PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc;
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91 PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc;
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92 PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc;
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93 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
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94
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95 //Configuracion pines del puerto E: PE3-PE0
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96 //Pines de entrada y totem_pullup: PIN3 - PIN0
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97 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
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98 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
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99 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
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100 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
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101 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
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102
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103 //Configuracion pines del puerto R: PR1-PR0
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104 //Pines de entrada y totem_pulldown: PIN0
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105 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
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106 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
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107 //Pines de entrada y totem_pulldup:PIN1
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108 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
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109
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110 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
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111
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112 PORTSPI.INT0MASK = SPI_MISO_bm;
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113 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
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114 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
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115
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116 } No newline at end of file
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1 /*
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2 * Ports.h
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3 *
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4 * Created: 23/11/15 13:55:28
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5 * Author: Francisco
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6 */
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7
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8
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9 #ifndef PORTS_H_
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10 #define PORTS_H_
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11
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12 #define F_CPU 32000000UL
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13 #include <avr/io.h>
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14
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15 #define INT_RDY PORTC_INT0_vect
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16
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17 void config_puertos(void);
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18
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19
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20
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21 #endif /* PORTS_H_ */ No newline at end of file
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1 /*
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2 * commSPI_ADC.c
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3 *
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4 * Created: 23/11/15 14:08:25
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5 * Author: Francisco
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6 */
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7
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8
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9 #define F_CPU 32000000UL
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10 #include <avr/io.h>
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11 #include "commSPI_ADC.h"
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12
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13 /*!
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14 * \fn config_spiparm
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15 * \brief Configuraci�n de los par�metros de reloj SPI
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16 *
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17 * fspi = fper/2 = fcpu/2 = 16MHz
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18 *
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19 * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una
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20 * nueva evaluaci�n
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21 * \
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22 */
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23 inline void config_spiparm(void){
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24 // Preescaler: clkper/2 = f_cpu/2.
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25 // Master
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26 // Mode 3: CPOL=1,CPHA=1
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27 // MSB --- LSB
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28 SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm |
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29 SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm;
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30 }
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31 No newline at end of file
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1 /*
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2 * commSPI_ADC.h
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3 *
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4 * Created: 23/11/15 14:06:45
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5 * Author: Francisco
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6 */
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7
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8
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9 #ifndef COMMSPI_ADC_H_
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10 #define COMMSPI_ADC_H_
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11
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12 #define F_CPU 32000000UL
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13 #include <avr/io.h>
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14
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15 #include "Ports.h"
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16
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17 #define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI
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18
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19 #define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS
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20 #define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI
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21 #define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO
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22 #define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK
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23
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24 #define SPI_SS_bm PIN4_bm // Pin de entrada - Totem
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25 #define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem
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26 #define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem
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27 #define SPI_SCK_bm PIN7_bm // Pin de salida - Totem
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28
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29 void config_spiparm(void);
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30
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31
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32 #endif /* COMMSPI_ADC_H_ */ No newline at end of file
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1 /*
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2 * fpga_port.c
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3 *
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4 * Created: 23/11/15 14:33:16
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5 * Author: Francisco
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6 */
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7
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8 #define F_CPU 32000000UL
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9 #include <avr/io.h>
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10
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11 #include "fpga_port.h"
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12
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13 inline void config_fpgaport()
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14 {
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15 //Configuracion pines del puerto D: PD6-PA1
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16 //Pines de entrada CLK_FPGA, LOCK_FPGA
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17 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
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18 PORT_FPGA.DIRCLR = LOCK_FPGA;
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19 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
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20 PORT_FPGA.DIRSET = CLK_FPGA;
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21 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc;
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22 PORT_FPGA.OUTSET = CLK_FPGA;
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23
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24 //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
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25 PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
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26 PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc;
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27 PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
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28
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29 //Configuracion pines del puerto B: PPS
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30 //Pines de entrada PPS_FPGA
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31 //Pines de entrada en pulldown
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32 PORT_PPS.DIRCLR = PPS_FPGA;
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33 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
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34
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35 //Configuracion pines del puerto A: LOCKOUT
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36 //Pines de salida LOCK_OUT
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37 //Pines de salida en baja
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38 PORT_LOCKOUT.DIRSET = LOCK_OUT;
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39 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
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40
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41
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42
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43 //Configuracion de interrupciones de LOCK_FPGA
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44
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45 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
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46 PORT_FPGA.INT0MASK = LOCK_FPGA;
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47 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
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48
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49 //Configuracion de interrupciones de CLK
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50 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
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51 //PORT_FPGA.INT1MASK = CLK_FPGA;
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52 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
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53
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54 //Configuracion de interrupciones de PPS
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55 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
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56 PORT_PPS.INT1MASK = PPS_FPGA;
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57 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
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58 }
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59
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60 void habilitar_interrupciones( uint8_t level_mask )
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61 {
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62 PMIC.CTRL = level_mask;
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63 }
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64
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65 void habilitar_interrupciones_globales( void )
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66 {
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67 sei();
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68 }
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69
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70 void deshabilitar_interrupciones_globales( void )
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71 {
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72 cli();
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73 }
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74
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75 void envio_nibble(uint8_t fpga_dato)
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76 {
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77 PORT_FPGA.OUTCLR = CLK_FPGA;
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78 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp);
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79 PORT_FPGA.OUTSET = CLK_FPGA;
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80 //asm("nop");
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81 PORT_FPGA.OUTCLR = CLK_FPGA;
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82 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp);
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83 PORT_FPGA.OUTSET = CLK_FPGA;
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84
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85 }
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86
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87 void envio_datos_fpga(void)
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88 {
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89 uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ;
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90 adcport_read_data(fpga_dato,ADC_DATASZ);
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91 aux_dato[0] = fpga_dato[0];
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92 aux_dato[1] = fpga_dato[1];
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93 aux_dato[2] = fpga_dato[2];
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94 adcport_read_data(fpga_dato,ADC_DATASZ);
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95
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96 envio_dato_adc(aux_dato);
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97 envio_dato_adc(fpga_dato);
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98 }
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99
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100 void envio_dato_adc(uint8_t* dato_adc)
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101 {
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102 for(int i=0; i<3 ; i++)
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103 envio_nibble(dato_adc[i]);
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104 }
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105 /*
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106 __attribute__((noinline)) void delay_nop(void)
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107 {
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108 asm("nop");
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109 }
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110 */
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111 No newline at end of file
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1 /*
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2 * fpga_port.h
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3 *
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4 * Created: 23/11/15 14:20:25
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5 * Author: Francisco
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6 */
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7
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8
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9 #ifndef FPGA_PORT_H_
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10 #define FPGA_PORT_H_
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11
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12 #define F_CPU 32000000UL
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13 #include <avr/io.h>
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14 #include <avr/interrupt.h>
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15 #include "ADC_7176_2.h"
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16
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17 //Port B
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18 #define PORT_PPS PORTB
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19 #define PPS_FPGA PIN2_bm
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20 #define PPS_FPGA_CTRL PIN2CTRL
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21 #define INT_PPS PORTB_INT1_vect
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22
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23 //Port A
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24 #define PORT_LOCKOUT PORTA
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25 #define LOCK_OUT PIN0_bm
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26
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27
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28 //Port D
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29 #define PORT_FPGA PORTD
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30 #define LOCK_FPGA PIN1_bm
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31 #define CLK_FPGA PIN2_bm
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32 #define CH_BIT0_FPGA PIN3_bm
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33 #define CH_BIT1_FPGA PIN4_bm
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34 #define CH_BIT2_FPGA PIN5_bm
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35 #define CH_BIT3_FPGA PIN6_bm
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36 #define INT_LOCK_FPGA PORTD_INT0_vect
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37
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38 #define LOCK_FPGA_CTRL PIN1CTRL
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39 #define CLK_FPGA_CTRL PIN2CTRL
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40 #define CH_BIT0_FPGA_CTRL PIN3CTRL
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41 #define CH_BIT1_FPGA_CTRL PIN4CTRL
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42 #define CH_BIT2_FPGA_CTRL PIN5CTRL
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43 #define CH_BIT3_FPGA_CTRL PIN6CTRL
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44
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45 void config_fpgaport();
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46 void habilitar_interrupciones( uint8_t level_mask );
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47 void habilitar_interrupciones_globales( );
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48 void deshabilitar_interrupciones_globales( );
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49
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50 //Habilitar
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51 #define hab_prioridad_alta PMIC_HILVLEN_bm
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52 #define hab_prioridad_media PMIC_MEDLVLEN_bm
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53 #define hab_prioridad_baja PMIC_LOLVLEN_bm
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54
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55 //M�scara de nibbles
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56 #define nibble_alto_bm 0xF0
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57 #define nibble_bajo_bm 0x0F
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58 #define fpga_salidas_bp 3
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59 #define fpga_salidas_bm 0x38
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60
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61 //funciones de env�o de datos
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62 void envio_nibble(uint8_t fpga_dato);
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63
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64 //funcion interrupcion por flanco de subida de RDY
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65 void envio_datos_fpga(void);
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66 void envio_dato_adc(uint8_t* dato_adc);
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67
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68 #endif /* FPGA_PORT_H_ */ No newline at end of file
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1 /*
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2 * ADCSPI_ver01.c
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3 *
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4 * Created: 26/10/15 12:02:22
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5 * Author : Francisco
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6 */
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7
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8 #define F_CPU 32000000UL
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9 #include <avr/io.h>
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10 #include "Ports.h"
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11 #include "commSPI_ADC.h"
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12 #include "sys_clock.h"
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13 #include "ADC_7176_2.h"
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14 #include "fpga_port.h"
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15
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16
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17 int main(void)
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18 {
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19 //uint8_t datos_adc[3];
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20 config_puertos();
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21 config_sysclock();
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22 config_spiparm();
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23 config_fpgaport();
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24
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25 //datos_adc[0] = 0x00;
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26 //datos_adc[1] = 0x00;
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27 //datos_adc[2] = 0x00;
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28 //PORTD.OUTSET = PIN5_bm;
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29
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30 PMIC.CTRL = hab_prioridad_alta;
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31 habilitar_interrupciones_globales();
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32
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33 /* Replace with your application code */
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34 while (1)
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35 {
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36 if (test_adc() == ADC_ID){
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37 PORTD.OUTSET = PIN6_bm | PIN5_bm;
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38 }
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39 //test_adc_2(datos_adc);
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40 //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){
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41 //PORTD.OUTSET = PIN4_bm;
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42 //}
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43 }
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44 return 0;
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45 }
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46
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47
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48 ISR(INT_LOCK_FPGA)
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49 {
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50 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
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51 {
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52 PMIC.CTRL |= hab_prioridad_media;
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53 PORT_LOCKOUT.OUTSET = LOCK_OUT;
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54 }
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55 else
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56 {
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57 PMIC.CTRL &= ~hab_prioridad_media;
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58 PMIC.CTRL &= ~hab_prioridad_baja;
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59 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
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60 }
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61 }
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62
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63 ISR(INT_PPS)
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64 {
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65 if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA)
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66 PMIC.CTRL |= hab_prioridad_baja;
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67 else
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68 PMIC.CTRL &= ~hab_prioridad_baja;
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69 }
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70
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71 ISR(INT_RDY)
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72 {
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73 envio_datos_fpga();
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74 }
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75
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76
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77 No newline at end of file
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1 /*
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2 * sys_clock.c
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3 *
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4 * Created: 23/11/15 14:04:36
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5 * Author: Francisco
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6 */
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7
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8
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9 /*!
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10 * \fn config_sysclock
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11 * \brief Configuraci�n del reloj interno del sistema
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12 * Reloj interno
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13 * fsys = 32MHz
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14 *
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15 * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL
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16 * \
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17 */
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18
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19 #define F_CPU 32000000UL
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20 #include <avr/io.h>
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21
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22 void config_sysclock(void){
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23
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24 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz
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25 do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj
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26 do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj
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27 CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla
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28 //con instrucciones en assembler
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29 CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler
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30 DFLLRC32M.CTRL = DFLL_ENABLE_bm;
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31 OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K
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32 OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno
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33 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
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34 OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
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35
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36 /*
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37 CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1
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38 OSC_XOSCCTRL = OSC_XOSCSEL_EXTCLK_gc; //usar external clock
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39
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40 OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | ( 0x02 & OSC_PLLFAC_gm);
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41
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42 OSC_CTRL |= OSC_PLLEN_bm; //usar external clock
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43 while(!(OSC_STATUS & OSC_XOSCRDY_bm));
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44 while(!(OSC_STATUS & OSC_PLLRDY_bm));
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45
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46 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
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47 CLK_CTRL = (CLK_SCLKSEL_PLL_gc) & CLK_SCLKSEL_gm; //CLK usa oscilador externo
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48
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49 OSC_CTRL &= ~OSC_RC2MEN_bm;
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50
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51 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
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52 OSC_XOSCFAIL = (OSC_PLLFDEN_bm)|(OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
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53 */
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54
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55 } No newline at end of file
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1 /*
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2 * sys_clock.h
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3 *
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4 * Created: 23/11/15 14:03:16
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5 * Author: Francisco
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6 */
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7
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8
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9 #ifndef SYS_CLOCK_H_
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10 #define SYS_CLOCK_H_
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11
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12
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13 #define F_CPU 32000000UL
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14 #include <avr/io.h>
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15
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16 void config_sysclock(void);
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17
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18
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19
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20 #endif /* SYS_CLOCK_H_ */ No newline at end of file
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1 En esta primera versi�n los activadores de interrupciones son LOCK y PPS.
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2 LOCK activa la interrupci�n deprioridad media.
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3 PPS activa la interrupci�n de prioridad baja.
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4 No newline at end of file
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