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Se añade primera versión del módulo del módulo de adquisición. Revisar las notas de versión. Posiblemente tenga bugs de sincronización en casos de PPS cercal LOCK.
lgonzales -
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1 
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161 </Project> No newline at end of file
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1 /*
2 * ADC_7176_2.c
3 *
4 * Created: 23/11/15 14:01:02
5 * Author: Francisco
6 */
7
8 /*!
9 * \fn test_adc
10 * \brief Lectura de ID del adc
11 *
12 * Lectura esperada: 0x0C94
13 *
14 * Esta funci�n tiene como fin probar la comunicaci�n on el ADC
15 *
16 #define ADC_WENbar_bm (1<<7)
17 #define ADC_RWbar_bm (1<<6)
18 #define ADC_ADDR_READ_ID 0x07
19 * \
20 */
21
22 #define F_CPU 32000000UL
23 #include <avr/io.h>
24 #include "ADC_7176_2.h"
25
26 inline uint16_t test_adc(void){
27 uint16_t aux;
28 PORTSPI.OUTCLR = SPI_SS_bm;
29 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
30 aux = adcport_tranceiv(0);
31 aux = (aux << 8) | adcport_tranceiv(0);
32 PORTSPI.OUTSET = SPI_SS_bm;
33 return aux;
34 }
35
36 inline void test_adc_2(uint8_t* dato){
37 PORTSPI.OUTCLR = SPI_SS_bm;
38 adcport_read_data(dato,ADC_DATASZ);
39 PORTSPI.OUTSET = SPI_SS_bm;
40 }
41 /*!
42 * \fn adcport_tranceiv
43 * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y
44 * el microcontrolador.
45 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
46 * transmision genera clock en el pin "sclk"
47 * \param El dato a transmitir
48 * \return El dato leido del ADC
49 */
50 inline uint8_t adcport_tranceiv(uint8_t data){
51 //
52 SPIC.DATA = data;
53
54 //Wait until transmission complete
55 while( !(SPIC.STATUS & SPI_IF_bm));
56
57 // Return received data
58
59 return SPIC.DATA;
60 }
61
62 /*!
63 * \fn adcport_readdata
64 * \brief Realiza la lectura de datos en modo de conversi�n continua
65 * el microcontrolador.
66 * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la
67 * transmision genera clock en el pin "sclk"
68 * \param La direcci�n del puntero a dato
69 * \return Ninguno s�lo se llena el puntero al dato
70 */
71 inline void adcport_read_data(uint8_t* dato,int j)
72 {
73
74 //Env�o del comando de lectura de datos 0x44
75 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
76
77 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
78
79 // Save received data
80 for(int i=0; i<j ; i++)
81 dato[j-i-1] = adcport_tranceiv(0);
82 }
83
84 void config_adc(void)
85 {
86 adcport_write_filtcon0();
87 //adcport_write_interfmode();
88
89 }
90
91 void adcport_write_filtcon0(void)
92 {
93 adcport_tranceiv((ADC_FILTCON0) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
94 adcport_tranceiv(0);
95 adcport_tranceiv((0b00<<ADC_FILT0_ORDER0_bp)|(0b01010<<ADC_FILT0_ODR0_bp));
96 }
97
98 void adcport_write_interfmode(void)
99 {
100 adcport_tranceiv((ADC_INTERFMODE) & (~ADC_WENbar_bm | ~ADC_RWbar_bm));
101 adcport_tranceiv(0);
102 adcport_tranceiv((1<<ADC_CONTREAD_bp)|(1<<ADC_WL16_bp));
103 } No newline at end of file
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1 /*
2 * ADC_7176_2.h
3 *
4 * Created: 23/11/15 13:59:46
5 * Author: Francisco
6 */
7
8
9 #ifndef ADC_7176_2_H_
10 #define ADC_7176_2_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14 #include "Ports.h"
15 #include "commSPI_ADC.h"
16
17 //ID esperada
18 //tama�o 16 bits
19 //Valor 0x0C94
20 #define ADC_ID 0x0C94
21 #define ADC_RD 0x04
22 #define ADC_FILTCON0 0x28
23 #define ADC_INTERFMODE 0x02
24 #define ADC_DATASZ 3
25
26 //Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n
27 #define ADC_WENbar_bm (1<<7)
28 #define ADC_RWbar_bm (1<<6)
29 #define ADC_ADDR_READ_ID (0x07)
30 #define ADC_FILT0_ORDER0_bp 5
31 #define ADC_FILT0_ODR0_bp 0
32 #define ADC_CONTREAD_bp 7
33 #define ADC_WL16_bp 0
34
35 uint8_t adcport_tranceiv(uint8_t data);
36 void adcport_read_data(uint8_t* dato,int j);
37
38 void adcport_write_filtcon0(void);
39 void adcport_write_interfmode(void);
40
41 uint16_t test_adc(void);
42 void test_adc_2(uint8_t* dato);
43 void config_adc(void);
44
45 #endif /* ADC_7176_2_H_ */ No newline at end of file
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63 :1003E00018951F920F920FB60F9211242F933F93DF
64 :1003F0004F935F936F937F938F939F93AF93BF932D
65 :10040000EF93FF930E946E01FF91EF91BF91AF9127
66 :100410009F918F917F916F915F914F913F912F911C
67 :100420000F900FBE0F901F901895E0E0F6E08EEF52
68 :10043000828388E1878B868B858B848B838B828BF1
69 :10044000818B21E0218398E3908B2683E0E2F6E024
70 :100450003FE03283838B828B818B808BE0E4F6E0FC
71 :100460002FE42283868B838B828B818B808B20EB86
72 :100470002183158A178A148A20E9258320E226839E
73 :10048000A0E6B6E027E812962C93129757968C9325
74 :10049000579750968C93509720E152962C935297F1
75 :1004A00051962C93519748E711964C931197569675
76 :1004B0009C93569755969C93559754969C93549716
77 :1004C00053969C93539716964C93A0E8B6E01296D9
78 :1004D0003C93129753968C93539752968C935297C2
79 :1004E00051968C93519750968C93A0EEB7E093E081
80 :1004F00012969C93129751962C93519750968C93E9
81 :1005000080E4828781858C7F816081878689887F6E
82 :100510008260868B0895E0E5F0E0808186608083CC
83 :10052000818181FFFDCFE0E5F0E0818182FFFDCF99
84 :1005300028ED24BFE0E4F0E080818160808391E0D9
85 :1005400090936000E0E5F0E08681168280818E7FE6
86 :0E055000808324BF909353000895F894FFCF4A
87 :00000001FF
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1
2 ADCSPI_ver01.elf: file format elf32-avr
3
4 Sections:
5 Idx Name Size VMA LMA File off Algn
6 0 .text 0000055e 00000000 00000000 00000054 2**1
7 CONTENTS, ALLOC, LOAD, READONLY, CODE
8 1 .data 00000000 00802000 00802000 000005b2 2**0
9 CONTENTS, ALLOC, LOAD, DATA
10 2 .comment 00000030 00000000 00000000 000005b2 2**0
11 CONTENTS, READONLY
12 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 000005e4 2**2
13 CONTENTS, READONLY
14 4 .debug_aranges 00000138 00000000 00000000 00000624 2**0
15 CONTENTS, READONLY, DEBUGGING
16 5 .debug_info 000014b5 00000000 00000000 0000075c 2**0
17 CONTENTS, READONLY, DEBUGGING
18 6 .debug_abbrev 00000644 00000000 00000000 00001c11 2**0
19 CONTENTS, READONLY, DEBUGGING
20 7 .debug_line 00000827 00000000 00000000 00002255 2**0
21 CONTENTS, READONLY, DEBUGGING
22 8 .debug_frame 00000278 00000000 00000000 00002a7c 2**2
23 CONTENTS, READONLY, DEBUGGING
24 9 .debug_str 000007d6 00000000 00000000 00002cf4 2**0
25 CONTENTS, READONLY, DEBUGGING
26 10 .debug_loc 000003d0 00000000 00000000 000034ca 2**0
27 CONTENTS, READONLY, DEBUGGING
28 11 .debug_ranges 000000d8 00000000 00000000 0000389a 2**0
29 CONTENTS, READONLY, DEBUGGING
30
31 Disassembly of section .text:
32
33 00000000 <__vectors>:
34 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end>
35 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
36 8: 0c 94 f1 01 jmp 0x3e2 ; 0x3e2 <__vector_2>
37 c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
38 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
39 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
40 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
41 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
42 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
43 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
44 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
45 2c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
46 30: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
47 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
48 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
49 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
50 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
51 44: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
52 48: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
53 4c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
54 50: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
55 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
56 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
57 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
58 60: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
59 64: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
60 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
61 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
62 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
63 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
64 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
65 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
66 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
67 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
68 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
69 8c: 0c 94 d2 01 jmp 0x3a4 ; 0x3a4 <__vector_35>
70 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
71 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
72 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
73 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
74 a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
75 a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
76 a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
77 ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
78 b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
79 b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
80 b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
81 bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
82 c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
83 c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
84 c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
85 cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
86 d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
87 d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
88 d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
89 dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
90 e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
91 e4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
92 e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
93 ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
94 f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
95 f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
96 f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
97 fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
98 100: 0c 94 ad 01 jmp 0x35a ; 0x35a <__vector_64>
99 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
100 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
101 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
102 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
103 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
104 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
105 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
106 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
107 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
108 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
109 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
110 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
111 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
112 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
113 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
114 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
115 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
116 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
117 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
118 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
119 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
120 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
121 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
122 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
123 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
124 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt>
125
126 0000016c <__ctors_end>:
127 16c: 11 24 eor r1, r1
128 16e: 1f be out 0x3f, r1 ; 63
129 170: cf ef ldi r28, 0xFF ; 255
130 172: cd bf out 0x3d, r28 ; 61
131 174: df e2 ldi r29, 0x2F ; 47
132 176: de bf out 0x3e, r29 ; 62
133 178: 0e 94 95 01 call 0x32a ; 0x32a <main>
134 17c: 0c 94 ad 02 jmp 0x55a ; 0x55a <_exit>
135
136 00000180 <__bad_interrupt>:
137 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors>
138
139 00000184 <test_adc>:
140 #include <avr/io.h>
141 #include "ADC_7176_2.h"
142
143 inline uint16_t test_adc(void){
144 uint16_t aux;
145 PORTSPI.OUTCLR = SPI_SS_bm;
146 184: 80 e1 ldi r24, 0x10 ; 16
147 186: 80 93 46 06 sts 0x0646, r24
148 * \param El dato a transmitir
149 * \return El dato leido del ADC
150 */
151 inline uint8_t adcport_tranceiv(uint8_t data){
152 //
153 SPIC.DATA = data;
154 18a: 87 e4 ldi r24, 0x47 ; 71
155 18c: 80 93 c3 08 sts 0x08C3, r24
156
157 //Wait until transmission complete
158 while( !(SPIC.STATUS & SPI_IF_bm));
159 190: e0 ec ldi r30, 0xC0 ; 192
160 192: f8 e0 ldi r31, 0x08 ; 8
161 194: 82 81 ldd r24, Z+2 ; 0x02
162 196: 88 23 and r24, r24
163 198: ec f7 brge .-6 ; 0x194 <test_adc+0x10>
164
165 // Return received data
166
167 return SPIC.DATA;
168 19a: e0 ec ldi r30, 0xC0 ; 192
169 19c: f8 e0 ldi r31, 0x08 ; 8
170 19e: 83 81 ldd r24, Z+3 ; 0x03
171 * \param El dato a transmitir
172 * \return El dato leido del ADC
173 */
174 inline uint8_t adcport_tranceiv(uint8_t data){
175 //
176 SPIC.DATA = data;
177 1a0: 13 82 std Z+3, r1 ; 0x03
178
179 //Wait until transmission complete
180 while( !(SPIC.STATUS & SPI_IF_bm));
181 1a2: 82 81 ldd r24, Z+2 ; 0x02
182 1a4: 88 23 and r24, r24
183 1a6: ec f7 brge .-6 ; 0x1a2 <test_adc+0x1e>
184
185 // Return received data
186
187 return SPIC.DATA;
188 1a8: e0 ec ldi r30, 0xC0 ; 192
189 1aa: f8 e0 ldi r31, 0x08 ; 8
190 1ac: 23 81 ldd r18, Z+3 ; 0x03
191
192 inline uint16_t test_adc(void){
193 uint16_t aux;
194 PORTSPI.OUTCLR = SPI_SS_bm;
195 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
196 aux = adcport_tranceiv(0);
197 1ae: 30 e0 ldi r19, 0x00 ; 0
198 aux = (aux << 8) | adcport_tranceiv(0);
199 1b0: 32 2f mov r19, r18
200 1b2: 22 27 eor r18, r18
201 * \param El dato a transmitir
202 * \return El dato leido del ADC
203 */
204 inline uint8_t adcport_tranceiv(uint8_t data){
205 //
206 SPIC.DATA = data;
207 1b4: 13 82 std Z+3, r1 ; 0x03
208
209 //Wait until transmission complete
210 while( !(SPIC.STATUS & SPI_IF_bm));
211 1b6: 92 81 ldd r25, Z+2 ; 0x02
212 1b8: 99 23 and r25, r25
213 1ba: ec f7 brge .-6 ; 0x1b6 <test_adc+0x32>
214
215 // Return received data
216
217 return SPIC.DATA;
218 1bc: 80 91 c3 08 lds r24, 0x08C3
219 uint16_t aux;
220 PORTSPI.OUTCLR = SPI_SS_bm;
221 adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm));
222 aux = adcport_tranceiv(0);
223 aux = (aux << 8) | adcport_tranceiv(0);
224 PORTSPI.OUTSET = SPI_SS_bm;
225 1c0: 90 e1 ldi r25, 0x10 ; 16
226 1c2: 90 93 45 06 sts 0x0645, r25
227 return aux;
228 }
229 1c6: a9 01 movw r20, r18
230 1c8: 48 2b or r20, r24
231 1ca: ca 01 movw r24, r20
232 1cc: 08 95 ret
233
234 000001ce <adcport_read_data>:
235 * transmision genera clock en el pin "sclk"
236 * \param La direcci�n del puntero a dato
237 * \return Ninguno s�lo se llena el puntero al dato
238 */
239 inline void adcport_read_data(uint8_t* dato,int j)
240 {
241 1ce: 9c 01 movw r18, r24
242 * \param El dato a transmitir
243 * \return El dato leido del ADC
244 */
245 inline uint8_t adcport_tranceiv(uint8_t data){
246 //
247 SPIC.DATA = data;
248 1d0: 84 e4 ldi r24, 0x44 ; 68
249 1d2: 80 93 c3 08 sts 0x08C3, r24
250
251 //Wait until transmission complete
252 while( !(SPIC.STATUS & SPI_IF_bm));
253 1d6: e0 ec ldi r30, 0xC0 ; 192
254 1d8: f8 e0 ldi r31, 0x08 ; 8
255 1da: 92 81 ldd r25, Z+2 ; 0x02
256 1dc: 99 23 and r25, r25
257 1de: ec f7 brge .-6 ; 0x1da <adcport_read_data+0xc>
258
259 // Return received data
260
261 return SPIC.DATA;
262 1e0: 80 91 c3 08 lds r24, 0x08C3
263 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
264
265 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
266
267 // Save received data
268 for(int i=0; i<j ; i++)
269 1e4: 16 16 cp r1, r22
270 1e6: 17 06 cpc r1, r23
271 1e8: 74 f4 brge .+28 ; 0x206 <adcport_read_data+0x38>
272 1ea: d9 01 movw r26, r18
273 1ec: a6 0f add r26, r22
274 1ee: b7 1f adc r27, r23
275 * \param El dato a transmitir
276 * \return El dato leido del ADC
277 */
278 inline uint8_t adcport_tranceiv(uint8_t data){
279 //
280 SPIC.DATA = data;
281 1f0: e0 ec ldi r30, 0xC0 ; 192
282 1f2: f8 e0 ldi r31, 0x08 ; 8
283 1f4: 13 82 std Z+3, r1 ; 0x03
284
285 //Wait until transmission complete
286 while( !(SPIC.STATUS & SPI_IF_bm));
287 1f6: 92 81 ldd r25, Z+2 ; 0x02
288 1f8: 99 23 and r25, r25
289 1fa: ec f7 brge .-6 ; 0x1f6 <adcport_read_data+0x28>
290
291 // Return received data
292
293 return SPIC.DATA;
294 1fc: 93 81 ldd r25, Z+3 ; 0x03
295
296 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
297
298 // Save received data
299 for(int i=0; i<j ; i++)
300 dato[j-i-1] = adcport_tranceiv(0);
301 1fe: 9e 93 st -X, r25
302 adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm));
303
304 //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0)
305
306 // Save received data
307 for(int i=0; i<j ; i++)
308 200: a2 17 cp r26, r18
309 202: b3 07 cpc r27, r19
310 204: b9 f7 brne .-18 ; 0x1f4 <adcport_read_data+0x26>
311 206: 08 95 ret
312
313 00000208 <config_spiparm>:
314 inline void config_spiparm(void){
315 // Preescaler: clkper/2 = f_cpu/2.
316 // Master
317 // Mode 3: CPOL=1,CPHA=1
318 // MSB --- LSB
319 SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm |
320 208: 8c ed ldi r24, 0xDC ; 220
321 20a: 80 93 c0 08 sts 0x08C0, r24
322 20e: 08 95 ret
323
324 00000210 <config_fpgaport>:
325 #include <avr/io.h>
326
327 #include "fpga_port.h"
328
329 inline void config_fpgaport()
330 {
331 210: cf 93 push r28
332 212: df 93 push r29
333 //Configuracion pines del puerto D: PD6-PA1
334 //Pines de entrada CLK_FPGA, LOCK_FPGA
335 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
336 PORT_FPGA.DIRCLR = LOCK_FPGA;
337 214: e0 e6 ldi r30, 0x60 ; 96
338 216: f6 e0 ldi r31, 0x06 ; 6
339 218: 22 e0 ldi r18, 0x02 ; 2
340 21a: 22 83 std Z+2, r18 ; 0x02
341 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
342 21c: 80 e1 ldi r24, 0x10 ; 16
343 21e: 81 8b std Z+17, r24 ; 0x11
344 PORT_FPGA.DIRSET = CLK_FPGA;
345 220: 94 e0 ldi r25, 0x04 ; 4
346 222: 91 83 std Z+1, r25 ; 0x01
347 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc;
348 224: 38 e1 ldi r19, 0x18 ; 24
349 226: 32 8b std Z+18, r19 ; 0x12
350 PORT_FPGA.OUTSET = CLK_FPGA;
351 228: 95 83 std Z+5, r25 ; 0x05
352
353 //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
354 PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
355 22a: 38 e7 ldi r19, 0x78 ; 120
356 22c: 31 83 std Z+1, r19 ; 0x01
357 PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc;
358 22e: 13 8a std Z+19, r1 ; 0x13
359 PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
360 230: 35 83 std Z+5, r19 ; 0x05
361
362 //Configuracion pines del puerto B: PPS
363 //Pines de entrada PPS_FPGA
364 //Pines de entrada en pulldown
365 PORT_PPS.DIRCLR = PPS_FPGA;
366 232: a0 e2 ldi r26, 0x20 ; 32
367 234: b6 e0 ldi r27, 0x06 ; 6
368 236: 12 96 adiw r26, 0x02 ; 2
369 238: 9c 93 st X, r25
370 23a: 12 97 sbiw r26, 0x02 ; 2
371 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
372 23c: 52 96 adiw r26, 0x12 ; 18
373 23e: 8c 93 st X, r24
374 240: 52 97 sbiw r26, 0x12 ; 18
375
376 //Configuracion pines del puerto A: LOCKOUT
377 //Pines de salida LOCK_OUT
378 //Pines de salida en baja
379 PORT_LOCKOUT.DIRSET = LOCK_OUT;
380 242: c0 e0 ldi r28, 0x00 ; 0
381 244: d6 e0 ldi r29, 0x06 ; 6
382 246: 81 e0 ldi r24, 0x01 ; 1
383 248: 89 83 std Y+1, r24 ; 0x01
384 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
385 24a: 8e 83 std Y+6, r24 ; 0x06
386
387
388
389 //Configuracion de interrupciones de LOCK_FPGA
390
391 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
392 24c: 81 85 ldd r24, Z+9 ; 0x09
393 24e: 83 60 ori r24, 0x03 ; 3
394 250: 81 87 std Z+9, r24 ; 0x09
395 PORT_FPGA.INT0MASK = LOCK_FPGA;
396 252: 22 87 std Z+10, r18 ; 0x0a
397 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
398 254: 81 89 ldd r24, Z+17 ; 0x11
399 256: 88 7f andi r24, 0xF8 ; 248
400 258: 81 8b std Z+17, r24 ; 0x11
401 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
402 //PORT_FPGA.INT1MASK = CLK_FPGA;
403 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
404
405 //Configuracion de interrupciones de PPS
406 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
407 25a: 81 85 ldd r24, Z+9 ; 0x09
408 25c: 83 7f andi r24, 0xF3 ; 243
409 25e: 88 60 ori r24, 0x08 ; 8
410 260: 19 96 adiw r26, 0x09 ; 9
411 262: 8c 93 st X, r24
412 264: 19 97 sbiw r26, 0x09 ; 9
413 PORT_PPS.INT1MASK = PPS_FPGA;
414 266: 1b 96 adiw r26, 0x0b ; 11
415 268: 9c 93 st X, r25
416 26a: 1b 97 sbiw r26, 0x0b ; 11
417 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
418 26c: 52 96 adiw r26, 0x12 ; 18
419 26e: 8c 91 ld r24, X
420 270: 52 97 sbiw r26, 0x12 ; 18
421 272: 88 7f andi r24, 0xF8 ; 248
422 274: 81 60 ori r24, 0x01 ; 1
423 276: 52 96 adiw r26, 0x12 ; 18
424 278: 8c 93 st X, r24
425 }
426 27a: df 91 pop r29
427 27c: cf 91 pop r28
428 27e: 08 95 ret
429
430 00000280 <habilitar_interrupciones_globales>:
431 PMIC.CTRL = level_mask;
432 }
433
434 void habilitar_interrupciones_globales( void )
435 {
436 sei();
437 280: 78 94 sei
438 282: 08 95 ret
439
440 00000284 <envio_nibble>:
441 cli();
442 }
443
444 void envio_nibble(uint8_t fpga_dato)
445 {
446 PORT_FPGA.OUTCLR = CLK_FPGA;
447 284: e0 e6 ldi r30, 0x60 ; 96
448 286: f6 e0 ldi r31, 0x06 ; 6
449 288: 24 e0 ldi r18, 0x04 ; 4
450 28a: 26 83 std Z+6, r18 ; 0x06
451 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp);
452 28c: 94 81 ldd r25, Z+4 ; 0x04
453 28e: 38 2f mov r19, r24
454 290: 30 7f andi r19, 0xF0 ; 240
455 292: 33 0f add r19, r19
456 294: 33 0f add r19, r19
457 296: 33 0f add r19, r19
458 298: 98 73 andi r25, 0x38 ; 56
459 29a: 93 2b or r25, r19
460 29c: 94 83 std Z+4, r25 ; 0x04
461 PORT_FPGA.OUTSET = CLK_FPGA;
462 29e: 25 83 std Z+5, r18 ; 0x05
463 //asm("nop");
464 PORT_FPGA.OUTCLR = CLK_FPGA;
465 2a0: 26 83 std Z+6, r18 ; 0x06
466 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp);
467 2a2: 94 81 ldd r25, Z+4 ; 0x04
468 2a4: 8f 70 andi r24, 0x0F ; 15
469 2a6: 88 0f add r24, r24
470 2a8: 88 0f add r24, r24
471 2aa: 88 0f add r24, r24
472 2ac: 98 73 andi r25, 0x38 ; 56
473 2ae: 89 2b or r24, r25
474 2b0: 84 83 std Z+4, r24 ; 0x04
475 PORT_FPGA.OUTSET = CLK_FPGA;
476 2b2: 25 83 std Z+5, r18 ; 0x05
477 2b4: 08 95 ret
478
479 000002b6 <envio_dato_adc>:
480 envio_dato_adc(aux_dato);
481 envio_dato_adc(fpga_dato);
482 }
483
484 void envio_dato_adc(uint8_t* dato_adc)
485 {
486 2b6: 0f 93 push r16
487 2b8: 1f 93 push r17
488 2ba: cf 93 push r28
489 2bc: df 93 push r29
490 2be: ec 01 movw r28, r24
491 2c0: 8c 01 movw r16, r24
492 2c2: 0d 5f subi r16, 0xFD ; 253
493 2c4: 1f 4f sbci r17, 0xFF ; 255
494 for(int i=0; i<3 ; i++)
495 envio_nibble(dato_adc[i]);
496 2c6: 89 91 ld r24, Y+
497 2c8: 0e 94 42 01 call 0x284 ; 0x284 <envio_nibble>
498 envio_dato_adc(fpga_dato);
499 }
500
501 void envio_dato_adc(uint8_t* dato_adc)
502 {
503 for(int i=0; i<3 ; i++)
504 2cc: c0 17 cp r28, r16
505 2ce: d1 07 cpc r29, r17
506 2d0: d1 f7 brne .-12 ; 0x2c6 <envio_dato_adc+0x10>
507 envio_nibble(dato_adc[i]);
508 }
509 2d2: df 91 pop r29
510 2d4: cf 91 pop r28
511 2d6: 1f 91 pop r17
512 2d8: 0f 91 pop r16
513 2da: 08 95 ret
514
515 000002dc <envio_datos_fpga>:
516 PORT_FPGA.OUTSET = CLK_FPGA;
517
518 }
519
520 void envio_datos_fpga(void)
521 {
522 2dc: cf 93 push r28
523 2de: df 93 push r29
524 2e0: cd b7 in r28, 0x3d ; 61
525 2e2: de b7 in r29, 0x3e ; 62
526 2e4: 26 97 sbiw r28, 0x06 ; 6
527 2e6: cd bf out 0x3d, r28 ; 61
528 2e8: de bf out 0x3e, r29 ; 62
529 uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ;
530 adcport_read_data(fpga_dato,ADC_DATASZ);
531 2ea: 63 e0 ldi r22, 0x03 ; 3
532 2ec: 70 e0 ldi r23, 0x00 ; 0
533 2ee: ce 01 movw r24, r28
534 2f0: 01 96 adiw r24, 0x01 ; 1
535 2f2: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data>
536 aux_dato[0] = fpga_dato[0];
537 2f6: 89 81 ldd r24, Y+1 ; 0x01
538 2f8: 8c 83 std Y+4, r24 ; 0x04
539 aux_dato[1] = fpga_dato[1];
540 2fa: 8a 81 ldd r24, Y+2 ; 0x02
541 2fc: 8d 83 std Y+5, r24 ; 0x05
542 aux_dato[2] = fpga_dato[2];
543 2fe: 8b 81 ldd r24, Y+3 ; 0x03
544 300: 8e 83 std Y+6, r24 ; 0x06
545 adcport_read_data(fpga_dato,ADC_DATASZ);
546 302: 63 e0 ldi r22, 0x03 ; 3
547 304: 70 e0 ldi r23, 0x00 ; 0
548 306: ce 01 movw r24, r28
549 308: 01 96 adiw r24, 0x01 ; 1
550 30a: 0e 94 e7 00 call 0x1ce ; 0x1ce <adcport_read_data>
551
552 envio_dato_adc(aux_dato);
553 30e: ce 01 movw r24, r28
554 310: 04 96 adiw r24, 0x04 ; 4
555 312: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc>
556 envio_dato_adc(fpga_dato);
557 316: ce 01 movw r24, r28
558 318: 01 96 adiw r24, 0x01 ; 1
559 31a: 0e 94 5b 01 call 0x2b6 ; 0x2b6 <envio_dato_adc>
560 }
561 31e: 26 96 adiw r28, 0x06 ; 6
562 320: cd bf out 0x3d, r28 ; 61
563 322: de bf out 0x3e, r29 ; 62
564 324: df 91 pop r29
565 326: cf 91 pop r28
566 328: 08 95 ret
567
568 0000032a <main>:
569
570
571 int main(void)
572 {
573 //uint8_t datos_adc[3];
574 config_puertos();
575 32a: 0e 94 15 02 call 0x42a ; 0x42a <config_puertos>
576 config_sysclock();
577 32e: 0e 94 8b 02 call 0x516 ; 0x516 <config_sysclock>
578 config_spiparm();
579 332: 0e 94 04 01 call 0x208 ; 0x208 <config_spiparm>
580 config_fpgaport();
581 336: 0e 94 08 01 call 0x210 ; 0x210 <config_fpgaport>
582 //datos_adc[0] = 0x00;
583 //datos_adc[1] = 0x00;
584 //datos_adc[2] = 0x00;
585 //PORTD.OUTSET = PIN5_bm;
586
587 PMIC.CTRL = hab_prioridad_alta;
588 33a: 84 e0 ldi r24, 0x04 ; 4
589 33c: 80 93 a2 00 sts 0x00A2, r24
590 habilitar_interrupciones_globales();
591 340: 0e 94 40 01 call 0x280 ; 0x280 <habilitar_interrupciones_globales>
592
593 /* Replace with your application code */
594 while (1)
595 {
596 if (test_adc() == ADC_ID){
597 PORTD.OUTSET = PIN6_bm | PIN5_bm;
598 344: 00 e6 ldi r16, 0x60 ; 96
599 346: 16 e0 ldi r17, 0x06 ; 6
600 348: c0 e6 ldi r28, 0x60 ; 96
601 habilitar_interrupciones_globales();
602
603 /* Replace with your application code */
604 while (1)
605 {
606 if (test_adc() == ADC_ID){
607 34a: 0e 94 c2 00 call 0x184 ; 0x184 <test_adc>
608 34e: 84 39 cpi r24, 0x94 ; 148
609 350: 9c 40 sbci r25, 0x0C ; 12
610 352: d9 f7 brne .-10 ; 0x34a <main+0x20>
611 PORTD.OUTSET = PIN6_bm | PIN5_bm;
612 354: f8 01 movw r30, r16
613 356: c5 83 std Z+5, r28 ; 0x05
614 358: f8 cf rjmp .-16 ; 0x34a <main+0x20>
615
616 0000035a <__vector_64>:
617 return 0;
618 }
619
620
621 ISR(INT_LOCK_FPGA)
622 {
623 35a: 1f 92 push r1
624 35c: 0f 92 push r0
625 35e: 0f b6 in r0, 0x3f ; 63
626 360: 0f 92 push r0
627 362: 11 24 eor r1, r1
628 364: 8f 93 push r24
629 366: ef 93 push r30
630 368: ff 93 push r31
631 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
632 36a: 80 91 68 06 lds r24, 0x0668
633 36e: 81 ff sbrs r24, 1
634 370: 09 c0 rjmp .+18 ; 0x384 <__vector_64+0x2a>
635 {
636 PMIC.CTRL |= hab_prioridad_media;
637 372: e0 ea ldi r30, 0xA0 ; 160
638 374: f0 e0 ldi r31, 0x00 ; 0
639 376: 82 81 ldd r24, Z+2 ; 0x02
640 378: 82 60 ori r24, 0x02 ; 2
641 37a: 82 83 std Z+2, r24 ; 0x02
642 PORT_LOCKOUT.OUTSET = LOCK_OUT;
643 37c: 81 e0 ldi r24, 0x01 ; 1
644 37e: 80 93 05 06 sts 0x0605, r24
645 382: 08 c0 rjmp .+16 ; 0x394 <__vector_64+0x3a>
646 }
647 else
648 {
649 PMIC.CTRL &= ~hab_prioridad_media;
650 384: e0 ea ldi r30, 0xA0 ; 160
651 386: f0 e0 ldi r31, 0x00 ; 0
652 388: 82 81 ldd r24, Z+2 ; 0x02
653 38a: 8d 7f andi r24, 0xFD ; 253
654 38c: 82 83 std Z+2, r24 ; 0x02
655 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
656 38e: 81 e0 ldi r24, 0x01 ; 1
657 390: 80 93 06 06 sts 0x0606, r24
658 }
659 }
660 394: ff 91 pop r31
661 396: ef 91 pop r30
662 398: 8f 91 pop r24
663 39a: 0f 90 pop r0
664 39c: 0f be out 0x3f, r0 ; 63
665 39e: 0f 90 pop r0
666 3a0: 1f 90 pop r1
667 3a2: 18 95 reti
668
669 000003a4 <__vector_35>:
670
671 ISR(INT_PPS)
672 {
673 3a4: 1f 92 push r1
674 3a6: 0f 92 push r0
675 3a8: 0f b6 in r0, 0x3f ; 63
676 3aa: 0f 92 push r0
677 3ac: 11 24 eor r1, r1
678 3ae: 8f 93 push r24
679 3b0: ef 93 push r30
680 3b2: ff 93 push r31
681 if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA)
682 3b4: 80 91 28 06 lds r24, 0x0628
683 3b8: 82 ff sbrs r24, 2
684 3ba: 06 c0 rjmp .+12 ; 0x3c8 <__vector_35+0x24>
685 PMIC.CTRL |= hab_prioridad_baja;
686 3bc: e0 ea ldi r30, 0xA0 ; 160
687 3be: f0 e0 ldi r31, 0x00 ; 0
688 3c0: 82 81 ldd r24, Z+2 ; 0x02
689 3c2: 81 60 ori r24, 0x01 ; 1
690 3c4: 82 83 std Z+2, r24 ; 0x02
691 3c6: 05 c0 rjmp .+10 ; 0x3d2 <__vector_35+0x2e>
692 else
693 PMIC.CTRL &= ~hab_prioridad_baja;
694 3c8: e0 ea ldi r30, 0xA0 ; 160
695 3ca: f0 e0 ldi r31, 0x00 ; 0
696 3cc: 82 81 ldd r24, Z+2 ; 0x02
697 3ce: 8e 7f andi r24, 0xFE ; 254
698 3d0: 82 83 std Z+2, r24 ; 0x02
699 }
700 3d2: ff 91 pop r31
701 3d4: ef 91 pop r30
702 3d6: 8f 91 pop r24
703 3d8: 0f 90 pop r0
704 3da: 0f be out 0x3f, r0 ; 63
705 3dc: 0f 90 pop r0
706 3de: 1f 90 pop r1
707 3e0: 18 95 reti
708
709 000003e2 <__vector_2>:
710
711 ISR(INT_RDY)
712 {
713 3e2: 1f 92 push r1
714 3e4: 0f 92 push r0
715 3e6: 0f b6 in r0, 0x3f ; 63
716 3e8: 0f 92 push r0
717 3ea: 11 24 eor r1, r1
718 3ec: 2f 93 push r18
719 3ee: 3f 93 push r19
720 3f0: 4f 93 push r20
721 3f2: 5f 93 push r21
722 3f4: 6f 93 push r22
723 3f6: 7f 93 push r23
724 3f8: 8f 93 push r24
725 3fa: 9f 93 push r25
726 3fc: af 93 push r26
727 3fe: bf 93 push r27
728 400: ef 93 push r30
729 402: ff 93 push r31
730 envio_datos_fpga();
731 404: 0e 94 6e 01 call 0x2dc ; 0x2dc <envio_datos_fpga>
732 }
733 408: ff 91 pop r31
734 40a: ef 91 pop r30
735 40c: bf 91 pop r27
736 40e: af 91 pop r26
737 410: 9f 91 pop r25
738 412: 8f 91 pop r24
739 414: 7f 91 pop r23
740 416: 6f 91 pop r22
741 418: 5f 91 pop r21
742 41a: 4f 91 pop r20
743 41c: 3f 91 pop r19
744 41e: 2f 91 pop r18
745 420: 0f 90 pop r0
746 422: 0f be out 0x3f, r0 ; 63
747 424: 0f 90 pop r0
748 426: 1f 90 pop r1
749 428: 18 95 reti
750
751 0000042a <config_puertos>:
752 #include "commSPI_ADC.h"
753
754 inline void config_puertos(void){
755 //Configuracion pines del puerto A: PA7-PA0
756 //Pines de entrada y totem_pullup
757 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
758 42a: e0 e0 ldi r30, 0x00 ; 0
759 42c: f6 e0 ldi r31, 0x06 ; 6
760 42e: 8e ef ldi r24, 0xFE ; 254
761 430: 82 83 std Z+2, r24 ; 0x02
762 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
763 432: 88 e1 ldi r24, 0x18 ; 24
764 434: 87 8b std Z+23, r24 ; 0x17
765 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
766 436: 86 8b std Z+22, r24 ; 0x16
767 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
768 438: 85 8b std Z+21, r24 ; 0x15
769 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
770 43a: 84 8b std Z+20, r24 ; 0x14
771 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
772 43c: 83 8b std Z+19, r24 ; 0x13
773 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
774 43e: 82 8b std Z+18, r24 ; 0x12
775 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
776 440: 81 8b std Z+17, r24 ; 0x11
777 //Pin de salida A0
778 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
779 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
780 //Valor por defecto salida: PA0 = low
781 PORTA.DIRSET = PIN0_bm;
782 442: 21 e0 ldi r18, 0x01 ; 1
783 444: 21 83 std Z+1, r18 ; 0x01
784 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
785 446: 98 e3 ldi r25, 0x38 ; 56
786 448: 90 8b std Z+16, r25 ; 0x10
787 PORTA.OUTCLR = PIN0_bm;
788 44a: 26 83 std Z+6, r18 ; 0x06
789
790 //Configuracion pines del puerto B: PB3-PB0
791 //Pines de entrada y totem_pullup
792 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
793 44c: e0 e2 ldi r30, 0x20 ; 32
794 44e: f6 e0 ldi r31, 0x06 ; 6
795 450: 3f e0 ldi r19, 0x0F ; 15
796 452: 32 83 std Z+2, r19 ; 0x02
797 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
798 454: 83 8b std Z+19, r24 ; 0x13
799 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
800 456: 82 8b std Z+18, r24 ; 0x12
801 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
802 458: 81 8b std Z+17, r24 ; 0x11
803 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
804 45a: 80 8b std Z+16, r24 ; 0x10
805
806 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
807 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
808 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
809 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
810 45c: e0 e4 ldi r30, 0x40 ; 64
811 45e: f6 e0 ldi r31, 0x06 ; 6
812 460: 2f e4 ldi r18, 0x4F ; 79
813 462: 22 83 std Z+2, r18 ; 0x02
814 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
815 464: 86 8b std Z+22, r24 ; 0x16
816 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
817 466: 83 8b std Z+19, r24 ; 0x13
818 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
819 468: 82 8b std Z+18, r24 ; 0x12
820 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
821 46a: 81 8b std Z+17, r24 ; 0x11
822 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
823 46c: 80 8b std Z+16, r24 ; 0x10
824 //Pines de salida wiredand-pull
825 //Valor por defecto salida: PC4,PC7 = low
826 //Valor por defecto salida: PC5 = set
827 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
828 46e: 20 eb ldi r18, 0xB0 ; 176
829 470: 21 83 std Z+1, r18 ; 0x01
830 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
831 472: 15 8a std Z+21, r1 ; 0x15
832 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
833 474: 17 8a std Z+23, r1 ; 0x17
834 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
835 476: 14 8a std Z+20, r1 ; 0x14
836 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
837 478: 20 e9 ldi r18, 0x90 ; 144
838 47a: 25 83 std Z+5, r18 ; 0x05
839 PORTSPI.OUTCLR = SPI_MOSI_bm;
840 47c: 20 e2 ldi r18, 0x20 ; 32
841 47e: 26 83 std Z+6, r18 ; 0x06
842 //Configuracion pines del puerto D: PD7-PD0
843 //Pines de entrada y totem_pullup: PIN7 y PIN0
844 //NOTA
845 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
846 //NOTA FIN
847 PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm;
848 480: a0 e6 ldi r26, 0x60 ; 96
849 482: b6 e0 ldi r27, 0x06 ; 6
850 484: 27 e8 ldi r18, 0x87 ; 135
851 486: 12 96 adiw r26, 0x02 ; 2
852 488: 2c 93 st X, r18
853 48a: 12 97 sbiw r26, 0x02 ; 2
854 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
855 48c: 57 96 adiw r26, 0x17 ; 23
856 48e: 8c 93 st X, r24
857 490: 57 97 sbiw r26, 0x17 ; 23
858 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
859 492: 50 96 adiw r26, 0x10 ; 16
860 494: 8c 93 st X, r24
861 496: 50 97 sbiw r26, 0x10 ; 16
862 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
863 PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
864 498: 20 e1 ldi r18, 0x10 ; 16
865 49a: 52 96 adiw r26, 0x12 ; 18
866 49c: 2c 93 st X, r18
867 49e: 52 97 sbiw r26, 0x12 ; 18
868 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
869 4a0: 51 96 adiw r26, 0x11 ; 17
870 4a2: 2c 93 st X, r18
871 4a4: 51 97 sbiw r26, 0x11 ; 17
872 //Pines de salida tipo wired-and-pull
873 //Valor por defecto PD6, PD5, PD4, PD3 = low
874 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
875 4a6: 48 e7 ldi r20, 0x78 ; 120
876 4a8: 11 96 adiw r26, 0x01 ; 1
877 4aa: 4c 93 st X, r20
878 4ac: 11 97 sbiw r26, 0x01 ; 1
879 PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc;
880 4ae: 56 96 adiw r26, 0x16 ; 22
881 4b0: 9c 93 st X, r25
882 4b2: 56 97 sbiw r26, 0x16 ; 22
883 PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc;
884 4b4: 55 96 adiw r26, 0x15 ; 21
885 4b6: 9c 93 st X, r25
886 4b8: 55 97 sbiw r26, 0x15 ; 21
887 PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc;
888 4ba: 54 96 adiw r26, 0x14 ; 20
889 4bc: 9c 93 st X, r25
890 4be: 54 97 sbiw r26, 0x14 ; 20
891 PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc;
892 4c0: 53 96 adiw r26, 0x13 ; 19
893 4c2: 9c 93 st X, r25
894 4c4: 53 97 sbiw r26, 0x13 ; 19
895 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
896 4c6: 16 96 adiw r26, 0x06 ; 6
897 4c8: 4c 93 st X, r20
898
899 //Configuracion pines del puerto E: PE3-PE0
900 //Pines de entrada y totem_pullup: PIN3 - PIN0
901 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
902 4ca: a0 e8 ldi r26, 0x80 ; 128
903 4cc: b6 e0 ldi r27, 0x06 ; 6
904 4ce: 12 96 adiw r26, 0x02 ; 2
905 4d0: 3c 93 st X, r19
906 4d2: 12 97 sbiw r26, 0x02 ; 2
907 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
908 4d4: 53 96 adiw r26, 0x13 ; 19
909 4d6: 8c 93 st X, r24
910 4d8: 53 97 sbiw r26, 0x13 ; 19
911 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
912 4da: 52 96 adiw r26, 0x12 ; 18
913 4dc: 8c 93 st X, r24
914 4de: 52 97 sbiw r26, 0x12 ; 18
915 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
916 4e0: 51 96 adiw r26, 0x11 ; 17
917 4e2: 8c 93 st X, r24
918 4e4: 51 97 sbiw r26, 0x11 ; 17
919 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
920 4e6: 50 96 adiw r26, 0x10 ; 16
921 4e8: 8c 93 st X, r24
922
923 //Configuracion pines del puerto R: PR1-PR0
924 //Pines de entrada y totem_pulldown: PIN0
925 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
926 4ea: a0 ee ldi r26, 0xE0 ; 224
927 4ec: b7 e0 ldi r27, 0x07 ; 7
928 4ee: 93 e0 ldi r25, 0x03 ; 3
929 4f0: 12 96 adiw r26, 0x02 ; 2
930 4f2: 9c 93 st X, r25
931 4f4: 12 97 sbiw r26, 0x02 ; 2
932 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
933 4f6: 51 96 adiw r26, 0x11 ; 17
934 4f8: 2c 93 st X, r18
935 4fa: 51 97 sbiw r26, 0x11 ; 17
936 //Pines de entrada y totem_pulldup:PIN1
937 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
938 4fc: 50 96 adiw r26, 0x10 ; 16
939 4fe: 8c 93 st X, r24
940
941 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
942
943 PORTSPI.INT0MASK = SPI_MISO_bm;
944 500: 80 e4 ldi r24, 0x40 ; 64
945 502: 82 87 std Z+10, r24 ; 0x0a
946 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
947 504: 81 85 ldd r24, Z+9 ; 0x09
948 506: 8c 7f andi r24, 0xFC ; 252
949 508: 81 60 ori r24, 0x01 ; 1
950 50a: 81 87 std Z+9, r24 ; 0x09
951 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
952 50c: 86 89 ldd r24, Z+22 ; 0x16
953 50e: 88 7f andi r24, 0xF8 ; 248
954 510: 82 60 ori r24, 0x02 ; 2
955 512: 86 8b std Z+22, r24 ; 0x16
956 514: 08 95 ret
957
958 00000516 <config_sysclock>:
959 #define F_CPU 32000000UL
960 #include <avr/io.h>
961
962 void config_sysclock(void){
963
964 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz
965 516: e0 e5 ldi r30, 0x50 ; 80
966 518: f0 e0 ldi r31, 0x00 ; 0
967 51a: 80 81 ld r24, Z
968 51c: 86 60 ori r24, 0x06 ; 6
969 51e: 80 83 st Z, r24
970 do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj
971 520: 81 81 ldd r24, Z+1 ; 0x01
972 522: 81 ff sbrs r24, 1
973 524: fd cf rjmp .-6 ; 0x520 <config_sysclock+0xa>
974 do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj
975 526: e0 e5 ldi r30, 0x50 ; 80
976 528: f0 e0 ldi r31, 0x00 ; 0
977 52a: 81 81 ldd r24, Z+1 ; 0x01
978 52c: 82 ff sbrs r24, 2
979 52e: fd cf rjmp .-6 ; 0x52a <config_sysclock+0x14>
980 CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla
981 530: 28 ed ldi r18, 0xD8 ; 216
982 532: 24 bf out 0x34, r18 ; 52
983 //con instrucciones en assembler
984 CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler
985 534: e0 e4 ldi r30, 0x40 ; 64
986 536: f0 e0 ldi r31, 0x00 ; 0
987 538: 80 81 ld r24, Z
988 53a: 81 60 ori r24, 0x01 ; 1
989 53c: 80 83 st Z, r24
990 DFLLRC32M.CTRL = DFLL_ENABLE_bm;
991 53e: 91 e0 ldi r25, 0x01 ; 1
992 540: 90 93 60 00 sts 0x0060, r25
993 OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K
994 544: e0 e5 ldi r30, 0x50 ; 80
995 546: f0 e0 ldi r31, 0x00 ; 0
996 548: 86 81 ldd r24, Z+6 ; 0x06
997 54a: 16 82 std Z+6, r1 ; 0x06
998 OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno
999 54c: 80 81 ld r24, Z
1000 54e: 8e 7f andi r24, 0xFE ; 254
1001 550: 80 83 st Z, r24
1002 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
1003 552: 24 bf out 0x34, r18 ; 52
1004 OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
1005 554: 90 93 53 00 sts 0x0053, r25
1006 558: 08 95 ret
1007
1008 0000055a <_exit>:
1009 55a: f8 94 cli
1010
1011 0000055c <__stop_program>:
1012 55c: ff cf rjmp .-2 ; 0x55c <__stop_program>
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1 Archive member included to satisfy reference by file (symbol)
2
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426 *(.efuse)
427
428 .lock
429 *(.lock*)
430
431 .signature
432 *(.signature*)
433
434 .user_signatures
435 *(.user_signatures*)
436
437 .stab
438 *(.stab)
439
440 .stabstr
441 *(.stabstr)
442
443 .stab.excl
444 *(.stab.excl)
445
446 .stab.exclstr
447 *(.stab.exclstr)
448
449 .stab.index
450 *(.stab.index)
451
452 .stab.indexstr
453 *(.stab.indexstr)
454
455 .comment 0x00000000 0x30
456 *(.comment)
457 .comment 0x00000000 0x30 ADC_7176_2.o
458 0x31 (size before relaxing)
459 .comment 0x00000030 0x31 commSPI_ADC.o
460 .comment 0x00000030 0x31 fpga_port.o
461 .comment 0x00000030 0x31 main.o
462 .comment 0x00000030 0x31 Ports.o
463 .comment 0x00000030 0x31 sys_clock.o
464
465 .note.gnu.avr.deviceinfo
466 0x00000000 0x40
467 .note.gnu.avr.deviceinfo
468 0x00000000 0x40 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o
469
470 .note.gnu.build-id
471 *(.note.gnu.build-id)
472
473 .debug
474 *(.debug)
475
476 .line
477 *(.line)
478
479 .debug_srcinfo
480 *(.debug_srcinfo)
481
482 .debug_sfnames
483 *(.debug_sfnames)
484
485 .debug_aranges 0x00000000 0x138
486 *(.debug_aranges)
487 .debug_aranges
488 0x00000000 0x50 ADC_7176_2.o
489 .debug_aranges
490 0x00000050 0x20 commSPI_ADC.o
491 .debug_aranges
492 0x00000070 0x50 fpga_port.o
493 .debug_aranges
494 0x000000c0 0x38 main.o
495 .debug_aranges
496 0x000000f8 0x20 Ports.o
497 .debug_aranges
498 0x00000118 0x20 sys_clock.o
499
500 .debug_pubnames
501 *(.debug_pubnames)
502
503 .debug_info 0x00000000 0x14b5
504 *(.debug_info .gnu.linkonce.wi.*)
505 .debug_info 0x00000000 0x53c ADC_7176_2.o
506 .debug_info 0x0000053c 0xf0 commSPI_ADC.o
507 .debug_info 0x0000062c 0x578 fpga_port.o
508 .debug_info 0x00000ba4 0x413 main.o
509 .debug_info 0x00000fb7 0x2ab Ports.o
510 .debug_info 0x00001262 0x253 sys_clock.o
511
512 .debug_abbrev 0x00000000 0x644
513 *(.debug_abbrev)
514 .debug_abbrev 0x00000000 0x1b6 ADC_7176_2.o
515 .debug_abbrev 0x000001b6 0x83 commSPI_ADC.o
516 .debug_abbrev 0x00000239 0x19b fpga_port.o
517 .debug_abbrev 0x000003d4 0x10d main.o
518 .debug_abbrev 0x000004e1 0xaa Ports.o
519 .debug_abbrev 0x0000058b 0xb9 sys_clock.o
520
521 .debug_line 0x00000000 0x827
522 *(.debug_line .debug_line.* .debug_line_end)
523 .debug_line 0x00000000 0x1c9 ADC_7176_2.o
524 .debug_line 0x000001c9 0x101 commSPI_ADC.o
525 .debug_line 0x000002ca 0x19c fpga_port.o
526 .debug_line 0x00000466 0x185 main.o
527 .debug_line 0x000005eb 0x12c Ports.o
528 .debug_line 0x00000717 0x110 sys_clock.o
529
530 .debug_frame 0x00000000 0x278
531 *(.debug_frame)
532 .debug_frame 0x00000000 0x84 ADC_7176_2.o
533 .debug_frame 0x00000084 0x24 commSPI_ADC.o
534 .debug_frame 0x000000a8 0xb4 fpga_port.o
535 .debug_frame 0x0000015c 0xd4 main.o
536 .debug_frame 0x00000230 0x24 Ports.o
537 .debug_frame 0x00000254 0x24 sys_clock.o
538
539 .debug_str 0x00000000 0x7d6
540 *(.debug_str)
541 .debug_str 0x00000000 0x2c0 ADC_7176_2.o
542 0x303 (size before relaxing)
543 .debug_str 0x000002c0 0x22 commSPI_ADC.o
544 0x1cc (size before relaxing)
545 .debug_str 0x000002e2 0x34d fpga_port.o
546 0x5e0 (size before relaxing)
547 .debug_str 0x0000062f 0x53 main.o
548 0x3c1 (size before relaxing)
549 .debug_str 0x00000682 0xd Ports.o
550 0x3f5 (size before relaxing)
551 .debug_str 0x0000068f 0x147 sys_clock.o
552 0x2ff (size before relaxing)
553
554 .debug_loc 0x00000000 0x3d0
555 *(.debug_loc)
556 .debug_loc 0x00000000 0xfc ADC_7176_2.o
557 .debug_loc 0x000000fc 0x15d fpga_port.o
558 .debug_loc 0x00000259 0x177 main.o
559
560 .debug_macinfo
561 *(.debug_macinfo)
562
563 .debug_weaknames
564 *(.debug_weaknames)
565
566 .debug_funcnames
567 *(.debug_funcnames)
568
569 .debug_typenames
570 *(.debug_typenames)
571
572 .debug_varnames
573 *(.debug_varnames)
574
575 .debug_pubtypes
576 *(.debug_pubtypes)
577
578 .debug_ranges 0x00000000 0xd8
579 *(.debug_ranges)
580 .debug_ranges 0x00000000 0x40 ADC_7176_2.o
581 .debug_ranges 0x00000040 0x10 commSPI_ADC.o
582 .debug_ranges 0x00000050 0x40 fpga_port.o
583 .debug_ranges 0x00000090 0x28 main.o
584 .debug_ranges 0x000000b8 0x10 Ports.o
585 .debug_ranges 0x000000c8 0x10 sys_clock.o
586
587 .debug_macro
588 *(.debug_macro)
589 OUTPUT(ADCSPI_ver01.elf elf32-avr)
590 LOAD linker stubs
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@@ -0,0 +1,44
1 ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h
15
16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
17
18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
19
20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
21
22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
23
24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
25
26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
27
28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
29
30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
31
32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
33
34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
35
36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
37
38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
39
40 .././ADC_7176_2.h:
41
42 .././Ports.h:
43
44 .././commSPI_ADC.h:
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@@ -0,0 +1,164
1 ################################################################################
2 # Automatically-generated file. Do not edit!
3 ################################################################################
4
5 SHELL := cmd.exe
6 RM := rm -rf
7
8 USER_OBJS :=
9
10 LIBS :=
11 PROJ :=
12
13 O_SRCS :=
14 C_SRCS :=
15 S_SRCS :=
16 S_UPPER_SRCS :=
17 OBJ_SRCS :=
18 ASM_SRCS :=
19 PREPROCESSING_SRCS :=
20 OBJS :=
21 OBJS_AS_ARGS :=
22 C_DEPS :=
23 C_DEPS_AS_ARGS :=
24 EXECUTABLES :=
25 OUTPUT_FILE_PATH :=
26 OUTPUT_FILE_PATH_AS_ARGS :=
27 AVR_APP_PATH :=$$$AVR_APP_PATH$$$
28 QUOTE := "
29 ADDITIONAL_DEPENDENCIES:=
30 OUTPUT_FILE_DEP:=
31 LIB_DEP:=
32 LINKER_SCRIPT_DEP:=
33
34 # Every subdirectory with source files must be described here
35 SUBDIRS :=
36
37
38 # Add inputs and outputs from these tool invocations to the build variables
39 C_SRCS += \
40 ../ADC_7176_2.c \
41 ../commSPI_ADC.c \
42 ../fpga_port.c \
43 ../main.c \
44 ../Ports.c \
45 ../sys_clock.c
46
47
48 PREPROCESSING_SRCS +=
49
50
51 ASM_SRCS +=
52
53
54 OBJS += \
55 ADC_7176_2.o \
56 commSPI_ADC.o \
57 fpga_port.o \
58 main.o \
59 Ports.o \
60 sys_clock.o
61
62 OBJS_AS_ARGS += \
63 ADC_7176_2.o \
64 commSPI_ADC.o \
65 fpga_port.o \
66 main.o \
67 Ports.o \
68 sys_clock.o
69
70 C_DEPS += \
71 ADC_7176_2.d \
72 commSPI_ADC.d \
73 fpga_port.d \
74 main.d \
75 Ports.d \
76 sys_clock.d
77
78 C_DEPS_AS_ARGS += \
79 ADC_7176_2.d \
80 commSPI_ADC.d \
81 fpga_port.d \
82 main.d \
83 Ports.d \
84 sys_clock.d
85
86 OUTPUT_FILE_PATH +=ADCSPI_ver01.elf
87
88 OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf
89
90 ADDITIONAL_DEPENDENCIES:=
91
92 OUTPUT_FILE_DEP:= ./makedep.mk
93
94 LIB_DEP+=
95
96 LINKER_SCRIPT_DEP+=
97
98
99 # AVR32/GNU C Compiler
100
101
102
103
104
105
106
107
108
109
110
111
112
113 ./%.o: .././%.c
114 @echo Building file: $<
115 @echo Invoking: AVR/GNU C Compiler : 4.9.2
116 $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
117 @echo Finished building: $<
118
119
120
121
122 # AVR32/GNU Preprocessing Assembler
123
124
125
126 # AVR32/GNU Assembler
127
128
129
130
131 ifneq ($(MAKECMDGOALS),clean)
132 ifneq ($(strip $(C_DEPS)),)
133 -include $(C_DEPS)
134 endif
135 endif
136
137 # Add inputs and outputs from these tool invocations to the build variables
138
139 # All Target
140 all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
141
142 $(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
143 @echo Building target: $@
144 @echo Invoking: AVR/GNU Linker : 4.9.2
145 $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4"
146 @echo Finished building target: $@
147 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex"
148 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0
149 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss"
150 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec"
151 "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf"
152
153
154
155
156
157
158
159 # Other Targets
160 clean:
161 -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
162 -$(RM) $(C_DEPS_AS_ARGS)
163 rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures"
164 No newline at end of file
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@@ -0,0 +1,42
1 Ports.d Ports.o: .././Ports.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././Ports.h .././commSPI_ADC.h
15
16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
17
18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
19
20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
21
22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
23
24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
25
26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
27
28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
29
30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
31
32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
33
34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
35
36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
37
38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
39
40 .././Ports.h:
41
42 .././commSPI_ADC.h:
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1 commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././commSPI_ADC.h .././Ports.h
15
16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
17
18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
19
20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
21
22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
23
24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
25
26 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
27
28 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
29
30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
31
32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
33
34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
35
36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
37
38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
39
40 .././commSPI_ADC.h:
41
42 .././Ports.h:
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1 fpga_port.d fpga_port.o: .././fpga_port.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././fpga_port.h \
15 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \
16 .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h
17
18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
19
20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
21
22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
23
24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
25
26 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
27
28 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
29
30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
31
32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
33
34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
35
36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
37
38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
39
40 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
41
42 .././fpga_port.h:
43
44 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
45
46 .././ADC_7176_2.h:
47
48 .././Ports.h:
49
50 .././commSPI_ADC.h:
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1 main.d main.o: .././main.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \
14 .././Ports.h .././commSPI_ADC.h .././sys_clock.h .././ADC_7176_2.h \
15 .././fpga_port.h \
16 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h
17
18 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
19
20 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
21
22 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
23
24 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
25
26 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
27
28 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
29
30 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
31
32 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
33
34 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
35
36 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
37
38 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
39
40 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
41
42 .././Ports.h:
43
44 .././commSPI_ADC.h:
45
46 .././sys_clock.h:
47
48 .././ADC_7176_2.h:
49
50 .././fpga_port.h:
51
52 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h:
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@@ -0,0 +1,16
1 ################################################################################
2 # Automatically-generated file. Do not edit or delete the file
3 ################################################################################
4
5 ADC_7176_2.c
6
7 commSPI_ADC.c
8
9 fpga_port.c
10
11 main.c
12
13 Ports.c
14
15 sys_clock.c
16
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@@ -0,0 +1,37
1 sys_clock.d sys_clock.o: .././sys_clock.c \
2 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \
3 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \
4 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \
5 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \
6 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \
7 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \
8 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \
9 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \
10 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \
11 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \
12 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \
13 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h
14
15 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h:
16
17 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h:
18
19 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h:
20
21 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h:
22
23 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h:
24
25 C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h:
26
27 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h:
28
29 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h:
30
31 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h:
32
33 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h:
34
35 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h:
36
37 c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h:
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1 /*
2 * Ports.c
3 *
4 * Created: 23/11/15 13:57:48
5 * Author: Francisco
6 */
7
8 /*!
9 * \fn config_puertos
10 * \brief Configuraci�n de todos los pines de I/O a usarse
11 * para la prueba. Para el firmware final se deben dejar de configurar en este segmento
12 * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo.
13 * Los criterios de asignaci�n de control:
14 * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
15 * Se sabe que la entrada ser� casi siempre alta.
16 * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si
17 * Se sabe que la entrada ser� casi siempre baja.
18 * WiredAndpull: Para evitar cortos de una salida al exterior del board.
19 * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board).
20 * \
21 */
22
23 #define F_CPU 32000000UL
24 #include <avr/io.h>
25
26 #include "Ports.h"
27 #include "commSPI_ADC.h"
28
29 inline void config_puertos(void){
30 //Configuracion pines del puerto A: PA7-PA0
31 //Pines de entrada y totem_pullup
32 PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm;
33 PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc;
34 PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc;
35 PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc;
36 PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc;
37 PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc;
38 PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc;
39 PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc;
40 //Pin de salida A0
41 //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n
42 //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta
43 //Valor por defecto salida: PA0 = low
44 PORTA.DIRSET = PIN0_bm;
45 PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc;
46 PORTA.OUTCLR = PIN0_bm;
47
48 //Configuracion pines del puerto B: PB3-PB0
49 //Pines de entrada y totem_pullup
50 PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm;
51 PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc;
52 PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc;
53 PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc;
54 PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc;
55
56 //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI
57 //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6
58 //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI.
59 PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C
60 PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc;
61 PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc;
62 PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc;
63 PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc;
64 PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc;
65 //Pines de salida wiredand-pull
66 //Valor por defecto salida: PC4,PC7 = low
67 //Valor por defecto salida: PC5 = set
68 PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm;
69 PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc;
70 PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc;
71 PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc;
72 PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm;
73 PORTSPI.OUTCLR = SPI_MOSI_bm;
74
75 //Configuracion pines del puerto D: PD7-PD0
76 //Pines de entrada y totem_pullup: PIN7 y PIN0
77 //NOTA
78 //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO
79 //NOTA FIN
80 PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm;
81 PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc;
82 PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc;
83 //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga
84 PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc;
85 PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
86 //Pines de salida tipo wired-and-pull
87 //Valor por defecto PD6, PD5, PD4, PD3 = low
88 PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
89 PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc;
90 PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc;
91 PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc;
92 PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc;
93 PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm;
94
95 //Configuracion pines del puerto E: PE3-PE0
96 //Pines de entrada y totem_pullup: PIN3 - PIN0
97 PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm;
98 PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc;
99 PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc;
100 PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc;
101 PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc;
102
103 //Configuracion pines del puerto R: PR1-PR0
104 //Pines de entrada y totem_pulldown: PIN0
105 PORTR.DIRCLR = PIN1_bm| PIN0_bm;
106 PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc;
107 //Pines de entrada y totem_pulldup:PIN1
108 PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc;
109
110 //Configuraci�n como interrupci�n del pin SPI_MISO_RDY
111
112 PORTSPI.INT0MASK = SPI_MISO_bm;
113 PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc;
114 PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
115
116 } No newline at end of file
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1 /*
2 * Ports.h
3 *
4 * Created: 23/11/15 13:55:28
5 * Author: Francisco
6 */
7
8
9 #ifndef PORTS_H_
10 #define PORTS_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14
15 #define INT_RDY PORTC_INT0_vect
16
17 void config_puertos(void);
18
19
20
21 #endif /* PORTS_H_ */ No newline at end of file
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1 /*
2 * commSPI_ADC.c
3 *
4 * Created: 23/11/15 14:08:25
5 * Author: Francisco
6 */
7
8
9 #define F_CPU 32000000UL
10 #include <avr/io.h>
11 #include "commSPI_ADC.h"
12
13 /*!
14 * \fn config_spiparm
15 * \brief Configuraci�n de los par�metros de reloj SPI
16 *
17 * fspi = fper/2 = fcpu/2 = 16MHz
18 *
19 * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una
20 * nueva evaluaci�n
21 * \
22 */
23 inline void config_spiparm(void){
24 // Preescaler: clkper/2 = f_cpu/2.
25 // Master
26 // Mode 3: CPOL=1,CPHA=1
27 // MSB --- LSB
28 SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm |
29 SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm;
30 }
31
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1 /*
2 * commSPI_ADC.h
3 *
4 * Created: 23/11/15 14:06:45
5 * Author: Francisco
6 */
7
8
9 #ifndef COMMSPI_ADC_H_
10 #define COMMSPI_ADC_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14
15 #include "Ports.h"
16
17 #define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI
18
19 #define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS
20 #define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI
21 #define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO
22 #define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK
23
24 #define SPI_SS_bm PIN4_bm // Pin de entrada - Totem
25 #define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem
26 #define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem
27 #define SPI_SCK_bm PIN7_bm // Pin de salida - Totem
28
29 void config_spiparm(void);
30
31
32 #endif /* COMMSPI_ADC_H_ */ No newline at end of file
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1 /*
2 * fpga_port.c
3 *
4 * Created: 23/11/15 14:33:16
5 * Author: Francisco
6 */
7
8 #define F_CPU 32000000UL
9 #include <avr/io.h>
10
11 #include "fpga_port.h"
12
13 inline void config_fpgaport()
14 {
15 //Configuracion pines del puerto D: PD6-PA1
16 //Pines de entrada CLK_FPGA, LOCK_FPGA
17 //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
18 PORT_FPGA.DIRCLR = LOCK_FPGA;
19 PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
20 PORT_FPGA.DIRSET = CLK_FPGA;
21 PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc;
22 PORT_FPGA.OUTSET = CLK_FPGA;
23
24 //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA
25 PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
26 PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc;
27 PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA;
28
29 //Configuracion pines del puerto B: PPS
30 //Pines de entrada PPS_FPGA
31 //Pines de entrada en pulldown
32 PORT_PPS.DIRCLR = PPS_FPGA;
33 PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc;
34
35 //Configuracion pines del puerto A: LOCKOUT
36 //Pines de salida LOCK_OUT
37 //Pines de salida en baja
38 PORT_LOCKOUT.DIRSET = LOCK_OUT;
39 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
40
41
42
43 //Configuracion de interrupciones de LOCK_FPGA
44
45 PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc;
46 PORT_FPGA.INT0MASK = LOCK_FPGA;
47 PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc;
48
49 //Configuracion de interrupciones de CLK
50 //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
51 //PORT_FPGA.INT1MASK = CLK_FPGA;
52 //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc;
53
54 //Configuracion de interrupciones de PPS
55 PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc;
56 PORT_PPS.INT1MASK = PPS_FPGA;
57 PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc;
58 }
59
60 void habilitar_interrupciones( uint8_t level_mask )
61 {
62 PMIC.CTRL = level_mask;
63 }
64
65 void habilitar_interrupciones_globales( void )
66 {
67 sei();
68 }
69
70 void deshabilitar_interrupciones_globales( void )
71 {
72 cli();
73 }
74
75 void envio_nibble(uint8_t fpga_dato)
76 {
77 PORT_FPGA.OUTCLR = CLK_FPGA;
78 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp);
79 PORT_FPGA.OUTSET = CLK_FPGA;
80 //asm("nop");
81 PORT_FPGA.OUTCLR = CLK_FPGA;
82 PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp);
83 PORT_FPGA.OUTSET = CLK_FPGA;
84
85 }
86
87 void envio_datos_fpga(void)
88 {
89 uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ;
90 adcport_read_data(fpga_dato,ADC_DATASZ);
91 aux_dato[0] = fpga_dato[0];
92 aux_dato[1] = fpga_dato[1];
93 aux_dato[2] = fpga_dato[2];
94 adcport_read_data(fpga_dato,ADC_DATASZ);
95
96 envio_dato_adc(aux_dato);
97 envio_dato_adc(fpga_dato);
98 }
99
100 void envio_dato_adc(uint8_t* dato_adc)
101 {
102 for(int i=0; i<3 ; i++)
103 envio_nibble(dato_adc[i]);
104 }
105 /*
106 __attribute__((noinline)) void delay_nop(void)
107 {
108 asm("nop");
109 }
110 */
111
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1 /*
2 * fpga_port.h
3 *
4 * Created: 23/11/15 14:20:25
5 * Author: Francisco
6 */
7
8
9 #ifndef FPGA_PORT_H_
10 #define FPGA_PORT_H_
11
12 #define F_CPU 32000000UL
13 #include <avr/io.h>
14 #include <avr/interrupt.h>
15 #include "ADC_7176_2.h"
16
17 //Port B
18 #define PORT_PPS PORTB
19 #define PPS_FPGA PIN2_bm
20 #define PPS_FPGA_CTRL PIN2CTRL
21 #define INT_PPS PORTB_INT1_vect
22
23 //Port A
24 #define PORT_LOCKOUT PORTA
25 #define LOCK_OUT PIN0_bm
26
27
28 //Port D
29 #define PORT_FPGA PORTD
30 #define LOCK_FPGA PIN1_bm
31 #define CLK_FPGA PIN2_bm
32 #define CH_BIT0_FPGA PIN3_bm
33 #define CH_BIT1_FPGA PIN4_bm
34 #define CH_BIT2_FPGA PIN5_bm
35 #define CH_BIT3_FPGA PIN6_bm
36 #define INT_LOCK_FPGA PORTD_INT0_vect
37
38 #define LOCK_FPGA_CTRL PIN1CTRL
39 #define CLK_FPGA_CTRL PIN2CTRL
40 #define CH_BIT0_FPGA_CTRL PIN3CTRL
41 #define CH_BIT1_FPGA_CTRL PIN4CTRL
42 #define CH_BIT2_FPGA_CTRL PIN5CTRL
43 #define CH_BIT3_FPGA_CTRL PIN6CTRL
44
45 void config_fpgaport();
46 void habilitar_interrupciones( uint8_t level_mask );
47 void habilitar_interrupciones_globales( );
48 void deshabilitar_interrupciones_globales( );
49
50 //Habilitar
51 #define hab_prioridad_alta PMIC_HILVLEN_bm
52 #define hab_prioridad_media PMIC_MEDLVLEN_bm
53 #define hab_prioridad_baja PMIC_LOLVLEN_bm
54
55 //M�scara de nibbles
56 #define nibble_alto_bm 0xF0
57 #define nibble_bajo_bm 0x0F
58 #define fpga_salidas_bp 3
59 #define fpga_salidas_bm 0x38
60
61 //funciones de env�o de datos
62 void envio_nibble(uint8_t fpga_dato);
63
64 //funcion interrupcion por flanco de subida de RDY
65 void envio_datos_fpga(void);
66 void envio_dato_adc(uint8_t* dato_adc);
67
68 #endif /* FPGA_PORT_H_ */ No newline at end of file
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1 /*
2 * ADCSPI_ver01.c
3 *
4 * Created: 26/10/15 12:02:22
5 * Author : Francisco
6 */
7
8 #define F_CPU 32000000UL
9 #include <avr/io.h>
10 #include "Ports.h"
11 #include "commSPI_ADC.h"
12 #include "sys_clock.h"
13 #include "ADC_7176_2.h"
14 #include "fpga_port.h"
15
16
17 int main(void)
18 {
19 //uint8_t datos_adc[3];
20 config_puertos();
21 config_sysclock();
22 config_spiparm();
23 config_fpgaport();
24
25 //datos_adc[0] = 0x00;
26 //datos_adc[1] = 0x00;
27 //datos_adc[2] = 0x00;
28 //PORTD.OUTSET = PIN5_bm;
29
30 PMIC.CTRL = hab_prioridad_alta;
31 habilitar_interrupciones_globales();
32
33 /* Replace with your application code */
34 while (1)
35 {
36 if (test_adc() == ADC_ID){
37 PORTD.OUTSET = PIN6_bm | PIN5_bm;
38 }
39 //test_adc_2(datos_adc);
40 //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){
41 //PORTD.OUTSET = PIN4_bm;
42 //}
43 }
44 return 0;
45 }
46
47
48 ISR(INT_LOCK_FPGA)
49 {
50 if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA)
51 {
52 PMIC.CTRL |= hab_prioridad_media;
53 PORT_LOCKOUT.OUTSET = LOCK_OUT;
54 }
55 else
56 {
57 PMIC.CTRL &= ~hab_prioridad_media;
58 PMIC.CTRL &= ~hab_prioridad_baja;
59 PORT_LOCKOUT.OUTCLR = LOCK_OUT;
60 }
61 }
62
63 ISR(INT_PPS)
64 {
65 if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA)
66 PMIC.CTRL |= hab_prioridad_baja;
67 else
68 PMIC.CTRL &= ~hab_prioridad_baja;
69 }
70
71 ISR(INT_RDY)
72 {
73 envio_datos_fpga();
74 }
75
76
77
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1 /*
2 * sys_clock.c
3 *
4 * Created: 23/11/15 14:04:36
5 * Author: Francisco
6 */
7
8
9 /*!
10 * \fn config_sysclock
11 * \brief Configuraci�n del reloj interno del sistema
12 * Reloj interno
13 * fsys = 32MHz
14 *
15 * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL
16 * \
17 */
18
19 #define F_CPU 32000000UL
20 #include <avr/io.h>
21
22 void config_sysclock(void){
23
24 OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz
25 do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj
26 do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj
27 CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla
28 //con instrucciones en assembler
29 CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler
30 DFLLRC32M.CTRL = DFLL_ENABLE_bm;
31 OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K
32 OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno
33 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
34 OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
35
36 /*
37 CLK_PSCTRL = ((0<<CLK_PSADIV_gp) & CLK_PSADIV_gm)|((0<<CLK_PSBCDIV_gp) & CLK_PSBCDIV_gm); //Prescaler A, B y C = 1
38 OSC_XOSCCTRL = OSC_XOSCSEL_EXTCLK_gc; //usar external clock
39
40 OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | ( 0x02 & OSC_PLLFAC_gm);
41
42 OSC_CTRL |= OSC_PLLEN_bm; //usar external clock
43 while(!(OSC_STATUS & OSC_XOSCRDY_bm));
44 while(!(OSC_STATUS & OSC_PLLRDY_bm));
45
46 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
47 CLK_CTRL = (CLK_SCLKSEL_PLL_gc) & CLK_SCLKSEL_gm; //CLK usa oscilador externo
48
49 OSC_CTRL &= ~OSC_RC2MEN_bm;
50
51 CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro
52 OSC_XOSCFAIL = (OSC_PLLFDEN_bm)|(OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de
53 */
54
55 } No newline at end of file
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1 /*
2 * sys_clock.h
3 *
4 * Created: 23/11/15 14:03:16
5 * Author: Francisco
6 */
7
8
9 #ifndef SYS_CLOCK_H_
10 #define SYS_CLOCK_H_
11
12
13 #define F_CPU 32000000UL
14 #include <avr/io.h>
15
16 void config_sysclock(void);
17
18
19
20 #endif /* SYS_CLOCK_H_ */ No newline at end of file
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1 En esta primera versi�n los activadores de interrupciones son LOCK y PPS.
2 LOCK activa la interrupci�n deprioridad media.
3 PPS activa la interrupci�n de prioridad baja.
4
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