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1 | <?xml version="1.0" encoding="UTF-8" standalone="no"?> | |||
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2 | <?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage"> | |||
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3 | <storageModule moduleId="org.eclipse.cdt.core.settings"> | |||
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4 | <cconfiguration id="de.innot.avreclipse.configuration.app.release.858010349"> | |||
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5 | <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="de.innot.avreclipse.configuration.app.release.858010349" moduleId="org.eclipse.cdt.core.settings" name="Release"> | |||
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6 | <externalSettings/> | |||
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7 | <extensions> | |||
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8 | <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |||
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9 | <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |||
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10 | <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |||
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11 | <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |||
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12 | <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> | |||
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13 | </extensions> | |||
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14 | </storageModule> | |||
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15 | <storageModule moduleId="cdtBuildSystem" version="4.0.0"> | |||
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16 | <configuration artifactName="${ProjName}" buildArtefactType="de.innot.avreclipse.buildArtefactType.app" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release,org.eclipse.cdt.build.core.buildArtefactType=de.innot.avreclipse.buildArtefactType.app" description="" id="de.innot.avreclipse.configuration.app.release.858010349" name="Release" parent="de.innot.avreclipse.configuration.app.release"> | |||
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17 | <folderInfo id="de.innot.avreclipse.configuration.app.release.858010349." name="/" resourcePath=""> | |||
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18 | <toolChain id="de.innot.avreclipse.toolchain.winavr.app.release.1201895281" name="AVR-GCC Toolchain" superClass="de.innot.avreclipse.toolchain.winavr.app.release"> | |||
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19 | <option id="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.release.1647185864" name="Generate HEX file for Flash memory" superClass="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.release"/> | |||
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20 | <option id="de.innot.avreclipse.toolchain.options.toolchain.objcopy.eeprom.app.release.1369579761" name="Generate HEX file for EEPROM" superClass="de.innot.avreclipse.toolchain.options.toolchain.objcopy.eeprom.app.release"/> | |||
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21 | <option id="de.innot.avreclipse.toolchain.options.toolchain.objdump.app.release.83828298" name="Generate Extended Listing (Source + generated Assembler)" superClass="de.innot.avreclipse.toolchain.options.toolchain.objdump.app.release"/> | |||
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22 | <option id="de.innot.avreclipse.toolchain.options.toolchain.size.app.release.684879297" name="Print Size" superClass="de.innot.avreclipse.toolchain.options.toolchain.size.app.release"/> | |||
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23 | <option id="de.innot.avreclipse.toolchain.options.toolchain.avrdude.app.release.1667066990" name="AVRDude" superClass="de.innot.avreclipse.toolchain.options.toolchain.avrdude.app.release"/> | |||
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24 | <targetPlatform id="de.innot.avreclipse.targetplatform.winavr.app.release.1768688297" name="AVR Cross-Target" superClass="de.innot.avreclipse.targetplatform.winavr.app.release"/> | |||
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25 | <builder buildPath="${workspace_loc:/acquisitiond}/Release" id="de.innot.avreclipse.target.builder.winavr.app.release.780027386" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="AVR GNU Make Builder" superClass="de.innot.avreclipse.target.builder.winavr.app.release"/> | |||
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26 | <tool id="de.innot.avreclipse.tool.assembler.winavr.app.release.2089771014" name="AVR Assembler" superClass="de.innot.avreclipse.tool.assembler.winavr.app.release"> | |||
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27 | <option id="de.innot.avreclipse.assembler.option.debug.level.1133662769" name="Generate Debugging Info" superClass="de.innot.avreclipse.assembler.option.debug.level" value="de.innot.avreclipse.assembler.option.debug.level.none" valueType="enumerated"/> | |||
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28 | <inputType id="de.innot.avreclipse.tool.assembler.input.1279294131" superClass="de.innot.avreclipse.tool.assembler.input"/> | |||
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29 | </tool> | |||
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30 | <tool id="de.innot.avreclipse.tool.compiler.winavr.app.release.271082271" name="AVR Compiler" superClass="de.innot.avreclipse.tool.compiler.winavr.app.release"> | |||
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31 | <option id="de.innot.avreclipse.compiler.option.debug.level.565091964" name="Generate Debugging Info" superClass="de.innot.avreclipse.compiler.option.debug.level" value="de.innot.avreclipse.compiler.option.debug.level.none" valueType="enumerated"/> | |||
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32 | <option id="de.innot.avreclipse.compiler.option.optimize.1018740717" name="Optimization Level" superClass="de.innot.avreclipse.compiler.option.optimize" value="de.innot.avreclipse.compiler.optimize.size" valueType="enumerated"/> | |||
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33 | <inputType id="de.innot.avreclipse.compiler.winavr.input.1924568625" name="C Source Files" superClass="de.innot.avreclipse.compiler.winavr.input"/> | |||
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34 | </tool> | |||
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35 | <tool id="de.innot.avreclipse.tool.cppcompiler.app.release.847105960" name="AVR C++ Compiler" superClass="de.innot.avreclipse.tool.cppcompiler.app.release"> | |||
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36 | <option id="de.innot.avreclipse.cppcompiler.option.debug.level.954847397" name="Generate Debugging Info" superClass="de.innot.avreclipse.cppcompiler.option.debug.level" value="de.innot.avreclipse.cppcompiler.option.debug.level.none" valueType="enumerated"/> | |||
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37 | <option id="de.innot.avreclipse.cppcompiler.option.optimize.1175987034" name="Optimization Level" superClass="de.innot.avreclipse.cppcompiler.option.optimize" value="de.innot.avreclipse.cppcompiler.optimize.size" valueType="enumerated"/> | |||
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38 | <inputType id="de.innot.avreclipse.cppcompiler.input.242019820" superClass="de.innot.avreclipse.cppcompiler.input"/> | |||
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39 | </tool> | |||
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40 | <tool id="de.innot.avreclipse.tool.linker.winavr.app.release.429279474" name="AVR C Linker" superClass="de.innot.avreclipse.tool.linker.winavr.app.release"/> | |||
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41 | <tool id="de.innot.avreclipse.tool.cpplinker.app.release.971097438" name="AVR C++ Linker" superClass="de.innot.avreclipse.tool.cpplinker.app.release"> | |||
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42 | <inputType id="de.innot.avreclipse.tool.cpplinker.input.337770889" name="OBJ Files" superClass="de.innot.avreclipse.tool.cpplinker.input"> | |||
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43 | <additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/> | |||
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44 | <additionalInput kind="additionalinput" paths="$(LIBS)"/> | |||
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45 | </inputType> | |||
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46 | </tool> | |||
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47 | <tool id="de.innot.avreclipse.tool.archiver.winavr.base.750925756" name="AVR Archiver" superClass="de.innot.avreclipse.tool.archiver.winavr.base"/> | |||
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48 | <tool id="de.innot.avreclipse.tool.objdump.winavr.app.release.399623506" name="AVR Create Extended Listing" superClass="de.innot.avreclipse.tool.objdump.winavr.app.release"/> | |||
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49 | <tool id="de.innot.avreclipse.tool.objcopy.flash.winavr.app.release.1920455843" name="AVR Create Flash image" superClass="de.innot.avreclipse.tool.objcopy.flash.winavr.app.release"/> | |||
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50 | <tool id="de.innot.avreclipse.tool.objcopy.eeprom.winavr.app.release.991951467" name="AVR Create EEPROM image" superClass="de.innot.avreclipse.tool.objcopy.eeprom.winavr.app.release"/> | |||
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51 | <tool id="de.innot.avreclipse.tool.size.winavr.app.release.864443464" name="Print Size" superClass="de.innot.avreclipse.tool.size.winavr.app.release"/> | |||
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52 | <tool id="de.innot.avreclipse.tool.avrdude.app.release.533373240" name="AVRDude" superClass="de.innot.avreclipse.tool.avrdude.app.release"/> | |||
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53 | </toolChain> | |||
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54 | </folderInfo> | |||
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55 | </configuration> | |||
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56 | </storageModule> | |||
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57 | <storageModule moduleId="org.eclipse.cdt.core.externalSettings"/> | |||
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58 | </cconfiguration> | |||
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59 | </storageModule> | |||
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60 | <storageModule moduleId="cdtBuildSystem" version="4.0.0"> | |||
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61 | <project id="acquisitiond.de.innot.avreclipse.project.winavr.elf_2.1.0.1252544761" name="AVR Cross Target Application" projectType="de.innot.avreclipse.project.winavr.elf_2.1.0"/> | |||
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62 | </storageModule> | |||
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63 | <storageModule moduleId="scannerConfiguration"> | |||
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64 | <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/> | |||
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65 | <scannerConfigBuildInfo instanceId="de.innot.avreclipse.configuration.app.release.858010349;de.innot.avreclipse.configuration.app.release.858010349.;de.innot.avreclipse.tool.cppcompiler.app.release.847105960;de.innot.avreclipse.cppcompiler.input.242019820"> | |||
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66 | <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="de.innot.avreclipse.core.AVRGCCManagedMakePerProjectProfileCPP"/> | |||
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67 | </scannerConfigBuildInfo> | |||
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68 | <scannerConfigBuildInfo instanceId="de.innot.avreclipse.configuration.app.release.858010349;de.innot.avreclipse.configuration.app.release.858010349.;de.innot.avreclipse.tool.compiler.winavr.app.release.271082271;de.innot.avreclipse.compiler.winavr.input.1924568625"> | |||
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69 | <autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId="de.innot.avreclipse.core.AVRGCCManagedMakePerProjectProfileC"/> | |||
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70 | </scannerConfigBuildInfo> | |||
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71 | </storageModule> | |||
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72 | <storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/> | |||
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73 | <storageModule moduleId="refreshScope"/> | |||
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74 | </cproject> No newline at end of file | |||
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1 | <?xml version="1.0" encoding="UTF-8"?> | |||
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2 | <projectDescription> | |||
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3 | <name>acquisitiond</name> | |||
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4 | <comment></comment> | |||
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5 | <projects> | |||
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6 | </projects> | |||
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7 | <buildSpec> | |||
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8 | <buildCommand> | |||
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9 | <name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name> | |||
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10 | <triggers>clean,full,incremental,</triggers> | |||
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11 | <arguments> | |||
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12 | </arguments> | |||
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13 | </buildCommand> | |||
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14 | <buildCommand> | |||
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15 | <name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name> | |||
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16 | <triggers>full,incremental,</triggers> | |||
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17 | <arguments> | |||
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18 | </arguments> | |||
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19 | </buildCommand> | |||
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20 | </buildSpec> | |||
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21 | <natures> | |||
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22 | <nature>org.eclipse.cdt.core.cnature</nature> | |||
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23 | <nature>org.eclipse.cdt.core.ccnature</nature> | |||
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24 | <nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature> | |||
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25 | <nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature> | |||
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26 | <nature>de.innot.avreclipse.core.avrnature</nature> | |||
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27 | </natures> | |||
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28 | </projectDescription> No newline at end of file | |||
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1 | avrtarget/ClockFrequency=1000000 | |||
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2 | avrtarget/ExtRAMSize=0 | |||
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3 | avrtarget/ExtendedRAM=false | |||
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4 | avrtarget/MCUType=atxmega32d4 | |||
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5 | avrtarget/UseEEPROM=false | |||
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6 | avrtarget/UseExtendedRAMforHeap=true | |||
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7 | avrtarget/perConfig=false | |||
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8 | eclipse.preferences.version=1 No newline at end of file | |||
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1 | /* | |||
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2 | * acquisitiond.c | |||
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3 | * | |||
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4 | * Created on: Mar 24, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #include "acquisitiond.h" | |||
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9 | #include "fpgaport.h" | |||
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10 | ||||
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11 | volatile uint8_t is_acquiring = 0; | |||
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12 | volatile uint8_t send_flg = 0; | |||
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13 | ||||
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14 | // Comandos para el ADC | |||
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15 | #define CMD_ACTV 0 | |||
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16 | #define CMD_DACTV 1 | |||
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17 | #define CMD_RATE 2 | |||
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18 | #define CMD_RPARAM 3 | |||
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19 | #define CMD_WPARAM 4 | |||
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20 | #define CMD_START 5 | |||
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21 | #define CMD_STOP 6 | |||
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22 | #define CMD_INFO 7 | |||
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23 | #define CMD_GAIN 8 | |||
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24 | #define CMD_ID 9 | |||
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25 | #define CMD_STATUS 10 | |||
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26 | #define CMD_PPS 11 | |||
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27 | ||||
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28 | ||||
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29 | /*! | |||
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30 | * \fn acq_chn_activate | |||
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31 | * \breif activa la comunicacion con el IC ADC | |||
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32 | * \see acq_chn_deactivate | |||
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33 | */ | |||
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34 | void acq_chn_activate(){ | |||
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35 | adcport_open(); | |||
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36 | } | |||
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37 | ||||
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38 | ||||
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39 | /*! | |||
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40 | * \fn acq_chn_deactivate | |||
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41 | * \breif desactiva la comunicacion con el IC ADC | |||
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42 | * \see acq_chn_activate | |||
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43 | */ | |||
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44 | void acq_chn_deactivate(){ | |||
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45 | adcport_close(); | |||
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46 | } | |||
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47 | ||||
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48 | ||||
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49 | /*! | |||
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50 | * \fn acq_chn_datarate | |||
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51 | * \breif Configura el datarate del ADC | |||
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52 | * \param datarate El datarate deseado | |||
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53 | */ | |||
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54 | void acq_chn_datarate(uint16_t datarate){ | |||
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55 | if(is_acquiring==1){ | |||
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56 | acq_stop_acquisiton(); | |||
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57 | } | |||
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58 | acq_set_param_to_adc(CMD_RATE,datarate); | |||
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59 | } | |||
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60 | ||||
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61 | ||||
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62 | /*! | |||
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63 | * \fn acq_send_information | |||
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64 | * \breif Envia informacion relevante al Embebido (a traves de FPGA) | |||
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65 | */ | |||
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66 | void acq_send_information(){ | |||
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67 | if(is_acquiring==1){ | |||
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68 | acq_stop_acquisiton(); | |||
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69 | } | |||
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70 | acq_send_param(CMD_RATE); | |||
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71 | acq_send_param(CMD_GAIN); | |||
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72 | acq_send_param(CMD_ID); | |||
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73 | acq_send_param(CMD_STATUS); | |||
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74 | acq_send_param(CMD_PPS); | |||
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75 | } | |||
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76 | ||||
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77 | ||||
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78 | /*! | |||
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79 | * \fn acq_chn_datarate | |||
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80 | * \breif Envia parametros al embebido a traves del FPGA (este se debe encargar | |||
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81 | * de hacer el puente al embebido) | |||
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82 | * \param param El parametro que se quiere enviar al embebido | |||
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83 | */ | |||
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84 | void acq_send_param(uint8_t param){ | |||
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85 | uint8_t data; | |||
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86 | fpgaport_open(); | |||
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87 | fpgaport_write(param); | |||
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88 | switch(param){ | |||
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89 | case CMD_RATE: | |||
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90 | // TODO secuencia de comandos para obtener el datarate del ADC | |||
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91 | break; | |||
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92 | case CMD_GAIN: | |||
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93 | data=adcport_get_param(GAIN0); | |||
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94 | break; | |||
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95 | case CMD_ID: | |||
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96 | data=adcport_get_param(ID); | |||
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97 | break; | |||
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98 | case CMD_STATUS: | |||
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99 | data=adcport_get_param(STATUS); | |||
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100 | break; | |||
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101 | case CMD_PPS: | |||
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102 | break;// TODO | |||
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103 | default: | |||
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104 | // con esta opcion se puede leer los registros del ADC definidos en | |||
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105 | // "adcpot.h" y enviarlos al embebido | |||
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106 | data= adcport_get_param(param); | |||
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107 | break; | |||
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108 | } | |||
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109 | ||||
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110 | fpgaport_write(data); | |||
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111 | fpgaport_close(); | |||
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112 | } | |||
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113 | ||||
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114 | ||||
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115 | /*! | |||
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116 | * \fn acq_send_buff | |||
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117 | * \breif Envia el contenido de un buffer de datos hacia el | |||
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118 | * FPGA para que sean pre-procesados. | |||
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119 | */ | |||
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120 | /* | |||
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121 | * Esta funcion debe ser ejecutada con la señal de una interrupcion externa | |||
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122 | * manejada por software, que le indicara que hay un buffer lleno listo | |||
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123 | * para pre-procesar (vea adcport.c ). | |||
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124 | */ | |||
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125 | void acq_send_buff(){ | |||
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126 | uint8_t i=0; | |||
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127 | uint32_t* pbuff = adcport_getbuff(); | |||
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128 | fpgaport_open(); | |||
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129 | while(!(i==BUFF_SIZE)){ | |||
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130 | fpgaport_write(pbuff[i]); | |||
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131 | i++; | |||
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132 | } | |||
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133 | fpgaport_close(); | |||
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134 | } | |||
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135 | ||||
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136 | ||||
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137 | /*! | |||
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|
138 | * \fn acq_chn_set_datarate | |||
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139 | * \breif configura edl datarate del ADC | |||
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140 | * \param datarate | |||
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141 | */ | |||
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142 | void acq_chn_set_datarate(uint8_t datarate){ | |||
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|
143 | // TODO secuencia de comandos para configurar el data rate | |||
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144 | } | |||
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145 | ||||
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146 | ||||
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147 | /*! | |||
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|
148 | * \fn acq_process_cmd | |||
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149 | * \breif Procesa todos los comandos enviados desde el FPGA. | |||
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150 | * \param cmd Comando a procesar. | |||
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151 | */ | |||
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152 | /* | |||
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153 | * Esta funcion debe ejecutarse al haber una interrupcion en el puerto que | |||
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154 | * conecta al FPGA | |||
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155 | */ | |||
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156 | void acq_process_cmd(uint8_t cmd){ | |||
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157 | static uint8_t param; | |||
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158 | static uint8_t data; | |||
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159 | cli();// desactiva interrupciones | |||
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160 | fpgaport_open(); | |||
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161 | switch(cmd){ | |||
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162 | case CMD_ACTV: acq_chn_activate(); | |||
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163 | break; | |||
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164 | case CMD_DACTV:acq_chn_deactivate(); | |||
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165 | break; | |||
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166 | case CMD_RATE: | |||
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167 | param=fpgaport_read(); | |||
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168 | acq_chn_set_datarate(param); | |||
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169 | break; | |||
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170 | case CMD_RPARAM: | |||
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|
|
171 | param=fpgaport_read(); | |||
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172 | acq_send_param(param); | |||
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173 | break; | |||
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|
174 | case CMD_WPARAM: | |||
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|
|
175 | cmd=fpgaport_read();//lee | |||
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176 | data=fpgaport_read();//lee valor | |||
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|
177 | acq_set_param_to_adc(cmd,data); | |||
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178 | break; | |||
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179 | case CMD_START: | |||
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|
180 | acq_start_acquisition(); | |||
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181 | break; | |||
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|
182 | case CMD_STOP: | |||
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|
183 | acq_stop_acquisition(); | |||
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184 | break; | |||
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185 | case CMD_INFO: | |||
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|
186 | acq_send_information(); | |||
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187 | break; | |||
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188 | default: break; | |||
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189 | } | |||
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190 | fpgaport_close(); | |||
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191 | sei();//acvtiva interrupciones | |||
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192 | } | |||
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193 | ||||
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194 | ||||
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195 | /*! | |||
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|
196 | * \fn acq_set_param | |||
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|
197 | * \breif Procesa todos los comandos enviados desde el FPGA. | |||
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198 | * \param param Parametro a configurar. | |||
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199 | * \param value Valor del parametro | |||
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200 | */ | |||
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201 | void acq_set_param(uint8_t param, uint8_t value){ | |||
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|
202 | adcport_tranceiv(param); | |||
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203 | adcport_tranceiv(value); | |||
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204 | } | |||
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205 | ||||
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206 | ||||
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207 | /*! | |||
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|
|
208 | * \fn acq_start_acquisition | |||
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|
|
209 | * \breif Inicia la adquisicion de datos, esta se hara a traves de interrupciones | |||
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210 | * "software" (ver adcport.c) | |||
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|
211 | */ | |||
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|
212 | void acq_start_acquisition(){ | |||
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213 | is_acquiring = 1; | |||
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214 | adcport_start(); | |||
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215 | } | |||
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216 | ||||
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217 | /*! | |||
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218 | * \fn acq_stop_acquisition | |||
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|
|
219 | * \breif Para la adquisicion de datos. Las interrupciones utilizadas para | |||
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|
|
220 | * este fin son desactivadas. | |||
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|
221 | */ | |||
|
|
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222 | void acq_stop_acquisition(){ | |||
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223 | is_acquiring=0; | |||
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224 | adcport_stop(); | |||
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225 | } | |||
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226 | ||||
|
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227 | ||||
|
|
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|
|
228 | /* | |||
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|
|
229 | * interrupcion en algun pin que no se este usdando. | |||
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230 | * Interrupcion software. No puede ser PORTC_INT0_vect | |||
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231 | * Se usara para le indiquen que ya hay un buffer lleno | |||
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232 | * (ver adcport.c) | |||
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|
233 | */ | |||
|
|
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|
|
234 | ISR(PORTx_INTx_vect){ // FIXME | |||
|
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|
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235 | send_flg=1; | |||
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|
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236 | } | |||
|
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|
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237 | ||||
|
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238 | ||||
|
|
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239 | ||||
|
|
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|
|
240 | /* | |||
|
|
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|
|
241 | * interrupcion en algun pin que no se este usdando. | |||
|
|
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|
|
242 | * Interrupcion software. No puede ser PORTC_INT0_vect | |||
|
|
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|
|
243 | * Se usara para le indiquen que ya hay un buffer lleno | |||
|
|
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|
244 | * (ver adcport.c) | |||
|
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|
|
245 | */ | |||
|
|
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|
|
246 | ISR(PORTx_INTx_vect){ // FIXME | |||
|
|
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|
|
247 | send_flg=1; | |||
|
|
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|
|
248 | } | |||
|
|
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|
|
249 | ||||
|
|
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|
|
250 | /*! | |||
|
|
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|
|
251 | * \brief Espera que un buffer este lleno para enviarlo al fpga | |||
|
|
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|
|
252 | */ | |||
|
|
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|
|
253 | int main(){ | |||
|
|
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|
|
254 | do{ | |||
|
|
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|
|
255 | if(send_flg==1){ | |||
|
|
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|
|
256 | send_flg=0; | |||
|
|
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|
|
257 | acq_send_buff(); | |||
|
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258 | } | |||
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259 | }while(1); | |||
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260 | return 0; | |||
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261 | } No newline at end of file | |||
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1 | /* | |||
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2 | * acquisitiond.h | |||
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3 | * | |||
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4 | * Created on: Mar 24, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #ifndef ACQUISITIOND_H_ | |||
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9 | #define ACQUISITIOND_H_ | |||
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10 | ||||
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11 | #include <avr/io.h> | |||
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12 | #include <avr/interrupt.h> | |||
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13 | #include "adcport.h" | |||
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14 | ||||
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15 | void acq_chn_activate(); | |||
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16 | void acq_chn_deactivate(); | |||
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17 | void acq_chn_datarate(uint16_t datarate); | |||
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18 | ||||
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19 | ||||
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20 | void acq_send_information(); | |||
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21 | void acq_send_param(uint8_t param); | |||
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22 | void acq_send_buff(); | |||
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23 | ||||
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24 | ||||
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25 | void acq_process_cmd(uint8_t cmd); | |||
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26 | ||||
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27 | void acq_set_param_to_adc(uint8_t cmd, uint8_t data); | |||
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28 | ||||
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29 | ||||
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30 | void acq_start_acquisition(); | |||
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31 | void acq_stop_acquisition(); | |||
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32 | ||||
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33 | ||||
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34 | ||||
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35 | #endif /* ACQUISITIOND_H_ */ No newline at end of file | |||
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1 | /* | |||
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2 | * adcport.c | |||
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3 | * | |||
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4 | * Created on: Mar 25, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #include "adcport.h" | |||
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9 | #include <avr/io.h> | |||
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10 | #include <avr/interrupt.h> | |||
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11 | ||||
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12 | ||||
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13 | #define SPI_SS_bm PIN4_bm /*!< \brief Bit mask para el pin SS. */ | |||
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14 | #define SPI_MOSI_bm PIN5_bm /*!< \brief Bit mask para el pin MOSI. */ | |||
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15 | #define SPI_MISO_bm PIN6_bm /*!< \brief Bit mask para el pin MISO. */ | |||
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16 | #define SPI_SCK_bm PIN7_bm /*!< \brief Bit mask para el pin SCK. */ | |||
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17 | ||||
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18 | ||||
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19 | #define SS_OFF PORTC.OUTSET=PIN4_bm;/*!< \brief Deselecciona el ADC (puerto SPI) */ | |||
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20 | #define SS_ON PORTC.OUTCLR=PIN4_bm;/*!< \brief Selecciona el ADC (puerto SPI) */ | |||
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21 | ||||
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22 | ||||
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23 | /* | |||
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24 | * Al iniciar la adquisicion se debe activar la interrupcion del pin RDY a | |||
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25 | * traves del PINC6 del XMEGA. | |||
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26 | * Luego al leer los datos digitalizados, se debe desactivar. Al terminar | |||
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27 | * se reactiva para esperar la siguiente interrupcion. | |||
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28 | * Esto se debe a que el DOUT y el RDY del ADC comparten el pin. Si se dejara | |||
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29 | * activa la interrupcion al leer, se generarian interrupciones e los flancos | |||
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30 | * de bajada generados por la transferencia de las muestras | |||
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31 | */ | |||
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32 | #define WAIT_DATA PORTC.INT0MASK=PIN6_bm/*!< \brief Activa interrupcion que indica dato nuevo */ | |||
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33 | #define GET_DATA PORTC.INT0MASK=0/*!< \brief Desactiva iterrupcion que indica dato nuevo */ | |||
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34 | ||||
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35 | ||||
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36 | volatile uint8_t buff_idx; | |||
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37 | uint32_t * pfull_buff; | |||
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38 | uint32_t * pread_buff; | |||
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39 | volatile uint8_t buff_full_flg = 0; | |||
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40 | ||||
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41 | /*! | |||
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42 | * \fn adcport_ready_interrupt_config | |||
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43 | * \brief configura el pin de MISO (conectado a DOUT del ADC), para que dispare | |||
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44 | * una interrupcion por flanco de bajada. | |||
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45 | * una vez disparada la interrupcion, se puede leer el pin; sin embargo, debe | |||
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46 | * desactivarse antes de leer la interrupcion por flanco (con GET_DATA). De lo | |||
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47 | * contrario se disparara la interrupcion varias veces al leer los datos, ya | |||
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48 | * que ese el pin RDY y DOUT es el mismo en el ADC. | |||
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49 | */ | |||
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50 | inline void adcport_ready_interrupt_config(){ | |||
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51 | // pin6: MISO(xmega) --> DOUT/RDY(ADC) => pin6 entrada | |||
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52 | PORTC.DIRCLR=PIN6_bm; | |||
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|
53 | // El ADC llevara a "low" RDY cuando la conversion de un dato haya concluido | |||
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54 | // Se debe leer el dato generado luego. Se espera una interrupcion de flanco | |||
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55 | // de bajada para manejar esto | |||
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|
56 | PORTC.PIN6CTRL=PORT_ISC_FALLING_gc; | |||
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57 | // Se mapea la interrupcion externa INT0 de PORTC a PINC6 | |||
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|
58 | PORTC.INT0MASK=PIN6_bm; | |||
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|
59 | // Debido a que esta interrupcion va a manejar la adquisicion de datos, se | |||
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60 | // le da maxima prioridad (nivel alto) | |||
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61 | PORTC.INTCTRL=PORT_INT0LVL_HI_gc; | |||
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62 | // Se habilita la atencion de interrupciones de nivel alto | |||
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63 | PMIC.CTRL|= PMIC_HILVLEN_bm; | |||
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64 | } | |||
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65 | ||||
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66 | ||||
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67 | /*! | |||
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68 | * \fn adcport_spi_config | |||
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69 | * \brief configura el puerto SPI para que coincida con el requerimiento del ADC | |||
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70 | * AD7178-2 | |||
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71 | */ | |||
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72 | inline void adcport_spi_config(){ | |||
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73 | PORTC.DIRSET = SPI_MOSI_bm | SPI_SCK_bm | SPI_SS_bm; | |||
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74 | // Preescaler: clkper/2 (con clk2x). Maestro. CPOL=1,CPHA=1 | |||
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75 | // MSB primero | |||
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76 | SPIC.CTRL = SPI_CLK2X_bm|SPI_ENABLE_bm|SPI_MASTER_bm| | |||
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77 | SPI_MODE1_bm|SPI_MODE0_bm; | |||
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78 | } | |||
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79 | ||||
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80 | ||||
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81 | /*! | |||
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82 | * \fn adcport_config | |||
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83 | * \brief Configura el microcontrolador para darle servicio a la interrupcion | |||
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84 | * del pin "RDY" del ADC, que reacciona con un flanco de bajada cuando se ha | |||
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85 | * terminado de digitalar una muestra nueva. | |||
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86 | * Tambien configura el puerto SPI que servira para comunicarse con el ADC. | |||
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87 | * \see adcport_ready_interrupt_config | |||
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88 | * \see adcport_spi_config | |||
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89 | */ | |||
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90 | inline void adcport_config(){ | |||
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91 | adcport_ready_interrupt_config(); | |||
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92 | adcport_spi_config(); | |||
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93 | // TODO configurar ADC: datarate, ganancia, desactivar CRC, formato numerico | |||
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94 | // de muestras debe ser "bipolar offset binary"(canales diferenciales). | |||
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95 | } | |||
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96 | ||||
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97 | ||||
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98 | /*! | |||
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99 | * \fn adcport_open | |||
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100 | * \brief Inicializa el buffer de entrada (para datos de 24bits del ADC) y | |||
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101 | * activa la comunicacion a traves del pin "SS" del puerto SPI. | |||
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102 | * \see adcport_close | |||
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103 | */ | |||
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104 | inline void adcport_open(){ | |||
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105 | buff_idx=0; | |||
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106 | // TODO configurar interrupcion externa PPS (pin 6) | |||
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107 | // TODO configurar interrupcion externa LOCK (pin 21) | |||
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108 | pfull_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); | |||
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109 | pread_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); | |||
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110 | adcport_config(); | |||
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111 | SS_ON; | |||
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112 | } | |||
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113 | ||||
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114 | ||||
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115 | /*! | |||
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116 | * \fn adcport_close | |||
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117 | * \brief Desactiva la comunicacion con el ADC a traves del pin "SS" del puerto | |||
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118 | * SPI. | |||
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119 | * \see adcport_open | |||
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120 | */ | |||
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121 | inline void adcport_close(){ | |||
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122 | SS_OFF; | |||
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123 | free(pfull_buff); | |||
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124 | free(pread_buff); | |||
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125 | } | |||
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126 | ||||
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127 | ||||
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128 | /*! | |||
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129 | * \fn adcport_start | |||
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130 | * \brief Inicia la digitalizacion de muestras del sensor. | |||
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131 | * SPI. | |||
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132 | * \see adcport_stop | |||
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133 | * \see adcport_open | |||
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134 | * \see adcport_close | |||
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135 | */ | |||
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136 | inline void adcport_start(){ | |||
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137 | // necesario para darle servicio con interrupciones al flanco de bajada | |||
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138 | // del pin "RDY" | |||
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139 | WAIT_DATA; | |||
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140 | // TODO enviar comandos al ADC para que inicie la adquisicion. | |||
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141 | } | |||
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142 | ||||
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143 | ||||
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144 | /*! | |||
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|
145 | * \fn adcport_stop | |||
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146 | * \brief Pausa la digitalizacion de muestras del sensor. | |||
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147 | * SPI. | |||
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148 | * \see adcport_start | |||
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149 | * \see adcport_open | |||
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150 | * \see adcport_close | |||
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151 | */ | |||
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152 | inline void adcport_stop(){ | |||
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153 | // TODO enviar comandos al ADC para que deje de adquirir. | |||
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154 | // necesario para cortar el servicio interrupcion del pin "RDY" | |||
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155 | GET_DATA; | |||
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156 | } | |||
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157 | ||||
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158 | ||||
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159 | /*! | |||
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160 | * \fn adcport_tranceiv | |||
|
|
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|
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161 | * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y | |||
|
|
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|
|
162 | * el microcontrolador. | |||
|
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|
|
163 | * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la | |||
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|
|
164 | * transmision genera clock en el pin "sclk" | |||
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165 | * \param El dato a transmitir | |||
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166 | * \return El dato leido del ADC | |||
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167 | */ | |||
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168 | inline uint8_t adcport_tranceiv(uint8_t data){ | |||
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169 | // | |||
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170 | SPIC.DATA = data; | |||
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171 | ||||
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172 | //Wait until transmission complete | |||
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173 | while(!(SPIC.STATUS)&SPI_IF_bm); | |||
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174 | ||||
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175 | // Return received data | |||
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176 | return SPIC.DATA; | |||
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177 | } | |||
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178 | ||||
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179 | ||||
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180 | /*! | |||
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181 | * \fn adcport_start | |||
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182 | * \brief Inicia la digitalizacion de muestras del sensor. | |||
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183 | * SPI. | |||
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184 | * \see adcport_open | |||
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185 | */ | |||
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186 | void adcport_read_sample(){ | |||
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187 | uint32_t aux; | |||
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188 | GET_DATA; // desactiva interrupciones de flaco de bajada | |||
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189 | // Se le indica al adc que se va a leer el registro de data. | |||
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190 | adcport_tranceiv(0x44); | |||
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191 | // El byte mas significativo de la variable de 32bits es cero | |||
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192 | // La codificacion de los numeros es "bipolar offset binary" y | |||
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193 | // la transmision es MSB first | |||
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194 | aux = adcport_tranceiv(0); | |||
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195 | aux = (aux<<8)|adcport_tranceiv(0); | |||
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196 | aux = (aux<<8)|adcport_tranceiv(0); | |||
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197 | aux = (aux<<8)|adcport_tranceiv(0); | |||
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198 | pread_buff[buff_idx]=aux; | |||
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199 | ||||
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200 | WAIT_DATA; // reactiva interrupciones de flanco de bajada | |||
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201 | } | |||
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202 | ||||
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203 | ||||
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204 | /*! | |||
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205 | * \fn adcport_getbuff | |||
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206 | * \brief Devuelve la direccion del buffer lleno | |||
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207 | * \return Direccion del buffer lleno. 0 si no esta lleno aun | |||
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208 | */ | |||
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209 | inline uint32_t* adcport_getbuff(){ | |||
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210 | if(buff_full_flg==1){ | |||
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211 | buff_full_flg=0; | |||
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212 | return pfull_buff; | |||
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213 | } | |||
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214 | return 0; | |||
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215 | } | |||
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216 | ||||
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217 | ||||
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218 | uint8_t adcport_get_param(uint8_t data){ | |||
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219 | adcport_tranceiv(data); | |||
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220 | return adcport_tranceiv(0); | |||
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221 | } | |||
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222 | ||||
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223 | ||||
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224 | /*! | |||
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225 | * \brief interrupcion externa debe dispararse en flanco de bajada en PC6 (RDY del ADC). | |||
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226 | * Cuando el ADC lleva este pin a "low", se debe leer el dato nuevo | |||
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227 | */ | |||
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228 | ISR(PORTC_INT0_vect){ | |||
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229 | adcport_read_sample(); | |||
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230 | buff_idx++; | |||
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231 | if(buff_idx>=100){ | |||
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232 | uint32_t* paux = pread_buff; | |||
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233 | pread_buff = pfull_buff; | |||
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234 | pfull_buff = paux; | |||
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235 | buff_full_flg=1; | |||
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236 | // TODO dar aviso al programa principal que el buffer esta lleno. | |||
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237 | // Puede ser a traves de una interrupcion "externa" en un pin que no se | |||
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238 | // use, para lo cual debe estar configurado como salida y para recibir | |||
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239 | // interrupciones de IO. | |||
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240 | // para hacer que funcione como una interrupcion software, solo escribir | |||
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241 | // en ese pin un valor segun se configure la interrupcion | |||
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242 | } | |||
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243 | } | |||
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244 | ||||
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245 | ||||
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246 | /* TODO | |||
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247 | * interrupcion del LOCK del GNSS (pin numero 21 del xmega) | |||
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248 | * servira para indicar que el GNSS esta sincronizado con satelites y la hora y | |||
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249 | * PPS son correctos, a partir de ese momento se pueden contar los PPS y | |||
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250 | * identificarlos en el header. | |||
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251 | */ | |||
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252 | ISR(PORTx_INTx_vect){ // FIXME | |||
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253 | ||||
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254 | } | |||
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255 | ||||
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256 | ||||
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257 | /* TODO | |||
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258 | * interrupcion del PPS del GNSS (pin numero 6 del xmega) | |||
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259 | * servira para sincronizar la hora. Debe agregar un numero de serie entre 0 y 255 | |||
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260 | * a la cabecera del buffer que indentifique al PPS; y el numero de muestra que se adquirio | |||
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261 | * en el momento de la llegada de esta interrupcion. | |||
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262 | */ | |||
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263 | ISR(PORTx_INTx_vect){ // FIXME | |||
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264 | ||||
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265 | } | |||
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266 | No newline at end of file | |||
| @@ -0,0 +1,60 | |||||
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1 | /* | |||
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2 | * adcport.h | |||
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3 | * | |||
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4 | * Created on: Mar 25, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #ifndef ADCPORT_H_ | |||
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9 | #define ADCPORT_H_ | |||
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10 | ||||
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11 | #include <inttypes.h> | |||
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12 | ||||
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13 | #define BUFF_SIZE 100 | |||
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14 | ||||
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15 | /* Direcciones de registros del ADC */ | |||
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16 | ||||
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17 | #define COMMS 0x00 | |||
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18 | #define STATUS 0x00 | |||
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19 | #define ADCMODE 0x01 | |||
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20 | #define IFMODE 0x02 | |||
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21 | #define REGCHECK 0x03 | |||
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22 | #define DATA 0X04 | |||
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23 | #define GPIOCON 0x06 | |||
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24 | #define ID 0x07 | |||
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25 | ||||
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26 | #define CHMAP0 0x10 | |||
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27 | #define CHMAP1 0x11 | |||
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28 | #define CHMAP2 0x12 | |||
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29 | #define CHMAP3 0x13 | |||
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30 | ||||
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31 | #define SETUPCON0 0x20 | |||
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32 | #define SETUPCON1 0x21 | |||
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33 | #define SETUPCON2 0x22 | |||
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34 | #define SETUPCON3 0x23 | |||
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35 | ||||
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36 | #define FILTCON0 0x28 | |||
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37 | #define FILTCON1 0x29 | |||
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38 | #define FILTCON2 0x2A | |||
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39 | #define FILTCON3 0x2B | |||
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40 | ||||
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41 | #define OFFSET0 0x30 | |||
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42 | #define OFFSET1 0x31 | |||
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43 | #define OFFSET2 0x32 | |||
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44 | #define OFFSET3 0x33 | |||
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45 | ||||
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46 | #define GAIN0 0x38 | |||
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47 | #define GAIN1 0x39 | |||
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48 | #define GAIN2 0x2A | |||
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49 | #define GAIN3 0x2B | |||
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50 | ||||
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51 | ||||
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52 | void adcport_open(); | |||
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53 | void adcport_close(); | |||
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54 | void adcport_start(); | |||
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55 | void adcport_stop(); | |||
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56 | uint32_t* adcport_getbuff(); | |||
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57 | uint8_t adcport_tranceiv(uint8_t data); | |||
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58 | uint8_t adcport_get_param(uint8_t data); | |||
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59 | ||||
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60 | #endif /* ADCPORT_H_ */ No newline at end of file | |||
| @@ -0,0 +1,57 | |||||
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|
1 | /* | |||
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2 | * fpgaport.c | |||
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3 | * | |||
|
|
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|
|
4 | * Created on: Mar 26, 2015 | |||
|
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|
|
5 | * Author: shinobi | |||
|
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6 | */ | |||
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|
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7 | ||||
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8 | ||||
|
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|
|
9 | /*! | |||
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|
|
10 | * \fn fpgaport_open | |||
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11 | * \brief actima la comunicacion con el FPGA | |||
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12 | */ | |||
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|
|
13 | inline void fpgaport_open(){ | |||
|
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|
|
14 | // TODO configurar puerto pfga e interrupcion externa (pin 22) | |||
|
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|
|
15 | // TODO configurar interrupcion externa PPS (pin 6) | |||
|
|
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|
|
16 | // TODO configurar interrupcion externa LOCK (pin 21) | |||
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|
|
17 | } | |||
|
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18 | ||||
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19 | ||||
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20 | /*! | |||
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|
|
21 | * \fn fpgaport_close | |||
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|
|
22 | * \brief Desactiva la comunicacion con el FPGA | |||
|
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|
|
23 | */ | |||
|
|
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|
|
24 | inline void fpgaport_close(){ | |||
|
|
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|
|
25 | // TODO configurar puerto pfga e interrupcion externa (pin 22) para | |||
|
|
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|
|
26 | // clock | |||
|
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|
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27 | } | |||
|
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|
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28 | ||||
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29 | ||||
|
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|
|
30 | /*! | |||
|
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|
|
31 | * \fn fpgaport_write | |||
|
|
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|
|
32 | * \breif activa la comunicacion con el IC ADC | |||
|
|
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|
|
33 | * \see acq_chn_deactivate | |||
|
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|
|
34 | */ | |||
|
|
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|
|
35 | inline void fpgaport_write(uint8_t data){ | |||
|
|
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|
|
36 | // TODO | |||
|
|
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|
|
37 | } | |||
|
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|
|
38 | ||||
|
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|
|
39 | ||||
|
|
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|
|
40 | /*! | |||
|
|
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|
|
41 | * \fn fpgaport_read | |||
|
|
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|
|
42 | * \breif activa la comunicacion con el IC ADC | |||
|
|
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|
|
43 | * \see acq_chn_deactivate | |||
|
|
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|
|
44 | */ | |||
|
|
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|
|
45 | inline uint8_t fpgaport_read(){ | |||
|
|
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|
|
46 | // TODO | |||
|
|
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|
|
47 | } | |||
|
|
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|
|
48 | ||||
|
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|
49 | ||||
|
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|
|
50 | /* | |||
|
|
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|
|
51 | * Interrupcion de dato entrante por el puerto FPGA. El pin debe ser alguno de los | |||
|
|
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|
|
52 | * que estan conectatos al FPGA (el bus) | |||
|
|
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53 | */ | |||
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54 | ISR(PORTx_INTx_vect){ | |||
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55 | // TODO debe idicar que se ejecute la funcion que procesa los comandos | |||
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56 | // que bienen del FPGA | |||
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57 | } No newline at end of file | |||
| @@ -0,0 +1,19 | |||||
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1 | /* | |||
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2 | * fpgaport.h | |||
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3 | * | |||
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4 | * Created on: Mar 26, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #ifndef FPGAPORT_H_ | |||
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9 | #define FPGAPORT_H_ | |||
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10 | ||||
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11 | #include <inttypes.h> | |||
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12 | ||||
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13 | void fpgaport_open(); | |||
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14 | void fpgaport_close(); | |||
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15 | void fpgaport_write(uint8_t data); | |||
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16 | uint8_t fpgaport_read(); | |||
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17 | ||||
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18 | ||||
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19 | #endif /* FPGAPORT_H_ */ No newline at end of file | |||
| @@ -0,0 +1,286 | |||||
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1 | /* | |||
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2 | * powerEngine.c | |||
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3 | * | |||
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4 | * Created on: Mar 23, 2015 | |||
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5 | * Author: shinobi | |||
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6 | */ | |||
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7 | ||||
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8 | #include "powerEngined.h" | |||
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9 | #include "usi_i2c_slave.h" | |||
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10 | #include <util/delay.h> | |||
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11 | #include <avr/interrupt.h> | |||
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12 | ||||
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|
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13 | #define DQ_HIGH DQ_PORT |= (1<<DQ_BIT) | |||
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14 | #define DQ_LOW DQ_PORT &= ~(1<<DQ_BIT) | |||
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15 | #define DQ_INPUT DQ_DDR &= ~(1<<DQ_BIT) | |||
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16 | #define DQ_OUTPUT DQ_DDR |= (1<<DQ_BIT) | |||
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17 | #define DQ_READ ((DQ_PIN&(1<<DQ_BIT))!=0)?0x01:0x00 | |||
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18 | ||||
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19 | #define US (1000000.0/ F_CPU ) | |||
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20 | ||||
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21 | ||||
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22 | #define TM0_ON TCCR0B |=(0<<CS02)|(0<<CS01)|(1<<CS00) | |||
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23 | #define TM0_OFF TCCR0B &= ~((1<<CS02)|(1<<CS01)|(1<<CS00)) | |||
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24 | ||||
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25 | #define TM1_ON TCCR1 |= (1<<CS13)|(1<<CS12)|(1<<CS11)|(1<<CS10) | |||
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26 | #define TM1_OFF TCCR1 &= ~((1<<CS13)|(1<<CS12)|(1<<CS11)|(1<<CS10)) | |||
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27 | ||||
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28 | #define MAX_TM_CYCLES 15 | |||
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29 | ||||
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30 | volatile uint8_t presenced_flg = 0; | |||
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31 | volatile uint8_t process_flg = 0; | |||
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32 | volatile uint8_t tm_cycles = 0; | |||
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33 | ||||
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34 | ||||
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35 | extern char* USI_Slave_register_buffer[]; | |||
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36 | ||||
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37 | /*! | |||
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38 | * \fn write_0_signal | |||
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39 | * \brief genera el simbolo que corresponde a '0' logico en el protocolo | |||
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40 | * especificatdo en el datasheet del IC DS2438Z | |||
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41 | * \see write_1_signal | |||
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42 | * \see write_byte | |||
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43 | */ | |||
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44 | void write_0_signal(){ | |||
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45 | DQ_LOW; | |||
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46 | _delay_us(65); | |||
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47 | DQ_HIGH; | |||
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48 | _delay_us(1); | |||
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49 | } | |||
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50 | ||||
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51 | /*! | |||
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52 | * \fn write_1_signal | |||
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53 | * \brief genera el simbolo que corresponde a '1' logico en el protocolo | |||
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54 | * especificatdo en el datasheet del IC DS2438Z | |||
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55 | * \see write_0_signal | |||
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56 | * \see write_byte | |||
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57 | */ | |||
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58 | void write_1_signal(){ | |||
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59 | DQ_LOW; | |||
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60 | _delay_us(10); | |||
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61 | DQ_HIGH; | |||
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62 | _delay_us(56); | |||
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63 | } | |||
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64 | ||||
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65 | ||||
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66 | /*! | |||
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67 | * \fn write_byte | |||
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|
|
68 | * \brief Escribe un byte por el puerto DQ | |||
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69 | * \param byte El byte a escribir | |||
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70 | * \see write_0_signal | |||
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71 | * \see write_1_signal | |||
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72 | */ | |||
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73 | void write_byte(uint8_t byte){ | |||
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74 | uint8_t mask = 0x00; | |||
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75 | ||||
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76 | while(mask!=0){ | |||
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77 | if((byte&mask)!=0){ | |||
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78 | write_1_signal(); | |||
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79 | }else{ | |||
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80 | write_0_signal(); | |||
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81 | } | |||
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82 | mask = (uint8_t)(mask << 1); | |||
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83 | } | |||
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84 | } | |||
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85 | ||||
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86 | /*! | |||
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87 | * \fn write_bytes | |||
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|
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88 | * \brief Escribe "len" bytes por el puerto DQ | |||
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89 | * \param pbytes Puntero a inicio de buffer que contiene los bytes | |||
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90 | * \param len >Numero de bytes a escribir | |||
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91 | * \see write_byte | |||
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92 | */ | |||
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93 | void write_bytes(uint8_t* pbytes,uint8_t len){ | |||
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94 | do{ | |||
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95 | len-=1; | |||
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96 | write_byte(pbytes[len]); | |||
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97 | }while(len>0); | |||
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98 | } | |||
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99 | ||||
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100 | ||||
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101 | /*! | |||
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102 | * \fn read_signal | |||
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103 | * \brief Lee un bit del puerto DQ | |||
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104 | * \return '1' o '0'. | |||
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105 | * \see read_byte | |||
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106 | */ | |||
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107 | uint8_t read_signal(){ | |||
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108 | uint8_t bit = 0; | |||
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109 | ||||
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110 | DQ_LOW; | |||
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111 | _delay_us(2); | |||
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112 | DQ_HIGH; | |||
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113 | ||||
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114 | DQ_INPUT; | |||
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115 | _delay_us(8); | |||
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116 | bit = DQ_READ; | |||
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117 | _delay_us(55); | |||
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118 | ||||
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119 | DQ_OUTPUT; | |||
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120 | DQ_HIGH; | |||
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121 | _delay_us(1); | |||
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122 | ||||
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123 | return bit; | |||
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124 | } | |||
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125 | ||||
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126 | ||||
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127 | /*! | |||
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128 | * \fn read_byte | |||
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129 | * \brief Lee un byte de el puerto DQ | |||
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130 | * \see read_signal | |||
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131 | * \see read_bytes | |||
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132 | */ | |||
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133 | uint8_t read_byte(){ | |||
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134 | uint8_t shift = 0x00; | |||
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135 | uint8_t byte = 0x00; | |||
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136 | uint8_t bit= 0; | |||
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137 | while(shift< 8){ | |||
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138 | bit = read_signal(); | |||
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139 | byte |= (bit<<shift); | |||
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140 | shift++; | |||
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141 | } | |||
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142 | return byte; | |||
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143 | } | |||
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144 | ||||
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145 | ||||
|
|
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146 | /*! | |||
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147 | * \fn read_bytes | |||
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|
148 | * \brief Lee "len" bytes de el puerto DQ | |||
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149 | * \param pbytes puntero a buffer, contendra los bytes leidos. | |||
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150 | * \param len Numero de bytes a leer. | |||
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151 | * \see read_byte | |||
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|
|
152 | */ | |||
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|
|
153 | void read_bytes(uint8_t* pbytes, uint8_t len){ | |||
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|
154 | do{ | |||
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|
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|
155 | len-=1; | |||
|
|
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|
|
156 | pbytes[len] = read_byte(); | |||
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|
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|
157 | }while(len>0); | |||
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|
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|
|
158 | } | |||
|
|
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|
|
159 | ||||
|
|
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|
|
160 | ||||
|
|
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|
|
161 | /*! | |||
|
|
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|
|
162 | * \fn initialization | |||
|
|
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|
|
163 | * \brief Inicia o reinicia al IC DS2438Z | |||
|
|
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|
|
164 | */ | |||
|
|
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|
|
165 | void initialization(){ | |||
|
|
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|
|
166 | TCNT0 = 0x0000; | |||
|
|
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|
|
167 | presenced_flg = 0; | |||
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|
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|
|
168 | DQ_LOW; | |||
|
|
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|
|
169 | _delay_us(490); | |||
|
|
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|
|
170 | TM0_ON; | |||
|
|
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|
|
171 | DQ_HIGH; | |||
|
|
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|
|
172 | while(presenced_flg != 1){} | |||
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|
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|
|
173 | } | |||
|
|
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|
|
174 | ||||
|
|
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|
|
175 | ||||
|
|
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|
|
176 | /*! | |||
|
|
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|
|
177 | * \fn memory_read | |||
|
|
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|
|
178 | * \brief Realiza la lectura de toda la memoria del IC DS2438Z | |||
|
|
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|
|
179 | */ | |||
|
|
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|
|
180 | void memory_read(uint8_t* pbytes, uint8_t page_addr){ | |||
|
|
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|
|
181 | uint8_t crc; | |||
|
|
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|
|
182 | initialization(); | |||
|
|
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|
|
183 | write_byte(SKIP_ROM); | |||
|
|
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|
|
184 | write_byte(READ_SP); | |||
|
|
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|
|
185 | write_byte(page_addr); | |||
|
|
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|
|
186 | read_bytes(pbytes,8); | |||
|
|
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|
|
187 | crc = read_byte(); | |||
|
|
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|
|
188 | initialization(); | |||
|
|
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|
|
189 | } | |||
|
|
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|
|
190 | ||||
|
|
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|
|
191 | /*! | |||
|
|
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|
|
192 | * \fn convert | |||
|
|
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|
|
193 | * \brief Inicia la conversion ADC de los parametros desados | |||
|
|
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|
|
194 | * \param cmd CONVERT_T para iniciar la conversion de temperatura. CONVERT_V | |||
|
|
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195 | * para iniciar la conversion de voltaje. | |||
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196 | */ | |||
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197 | void convert(uint8_t cmd){ | |||
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198 | uint8_t bit = 0; | |||
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199 | initialization(); | |||
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200 | write_byte(SKIP_ROM); | |||
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201 | write_byte(cmd); | |||
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202 | do{ | |||
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203 | bit = read_signal(); | |||
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204 | }while(bit != 1); | |||
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205 | initialization(); | |||
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206 | } | |||
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207 | ||||
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208 | /*! | |||
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209 | * \fn void send_data | |||
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210 | * \brief Envia data al sistema enbebido por puerto twi | |||
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211 | * \param pbytes Puntero a buffer de bytes a enviar. | |||
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212 | * \param len Numero de bytes a enviar. Debe ser menor o igual a USI_SLAVE_REGISTER_COUNT. | |||
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213 | */ | |||
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214 | void send_data(uint8_t* pbytes, uint8_t len){ | |||
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215 | int i; | |||
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216 | for(i=0;i<USI_SLAVE_REGISTER_COUNT;i++){ | |||
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217 | if(i<len){ | |||
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218 | USI_Slave_register_buffer[i]=(char)(pbytes[i]); | |||
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219 | }else{ | |||
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220 | USI_Slave_register_buffer[i]='\0'; | |||
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221 | } | |||
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222 | } | |||
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223 | ||||
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224 | } | |||
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225 | ||||
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226 | ||||
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227 | //usado para cronometrar la lectura del presence pulse | |||
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228 | ISR(TIM0_COMPA_vect ){ | |||
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229 | TM0_OFF; | |||
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230 | } | |||
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231 | ||||
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232 | ||||
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233 | //detecta el nivel bajo. usado para detectar el presence pulse | |||
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234 | ISR(PCINT0_vect){ | |||
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235 | uint16_t cnt; | |||
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236 | if((PINB&(1<<PINB3))==0x00){ | |||
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237 | if((cnt>=60*US)&&(cnt<=240*US)){ | |||
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238 | presenced_flg=1; | |||
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239 | } | |||
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240 | } | |||
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241 | } | |||
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242 | ||||
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243 | ||||
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244 | ISR(TIM1_COMPB_vect){ | |||
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245 | tm_cycles++; // cuenta de 60 segundos | |||
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246 | if(tm_cycles>=MAX_TM_CYCLES){ | |||
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247 | process_flg = 1; | |||
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248 | tm_cycles=0; | |||
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249 | } | |||
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250 | } | |||
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251 | ||||
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252 | ||||
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253 | int main(){ | |||
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254 | uint8_t pbytes[8]; | |||
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255 | // inicializa | |||
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256 | USI_I2C_Init(I2C_SLAVE_ADDR); | |||
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257 | cli(); | |||
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258 | // interrupcion externa | |||
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259 | GIMSK |= _BV(PCIE); // Turn on Pin Change interrupt | |||
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260 | PCMSK |= _BV(PCINT3); // Which pins are affected by the interrupt | |||
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261 | // timer0 CTC con OCRA como top. Debe interrumpir en 250us luego de | |||
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262 | // TM0_ON | |||
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263 | TCCR0A = (1<<COM0A1)|(1<<COM0A0)|(1<<WGM01)|(0<<WGM00); | |||
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264 | TCCR0B = (0<<WGM02); | |||
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265 | TM0_OFF; | |||
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266 | OCR0A = (uint8_t)(250*US); | |||
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267 | // timer1 CTC TOP : OCR1C ; pre-scaler 16384 | |||
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268 | TCCR1 = (1<<COM1A1)|(1<<COM1A0); | |||
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269 | TM1_OFF; | |||
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270 | OCR1A = (uint8_t)(244*US);// x 15 ciclo x 16384 (pre-scaler) | |||
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271 | //Activa interrupciones de timers | |||
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272 | TIMSK |= (1<<OCIE1A)|(1<<OCIE0A); | |||
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273 | ||||
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274 | presenced_flg=0; | |||
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275 | sei(); | |||
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276 | do{ | |||
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277 | process_flg = 0; | |||
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278 | convert(CONV_T); | |||
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279 | convert(CONV_V); | |||
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280 | memory_read(pbytes,PAGE_0); | |||
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281 | send_data(pbytes,8); | |||
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282 | while(!(process_flg==1)){}; | |||
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283 | }while(1==1); | |||
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284 | ||||
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285 | return 0; | |||
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|
286 | } No newline at end of file | |||
| @@ -0,0 +1,349 | |||||
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|
1 | /*-----------------------------------------------------*\ | |||
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2 | | USI I2C Slave Driver | | |||
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3 | | | | |||
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4 | | This library provides a robust, interrupt-driven I2C | | |||
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5 | | slave implementation built on the ATTiny Universal | | |||
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6 | | Serial Interface (USI) hardware. Slave operation is | | |||
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7 | | implemented as a register bank, where each 'register' | | |||
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8 | | is a pointer to an 8-bit variable in the main code. | | |||
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9 | | This was chosen to make I2C integration transparent | | |||
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10 | | to the mainline code and making I2C reads simple. | | |||
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11 | | This library also works well with the Linux I2C-Tools | | |||
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12 | | utilities i2cdetect, i2cget, i2cset, and i2cdump. | | |||
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13 | | | | |||
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14 | | Adam Honse (GitHub: CalcProgrammer1) - 7/29/2012 | | |||
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|
15 | | -calcprogrammer1@gmail.com | | |||
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16 | \*-----------------------------------------------------*/ | |||
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17 | ||||
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18 | #include "usi_i2c_slave.h" | |||
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19 | ||||
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20 | char usi_i2c_slave_internal_address; | |||
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21 | char usi_i2c_slave_address; | |||
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22 | char usi_i2c_mode; | |||
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23 | ||||
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24 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |||
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25 | ////USI Slave States/////////////////////////////////////////////////////////////////////////////// | |||
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26 | /////////////////////////////////////////////////////////////////////////////////////////////////// | |||
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27 | ||||
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28 | ||||
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29 | ||||
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30 | // The I2C register file is stored as an array of pointers, point these to whatever your I2C registers | |||
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31 | // need to read/write in your code. This abstracts the buffer and makes it easier to write directly | |||
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32 | // to values in your code. | |||
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33 | char* USI_Slave_register_buffer[USI_SLAVE_REGISTER_COUNT]; | |||
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34 | char USI_Slave_internal_address = 0; | |||
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35 | char USI_Slave_internal_address_set = 0; | |||
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36 | ||||
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37 | enum | |||
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38 | ||||
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39 | { | |||
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40 | ||||
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41 | USI_SLAVE_CHECK_ADDRESS, | |||
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42 | USI_SLAVE_SEND_DATA, | |||
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43 | USI_SLAVE_SEND_DATA_ACK_WAIT, | |||
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44 | USI_SLAVE_SEND_DATA_ACK_CHECK, | |||
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45 | ||||
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46 | USI_SLAVE_RECV_DATA_WAIT, | |||
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47 | ||||
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48 | USI_SLAVE_RECV_DATA_ACK_SEND | |||
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49 | ||||
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50 | } USI_I2C_Slave_State; | |||
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51 | ||||
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52 | ///////////////////////////////////////////////// | |||
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|
53 | ////USI Register Setup Values//////////////////// | |||
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54 | ///////////////////////////////////////////////// | |||
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55 | ||||
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|
56 | #define USI_SLAVE_COUNT_ACK_USISR 0b01110000 | (0x0E << USICNT0) //Counts one clock (ACK) | |||
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57 | #define USI_SLAVE_COUNT_BYTE_USISR 0b01110000 | (0x00 << USICNT0) //Counts 8 clocks (BYTE) | |||
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58 | #define USI_SLAVE_CLEAR_START_USISR 0b11110000 | (0x00 << USICNT0) //Clears START flag | |||
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59 | #define USI_SLAVE_SET_START_COND_USISR 0b01110000 | (0x00 << USICNT0) | |||
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|
60 | #define USI_SLAVE_SET_START_COND_USICR 0b10101000 | |||
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|
61 | #define USI_SLAVE_STOP_DID_OCCUR_USICR 0b10111000 | |||
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|
|
62 | #define USI_SLAVE_STOP_NOT_OCCUR_USICR 0b11101000 | |||
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63 | ||||
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|
|
64 | ///////////////////////////////////////////////// | |||
|
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|
|
65 | ////USI Direction Macros///////////////////////// | |||
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66 | ///////////////////////////////////////////////// | |||
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67 | ||||
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68 | #define USI_SET_SDA_OUTPUT() { DDR_USI |= (1 << PORT_USI_SDA); } | |||
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|
69 | #define USI_SET_SDA_INPUT() { DDR_USI &= ~(1 << PORT_USI_SDA); } | |||
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70 | ||||
|
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|
71 | #define USI_SET_SCL_OUTPUT() { DDR_USI |= (1 << PORT_USI_SCL); } | |||
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|
72 | #define USI_SET_SCL_INPUT() { DDR_USI &= ~(1 << PORT_USI_SCL); } | |||
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|
73 | ||||
|
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|
|
74 | #define USI_SET_BOTH_OUTPUT() { DDR_USI |= (1 << PORT_USI_SDA) | (1 << PORT_USI_SCL); } | |||
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|
75 | #define USI_SET_BOTH_INPUT() { DDR_USI &= ~((1 << PORT_USI_SDA) | (1 << PORT_USI_SCL)); } | |||
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76 | ||||
|
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|
|
77 | //////////////////////////////////////////////////////////////////////////////////////////////////// | |||
|
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|
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78 | ||||
|
|
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|
|
79 | void USI_I2C_Init(char address) | |||
|
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|
|
80 | { | |||
|
|
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|
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81 | PORT_USI &= ~(1 << PORT_USI_SCL); | |||
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82 | PORT_USI &= ~(1 << PORT_USI_SDA); | |||
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83 | ||||
|
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|
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84 | usi_i2c_slave_address = address; | |||
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85 | ||||
|
|
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|
86 | USI_SET_BOTH_INPUT(); | |||
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|
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|
87 | ||||
|
|
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|
|
88 | USICR = (1 << USISIE) | (0 << USIOIE) | (1 << USIWM1) | (0 << USIWM0) | (1 << USICS1) | (0 << USICS0) | (0 << USICLK) | (0 << USITC); | |||
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|
|
89 | USISR = (1 << USISIF) | (1 << USIOIF) | (1 << USIPF) | (1 << USIDC); | |||
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90 | } | |||
|
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91 | ||||
|
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|
|
92 | ///////////////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
93 | // ISR USI_START_vect - USI Start Condition Detector Interrupt // | |||
|
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|
|
94 | // // | |||
|
|
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|
|
95 | // This interrupt occurs when the USI Start Condition Detector detects a // | |||
|
|
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|
|
96 | // start condition. A start condition marks the beginning of an I2C // | |||
|
|
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|
|
97 | // transmission and occurs when SDA has a high->low transition followed by an // | |||
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|
|
98 | // SCL high->low transition. When a start condition occurs, the I2C slave // | |||
|
|
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|
|
99 | // state is set to check address mode and the counter is set to wait 8 clocks // | |||
|
|
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|
|
100 | // (enough for the address/rw byte to be transmitted) before overflowing and // | |||
|
|
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|
|
101 | // triggering the first state table interrupt. If a stop condition occurs, // | |||
|
|
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|
|
102 | // reset the start condition detector to detect the next start condition. // | |||
|
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|
|
103 | ///////////////////////////////////////////////////////////////////////////////// | |||
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|
|
104 | ||||
|
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|
|
105 | ISR(USI_START_vect) | |||
|
|
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|
|
106 | ||||
|
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|
|
107 | { | |||
|
|
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|
|
108 | ||||
|
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109 | USI_I2C_Slave_State = USI_SLAVE_CHECK_ADDRESS; | |||
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110 | ||||
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111 | ||||
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112 | USI_SET_SDA_INPUT(); | |||
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113 | ||||
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114 | ||||
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115 | ||||
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116 | // wait for SCL to go low to ensure the Start Condition has completed (the | |||
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117 | ||||
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118 | // start detector will hold SCL low ) - if a Stop Condition arises then leave | |||
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119 | ||||
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120 | // the interrupt to prevent waiting forever - don't use USISR to test for Stop | |||
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121 | ||||
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122 | // Condition as in Application Note AVR312 because the Stop Condition Flag is | |||
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123 | ||||
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124 | // going to be set from the last TWI sequence | |||
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125 | ||||
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126 | while((PIN_USI & (1 << PIN_USI_SCL)) && !((PIN_USI & (1 << PIN_USI_SDA)))); | |||
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127 | ||||
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128 | ||||
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129 | ||||
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130 | if(!(PIN_USI & (1 << PIN_USI_SDA))) | |||
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131 | ||||
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132 | { | |||
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133 | ||||
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134 | // a Stop Condition did not occur | |||
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135 | ||||
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136 | USICR = USI_SLAVE_STOP_NOT_OCCUR_USICR; | |||
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137 | ||||
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138 | } | |||
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139 | ||||
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140 | else | |||
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141 | ||||
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142 | { | |||
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|
|
143 | // a Stop Condition did occur | |||
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|
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144 | ||||
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|
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145 | USICR = USI_SLAVE_STOP_DID_OCCUR_USICR; | |||
|
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146 | ||||
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147 | } | |||
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148 | ||||
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149 | ||||
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150 | ||||
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151 | USISR = USI_SLAVE_CLEAR_START_USISR; | |||
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152 | ||||
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153 | } | |||
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154 | ||||
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|
|
155 | ///////////////////////////////////////////////////////////////////////////////// | |||
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|
|
156 | // ISR USI_OVERFLOW_vect - USI Overflow Interrupt // | |||
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157 | // // | |||
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158 | // This interrupt occurs when the USI counter overflows. By setting this // | |||
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|
|
159 | // counter to 8, the USI can be commanded to wait one byte length before // | |||
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160 | // causing another interrupt (and thus state change). To wait for an ACK, // | |||
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161 | // set the counter to 1 (actually -1, or 0x0E) it will wait one clock. // | |||
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|
|
162 | // This is used to set up a state table of I2C transmission states that fits // | |||
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|
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163 | // the I2C protocol for proper transmission. // | |||
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164 | ///////////////////////////////////////////////////////////////////////////////// | |||
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165 | ||||
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166 | ISR(USI_OVERFLOW_vect) | |||
|
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|
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167 | ||||
|
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|
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168 | { | |||
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|
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169 | switch (USI_I2C_Slave_State) | |||
|
|
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170 | ||||
|
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|
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171 | { | |||
|
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|
|
172 | ///////////////////////////////////////////////////////////////////////// | |||
|
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|
|
173 | // Case USI_SLAVE_CHECK_ADDRESS // | |||
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|
174 | // // | |||
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|
|
175 | // The first state after the start condition, this state checks the // | |||
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|
|
176 | // received byte against the stored slave address as well as the // | |||
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|
|
177 | // global transmission address of 0x00. If there is a match, the R/W // | |||
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|
|
178 | // bit is checked to branch either to sending or receiving modes. // | |||
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|
|
179 | // If the address was not for this device, the USI system is // | |||
|
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|
|
180 | // re-initialized for start condition. // | |||
|
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|
|
181 | ///////////////////////////////////////////////////////////////////////// | |||
|
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|
|
182 | ||||
|
|
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|
|
183 | case USI_SLAVE_CHECK_ADDRESS: | |||
|
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|
|
184 | ||||
|
|
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|
|
185 | ||||
|
|
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|
|
186 | if((USIDR == 0) || ((USIDR >> 1) == usi_i2c_slave_address)) | |||
|
|
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|
|
187 | ||||
|
|
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|
|
188 | { | |||
|
|
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|
|
189 | if (USIDR & 0x01) | |||
|
|
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|
|
190 | ||||
|
|
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|
|
191 | { | |||
|
|
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|
|
192 | USI_I2C_Slave_State = USI_SLAVE_SEND_DATA; | |||
|
|
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|
|
193 | ||||
|
|
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|
|
194 | } | |||
|
|
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|
|
195 | ||||
|
|
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|
|
196 | else | |||
|
|
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|
|
197 | ||||
|
|
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|
|
198 | { | |||
|
|
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|
|
199 | USI_Slave_internal_address_set = 0; | |||
|
|
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|
|
200 | USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_WAIT; | |||
|
|
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|
|
201 | ||||
|
|
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|
|
202 | } | |||
|
|
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|
|
203 | ||||
|
|
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|
|
204 | //Set USI to send ACK | |||
|
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|
|
205 | ||||
|
|
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|
|
206 | USIDR = 0; | |||
|
|
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|
|
207 | ||||
|
|
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|
|
208 | USI_SET_SDA_OUTPUT(); | |||
|
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|
|
209 | ||||
|
|
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|
|
210 | USISR = USI_SLAVE_COUNT_ACK_USISR; | |||
|
|
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|
|
211 | } | |||
|
|
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|
|
212 | ||||
|
|
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|
|
213 | else | |||
|
|
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|
|
214 | ||||
|
|
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|
|
215 | { | |||
|
|
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|
|
216 | //Set USI to Start Condition Mode | |||
|
|
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|
|
217 | ||||
|
|
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|
|
218 | USICR = USI_SLAVE_SET_START_COND_USICR; | |||
|
|
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|
|
219 | ||||
|
|
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|
|
220 | USISR = USI_SLAVE_SET_START_COND_USISR; | |||
|
|
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|
|
221 | } | |||
|
|
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|
|
222 | ||||
|
|
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|
|
223 | break; | |||
|
|
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|
|
224 | ||||
|
|
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|
|
225 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
226 | // Case USI_SLAVE_SEND_DATA_ACK_WAIT // | |||
|
|
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|
|
227 | // // | |||
|
|
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|
|
228 | // Wait 1 clock period for the master to ACK or NACK the sent data // | |||
|
|
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|
|
229 | // If master NACK's, it means that master doesn't want any more data. // | |||
|
|
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|
|
230 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
231 | case USI_SLAVE_SEND_DATA_ACK_WAIT: | |||
|
|
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|
|
232 | ||||
|
|
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|
|
233 | //After sending, immediately shut off PORT = 1 to prevent driving | |||
|
|
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|
|
234 | //the line high (I2C should *NEVER* drive high, and could damage | |||
|
|
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|
|
235 | //connected devices if operating at different voltage levels) | |||
|
|
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|
|
236 | PORT_USI &= ~(1 << PORT_USI_SDA); | |||
|
|
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|
|
237 | ||||
|
|
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|
|
238 | ||||
|
|
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|
|
239 | USI_I2C_Slave_State = USI_SLAVE_SEND_DATA_ACK_CHECK; | |||
|
|
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|
|
240 | USI_SET_SDA_INPUT(); | |||
|
|
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|
|
241 | USISR = USI_SLAVE_COUNT_ACK_USISR; | |||
|
|
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|
|
242 | break; | |||
|
|
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|
|
243 | ||||
|
|
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|
|
244 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
245 | // Case USI_SLAVE_SEND_DATA_ACK_CHECK // | |||
|
|
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|
|
246 | // // | |||
|
|
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|
|
247 | // Check USIDR to see if master sent ACK or NACK. If NACK, set up // | |||
|
|
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|
|
248 | // a reset to START conditions, if ACK, fall through into SEND_DATA // | |||
|
|
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|
|
249 | // to continue sending data. // | |||
|
|
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|
|
250 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
251 | case USI_SLAVE_SEND_DATA_ACK_CHECK: | |||
|
|
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|
|
252 | ||||
|
|
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|
|
253 | if(USIDR) | |||
|
|
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|
|
254 | { | |||
|
|
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|
|
255 | //The master sent a NACK, indicating that it will not accept | |||
|
|
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|
|
256 | //more data. Reset into START condition state | |||
|
|
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|
|
257 | USICR = USI_SLAVE_SET_START_COND_USICR; | |||
|
|
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|
|
258 | USISR = USI_SLAVE_SET_START_COND_USISR; | |||
|
|
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|
|
259 | return; | |||
|
|
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|
|
260 | } | |||
|
|
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|
|
261 | //else: fall through into SEND_DATA | |||
|
|
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|
|
262 | ||||
|
|
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|
|
263 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
264 | // Case USI_SLAVE_SEND_DATA // | |||
|
|
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|
|
265 | // // | |||
|
|
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|
|
266 | // Set USIDR to the data to be sent, then set up SDA registers to // | |||
|
|
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|
|
267 | // enable data transmission in the next 8 clocks. Set to wait 8 // | |||
|
|
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|
|
268 | // clocks and proceed to wait for ACK. // | |||
|
|
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|
|
269 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
270 | case USI_SLAVE_SEND_DATA: | |||
|
|
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|
|
271 | ||||
|
|
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|
|
272 | if(USI_Slave_internal_address <= USI_SLAVE_REGISTER_COUNT) | |||
|
|
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|
|
273 | { | |||
|
|
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|
|
274 | USIDR = *(USI_Slave_register_buffer[USI_Slave_internal_address]); | |||
|
|
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|
|
275 | } | |||
|
|
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|
|
276 | else | |||
|
|
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|
|
277 | { | |||
|
|
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|
|
278 | USIDR = 0x00; | |||
|
|
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|
|
279 | } | |||
|
|
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|
|
280 | USI_Slave_internal_address++; | |||
|
|
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|
|
281 | ||||
|
|
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|
|
282 | ||||
|
|
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|
|
283 | USI_I2C_Slave_State = USI_SLAVE_SEND_DATA_ACK_WAIT; | |||
|
|
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|
|
284 | ||||
|
|
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|
|
285 | ||||
|
|
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|
|
286 | //To send data, DDR for SDA must be 1 (Output) and PORT for SDA | |||
|
|
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|
|
287 | //must also be 1 (line drives low on USIDR MSB = 0 or PORT = 0) | |||
|
|
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|
|
288 | ||||
|
|
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|
|
289 | USI_SET_SDA_OUTPUT(); | |||
|
|
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|
|
290 | PORT_USI |= (1 << PORT_USI_SDA); | |||
|
|
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|
|
291 | ||||
|
|
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|
|
292 | USISR = USI_SLAVE_COUNT_BYTE_USISR; | |||
|
|
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|
|
293 | ||||
|
|
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|
|
294 | break; | |||
|
|
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|
|
295 | ||||
|
|
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|
|
296 | ||||
|
|
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|
|
297 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
298 | // Case USI_SLAVE_RECV_DATA_WAIT // | |||
|
|
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|
|
299 | // // | |||
|
|
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|
|
300 | // Prepares to wait 8 clocks to receive a data byte from the master. // | |||
|
|
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|
|
301 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
302 | ||||
|
|
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|
|
303 | case USI_SLAVE_RECV_DATA_WAIT: | |||
|
|
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|
|
304 | ||||
|
|
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|
|
305 | USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_ACK_SEND; | |||
|
|
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|
|
306 | ||||
|
|
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|
|
307 | USI_SET_SDA_INPUT(); | |||
|
|
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|
|
308 | ||||
|
|
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|
|
309 | USISR = USI_SLAVE_COUNT_BYTE_USISR; | |||
|
|
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|
|
310 | ||||
|
|
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|
|
311 | break; | |||
|
|
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|
|
312 | ||||
|
|
No newline at end of file | ||||
|
|
313 | ||||
|
|
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|
|
314 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
315 | // Case USI_SLAVE_RECV_DATA_ACK_SEND // | |||
|
|
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|
|
316 | // // | |||
|
|
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|
|
317 | // After waiting for the master to finish transmission, this reads // | |||
|
|
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|
|
318 | // USIDR into either the i2c buffer or internal address, then sends // | |||
|
|
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|
|
319 | // an acknowledgement to the master. // | |||
|
|
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|
|
320 | ///////////////////////////////////////////////////////////////////////// | |||
|
|
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|
|
321 | ||||
|
|
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|
|
322 | case USI_SLAVE_RECV_DATA_ACK_SEND: | |||
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323 | ||||
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324 | ||||
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325 | ||||
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326 | USI_I2C_Slave_State = USI_SLAVE_RECV_DATA_WAIT; | |||
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327 | ||||
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328 | ||||
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329 | if(USI_Slave_internal_address_set == 0) | |||
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330 | { | |||
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331 | USI_Slave_internal_address = USIDR; | |||
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332 | USI_Slave_internal_address_set = 1; | |||
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333 | } | |||
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334 | else if(USI_Slave_internal_address <= USI_SLAVE_REGISTER_COUNT) | |||
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335 | { | |||
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336 | *(USI_Slave_register_buffer[USI_Slave_internal_address]) = USIDR; | |||
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337 | } | |||
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338 | ||||
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339 | USIDR = 0; | |||
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340 | ||||
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341 | USI_SET_SDA_OUTPUT(); | |||
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342 | ||||
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343 | USISR = USI_SLAVE_COUNT_ACK_USISR; | |||
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344 | ||||
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345 | break; | |||
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346 | ||||
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347 | } | |||
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348 | ||||
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349 | } No newline at end of file | |||
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1 | /*-----------------------------------------------------*\ | |||
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2 | | USI I2C Slave Driver | | |||
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3 | | | | |||
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4 | | This library provides a robust, interrupt-driven I2C | | |||
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5 | | slave implementation built on the ATTiny Universal | | |||
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6 | | Serial Interface (USI) hardware. Slave operation is | | |||
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7 | | implemented as a register bank, where each 'register' | | |||
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8 | | is a pointer to an 8-bit variable in the main code. | | |||
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9 | | This was chosen to make I2C integration transparent | | |||
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10 | | to the mainline code and making I2C reads simple. | | |||
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11 | | This library also works well with the Linux I2C-Tools | | |||
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12 | | utilities i2cdetect, i2cget, i2cset, and i2cdump. | | |||
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13 | | | | |||
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14 | | Adam Honse (GitHub: CalcProgrammer1) - 7/29/2012 | | |||
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15 | | -calcprogrammer1@gmail.com | | |||
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16 | \*-----------------------------------------------------*/ | |||
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17 | #ifndef USI_I2C_SLAVE_H | |||
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18 | #define USI_I2C_SLAVE_H | |||
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19 | ||||
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20 | #include <avr/io.h> | |||
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21 | #include <avr/interrupt.h> | |||
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22 | ||||
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23 | #ifdef __AVR_ATtiny85__ | |||
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24 | #define DDR_USI DDRB | |||
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25 | #define PORT_USI PORTB | |||
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26 | #define PIN_USI PINB | |||
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27 | #define PORT_USI_SDA PB0 | |||
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28 | #define PORT_USI_SCL PB2 | |||
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29 | #define PIN_USI_SDA PINB0 | |||
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30 | #define PIN_USI_SCL PINB2 | |||
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31 | #endif | |||
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32 | ||||
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33 | #define USI_SLAVE_REGISTER_COUNT 8 | |||
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34 | ||||
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35 | //USI I2C Initialize | |||
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36 | // address - If slave, this parameter is the slave address | |||
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37 | void USI_I2C_Init(char address); | |||
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38 | ||||
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39 | #endif No newline at end of file | |||
| @@ -0,0 +1,17 | |||||
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1 | <?xml version="1.0" encoding="UTF-8"?> | |||
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2 | <projectDescription> | |||
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3 | <name>int_cic_simul</name> | |||
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4 | <comment></comment> | |||
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5 | <projects> | |||
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6 | </projects> | |||
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7 | <buildSpec> | |||
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8 | <buildCommand> | |||
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9 | <name>org.python.pydev.PyDevBuilder</name> | |||
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10 | <arguments> | |||
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11 | </arguments> | |||
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12 | </buildCommand> | |||
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13 | </buildSpec> | |||
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14 | <natures> | |||
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15 | <nature>org.python.pydev.pythonNature</nature> | |||
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16 | </natures> | |||
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17 | </projectDescription> No newline at end of file | |||
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1 | <?xml version="1.0" encoding="UTF-8" standalone="no"?> | |||
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2 | <?eclipse-pydev version="1.0"?><pydev_project> | |||
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3 | <pydev_pathproperty name="org.python.pydev.PROJECT_SOURCE_PATH"> | |||
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4 | <path>/${PROJECT_DIR_NAME}</path> | |||
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5 | </pydev_pathproperty> | |||
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6 | <pydev_property name="org.python.pydev.PYTHON_PROJECT_VERSION">python 2.7</pydev_property> | |||
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7 | <pydev_property name="org.python.pydev.PYTHON_PROJECT_INTERPRETER">Default</pydev_property> | |||
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8 | </pydev_project> No newline at end of file | |||
| 1 | NO CONTENT: new file 10644 |
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1 | ''' | |||
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2 | Created on Jan 6, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | from primitives.wire import wire | |||
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7 | from cic.integrator import integrator | |||
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8 | from cic.comb import comb | |||
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9 | from primitives.attenuator import atten | |||
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10 | ||||
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11 | ||||
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12 | class cic_decimator(object): | |||
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13 | ''' | |||
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14 | classdocs | |||
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15 | ''' | |||
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16 | ||||
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17 | def __init__(self, clk,wire_in, wire_out, k=1, r=1, m=1): | |||
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18 | ''' | |||
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19 | Constructor | |||
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20 | ''' | |||
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21 | self.__clk__ = clk; | |||
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22 | self.__dec__ = r; | |||
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23 | self.__stages__ = k; | |||
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24 | self.__dly__ = m; | |||
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25 | ||||
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26 | self.__wire_int_in__ = wire_in; | |||
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27 | self.__wire_1__ = None; | |||
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28 | self.__wire_int_out__ = wire_out; | |||
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29 | ||||
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30 | self.wires=[]; | |||
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31 | ||||
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32 | self.wires.append(wire_in); | |||
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33 | self.__generate_integrator__(); | |||
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34 | self.__generate_comb__(); | |||
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35 | self.wires.append(wire_out); | |||
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36 | ||||
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37 | self.__aux=0; | |||
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38 | ||||
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39 | ||||
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40 | ||||
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41 | def __generate_integrator__(self): | |||
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42 | wire_in = self.__wire_int_in__; | |||
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43 | clk = self.__clk__; | |||
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44 | for i in range(self.__stages__): | |||
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45 | wire_out1 = wire(); | |||
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46 | wire_out2 = wire(); | |||
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47 | integrator(clk,wire_in,wire_out1); | |||
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48 | atten( wire_out1, wire_out2 , atte=float(self.__dec__)); | |||
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49 | wire_in = wire_out2; | |||
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50 | self.__wire_1__ = wire_out2; | |||
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51 | ||||
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52 | ||||
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53 | ||||
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54 | ||||
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55 | def __generate_comb__(self): | |||
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56 | wire_in = self.__wire_1__; | |||
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57 | clk = self.__clk__; | |||
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58 | for i in range(self.__stages__-1): | |||
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59 | wire_out = wire(); | |||
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60 | self.wires.append(wire_out); | |||
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61 | comb(clk,wire_in,wire_out,deep=self.__dec__*self.__dly__); | |||
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62 | wire_in = wire_out; | |||
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63 | comb(clk,wire_in,self.__wire_int_out__,deep=self.__dec__*self.__dly__); | |||
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64 | ||||
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65 | ||||
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66 | if __name__=="__main__": | |||
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67 | from primitives.clock import clock | |||
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68 | from primitives.pin import pin | |||
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69 | from primitives.pout import pout | |||
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70 | ||||
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71 | import matplotlib.pyplot as plt | |||
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72 | import numpy as np | |||
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73 | ||||
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74 | # parametros de decimacion | |||
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75 | dec = 64; # decimacion | |||
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76 | stgs = 3; # numero de pares integrador-comba | |||
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77 | dtsz = 2**16; # cantidad de muestras de data original | |||
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78 | dtszd= dtsz/dec # cantidad de muestras de data decimada | |||
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79 | Fs = 1.0;#1000.0; # frecuencia de muestreo de data original | |||
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|
80 | Fsd = Fs/dec; # frecuencia de muestreo de data decimada | |||
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81 | Ts = 1.0/Fs; # tiempo de muestreo de data original | |||
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82 | Tsd = 1.0/Fsd; # tiempo de muestreo de data decimada | |||
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83 | Tt = Ts*dtsz; # tiempo total | |||
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84 | Fst = Fs/dtsz; | |||
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85 | ||||
|
|
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|
|
86 | # data original (impulso) | |||
|
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|
|
87 | sig = [0 for i in range(dtsz)]; | |||
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88 | sig[0] = 1; | |||
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89 | ||||
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90 | ||||
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91 | tsig = [Ts*i for i in range(dtsz)]; | |||
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|
92 | freq = [Fst*i-Fs/2 for i in range(dtsz)]; | |||
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93 | ||||
|
|
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94 | ||||
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|
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|
|
95 | # descripcion del circuito | |||
|
|
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|
|
96 | clk = clock(); # clock maestro | |||
|
|
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97 | ||||
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|
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|
|
98 | sig0 = wire(); | |||
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|
|
99 | sig1 = wire(); | |||
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|
100 | cic = cic_decimator(clk,sig0,sig1,k=stgs,r=dec,m=1); | |||
|
|
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101 | ||||
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|
102 | p_int = pin(clk,sig0); | |||
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103 | p_int.set_data(sig); | |||
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104 | ||||
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|
|
105 | p3 = pout(clk,sig0); | |||
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|
106 | p4 = pout(clk,sig1); | |||
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107 | ||||
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|
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|
108 | for x in range(dtsz): | |||
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|
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109 | clk.tick(); | |||
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110 | ||||
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111 | ||||
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112 | out = np.array(p4.get_data()); | |||
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113 | ||||
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114 | ||||
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115 | fft_out = np.fft.fft(out); | |||
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116 | fft_out = np.fft.fftshift(fft_out); | |||
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117 | fft_gain = np.abs(fft_out*np.conj(fft_out))+0.000000001; | |||
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118 | fft_db = 10.0*np.log10(fft_gain); | |||
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119 | ||||
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120 | ||||
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121 | fig = plt.figure() | |||
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122 | amp_f = fig.add_subplot(2,1,1) | |||
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123 | amp_f.plot(freq,fft_db, color='blue'); | |||
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124 | amp_f.grid(); | |||
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125 | amp_t = fig.add_subplot(2,1,2) | |||
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126 | amp_t.plot(tsig,out, color='blue'); | |||
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127 | amp_t.plot(tsig,p3.get_data(), color='red'); | |||
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128 | amp_t.grid(); | |||
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129 | plt.show(); | |||
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130 | ||||
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131 | No newline at end of file | |||
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1 | ''' | |||
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2 | Created on Jan 7, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | ||||
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7 | from primitives.delay import delay | |||
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8 | from primitives.adder import adder,NEG | |||
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9 | from primitives.wire import wire | |||
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10 | ||||
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11 | ||||
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12 | class comb(object): | |||
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13 | ''' | |||
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14 | classdocs | |||
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15 | ''' | |||
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16 | ||||
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17 | ||||
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18 | def __init__(self, clk , wire_in, wire_out, deep=1): | |||
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19 | ''' | |||
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20 | Constructor | |||
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21 | ''' | |||
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22 | self.__wire_in = wire_in; | |||
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23 | self.__wire_out = wire_out; | |||
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24 | self.__wire_1 = wire(); | |||
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25 | ||||
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26 | self.__adder = adder(); | |||
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27 | self.__z1 = delay(clk,self.__wire_in,self.__wire_1, deep=deep); | |||
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28 | self.__clk = clk; | |||
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29 | ||||
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30 | self.__adder.connect_to_in(self.__wire_in); | |||
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31 | self.__adder.connect_to_in(self.__wire_1 , NEG); | |||
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32 | self.__adder.connect_to_out(self.__wire_out); | |||
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33 | ||||
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34 | ||||
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35 | ||||
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36 | ||||
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37 | if __name__=="__main__": | |||
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38 | from primitives.clock import clock | |||
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39 | from primitives.pin import pin | |||
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40 | from primitives.pout import pout | |||
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41 | ||||
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42 | ||||
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43 | segnal = [i for i in range(30)]; | |||
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44 | segnal[0]=0.0; | |||
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45 | clk = clock(); | |||
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46 | sig0 = wire(); | |||
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47 | sig1 = wire(); | |||
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48 | ||||
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49 | comb1 = comb(clk,sig0,sig1,deep=2); | |||
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50 | ||||
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51 | p_int = pin(clk,sig0); | |||
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52 | p_int.set_data(segnal); | |||
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53 | pi = pout(clk,sig0); | |||
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54 | po = pout(clk,sig1); | |||
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55 | ||||
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56 | for sig in segnal: | |||
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57 | clk.tick(); | |||
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58 | comb1.print_() | |||
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59 | ||||
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60 | print pi.get_data() | |||
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61 | print po.get_data() No newline at end of file | |||
| @@ -0,0 +1,113 | |||||
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1 | ''' | |||
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2 | Created on Feb 10, 2015 | |||
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3 | ||||
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4 | @author: shinobi | |||
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5 | ''' | |||
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6 | ||||
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7 | from primitives.wire import wire | |||
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8 | from primitives.delay import delay | |||
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9 | from primitives.gain import gain | |||
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10 | from primitives.adder import adder | |||
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11 | ||||
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12 | class Hc(object): | |||
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13 | def __init__(self,clk,M,Kc,wire_in, wire_out): | |||
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14 | ||||
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15 | self.__A = -2**-4; | |||
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16 | self.__B = -(2**4+2); | |||
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17 | self.__Kc = Kc; | |||
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18 | self.__M = M; | |||
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19 | self.__wire_in = wire_in; | |||
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20 | self.__wire_out = wire_out; | |||
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21 | self.__clk = clk; | |||
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22 | ||||
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23 | ||||
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24 | for i in range(Kc-1): | |||
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25 | wire_out = wire(); | |||
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26 | self.__generate_single_module(wire_in, wire_out); | |||
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27 | wire_in = wire_out; | |||
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28 | self.__generate_single_module(wire_in, self.__wire_out); | |||
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29 | ||||
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30 | ||||
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31 | def __generate_single_module(self,wire_in,wire_out): | |||
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32 | clk = self.__clk; | |||
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33 | M = self.__M; | |||
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34 | A = self.__A; B = self.__B; | |||
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35 | w1 = wire(); | |||
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36 | w2 = wire(); | |||
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37 | w3 = wire(); | |||
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38 | w4 = wire(); | |||
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39 | delay(clk, wire_in, w1, deep=M); | |||
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40 | delay(clk, w1, w2, deep=M); | |||
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41 | gain(w1, w3, gain=B); | |||
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42 | ad = adder(); | |||
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43 | ad.connect_to_in(wire_in); | |||
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44 | ad.connect_to_in(w3); | |||
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45 | ad.connect_to_in(w2); | |||
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46 | ad.connect_to_out(w4); | |||
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47 | gain(w4, wire_out, gain=A); | |||
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48 | ||||
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49 | if __name__=="__main__": | |||
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50 | from primitives.clock import clock | |||
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51 | from primitives.pin import pin | |||
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52 | from primitives.pout import pout | |||
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53 | import numpy as np | |||
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54 | ||||
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55 | import matplotlib.pyplot as plt | |||
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56 | ||||
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57 | # parametros de decimacion | |||
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58 | M1 = 2 | |||
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59 | M2 = 5; | |||
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60 | M = M1*M2; | |||
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61 | Kc = 4; | |||
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62 | ||||
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63 | dtsz = 2**16; # cantidad de muestras de data original | |||
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64 | Fs = 1000.0; # frecuencia de muestreo de data original | |||
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65 | Ts = 1.0/Fs; # tiempo de muestreo de data original | |||
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66 | Tt = Ts*dtsz; # tiempo total | |||
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67 | Fst = Fs/dtsz; | |||
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68 | ||||
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69 | # data original (impulso) | |||
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70 | sig = [0 for i in range(dtsz)]; | |||
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71 | sig[0] = 1; | |||
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72 | ||||
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73 | tsig = [Ts*i for i in range(dtsz)]; | |||
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74 | freq = [Fst*i-Fs/2 for i in range(dtsz)]; | |||
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75 | ||||
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76 | # descripcion del circuito | |||
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77 | clk = clock(); # clock maestro | |||
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78 | ||||
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79 | sig0 = wire(); | |||
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80 | sig1 = wire(); | |||
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81 | ||||
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82 | h = Hc(clk,M,Kc,sig0, sig1); | |||
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83 | ||||
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84 | p_int = pin(clk,sig0); | |||
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85 | p_int.set_data(sig); | |||
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86 | ||||
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87 | p3 = pout(clk,sig0); | |||
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88 | p4 = pout(clk,sig1); | |||
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89 | ||||
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90 | for x in range(dtsz): | |||
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91 | clk.tick(); | |||
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92 | ||||
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93 | ||||
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94 | out = np.array(p4.get_data()); | |||
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95 | ||||
|
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96 | ||||
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97 | fft_out = np.fft.fft(out); | |||
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98 | fft_out = np.fft.fftshift(fft_out); | |||
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99 | fft_gain = np.abs(fft_out*np.conj(fft_out))+0.000000001; | |||
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100 | fft_db = 10.0*np.log10(fft_gain); | |||
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101 | ||||
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102 | ||||
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103 | fig = plt.figure() | |||
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104 | amp_f = fig.add_subplot(2,1,1) | |||
|
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105 | amp_f.plot(freq,fft_db, color='blue'); | |||
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106 | amp_f.grid(); | |||
|
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|
107 | amp_t = fig.add_subplot(2,1,2) | |||
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108 | amp_t.plot(tsig,out, color='blue'); | |||
|
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109 | amp_t.plot(tsig,p3.get_data(), color='red'); | |||
|
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110 | amp_t.grid(); | |||
|
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111 | plt.show(); | |||
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|
112 | ||||
|
|
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|
|
113 | No newline at end of file | |||
| @@ -0,0 +1,126 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Jan 7, 2015 | |||
|
|
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|
|
3 | ||||
|
|
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|
|
4 | @author: aras | |||
|
|
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|
|
5 | ''' | |||
|
|
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|
|
6 | from primitives.adder import adder | |||
|
|
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|
|
7 | from primitives.delay import delay | |||
|
|
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|
|
8 | from primitives.wire import wire | |||
|
|
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|
|
9 | from primitives.gain import gain | |||
|
|
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10 | ||||
|
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|
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11 | ||||
|
|
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12 | ||||
|
|
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|
13 | class fir_decimator(object): | |||
|
|
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|
|
14 | ''' | |||
|
|
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|
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15 | classdocs | |||
|
|
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|
|
16 | ''' | |||
|
|
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|
|
17 | ||||
|
|
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|
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18 | ||||
|
|
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|
|
19 | def __init__(self, clk,wire_in, wire_out, dec = 1 ): | |||
|
|
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|
|
20 | ''' | |||
|
|
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21 | Constructor | |||
|
|
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|
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22 | ''' | |||
|
|
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|
|
23 | self.__clk = clk; | |||
|
|
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|
|
24 | ||||
|
|
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|
|
25 | self.__win = wire_in; | |||
|
|
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|
|
26 | self.__wout = wire_out; | |||
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27 | self.__w1 = wire(); | |||
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28 | self.__w2 = wire(); | |||
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29 | self.__w3 = wire(); | |||
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30 | self.__w4 = wire(); | |||
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31 | self.__w5 = wire(); | |||
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32 | self.__w6 = wire(); | |||
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33 | ||||
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34 | ||||
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35 | self.__z1 = delay(clk,deep=3); | |||
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36 | self.__z2 = delay(clk,deep=dec); | |||
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37 | self.__z3 = delay(clk,deep=dec); | |||
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38 | self.__g1 = gain(gain=1); | |||
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39 | self.__g2 = gain(gain=-1.3) | |||
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40 | self.__g3 = gain(gain=-1.7) | |||
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41 | self.__adder = adder(); | |||
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42 | ||||
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43 | self.__z1.connect_to_in(self.__win); | |||
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44 | self.__z1.connect_to_out(self.__w2); | |||
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45 | self.__g1.connect_to_in(self.__w2); | |||
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46 | self.__g1.connect_to_out(self.__w3); | |||
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47 | ||||
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48 | self.__z2.connect_to_in(self.__win); | |||
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49 | self.__z2.connect_to_out(self.__w1); | |||
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50 | self.__g2.connect_to_in(self.__w1); | |||
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51 | self.__g2.connect_to_out(self.__w6); | |||
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52 | ||||
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53 | self.__z3.connect_to_in(self.__w3); | |||
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54 | self.__z3.connect_to_out(self.__w4); | |||
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55 | self.__g3.connect_to_in(self.__w4); | |||
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56 | self.__g3.connect_to_out(self.__w5); | |||
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57 | ||||
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58 | ||||
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59 | self.__adder.connect_to_in(self.__w5); | |||
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60 | self.__adder.connect_to_in(self.__w6); | |||
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61 | self.__adder.connect_to_out(self.__wout); | |||
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62 | ||||
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63 | def print_(self): | |||
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64 | print "in",self.__win.read(); | |||
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65 | print "1", self.__w1.read(); | |||
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66 | print "2",self.__w2.read(); | |||
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67 | print "3", self.__w3.read(); | |||
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68 | print "out",self.__wout.read(); | |||
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69 | ||||
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70 | ||||
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71 | if __name__=="__main__": | |||
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72 | from primitives.clock import clock | |||
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73 | from primitives.pin import pin | |||
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74 | from primitives.pout import pout | |||
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75 | ||||
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76 | import matplotlib.pyplot as plt | |||
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77 | import numpy as np | |||
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78 | ||||
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79 | # parametros de decimacion | |||
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80 | dec = 20; # decimacion | |||
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81 | dtsz = 2**16; # cantidad de muestras de data original | |||
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82 | Fs = 1.0#300.0/dec; # frecuencia de muestreo de data original | |||
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83 | Ts = 1.0/Fs; # tiempo de muestreo de data original | |||
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84 | Tt = Ts*dtsz; # tiempo total | |||
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85 | Fst = 2*Fs/dtsz; | |||
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86 | ||||
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87 | sig = [0.0 for i in range(dtsz)]; | |||
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88 | sig[1] = 1.0 | |||
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89 | tsig = [Ts*i for i in range(dtsz)]; | |||
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|
90 | freq = [Fst*i - Fs for i in range(dtsz)]; | |||
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91 | ||||
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92 | # descripcion del circuito | |||
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93 | clk = clock(); # clock maestro | |||
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94 | ||||
|
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|
95 | sig0 = wire(); | |||
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|
96 | sig1 = wire(); | |||
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|
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|
|
97 | fir = fir_decimator(clk, sig0, sig1, dec=dec); | |||
|
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|
98 | ||||
|
|
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|
|
99 | p_int = pin(clk,sig0); | |||
|
|
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|
100 | p_int.set_data(sig); | |||
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|
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101 | ||||
|
|
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|
|
102 | p3 = pout(clk,sig0); | |||
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|
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|
|
103 | p4 = pout(clk,sig1); | |||
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104 | ||||
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105 | ||||
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106 | for x in range(dtsz): | |||
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|
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|
107 | clk.tick(); | |||
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|
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108 | ||||
|
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|
109 | out = np.array(p4.get_data()); | |||
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110 | ||||
|
|
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111 | ||||
|
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|
|
112 | fft_out = np.fft.fft(out); | |||
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|
|
113 | fft_out = np.fft.fftshift(fft_out); | |||
|
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|
|
114 | fft_gain = np.abs(fft_out*np.conj(fft_out))+0.000000001; | |||
|
|
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|
|
115 | fft_db = 10.0*np.log10(fft_gain); | |||
|
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|
116 | ||||
|
|
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|
|
117 | fig = plt.figure() | |||
|
|
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|
|
118 | amp_f = fig.add_subplot(2,1,1) | |||
|
|
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|
119 | amp_f.plot(freq,fft_db, color='blue'); | |||
|
|
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|
|
120 | amp_f.grid(); | |||
|
|
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|
|
121 | amp_t = fig.add_subplot(2,1,2) | |||
|
|
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|
|
122 | amp_t.plot(tsig,out, color='blue'); | |||
|
|
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|
|
123 | amp_t.plot(tsig,p3.get_data(), color='red'); | |||
|
|
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|
|
124 | amp_t.grid(); | |||
|
|
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|
|
125 | plt.show(); | |||
|
|
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|
|
126 | No newline at end of file | |||
| @@ -0,0 +1,61 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Jan 7, 2015 | |||
|
|
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|
|
3 | ||||
|
|
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|
|
4 | @author: aras | |||
|
|
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|
|
5 | ''' | |||
|
|
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|
|
6 | ||||
|
|
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|
|
7 | from primitives.delay import delay | |||
|
|
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|
|
8 | from primitives.adder import adder | |||
|
|
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|
|
9 | from primitives.wire import wire | |||
|
|
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|
|
10 | ||||
|
|
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|
|
11 | ||||
|
|
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|
|
12 | class integrator(object): | |||
|
|
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|
|
13 | ''' | |||
|
|
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|
|
14 | classdocs | |||
|
|
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|
|
15 | ''' | |||
|
|
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|
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16 | ||||
|
|
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|
|
17 | ||||
|
|
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|
|
18 | def __init__(self, clk , wire_in, wire_out, deep=1): | |||
|
|
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|
|
19 | ''' | |||
|
|
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|
|
20 | Constructor | |||
|
|
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|
|
21 | ''' | |||
|
|
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|
|
22 | self.__wire_in = wire_in; | |||
|
|
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|
|
23 | self.__wire_out = wire_out; | |||
|
|
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|
|
24 | self.__wire_1 = wire(); | |||
|
|
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|
|
25 | ||||
|
|
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|
|
26 | ||||
|
|
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|
|
27 | self.__adder = adder(); | |||
|
|
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|
|
28 | self.__z1 = delay(clk,self.__wire_out,self.__wire_1, deep=deep); | |||
|
|
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|
|
29 | self.__clk = clk; | |||
|
|
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|
|
30 | ||||
|
|
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|
|
31 | ||||
|
|
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|
|
32 | self.__adder.connect_to_in(self.__wire_in); | |||
|
|
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|
|
33 | self.__adder.connect_to_in(self.__wire_1); | |||
|
|
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|
|
34 | self.__adder.connect_to_out(self.__wire_out); | |||
|
|
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|
|
35 | ||||
|
|
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|
|
36 | ||||
|
|
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|
|
37 | ||||
|
|
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|
|
38 | if __name__=="__main__": | |||
|
|
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|
|
39 | from primitives.clock import clock | |||
|
|
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|
|
40 | from primitives.pin import pin | |||
|
|
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|
|
41 | from primitives.pout import pout | |||
|
|
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|
|
42 | ||||
|
|
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|
|
43 | segnal = [ 1 for i in range(1,11)]; | |||
|
|
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|
|
44 | segnal += [ -1 for i in range(1,11)]; | |||
|
|
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|
|
45 | segnal += [ 0 for i in range(1,11)]; | |||
|
|
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|
|
46 | ||||
|
|
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|
|
47 | clk = clock(); | |||
|
|
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|
|
48 | sig0 = wire(); | |||
|
|
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|
|
49 | sig1 = wire(); | |||
|
|
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|
|
50 | inte1 = integrator(clk,sig0,sig1); | |||
|
|
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|
|
51 | ||||
|
|
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|
|
52 | p_int = pin(clk,sig0); | |||
|
|
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|
|
53 | p_int.set_data(segnal); | |||
|
|
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|
|
54 | pi = pout(clk,sig0); | |||
|
|
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|
|
55 | po = pout(clk,sig1); | |||
|
|
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|
|
56 | ||||
|
|
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|
|
57 | for sig in segnal: | |||
|
|
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|
|
58 | clk.tick(); | |||
|
|
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|
|
59 | ||||
|
|
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|
|
60 | print pi.get_data() | |||
|
|
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|
|
61 | print po.get_data() No newline at end of file | |||
| @@ -0,0 +1,244 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Feb 10, 2015 | |||
|
|
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|
|
3 | ||||
|
|
No newline at end of file | ||||
|
|
4 | @author: shinobi | |||
|
|
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|
|
5 | ''' | |||
|
|
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|
|
6 | ||||
|
|
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|
|
7 | from primitives.wire import wire | |||
|
|
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|
|
8 | from cic.comb import comb | |||
|
|
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|
|
9 | from cic.integrator import integrator | |||
|
|
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|
|
10 | from cic.rotated_zero_filter import Hr | |||
|
|
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|
|
11 | from cic.droop_correction_filter import Hc | |||
|
|
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|
|
12 | from numpy import math | |||
|
|
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|
|
13 | from primitives.attenuator import atten | |||
|
|
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|
|
14 | from primitives.clock import clock | |||
|
|
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|
|
15 | from primitives.pin import pin | |||
|
|
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|
|
16 | from primitives.pout import pout | |||
|
|
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|
|
17 | ||||
|
|
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|
|
18 | ||||
|
|
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|
|
19 | import numpy as np | |||
|
|
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|
|
20 | import matplotlib.pyplot as plt | |||
|
|
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|
|
21 | ||||
|
|
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|
|
22 | class Hx(object): | |||
|
|
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|
|
23 | def __init__(self, clk,wire_in, wire_out,M=1, k=1, cm=1, im=1): | |||
|
|
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|
|
24 | ''' | |||
|
|
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|
|
25 | Constructor | |||
|
|
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|
|
26 | ''' | |||
|
|
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|
|
27 | self.__clk = clk; | |||
|
|
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|
|
28 | self.__stages = k; | |||
|
|
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|
|
29 | self.__cdly = cm; | |||
|
|
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|
|
30 | self.__idly = im; | |||
|
|
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|
|
31 | self.__M = M; | |||
|
|
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|
|
32 | ||||
|
|
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|
|
33 | self.__wire_int_in = wire_in; | |||
|
|
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|
|
34 | self.__wire_1 = None; | |||
|
|
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|
|
35 | self.__wire_int_out = wire_out; | |||
|
|
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|
|
36 | ||||
|
|
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|
|
37 | ||||
|
|
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|
|
38 | self.__generate_integrator(); | |||
|
|
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|
|
39 | self.__generate_comb(); | |||
|
|
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|
|
40 | ||||
|
|
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|
|
41 | self.__aux=0; | |||
|
|
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|
|
42 | ||||
|
|
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|
|
43 | def __generate_integrator(self): | |||
|
|
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|
|
44 | wire_in = self.__wire_int_in; | |||
|
|
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|
|
45 | clk = self.__clk; | |||
|
|
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|
|
46 | for i in range(self.__stages): | |||
|
|
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|
|
47 | wire_out1 = wire(); | |||
|
|
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|
|
48 | wire_out2 = wire(); | |||
|
|
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|
|
49 | atten(wire_in, wire_out1, atte=float(self.__M)); | |||
|
|
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|
|
50 | integrator(clk,wire_out1,wire_out2,deep=self.__idly); | |||
|
|
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|
|
51 | wire_in = wire_out2; | |||
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52 | self.__wire_1 = wire_out2; | |||
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53 | ||||
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54 | ||||
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55 | def __generate_comb(self): | |||
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56 | wire_in = self.__wire_1; | |||
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57 | clk = self.__clk; | |||
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58 | for i in range(self.__stages-1): | |||
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59 | wire_out = wire(); | |||
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60 | comb(clk,wire_in,wire_out,deep=self.__cdly); | |||
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61 | wire_in = wire_out; | |||
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62 | comb(clk,wire_in,self.__wire_int_out,deep=self.__cdly); | |||
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63 | ||||
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64 | ||||
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65 | ||||
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66 | ||||
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67 | class cic_designer(object): | |||
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68 | ||||
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69 | def __init__(self,M,K,b0, clk,wire_in, wire_out): | |||
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70 | self.__M1 = 1; | |||
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71 | self.__M2 = 1; | |||
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72 | self.__M = M; | |||
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73 | self.__K1 = K; | |||
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74 | self.__K2 = K; | |||
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75 | self.__Kc = K+1; | |||
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76 | self.__calc_dowsmpls(); | |||
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77 | self.__clk = clk; | |||
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78 | self.__win = wire_in; | |||
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79 | self.__wout= wire_out; | |||
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80 | ||||
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81 | self.w1 = wire(); | |||
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82 | self.w2 = wire(); | |||
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83 | self.w3 = wire(); | |||
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84 | # H1 | |||
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85 | Hx(clk,wire_in, self.w1, k=self.__K1, M=self.__M1, cm=self.__M1, im=1); | |||
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86 | # H2 | |||
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87 | Hx(clk,self.w1,self.w2, k=self.__K2, M=self.__M2, cm=self.__M, im=self.__M1); | |||
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88 | # Hr | |||
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89 | Hr(clk,self.__M1,self.__M2,b0, self.w2, self.w3); | |||
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90 | # Hc | |||
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91 | Hc(clk,M,self.__Kc, self.w3, wire_out); | |||
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92 | ||||
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93 | ||||
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94 | ||||
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95 | def simulate(self,sig): | |||
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96 | # descripcion del circuito | |||
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97 | clk = self.__clk; | |||
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98 | p_int = pin(clk,self.__win); | |||
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99 | p_int.set_data(sig); | |||
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100 | self.dtsz = len(sig); | |||
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101 | ||||
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102 | self.pin = pout(clk,self.__win); | |||
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103 | self.p1 = pout(clk,self.w1); | |||
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104 | self.p2 = pout(clk,self.w2); | |||
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105 | self.p3 = pout(clk,self.w3); | |||
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106 | self.pout = pout(clk,self.__wout); | |||
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107 | ||||
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108 | for x in range(self.dtsz): | |||
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109 | clk.tick(); | |||
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110 | ||||
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111 | ||||
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112 | def plot_frequency_response(self,Fs): | |||
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113 | # parametros de decimacion | |||
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114 | ||||
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115 | dtsz = self.dtsz; | |||
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116 | Fst = Fs/dtsz; | |||
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117 | Ts = 1.0/Fs; | |||
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118 | tsig = [Ts*i for i in range(dtsz)]; | |||
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119 | # freq = [Fst*i-Fs/2 for i in range(dtsz)]; | |||
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120 | ||||
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121 | t_in = np.array(self.pin.get_data()); | |||
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122 | # t_s1 = np.array(self.p1.get_data()); | |||
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123 | # t_s2 = np.array(self.p2.get_data()); | |||
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124 | # t_s3 = np.array(self.p3.get_data()); | |||
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125 | # t_out = np.array(self.pout.get_data()); | |||
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126 | ||||
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127 | # f_in = self.__calc_fft(t_in); | |||
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128 | # f_s1 = self.__calc_fft(t_s1); | |||
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129 | # f_s2 = self.__calc_fft(t_s2); | |||
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130 | # f_s3 = self.__calc_fft(t_s3); | |||
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131 | # f_out = self.__calc_fft(t_out); | |||
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132 | ||||
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133 | # plt.figure(); | |||
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134 | # plt.title("Seismic Signal"); | |||
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135 | # plt.plot(freq,f_in); | |||
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136 | # plt.grid(); | |||
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137 | ||||
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138 | plt.figure(); | |||
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139 | # plt.subplot(231); | |||
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140 | # plt.title("Comparacion"); | |||
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141 | # i0 = len(freq)/2; | |||
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142 | # plt.plot(freq[i0:7*i0/5],f_s1[i0:7*i0/5],'r--',freq[i0:7*i0/5],f_s2[i0:7*i0/5],'g--', | |||
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143 | # freq[i0:7*i0/5],f_s3[i0:7*i0/5],'b--',freq[i0:7*i0/5],f_out[i0:7*i0/5],'r'); | |||
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144 | # plt.ylim(-300, 25); | |||
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145 | # plt.grid(); | |||
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146 | ||||
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147 | # plt.subplot(232); | |||
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148 | # plt.title("H1"); | |||
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149 | # plt.plot(freq,f_s1); | |||
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150 | # plt.grid(); | |||
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151 | # | |||
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152 | # plt.subplot(233); | |||
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153 | # plt.title("H1 + H2 (CIC)"); | |||
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154 | # plt.plot(freq,f_s2); | |||
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155 | # plt.grid(); | |||
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156 | # | |||
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157 | # plt.subplot(234); | |||
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158 | # plt.title("H1 + H2 + Hr (CIC + Rotacion de Zero)"); | |||
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159 | # plt.plot(freq,f_s3); | |||
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160 | # plt.grid(); | |||
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161 | # | |||
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162 | # plt.subplot(235); | |||
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163 | # plt.title("CIC + Rotacion de Zero + Compensador"); | |||
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164 | # plt.plot(freq,f_out); | |||
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165 | # plt.grid(); | |||
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166 | # | |||
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167 | # plt.subplot(236); | |||
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168 | plt.title("Respuesta al Impulso del Filtro"); | |||
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169 | #i1 = len(tsig)/8; | |||
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170 | plt.plot(tsig,t_out,'blue'); | |||
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171 | plt.plot(tsig,t_in,'red'); | |||
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172 | plt.grid(); | |||
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173 | plt.show(); | |||
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174 | ||||
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175 | ||||
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176 | ||||
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177 | ||||
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178 | def __calc_fft(self,sig): | |||
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179 | fft_out = np.fft.fft(sig); | |||
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180 | fft_out = np.fft.fftshift(fft_out); | |||
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181 | fft_gain = np.abs(fft_out*np.conj(fft_out)); | |||
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182 | fft_db = 10.0*np.log10(fft_gain); | |||
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183 | return fft_db; | |||
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184 | ||||
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185 | ||||
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186 | ||||
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187 | def __calc_dowsmpls(self): | |||
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188 | sqrm_ = int(math.floor(math.sqrt(self.__M))); | |||
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189 | if self.__M <= 64: | |||
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190 | # if M <= 64 , M2 >= M1; whenever possible M1 = M2 | |||
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191 | rang = range(1,sqrm_+1); | |||
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192 | rang.reverse(); | |||
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193 | for m1_ in rang: | |||
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194 | if ((self.__M % m1_) == 0) and (m1_ <> 1): | |||
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195 | self.__M2 = int(self.__M/m1_); | |||
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196 | self.__M1 = int(m1_); | |||
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197 | print self.__M, self.__M1,self.__M2 | |||
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198 | return; | |||
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199 | else: | |||
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200 | # if M > 64 , M2 < M1 | |||
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201 | rang = range(1,sqrm_); | |||
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202 | rang.reverse(); | |||
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203 | for m2_ in rang: | |||
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204 | if ((self.__M % m2_) == 0) and (m2_ <> 1): | |||
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205 | self.__M1 = int(self.__M/m2_); | |||
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206 | self.__M2 = int(m2_); | |||
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207 | print self.__M, self.__M1,self.__M2 | |||
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208 | return; | |||
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209 | ||||
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210 | print "Elegir otro valor para M", self.__M, self.__M1,self.__M2; | |||
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211 | self.__M1 = -1; | |||
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212 | self.__M2 = -1; | |||
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213 | ||||
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214 | ||||
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215 | ||||
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216 | def test_downsamples(self): | |||
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217 | for i in range(1,101): | |||
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218 | self.__M=i; | |||
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219 | self.__calc_dowsmpls(); | |||
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220 | ||||
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221 | ||||
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222 | ||||
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223 | if __name__=="__main__": | |||
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224 | M = 2; | |||
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225 | K = 3; | |||
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226 | ro= 100; | |||
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227 | ||||
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228 | dtsz = 2**16; # cantidad de muestras de data original | |||
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229 | Fs = 1.0; # frecuencia de muestreo de data original | |||
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230 | ||||
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231 | # data original (impulso) | |||
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232 | #sig = np.random.normal(0,1,dtsz); | |||
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233 | sig = [0 for i in range(dtsz)]; | |||
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234 | sig[0] =1; | |||
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235 | ||||
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236 | win = wire(); | |||
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237 | wout = wire(); | |||
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238 | clk = clock(); | |||
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239 | cic = cic_designer(M,K,ro, clk,win, wout); | |||
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240 | ||||
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241 | cic.simulate(sig); | |||
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242 | cic.plot_frequency_response(Fs); | |||
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243 | ||||
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244 | No newline at end of file | |||
| @@ -0,0 +1,136 | |||||
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1 | ''' | |||
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2 | Created on Feb 10, 2015 | |||
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3 | ||||
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4 | @author: shinobi | |||
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5 | ''' | |||
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6 | ||||
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7 | from primitives.wire import wire | |||
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8 | from primitives.gain import gain | |||
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9 | from primitives.delay import delay | |||
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10 | from primitives.adder import adder | |||
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11 | import numpy as np | |||
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12 | from primitives.attenuator import atten | |||
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13 | ||||
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14 | class Hr(object): | |||
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15 | def __init__(self,clk,M1,M2,ro,wire_in, wire_out): | |||
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16 | self.__clk = clk; | |||
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17 | self.__M1 = M1; | |||
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18 | self.__M2 = M2; | |||
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19 | self.__ro = ro; # oversampling factor | |||
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20 | self.__C = []; | |||
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21 | self.__calc_zero_rotated_coefs(); | |||
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22 | self.__wiew_in = wire_in; | |||
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23 | self.__wire_out = wire_out; | |||
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24 | self.__generate_filter(); | |||
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25 | self.__atte = 1; | |||
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26 | ||||
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27 | ||||
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28 | def __generate_filter(self): | |||
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29 | wire_1 = self.__wiew_in; | |||
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30 | clk = self.__clk; | |||
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31 | M = self.__M1*self.__M2; | |||
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32 | M2 = self.__M2; | |||
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33 | M1 = self.__M1; | |||
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34 | C = self.__C; | |||
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35 | wadd = []; | |||
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36 | ||||
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37 | for i in range(self.__M2-1): | |||
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38 | w2 = wire(); | |||
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39 | w3 = wire(); | |||
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40 | w4 = wire(); | |||
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41 | w5 = wire(); | |||
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42 | wadd.append(w5); | |||
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43 | wout = wire(); | |||
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44 | delay(clk, wire_1, w2,deep=M); | |||
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45 | gain(wire_1, w3, C[i]); | |||
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46 | gain(w2, w4, C[M2-2-i]); | |||
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47 | ad = adder(); | |||
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48 | ad.connect_to_in(w3);ad.connect_to_in(w4); | |||
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49 | ad.connect_to_out(w5); | |||
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50 | delay(clk, wire_1, wout,deep=M1); | |||
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51 | wire_1 = wout; | |||
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52 | ||||
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53 | w5 = wire(); | |||
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54 | w6 = wire(); | |||
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55 | wadd.append(w5); | |||
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56 | gain(wire_1,w5 , C[i]); | |||
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57 | ||||
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58 | ad = adder(); | |||
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59 | for w in wadd: | |||
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60 | ad.connect_to_in(w); | |||
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61 | ad.connect_to_out(w6); | |||
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62 | self.__atte = atten(w6,self.__wire_out, atte=M2**2); | |||
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63 | ||||
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64 | ||||
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65 | def __calc_zero_rotated_coefs(self): | |||
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66 | betha = np.pi*self.__M1/(2.0*self.__ro); | |||
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67 | c = [1.0 , 2*np.cos(betha)]; | |||
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68 | for i in range(2, self.__M2): | |||
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69 | c.append(2*np.cos(betha)*c[i-1]-c[i-2]); | |||
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70 | for i in range(self.__M2): | |||
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71 | self.__C.append(np.round(c[i]/2**-5)*2**-5); | |||
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72 | ||||
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73 | if __name__=="__main__": | |||
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74 | from primitives.clock import clock | |||
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75 | from primitives.pin import pin | |||
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76 | from primitives.pout import pout | |||
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77 | ||||
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78 | import matplotlib.pyplot as plt | |||
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79 | ||||
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80 | # parametros de decimacion | |||
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81 | M1 = 6 | |||
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82 | M2 = 10; | |||
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83 | ro = 70;#18.85; | |||
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84 | ||||
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85 | dtsz = 2**16; # cantidad de muestras de data original | |||
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86 | Fs = 1000.0; # frecuencia de muestreo de data original | |||
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87 | Ts = 1.0/Fs; # tiempo de muestreo de data original | |||
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88 | Tt = Ts*dtsz; # tiempo total | |||
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89 | Fst = Fs/dtsz; | |||
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90 | ||||
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91 | # data original (impulso) | |||
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92 | sig = [0 for i in range(dtsz)]; | |||
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93 | sig[0] = 1; | |||
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94 | ||||
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95 | tsig = [Ts*i for i in range(dtsz)]; | |||
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96 | freq = [Fst*i-Fs/2 for i in range(dtsz)]; | |||
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97 | ||||
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98 | # descripcion del circuito | |||
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99 | clk = clock(); # clock maestro | |||
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100 | ||||
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101 | sig0 = wire(); | |||
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102 | sig1 = wire(); | |||
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103 | ||||
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104 | h = Hr(clk,M1,M2,ro,sig0, sig1); | |||
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105 | ||||
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106 | p_int = pin(clk,sig0); | |||
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107 | p_int.set_data(sig); | |||
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108 | ||||
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109 | p3 = pout(clk,sig0); | |||
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110 | p4 = pout(clk,sig1); | |||
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111 | ||||
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112 | for x in range(dtsz): | |||
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113 | clk.tick(); | |||
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114 | #cic.print_() | |||
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115 | ||||
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116 | ||||
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117 | out = np.array(p4.get_data()); | |||
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118 | ||||
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119 | ||||
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120 | fft_out = np.fft.fft(out); | |||
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121 | fft_out = np.fft.fftshift(fft_out); | |||
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122 | fft_gain = np.abs(fft_out*np.conj(fft_out))+0.000000001; | |||
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123 | fft_db = 10.0*np.log10(fft_gain); | |||
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124 | ||||
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125 | ||||
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126 | fig = plt.figure() | |||
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127 | amp_f = fig.add_subplot(2,1,1) | |||
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128 | amp_f.plot(freq,fft_db, color='blue'); | |||
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129 | amp_f.grid(); | |||
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130 | amp_t = fig.add_subplot(2,1,2) | |||
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131 | amp_t.plot(tsig,out, color='blue'); | |||
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132 | amp_t.plot(tsig,p3.get_data(), color='red'); | |||
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133 | amp_t.grid(); | |||
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134 | plt.show(); | |||
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135 | ||||
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136 | No newline at end of file | |||
| 1 | NO CONTENT: new file 10644 |
|
NO CONTENT: new file 10644 |
| @@ -0,0 +1,85 | |||||
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1 | ''' | |||
|
|
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2 | Created on Jan 6, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | ||||
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7 | from decimal import * | |||
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8 | ||||
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9 | POS = 1; | |||
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10 | NEG = -1; | |||
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11 | ||||
|
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12 | class adder(object): | |||
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13 | ''' | |||
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14 | classdocs | |||
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15 | ''' | |||
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16 | ||||
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17 | def __init__(self): | |||
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18 | ''' | |||
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19 | Constructor | |||
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|
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20 | ''' | |||
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21 | self.__wires_in__ = []; | |||
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22 | self.__wire_out__ = None; | |||
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23 | ||||
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|
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24 | self.__wires_in_signs__ = []; | |||
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25 | ||||
|
|
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26 | ||||
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|
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27 | def __update__(self): | |||
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|
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|
|
28 | acum = 0; | |||
|
|
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|
|
29 | inputs = zip(self.__wires_in__,self.__wires_in_signs__); | |||
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|
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30 | for adding,sign in inputs: | |||
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|
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|
|
31 | acum += adding.read()*sign; | |||
|
|
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|
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32 | if type(self.__wire_out__)<> type(None): | |||
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|
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|
|
33 | self.__wire_out__.drive(acum); | |||
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34 | ||||
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35 | ||||
|
|
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|
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36 | ||||
|
|
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|
|
37 | def connect_to_in(self,wire_in,sign=POS): | |||
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|
|
38 | self.__wires_in__.append(wire_in); | |||
|
|
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|
|
39 | self.__wires_in_signs__.append(sign); | |||
|
|
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|
|
40 | wire_in.async_element(self); | |||
|
|
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|
|
41 | self.__update__(); | |||
|
|
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|
|
42 | ||||
|
|
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|
|
43 | def connect_to_out(self,wire_out): | |||
|
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|
|
44 | self.__wire_out__ = wire_out; | |||
|
|
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|
|
45 | self.__wire_out__.drive(0); | |||
|
|
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|
|
46 | self.__update__(); | |||
|
|
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|
|
47 | ||||
|
|
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|
|
48 | if __name__=="__main__": | |||
|
|
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|
|
49 | from primitives.clock import clock | |||
|
|
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|
|
50 | from primitives.pin import pin | |||
|
|
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|
|
51 | from primitives.wire import wire | |||
|
|
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|
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52 | ||||
|
|
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|
|
53 | clk = clock(); | |||
|
|
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|
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54 | ||||
|
|
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|
|
55 | s = adder(); | |||
|
|
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|
|
56 | sig1 = wire(); | |||
|
|
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|
|
57 | sig2 = wire(); | |||
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|
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|
|
58 | sig3 = wire(); | |||
|
|
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59 | sig4 = wire(); | |||
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|
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60 | ||||
|
|
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|
|
61 | s.connect_to_in(sig1); | |||
|
|
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|
|
62 | s.connect_to_in(sig2); | |||
|
|
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|
|
63 | #s.connect_to_in(sig3,NEG); | |||
|
|
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|
|
64 | s.connect_to_out(sig4); | |||
|
|
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|
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65 | ||||
|
|
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|
|
66 | segnal1 = [ Decimal(1) *i for i in range(100)]; | |||
|
|
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|
|
67 | segnal2 = [ Decimal(2) for i in range(100)]; | |||
|
|
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|
|
68 | #segnal3 = [3 for i in range(100)]; | |||
|
|
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|
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69 | ||||
|
|
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|
|
70 | p1 = pin(clk,sig1); | |||
|
|
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|
|
71 | p1.set_data(segnal1); | |||
|
|
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|
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72 | ||||
|
|
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|
|
73 | p2 = pin(clk,sig2); | |||
|
|
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|
|
74 | p2.set_data(segnal2); | |||
|
|
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|
|
75 | ||||
|
|
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|
|
76 | #p3 = pin(clk,sig3); | |||
|
|
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|
|
77 | #p3.set_data(segnal3); | |||
|
|
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|
|
78 | ||||
|
|
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|
|
79 | ||||
|
|
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|
|
80 | for i in segnal1: | |||
|
|
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|
|
81 | clk.tick(); | |||
|
|
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|
|
82 | print sig1.read(),sig2.read()#,sig3.read(); | |||
|
|
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|
|
83 | print sig4.read(); | |||
|
|
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|
|
84 | print "-------" | |||
|
|
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|
|
85 | No newline at end of file | |||
| @@ -0,0 +1,45 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Jan 8, 2015 | |||
|
|
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|
|
3 | ||||
|
|
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|
|
4 | @author: aras | |||
|
|
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5 | ''' | |||
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6 | from primitives.wire import wire | |||
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7 | import numpy as np | |||
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8 | from decimal import * | |||
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9 | ||||
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10 | class atten(object): | |||
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11 | ''' | |||
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12 | classdocs | |||
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13 | ''' | |||
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14 | ||||
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15 | ||||
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16 | def __init__(self, wire_in,wire_out, atte = Decimal(1)): | |||
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17 | ''' | |||
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18 | Constructor | |||
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19 | ''' | |||
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20 | ||||
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21 | self.__wire_in = wire_in; | |||
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22 | self.__wire_out = wire_out; | |||
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23 | ||||
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24 | wire_in.async_element(self); | |||
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25 | self.__atte = Decimal(atte); | |||
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26 | self.__wire_out.drive(Decimal(0)); | |||
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27 | self.__update__() | |||
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28 | ||||
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29 | ||||
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30 | def __update__(self): | |||
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31 | if type(self.__wire_out)<> type(None): | |||
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32 | self.__wire_out.drive(self.__wire_in.read()/self.__atte); | |||
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33 | ||||
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34 | ||||
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35 | if __name__=="__main__": | |||
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36 | sig1 = wire(Decimal(2)); | |||
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37 | sig2 = wire(); | |||
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38 | g = atten(sig1,sig2,atte=Decimal(10)); | |||
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39 | ||||
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40 | ||||
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41 | print sig2.read(); | |||
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42 | ||||
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43 | sig1.drive(Decimal(2500)); | |||
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44 | ||||
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45 | print sig2.read(); No newline at end of file | |||
| @@ -0,0 +1,110 | |||||
|
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1 | ''' | |||
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2 | Created on Jan 7, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | ||||
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7 | class clock(object): | |||
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8 | ''' | |||
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9 | classdocs | |||
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10 | ''' | |||
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11 | ||||
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12 | def __init__(self,steps=1,name=""): | |||
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13 | ''' | |||
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14 | Constructor | |||
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15 | ''' | |||
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16 | self.__elems__ = []; | |||
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17 | self.__clks__ = []; | |||
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18 | self.__steps__ = steps; | |||
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19 | self.__cnt__ = steps; | |||
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20 | self.__name = name; | |||
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21 | self.__first_tick__=True; | |||
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22 | ||||
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23 | def connect_element(self,elem): | |||
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24 | if type(elem) <> type(self): | |||
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25 | self.__elems__.append(elem); | |||
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26 | ||||
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27 | def get_subclock(self,div): | |||
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28 | clk = clock(steps=div); | |||
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29 | self.__clks__.append(clk); | |||
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30 | return clk; | |||
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31 | ||||
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32 | def __initialization__(self): | |||
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33 | for elem in self.__elems__: | |||
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34 | elem.__initialization__(); | |||
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35 | for elem in self.__clks__: | |||
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36 | elem.__initialization__(); | |||
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37 | ||||
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38 | def tick(self): | |||
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39 | if self.__first_tick__: | |||
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40 | self.__first_tick__= False; | |||
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41 | self.__initialization__(); | |||
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42 | self.__next_sample__(); | |||
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43 | self.__edge__(); | |||
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44 | self.__stabilize__(); | |||
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45 | self.__propagate__(); | |||
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46 | self.__read_sample__(); | |||
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47 | ||||
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48 | #print "--------------------" | |||
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49 | ||||
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50 | def __next_sample__(self): | |||
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51 | self.__cnt__ += 1; | |||
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52 | if self.__cnt__ >= self.__steps__: | |||
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53 | ||||
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54 | for elem in self.__elems__: | |||
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55 | elem.__next_sample__(); | |||
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56 | for elem in self.__clks__: | |||
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57 | elem.__next_sample__(); | |||
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|
58 | #print "next sample",self.__name; | |||
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59 | ||||
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60 | def __edge__(self): | |||
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|
61 | if self.__cnt__ >= self.__steps__: | |||
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62 | for elem in self.__elems__: | |||
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63 | elem.__edge__(); | |||
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64 | for elem in self.__clks__: | |||
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65 | elem.__edge__(); | |||
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66 | #print "edge",self.__name,self.__cnt__,self.__steps__; | |||
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67 | ||||
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68 | def __stabilize__(self): | |||
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|
69 | if self.__cnt__ >= self.__steps__: | |||
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70 | for elem in self.__elems__: | |||
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71 | elem.__stabilize__(); | |||
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72 | for elem in self.__clks__: | |||
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73 | elem.__stabilize__(); | |||
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74 | #print "stabilize",self.__name;; | |||
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75 | ||||
|
|
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76 | ||||
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77 | def __propagate__(self): | |||
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|
78 | if self.__cnt__ >= self.__steps__: | |||
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79 | for elem in self.__elems__: | |||
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80 | elem.__propagate__(); | |||
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81 | for elem in self.__clks__: | |||
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|
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|
|
82 | elem.__propagate__(); | |||
|
|
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|
|
83 | #print "propagate",self.__name; | |||
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|
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|
84 | ||||
|
|
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|
|
85 | ||||
|
|
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|
|
86 | def __read_sample__(self): | |||
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|
|
87 | if self.__cnt__ >= self.__steps__: | |||
|
|
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|
|
88 | self.__cnt__ = 0; | |||
|
|
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|
|
89 | for elem in self.__elems__: | |||
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|
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|
|
90 | elem.__read_sample__(); | |||
|
|
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|
91 | for elem in self.__clks__: | |||
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|
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|
|
92 | elem.__read_sample__(); | |||
|
|
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|
|
93 | #print "read sample",self.__name; | |||
|
|
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|
|
94 | ||||
|
|
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|
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95 | ||||
|
|
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|
|
96 | def get_cnt(self): | |||
|
|
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|
|
97 | return self.__cnt__; | |||
|
|
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98 | ||||
|
|
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|
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99 | ||||
|
|
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|
|
100 | if __name__=="__main__": | |||
|
|
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|
|
101 | clk1 = clock(name="master"); | |||
|
|
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|
|
102 | clk2 = clk1.get_subclock(4); | |||
|
|
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|
|
103 | clk1.tick() | |||
|
|
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|
|
104 | clk1.tick() | |||
|
|
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|
|
105 | clk1.tick() | |||
|
|
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|
|
106 | clk1.tick() | |||
|
|
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|
107 | clk1.tick() | |||
|
|
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|
|
108 | clk1.tick() | |||
|
|
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|
|
109 | clk1.tick() | |||
|
|
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|
|
110 | clk1.tick() No newline at end of file | |||
| @@ -0,0 +1,74 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Jan 6, 2015 | |||
|
|
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|
|
3 | ||||
|
|
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|
|
4 | @author: aras | |||
|
|
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|
|
5 | ''' | |||
|
|
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|
|
6 | from decimal import * | |||
|
|
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|
|
7 | ||||
|
|
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|
|
8 | class delay(object): | |||
|
|
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|
|
9 | ''' | |||
|
|
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|
|
10 | classdocs | |||
|
|
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|
|
11 | ''' | |||
|
|
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|
|
12 | ||||
|
|
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|
|
13 | def __init__(self,clk,wire_in, wire_out, deep=1): | |||
|
|
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|
|
14 | ''' | |||
|
|
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|
|
15 | Constructor | |||
|
|
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|
|
16 | ''' | |||
|
|
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|
|
17 | self.__wire_in = wire_in; | |||
|
|
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|
|
18 | self.__wire_out = wire_out; | |||
|
|
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|
|
19 | self.__stt = [Decimal(0) for i in range(deep)]; | |||
|
|
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|
|
20 | self.__clk = clk; | |||
|
|
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|
|
21 | self.__clk.connect_element(self); | |||
|
|
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|
|
22 | ||||
|
|
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|
|
23 | ||||
|
|
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|
|
24 | ||||
|
|
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|
|
25 | def __initialization__(self): | |||
|
|
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|
|
26 | self.__wire_out.drive(Decimal(0)); | |||
|
|
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|
|
27 | ||||
|
|
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|
|
28 | ||||
|
|
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|
|
29 | def __next_sample__(self): | |||
|
|
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|
|
30 | pass; | |||
|
|
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|
|
31 | ||||
|
|
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|
|
32 | ||||
|
|
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|
|
33 | def __edge__(self): | |||
|
|
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|
|
34 | pass; | |||
|
|
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|
|
35 | ||||
|
|
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|
|
36 | ||||
|
|
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|
|
37 | def __stabilize__(self): | |||
|
|
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|
|
38 | self.__wire_out.drive(self.__stt.pop(0)); | |||
|
|
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|
|
39 | ||||
|
|
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|
|
40 | ||||
|
|
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|
|
41 | def __propagate__(self): | |||
|
|
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|
|
42 | self.__stt.append(self.__wire_in.read()); | |||
|
|
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|
|
43 | ||||
|
|
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|
|
44 | ||||
|
|
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|
|
45 | def __read_sample__(self): | |||
|
|
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|
|
46 | pass; | |||
|
|
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|
|
47 | ||||
|
|
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|
|
48 | ||||
|
|
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|
|
49 | ||||
|
|
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|
|
50 | ||||
|
|
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|
|
51 | if __name__=="__main__": | |||
|
|
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|
|
52 | from primitives.wire import wire | |||
|
|
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|
|
53 | from primitives.clock import clock | |||
|
|
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|
|
54 | from primitives.pin import pin | |||
|
|
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|
|
55 | ||||
|
|
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|
|
56 | signal = [Decimal(i) for i in range(1,31)]; | |||
|
|
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|
|
57 | #signal[0]=1; | |||
|
|
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|
|
58 | ||||
|
|
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|
|
59 | clk = clock(); | |||
|
|
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|
|
60 | sig0 = wire(); | |||
|
|
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|
|
61 | sig1 = wire(); | |||
|
|
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|
|
62 | z1 = delay(clk,sig0,sig1,deep=1); | |||
|
|
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|
|
63 | ||||
|
|
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|
|
64 | ||||
|
|
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|
|
65 | p_int = pin(clk,wire_out=sig0); | |||
|
|
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|
|
66 | p_int.set_data(signal); | |||
|
|
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|
|
67 | ||||
|
|
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|
|
68 | ||||
|
|
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|
|
69 | ||||
|
|
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|
|
70 | for i in signal: | |||
|
|
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|
|
71 | clk.tick(); | |||
|
|
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|
|
72 | print sig0.read(), sig1.read(); | |||
|
|
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|
|
73 | print "-----------------" | |||
|
|
No newline at end of file | ||||
|
|
74 | No newline at end of file | |||
| @@ -0,0 +1,104 | |||||
|
|
1 | ''' | |||
|
|
No newline at end of file | ||||
|
|
2 | Created on Jan 7, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | from primitives.wire import wire | |||
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7 | from primitives.clock import clock | |||
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8 | ||||
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9 | class downsampler(object): | |||
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10 | ''' | |||
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11 | classdocs | |||
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12 | ''' | |||
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13 | ||||
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14 | ||||
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15 | def __init__(self, clk, dec): | |||
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16 | ''' | |||
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17 | Constructor | |||
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18 | ''' | |||
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19 | self.__wire_in__ = None; | |||
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20 | self.__stt__ = 0; | |||
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21 | if dec <= 0 : dec = 1; | |||
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22 | self.__dwn_clk__ = clk.get_subclock(dec); | |||
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23 | self.__wire_out__ = None; | |||
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24 | self.__clk__ = clk; | |||
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25 | self.__dwn_clk__.connect_element(self); | |||
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26 | ||||
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27 | self.__high_level__ = False; | |||
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28 | ||||
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29 | ||||
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30 | def get_down_clock(self): | |||
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31 | return self.__dwn_clk__; | |||
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32 | ||||
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33 | def __update__(self): | |||
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34 | pass; | |||
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35 | ||||
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36 | ||||
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37 | ||||
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38 | def __initialization__(self): | |||
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39 | self.__wire_out__.drive(0); | |||
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40 | ||||
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41 | ||||
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42 | def __next_sample__(self): | |||
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43 | pass; | |||
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44 | ||||
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45 | ||||
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46 | def __edge__(self): | |||
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47 | pass; | |||
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48 | # self.__high_level__ = True; | |||
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49 | # self.__wire_out__.drive(self.__wire_in__.read()); | |||
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50 | ||||
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51 | ||||
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52 | def __stabilize__(self): | |||
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53 | self.__wire_out__.drive(self.__wire_in__.read()); | |||
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54 | ||||
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55 | ||||
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56 | def __propagate__(self): | |||
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57 | pass; | |||
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58 | ||||
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59 | ||||
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60 | def __read_sample__(self): | |||
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61 | self.__high_level__ = False; | |||
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62 | ||||
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63 | def connect_to_in(self,wire_in): | |||
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64 | self.__wire_in__ = wire_in; | |||
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65 | #wire_in.async_element(self); | |||
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66 | ||||
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67 | ||||
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68 | def connect_to_out(self,wire_out): | |||
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69 | self.__wire_out__ = wire_out; | |||
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70 | ||||
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71 | ||||
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72 | if __name__=="__main__": | |||
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73 | from primitives.pin import pin | |||
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74 | from primitives.pout import pout | |||
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75 | segnal = [i for i in range(1,101)]; | |||
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76 | dec = 5; | |||
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77 | ||||
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78 | clk = clock(); | |||
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79 | d1 = downsampler(clk,dec); | |||
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80 | dclk = d1.get_down_clock() | |||
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81 | ||||
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82 | ||||
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83 | sig0 = wire(); | |||
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84 | sig1 = wire(); | |||
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85 | ||||
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86 | d1.connect_to_in(sig0); | |||
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87 | d1.connect_to_out(sig1); | |||
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88 | ||||
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89 | ||||
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90 | p_int = pin(clk,sig0); | |||
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91 | p_int.set_data(segnal); | |||
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92 | ||||
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93 | p4 = pout(clk,sig0); | |||
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94 | p5 = pout(dclk,sig1); | |||
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95 | ||||
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96 | ||||
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97 | print sig0.read(),sig1.read(); | |||
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98 | for sig in segnal[1:103]: | |||
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99 | clk.tick(); | |||
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100 | print sig0.read(),sig1.read(); | |||
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101 | ||||
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102 | print segnal; | |||
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103 | print p4.get_data(); | |||
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104 | print p5.get_data(); No newline at end of file | |||
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1 | ''' | |||
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2 | Created on Jan 8, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | from primitives.wire import wire | |||
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7 | import numpy as np | |||
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8 | from decimal import * | |||
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9 | ||||
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10 | class gain(object): | |||
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11 | ''' | |||
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12 | classdocs | |||
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13 | ''' | |||
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14 | ||||
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15 | ||||
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16 | def __init__(self, wire_in,wire_out, gain = Decimal(1)): | |||
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17 | ''' | |||
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18 | Constructor | |||
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19 | ''' | |||
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20 | ||||
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21 | self.__wire_in = wire_in; | |||
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22 | self.__wire_out = wire_out; | |||
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23 | ||||
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24 | wire_in.async_element(self); | |||
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25 | self.__gain = Decimal(gain); | |||
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26 | self.__wire_out.drive(Decimal(0)); | |||
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27 | self.__update__() | |||
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28 | ||||
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29 | ||||
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30 | def __update__(self): | |||
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31 | if type(self.__wire_out)<> type(None): | |||
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32 | self.__wire_out.drive(self.__wire_in.read()*self.__gain); | |||
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33 | ||||
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34 | ||||
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35 | if __name__=="__main__": | |||
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36 | sig1 = wire(Decimal(2)); | |||
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37 | sig2 = wire(); | |||
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38 | g = gain(sig1,sig2,gain=Decimal(100)); | |||
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39 | ||||
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40 | ||||
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41 | print sig2.read(); | |||
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42 | ||||
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43 | sig1.drive(Decimal(25)); | |||
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44 | ||||
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45 | print sig2.read(); No newline at end of file | |||
| @@ -0,0 +1,67 | |||||
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1 | ''' | |||
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2 | Created on Jan 8, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | ||||
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7 | from primitives.wire import wire | |||
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8 | from decimal import * | |||
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9 | ||||
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10 | class pin(object): | |||
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11 | ''' | |||
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12 | classdocs | |||
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13 | ''' | |||
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14 | ||||
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15 | ||||
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16 | def __init__(self,clk,wire_out=wire()): | |||
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17 | ''' | |||
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18 | Constructor | |||
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19 | ''' | |||
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20 | ||||
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21 | self.__clk__ = clk; | |||
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22 | self.__clk__.connect_element(self); | |||
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23 | self.__wire_out__ = None; | |||
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24 | ||||
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25 | self.__data__ = []; | |||
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26 | self.__size__ = 0; | |||
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27 | self.__tick_idx__ = 0; | |||
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28 | ||||
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29 | self.__wire_out__ = wire_out; | |||
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30 | ||||
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31 | def __initialization__(self): | |||
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32 | self.__wire_out__.drive(0); | |||
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33 | ||||
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34 | ||||
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35 | def __next_sample__(self): | |||
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36 | self.__wire_out__.drive(Decimal(self.__data__[self.__tick_idx__])); | |||
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37 | self.__tick_idx__ += 1; | |||
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38 | if self.__tick_idx__ < self.__size__: | |||
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39 | pass | |||
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40 | else: | |||
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41 | self.__wire_out__.drive(0); | |||
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42 | #self.__tick_idx__ = 0; | |||
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43 | ||||
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44 | def __edge__(self): | |||
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45 | pass; | |||
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46 | ||||
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47 | def __stabilize__(self): | |||
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48 | pass; | |||
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49 | ||||
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50 | ||||
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51 | def __propagate__(self): | |||
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52 | pass; | |||
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53 | ||||
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54 | ||||
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55 | def __read_sample__(self): | |||
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56 | pass; | |||
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57 | ||||
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58 | ||||
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59 | def set_data(self,data=[]): | |||
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60 | self.__data__ = data; | |||
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61 | self.__size__ = len(data); | |||
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62 | self.__index__ = 0; | |||
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63 | self.__wire_out__.drive(Decimal(data[self.__index__])); | |||
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64 | ||||
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65 | ||||
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66 | ||||
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67 | No newline at end of file | |||
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1 | ''' | |||
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2 | Created on Jan 12, 2015 | |||
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3 | ||||
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4 | @author: aras | |||
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5 | ''' | |||
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6 | ||||
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7 | from primitives.wire import wire | |||
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8 | ||||
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9 | class pout(object): | |||
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10 | ''' | |||
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11 | classdocs | |||
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12 | ''' | |||
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13 | ||||
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14 | ||||
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15 | def __init__(self, clk, wire_in=wire()): | |||
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16 | ''' | |||
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17 | Constructor | |||
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18 | ''' | |||
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|
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19 | self.__wire_in__ = wire_in; | |||
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20 | self.__data__ = []; | |||
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21 | ||||
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|
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22 | self.__clk__ = clk; | |||
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|
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23 | clk.connect_element(self); | |||
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24 | ||||
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25 | def __initialization__(self): | |||
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26 | pass; | |||
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27 | ||||
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28 | ||||
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29 | def __next_sample__(self): | |||
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30 | pass; | |||
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31 | ||||
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32 | ||||
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33 | def __edge__(self): | |||
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34 | pass; | |||
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35 | ||||
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36 | def __stabilize__(self): | |||
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37 | pass; | |||
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38 | ||||
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39 | ||||
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40 | def __propagate__(self): | |||
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41 | pass; | |||
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42 | ||||
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43 | ||||
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44 | def __read_sample__(self): | |||
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45 | self.__data__.append(float(self.__wire_in__.read())); | |||
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46 | ||||
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47 | ||||
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48 | def get_data(self): | |||
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49 | data = self.__data__; | |||
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50 | self.__data__ = []; | |||
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51 | return data; | |||
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52 | ||||
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53 | if __name__=="__main__": | |||
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54 | from primitives.clock import clock | |||
|
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55 | from primitives.pin import pin | |||
|
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56 | ||||
|
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|
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57 | segnal = [float(i) for i in range(1,31)]; | |||
|
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58 | clk = clock(); | |||
|
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|
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59 | sig0 = wire(); | |||
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|
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60 | ||||
|
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|
|
61 | p_int = pin(clk,wire_out=sig0); | |||
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|
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62 | p_int.set_data(segnal); | |||
|
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63 | ||||
|
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|
|
64 | p_out = pout(clk,wire_in=sig0); | |||
|
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|
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65 | ||||
|
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66 | print sig0.read(); | |||
|
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67 | ||||
|
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|
|
68 | for sig in segnal: | |||
|
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|
|
69 | clk.tick(); | |||
|
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|
|
70 | print sig0.read(); | |||
|
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|
|
71 | ||||
|
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|
|
72 | print p_out.get_data() No newline at end of file | |||
| @@ -0,0 +1,60 | |||||
|
|
1 | ''' | |||
|
|
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|
|
2 | Created on Jan 6, 2015 | |||
|
|
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|
|
3 | ||||
|
|
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|
|
4 | @author: aras | |||
|
|
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|
|
5 | ''' | |||
|
|
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|
|
6 | from decimal import * | |||
|
|
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|
|
7 | ||||
|
|
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|
|
8 | class wire(object): | |||
|
|
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|
|
9 | ''' | |||
|
|
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|
|
10 | classdocs | |||
|
|
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|
|
11 | ''' | |||
|
|
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|
|
12 | wire_cnt = 0; | |||
|
|
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|
|
13 | all_wires = {}; | |||
|
|
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|
|
14 | ||||
|
|
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|
|
15 | @staticmethod | |||
|
|
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|
|
16 | def get_wires(): | |||
|
|
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|
|
17 | return wire.all_wires; | |||
|
|
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|
|
18 | ||||
|
|
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|
|
19 | def __init__(self,initval=Decimal(0)): | |||
|
|
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|
|
20 | ''' | |||
|
|
No newline at end of file | ||||
|
|
21 | Constructor | |||
|
|
No newline at end of file | ||||
|
|
22 | ''' | |||
|
|
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|
|
23 | wire.wire_cnt += 1; | |||
|
|
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|
|
24 | ||||
|
|
No newline at end of file | ||||
|
|
25 | self.__wire_stt__ = initval; | |||
|
|
No newline at end of file | ||||
|
|
26 | self.__asyncs__ = []; | |||
|
|
No newline at end of file | ||||
|
|
27 | ||||
|
|
No newline at end of file | ||||
|
|
28 | self.__wire_name__ = "__wire_"+str(wire.wire_cnt)+"__"; | |||
|
|
No newline at end of file | ||||
|
|
29 | wire.all_wires[self.__wire_name__] = self; | |||
|
|
No newline at end of file | ||||
|
|
30 | ||||
|
|
No newline at end of file | ||||
|
|
31 | ||||
|
|
No newline at end of file | ||||
|
|
32 | ||||
|
|
No newline at end of file | ||||
|
|
33 | def get_name(self): | |||
|
|
No newline at end of file | ||||
|
|
34 | return self.__wire_name__; | |||
|
|
No newline at end of file | ||||
|
|
35 | ||||
|
|
No newline at end of file | ||||
|
|
36 | def drive(self, val): | |||
|
|
No newline at end of file | ||||
|
|
37 | self.__set_val__(val); | |||
|
|
No newline at end of file | ||||
|
|
38 | self.__update__(); | |||
|
|
No newline at end of file | ||||
|
|
39 | ||||
|
|
No newline at end of file | ||||
|
|
40 | def __set_val__(self,val): | |||
|
|
No newline at end of file | ||||
|
|
41 | self.__wire_stt__ = val; | |||
|
|
No newline at end of file | ||||
|
|
42 | ||||
|
|
No newline at end of file | ||||
|
|
43 | def __update__(self): | |||
|
|
No newline at end of file | ||||
|
|
44 | for elem in self.__asyncs__: | |||
|
|
No newline at end of file | ||||
|
|
45 | elem.__update__(); | |||
|
|
No newline at end of file | ||||
|
|
46 | ||||
|
|
No newline at end of file | ||||
|
|
47 | def read(self): | |||
|
|
No newline at end of file | ||||
|
|
48 | return self.__wire_stt__; | |||
|
|
No newline at end of file | ||||
|
|
49 | ||||
|
|
No newline at end of file | ||||
|
|
50 | def async_element(self,elem): | |||
|
|
No newline at end of file | ||||
|
|
51 | self.__asyncs__.append(elem); | |||
|
|
No newline at end of file | ||||
|
|
52 | ||||
|
|
No newline at end of file | ||||
|
|
53 | if __name__=="__main__": | |||
|
|
No newline at end of file | ||||
|
|
54 | wi1 = wire(); print wire.wire_cnt | |||
|
|
No newline at end of file | ||||
|
|
55 | wi2 = wire(); print wire.wire_cnt | |||
|
|
No newline at end of file | ||||
|
|
56 | wi3 = wire(); print wire.wire_cnt | |||
|
|
No newline at end of file | ||||
|
|
57 | wi4 = wire(); print wire.wire_cnt | |||
|
|
No newline at end of file | ||||
|
|
58 | wi5 = wire(); print wire.wire_cnt | |||
|
|
No newline at end of file | ||||
|
|
59 | print wire.get_wires() | |||
|
|
No newline at end of file | ||||
|
|
60 | No newline at end of file | |||
| @@ -0,0 +1,49 | |||||
|
|
1 | ''' | |||
|
|
No newline at end of file | ||||
|
|
2 | Created on Feb 16, 2015 | |||
|
|
No newline at end of file | ||||
|
|
3 | ||||
|
|
No newline at end of file | ||||
|
|
4 | @author: shinobi | |||
|
|
No newline at end of file | ||||
|
|
5 | ''' | |||
|
|
No newline at end of file | ||||
|
|
6 | import obspy | |||
|
|
No newline at end of file | ||||
|
|
7 | from cic.mless_cic import cic_designer | |||
|
|
No newline at end of file | ||||
|
|
8 | from primitives.wire import wire | |||
|
|
No newline at end of file | ||||
|
|
9 | from primitives.clock import clock | |||
|
|
No newline at end of file | ||||
|
|
10 | from copy import copy | |||
|
|
No newline at end of file | ||||
|
|
11 | import numpy | |||
|
|
No newline at end of file | ||||
|
|
12 | from decimal import * | |||
|
|
No newline at end of file | ||||
|
|
13 | ||||
|
|
No newline at end of file | ||||
|
|
14 | if __name__ == '__main__': | |||
|
|
No newline at end of file | ||||
|
|
15 | trace = obspy.read("./ENEFEB15/015930/PE.STPO..BHZ.MSEED"); | |||
|
|
No newline at end of file | ||||
|
|
16 | #print trace[0].stats; | |||
|
|
No newline at end of file | ||||
|
|
17 | data = trace[0].data; | |||
|
|
No newline at end of file | ||||
|
|
18 | dat = copy(data); | |||
|
|
No newline at end of file | ||||
|
|
19 | dat.sort(); | |||
|
|
No newline at end of file | ||||
|
|
20 | dc = dat[len(dat)/2]; | |||
|
|
No newline at end of file | ||||
|
|
21 | #print dc | |||
|
|
No newline at end of file | ||||
|
|
22 | data = numpy.array(data,Decimal); | |||
|
|
No newline at end of file | ||||
|
|
23 | data = data -dc; | |||
|
|
No newline at end of file | ||||
|
|
24 | trace[0].data = data; | |||
|
|
No newline at end of file | ||||
|
|
25 | #trace.plot() | |||
|
|
No newline at end of file | ||||
|
|
26 | #print data | |||
|
|
No newline at end of file | ||||
|
|
27 | ||||
|
|
No newline at end of file | ||||
|
|
28 | M = 10; | |||
|
|
No newline at end of file | ||||
|
|
29 | K = 5; | |||
|
|
No newline at end of file | ||||
|
|
30 | ro= 8*2; | |||
|
|
No newline at end of file | ||||
|
|
31 | ||||
|
|
No newline at end of file | ||||
|
|
32 | dtsz = len(data); # cantidad de muestras de data original | |||
|
|
No newline at end of file | ||||
|
|
33 | print dtsz; | |||
|
|
No newline at end of file | ||||
|
|
34 | Fs = 100.0; # frecuencia de muestreo de data original | |||
|
|
No newline at end of file | ||||
|
|
35 | ||||
|
|
No newline at end of file | ||||
|
|
36 | sig = numpy.array([0 for i in range(dtsz)]); | |||
|
|
No newline at end of file | ||||
|
|
37 | sig[0]=Decimal(1); | |||
|
|
No newline at end of file | ||||
|
|
38 | ||||
|
|
No newline at end of file | ||||
|
|
39 | win = wire(); | |||
|
|
No newline at end of file | ||||
|
|
40 | wout = wire(); | |||
|
|
No newline at end of file | ||||
|
|
41 | clk = clock(); | |||
|
|
No newline at end of file | ||||
|
|
42 | ||||
|
|
No newline at end of file | ||||
|
|
43 | cic = cic_designer(M,K,ro, clk,win, wout); | |||
|
|
No newline at end of file | ||||
|
|
44 | cic.test_downsamples(); | |||
|
|
No newline at end of file | ||||
|
|
45 | exit(); | |||
|
|
No newline at end of file | ||||
|
|
46 | cic.simulate(data); | |||
|
|
No newline at end of file | ||||
|
|
47 | cic.plot_frequency_response(Fs); | |||
|
|
No newline at end of file | ||||
|
|
48 | ||||
|
|
No newline at end of file | ||||
|
|
49 | No newline at end of file | |||
| @@ -5,15 +5,15 | |||||
| 5 | <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="de.innot.avreclipse.configuration.app.debug.2000262611" moduleId="org.eclipse.cdt.core.settings" name="Debug"> No newline at end of file |
|
5 | <storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="de.innot.avreclipse.configuration.app.debug.2000262611" moduleId="org.eclipse.cdt.core.settings" name="Debug"> | |
| 6 | <externalSettings/> No newline at end of file |
|
6 | <externalSettings/> | |
| 7 | <extensions> |
|
7 | <extensions> | |
| No newline at end of file |
|
||||
| 8 | <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> No newline at end of file |
|
|||
| 9 | <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> No newline at end of file |
|
8 | <extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |
| 10 | <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> No newline at end of file |
|
9 | <extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |
| 11 | <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> No newline at end of file |
|
10 | <extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |
| 12 | <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> No newline at end of file |
|
11 | <extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/> | |
|
|
12 | <extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/> No newline at end of file | |||
| 13 | </extensions> No newline at end of file |
|
13 | </extensions> | |
| 14 | </storageModule> No newline at end of file |
|
14 | </storageModule> | |
| 15 | <storageModule moduleId="cdtBuildSystem" version="4.0.0"> |
|
15 | <storageModule moduleId="cdtBuildSystem" version="4.0.0"> | |
| No newline at end of file |
|
16 | <configuration artifactName="${ProjName}" buildArtefactType="de.innot.avreclipse.buildArtefactType.app" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=de.innot.avreclipse.buildArtefactType.app" description="" id="de.innot.avreclipse.configuration.app.debug.2000262611" name="Debug" parent="de.innot.avreclipse.configuration.app.debug"> No newline at end of file | ||
| 16 | <configuration artifactName="${ProjName}" buildArtefactType="de.innot.avreclipse.buildArtefactType.app" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=de.innot.avreclipse.buildArtefactType.app,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" description="" id="de.innot.avreclipse.configuration.app.debug.2000262611" name="Debug" parent="de.innot.avreclipse.configuration.app.debug"> No newline at end of file |
|
|||
| 17 | <folderInfo id="de.innot.avreclipse.configuration.app.debug.2000262611." name="/" resourcePath=""> No newline at end of file |
|
17 | <folderInfo id="de.innot.avreclipse.configuration.app.debug.2000262611." name="/" resourcePath=""> | |
| 18 | <toolChain id="de.innot.avreclipse.toolchain.winavr.app.debug.822649946" name="AVR-GCC Toolchain" superClass="de.innot.avreclipse.toolchain.winavr.app.debug"> No newline at end of file |
|
18 | <toolChain id="de.innot.avreclipse.toolchain.winavr.app.debug.822649946" name="AVR-GCC Toolchain" superClass="de.innot.avreclipse.toolchain.winavr.app.debug"> | |
| 19 | <option id="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.debug.2015112688" name="Generate HEX file for Flash memory" superClass="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.debug"/> No newline at end of file |
|
19 | <option id="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.debug.2015112688" name="Generate HEX file for Flash memory" superClass="de.innot.avreclipse.toolchain.options.toolchain.objcopy.flash.app.debug"/> | |
| @@ -7,23 +7,57 | |||||
| 7 | No newline at end of file |
|
7 | ||
| 8 | #ifndef POWERENGINED_POWERENGINED_H_ No newline at end of file |
|
8 | #ifndef POWERENGINED_POWERENGINED_H_ | |
| 9 | #define POWERENGINED_POWERENGINED_H_ |
|
9 | #define POWERENGINED_POWERENGINED_H_ | |
| No newline at end of file |
|
10 | #include <avr/io.h> No newline at end of file | ||
| 10 | #include <inttypes.h> No newline at end of file |
|
|||
| 11 | No newline at end of file |
|
11 | ||
| 12 | /* primitivas 1-wire transaction ds2438 . toda data/comandos es leida y escrita No newline at end of file |
|
12 | /* primitivas 1-wire transaction ds2438 . toda data/comandos es leida y escrita | |
| 13 | * primero el bit menos significativo */ No newline at end of file |
|
13 | * primero el bit menos significativo */ | |
| 14 | No newline at end of file |
|
14 | ||
| 15 | No newline at end of file |
|
15 | ||
| 16 | No newline at end of file |
|
16 | ||
|
|
17 | /* Hardware definitions */ | |||
|
|
No newline at end of file | ||||
|
|
18 | #define I2C_SLAVE_ADDR 0x26 No newline at end of file | |||
| 17 |
|
19 | |||
| No newline at end of file |
|
20 | #define DQ_BIT PB3 | ||
| 18 | inline void write_0_signal();//pull-low, wait 15us, remain low 45us (min), release (high),wait 1us |
|
No newline at end of file | ||
| No newline at end of file |
|
21 | #define DQ_PORT PORTB | ||
| 19 | inline void write_1_signal();//pull-low, wait 10us, release (high) 50us (min), remain high,wait 1us |
|
No newline at end of file | ||
| No newline at end of file |
|
22 | #define DQ_PIN PINB | ||
| 20 | inline void write_byte(uint8_t byte); No newline at end of file |
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23 | #define DQ_DDR DDRB | |||
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24 | ||||
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25 | /* DS2438Z definitions */ | |||
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26 | #define READ_ROM 0X33 | |||
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27 | #define MATCH_ROM 0x55 | |||
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28 | #define SEARCH_ROM 0xF0 | |||
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29 | #define SKIP_ROM 0xCC | |||
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30 | #define WRITE_SP 0x4E | |||
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31 | #define READ_SP 0xBE | |||
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32 | #define COPY_SP 0x48 | |||
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33 | #define CONV_T 0x44 | |||
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34 | #define CONV_V 0xB4 | |||
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35 | #define RCALL_MEM 0xB8 | |||
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36 | ||||
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37 | ||||
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38 | /* DS2438Z Memory Pages (ver datasheet) */ | |||
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39 | #define PAGE_0 0x00 | |||
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40 | #define PAGE_1 0x01 | |||
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41 | #define PAGE_2 0x02 | |||
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42 | #define PAGE_3 0x03 | |||
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43 | #define PAGE_4 0x04 | |||
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44 | #define PAGE_5 0x05 | |||
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45 | #define PAGE_6 0x06 | |||
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46 | #define PAGE_7 0x07 | |||
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47 | ||||
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48 | ||||
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49 | ||||
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50 | ||||
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51 | /* Funciones de escritura */ | |||
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52 | void write_0_signal();//pull-low, wait 15us, remain low 45us (min), release (high),wait 1us | |||
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53 | void write_1_signal();//pull-low, wait 10us, release (high) 50us (min), remain high,wait 1us | |||
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54 | void write_byte(uint8_t byte); No newline at end of file | |||
| 21 | void write_bytes(uint8_t* pbytes,uint8_t len); No newline at end of file |
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55 | void write_bytes(uint8_t* pbytes,uint8_t len); | |
| 22 |
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56 | |||
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57 | /* Funciones de lectura */ | ||
| 23 |
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58 | uint8_t read_signal();//pull-low, wait 1us, release, pin I , wait 9us, read line, No newline at end of file | ||
| 24 | inline uint8_t read_signal();//pull-low, wait 1us, release, pin I , wait 9us, read line, No newline at end of file |
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| 25 | //wait 50us(min), pin O, wait 1us |
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59 | //wait 50us(min), pin O, wait 1us | |
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60 | uint8_t read_byte(); No newline at end of file | ||
| 26 | inline uint8_t read_byte(); No newline at end of file |
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| 27 | void read_bytes(uint8_t* pbytes, uint8_t len); No newline at end of file |
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61 | void read_bytes(uint8_t* pbytes, uint8_t len); | |
| 28 | No newline at end of file |
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62 | ||
| 29 | No newline at end of file |
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63 | ||
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| 9 | No newline at end of file |
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9 | ||
| 10 | channel::channel(): No newline at end of file |
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10 | channel::channel(): | |
| 11 | chn_id(0),chn_name{"\0"},chn_gain(0), |
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11 | chn_id(0),chn_name{"\0"},chn_gain(0), | |
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12 | chn_datarate(0),chn_status(0) No newline at end of file | ||
| 12 | chn_baudrate(0),chn_status(0) No newline at end of file |
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| 13 | { No newline at end of file |
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13 | { | |
| 14 | // TODO Auto-generated constructor stub No newline at end of file |
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14 | // TODO Auto-generated constructor stub | |
| 15 | No newline at end of file |
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15 | ||
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| 8 | #include "processEnginectrl.h" No newline at end of file |
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8 | #include "processEnginectrl.h" | |
| 9 | No newline at end of file |
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9 | ||
| 10 | processEngine_ctrl::processEngine_ctrl(): |
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10 | processEngine_ctrl::processEngine_ctrl(): | |
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11 | pdtpkg(nullptr),pe_chns(nullptr),conf_dir(nullptr){ No newline at end of file | ||
| 11 | pdtpkg(nullptr),pe_chns(nullptr){ No newline at end of file |
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| 12 | // TODO Auto-generated constructor stub No newline at end of file |
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12 | // TODO Auto-generated constructor stub | |
| 13 | No newline at end of file |
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13 | ||
| 14 | } No newline at end of file |
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14 | } | |
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