##// END OF EJS Templates
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1 ---------------------------------------------------------------------
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2 library IEEE;
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3 use IEEE.STD_LOGIC_1164.ALL;
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4 use IEEE.numeric_std.all;
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5
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6 use work.cic_utils.all;
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7
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8 entity hc is
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9 Port ( clk : in std_logic;
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10 reset: in std_logic;
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11 input : in std_logic_vector(FIXWIDTH-1 downto 0);
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12 output : out std_logic_vector(FIXWIDTH-1 downto 0));
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13 end hc;
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14
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15 architecture Behavioral of hc is
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16 component hc_block
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17 Port ( clk : in std_logic;
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18 reset: in std_logic;
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19 input : in std_logic_vector(FIXWIDTH-1 downto 0);
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20 output : out std_logic_vector(FIXWIDTH-1 downto 0));
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21 end component;
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22
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23 type filt_bus is array (0 to STAGES+1) of std_logic_vector(FIXWIDTH-1 downto 0);
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24 signal s : filt_bus;
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25
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26 begin
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27 s(0) <= input;
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28 output <= s(STAGES+1);
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29
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30 compensation_filter: for i in 1 to STAGES+1 generate
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31 begin
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32 hc_filt_stage: component hc_block
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33 --(clk,reset,input,output)
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34 port map (clk,reset,s(i-1),s(i));
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35
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36 end generate compensation_filter;
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37
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38 end Behavioral; No newline at end of file
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1 ---------------------------------------------------------------------
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2 library IEEE;
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3 use IEEE.STD_LOGIC_1164.ALL;
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4 use IEEE.numeric_std.all;
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5
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6 use work.cic_utils.all;
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7
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8
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9 entity hc_block is
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10 Port ( clk : in std_logic;
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11 reset: in std_logic;
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12 input : in std_logic_vector(FIXWIDTH-1 downto 0);
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13 output : out std_logic_vector(FIXWIDTH-1 downto 0));
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14 end hc_block;
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15
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16 architecture Behavioral of hc_block is
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17 signal s0,s1,s2,s3: std_logic_vector(FIXWIDTH-1 downto 0);
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18 signal t0 : std_logic_vector(FIXWIDTH-1 downto 0);
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19 constant A : integer := (-625*(2**MANTISSA_BITS))/10000; -- -2^-4
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20 constant B : integer := -18 * (2**MANTISSA_BITS); -- -(2^4 + 2)
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21 begin
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22
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23 process(clk,reset)
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24 begin
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25 if reset='1' then
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26 s1 <= (others=>'0');--to_sfixed(0,s0);
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27 s2 <= (others=>'0');--to_sfixed(0,s0);
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28 elsif clk'event and clk='1' then
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29 s2 <= s1;
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30 s1 <= s0;
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31 end if;
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32 end process;
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33
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34 s0 <= mul(input,to_fix(A));
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35 s3 <= mul(s1,to_fix(B));
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36 t0 <= add(s0,s2);
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37 output <= add(t0,s3);
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38
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39 end Behavioral;
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40 No newline at end of file
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1 -- test_hr Template
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2
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3 LIBRARY ieee;
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4 USE ieee.std_logic_1164.ALL;
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5 USE ieee.numeric_std.ALL;
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6 library IEEE_proposed;
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7 use IEEE_proposed.fixed_pkg.all;
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8 use work.cic_utils.all;
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9
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10
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11 ENTITY test_hr IS
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12 END test_hr;
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13
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14 ARCHITECTURE behavior OF test_hr IS
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15
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16 -- Component Declaration
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17 COMPONENT Hr_block
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18 Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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19 outCa : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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20 outCb : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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21 clk : in std_logic;
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22 ka : in integer range 0 to 18;
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23 kb : in integer range 0 to 18);
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24 END COMPONENT;
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25
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26 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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27 signal outCa : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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28 signal outCb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
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29 signal clk : std_logic;
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30 signal ka : integer range 0 to 18;
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31 signal kb : integer range 0 to 18;
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32
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33 -- Clock period definitions
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34 constant clk_period : time := 1 ms;
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35
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36 BEGIN
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37
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38 -- Component Instantiation
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39 uut: Hr_block PORT MAP(
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40 input => input,
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41 outCa => outCa,
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42 outCb => outCb,
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43 clk => clk,
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44 ka => ka,
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45 kb => kb
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46 );
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47
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48 kb <= 3;
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49 ka <= 0;
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50
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51 -- Clock process definitions
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52 clk_process :process
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53 begin
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54 clk <= '1';
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55 wait for clk_period/2;
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56 clk <= '0';
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57 wait for clk_period/2;
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58 end process;
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59
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60
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61 -- Test Bench Statements
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62 tb : PROCESS
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63 BEGIN
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64
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65 -- hold reset state for 1 ms.
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66 input <= to_sfixed(1,input);
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67 wait for clk_period;
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68 input <= to_sfixed(16,input);
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69 wait for clk_period;
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70
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71 wait;
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72 END PROCESS tb;
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73 -- End Test Bench
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74
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75 END; No newline at end of file
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1 ----------------------------------------------------------------------------------
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2 -- Company:
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3 -- Engineer:
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4 --
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5 -- Create Date: 17:26:48 03/19/2015
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6 -- Design Name:
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7 -- Module Name: integra_gain1 - Behavioral
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8 -- Project Name:
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9 -- Target Devices:
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10 -- Tool versions:
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11 -- Description:
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12 --
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13 -- Dependencies:
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14 --
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15 -- Revision:
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16 -- Revision 0.01 - File Created
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17 -- Additional Comments:
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18 --
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19 ----------------------------------------------------------------------------------
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20 library IEEE;
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21 use IEEE.std_logic_1164.all;
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22 use IEEE.numeric_std.all;
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23
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24 use work.cic_utils.all;
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25
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26 -- entity declaration --------------------------------
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27
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28
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29 entity integra_gain1 is
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30 port (
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31 clk : in std_logic;
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32 N : in integer range 1 to MAX_M2_DEC;
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33 input : in std_logic_vector(FIXWIDTH-1 downto 0);
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34 output : out std_logic_vector(FIXWIDTH-1 downto 0)
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35 );
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36 end integra_gain1;
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37
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38 architecture Behavioral of integra_gain1 is
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39 component integrator
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40 port (
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41 clk : in std_logic;
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42 input : in std_logic_vector(FIXWIDTH-1 downto 0);
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43 output : out std_logic_vector(FIXWIDTH-1 downto 0)
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44 );
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45 end component;
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46 signal s1 ,s2: std_logic_vector(FIXWIDTH-1 downto 0);
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47 begin
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48 inte: integrator port map(
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49 clk => clk,
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50 input => input,
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51 output => s1
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52 );
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53
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54 s2 <= to_fix(ONE/N);
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55 output <= s2*s1;
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56 end Behavioral;
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57 No newline at end of file
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