##// END OF EJS Templates
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1 ---------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5
6 use work.cic_utils.all;
7
8 entity hc is
9 Port ( clk : in std_logic;
10 reset: in std_logic;
11 input : in std_logic_vector(FIXWIDTH-1 downto 0);
12 output : out std_logic_vector(FIXWIDTH-1 downto 0));
13 end hc;
14
15 architecture Behavioral of hc is
16 component hc_block
17 Port ( clk : in std_logic;
18 reset: in std_logic;
19 input : in std_logic_vector(FIXWIDTH-1 downto 0);
20 output : out std_logic_vector(FIXWIDTH-1 downto 0));
21 end component;
22
23 type filt_bus is array (0 to STAGES+1) of std_logic_vector(FIXWIDTH-1 downto 0);
24 signal s : filt_bus;
25
26 begin
27 s(0) <= input;
28 output <= s(STAGES+1);
29
30 compensation_filter: for i in 1 to STAGES+1 generate
31 begin
32 hc_filt_stage: component hc_block
33 --(clk,reset,input,output)
34 port map (clk,reset,s(i-1),s(i));
35
36 end generate compensation_filter;
37
38 end Behavioral;
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1 ---------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5
6 use work.cic_utils.all;
7
8
9 entity hc_block is
10 Port ( clk : in std_logic;
11 reset: in std_logic;
12 input : in std_logic_vector(FIXWIDTH-1 downto 0);
13 output : out std_logic_vector(FIXWIDTH-1 downto 0));
14 end hc_block;
15
16 architecture Behavioral of hc_block is
17 signal s0,s1,s2,s3: std_logic_vector(FIXWIDTH-1 downto 0);
18 signal t0 : std_logic_vector(FIXWIDTH-1 downto 0);
19 constant A : integer := (-625*(2**MANTISSA_BITS))/10000; -- -2^-4
20 constant B : integer := -18 * (2**MANTISSA_BITS); -- -(2^4 + 2)
21 begin
22
23 process(clk,reset)
24 begin
25 if reset='1' then
26 s1 <= (others=>'0');--to_sfixed(0,s0);
27 s2 <= (others=>'0');--to_sfixed(0,s0);
28 elsif clk'event and clk='1' then
29 s2 <= s1;
30 s1 <= s0;
31 end if;
32 end process;
33
34 s0 <= mul(input,to_fix(A));
35 s3 <= mul(s1,to_fix(B));
36 t0 <= add(s0,s2);
37 output <= add(t0,s3);
38
39 end Behavioral;
40
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1 -- test_hr Template
2
3 LIBRARY ieee;
4 USE ieee.std_logic_1164.ALL;
5 USE ieee.numeric_std.ALL;
6 library IEEE_proposed;
7 use IEEE_proposed.fixed_pkg.all;
8 use work.cic_utils.all;
9
10
11 ENTITY test_hr IS
12 END test_hr;
13
14 ARCHITECTURE behavior OF test_hr IS
15
16 -- Component Declaration
17 COMPONENT Hr_block
18 Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
19 outCa : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
20 outCb : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
21 clk : in std_logic;
22 ka : in integer range 0 to 18;
23 kb : in integer range 0 to 18);
24 END COMPONENT;
25
26 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
27 signal outCa : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
28 signal outCb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
29 signal clk : std_logic;
30 signal ka : integer range 0 to 18;
31 signal kb : integer range 0 to 18;
32
33 -- Clock period definitions
34 constant clk_period : time := 1 ms;
35
36 BEGIN
37
38 -- Component Instantiation
39 uut: Hr_block PORT MAP(
40 input => input,
41 outCa => outCa,
42 outCb => outCb,
43 clk => clk,
44 ka => ka,
45 kb => kb
46 );
47
48 kb <= 3;
49 ka <= 0;
50
51 -- Clock process definitions
52 clk_process :process
53 begin
54 clk <= '1';
55 wait for clk_period/2;
56 clk <= '0';
57 wait for clk_period/2;
58 end process;
59
60
61 -- Test Bench Statements
62 tb : PROCESS
63 BEGIN
64
65 -- hold reset state for 1 ms.
66 input <= to_sfixed(1,input);
67 wait for clk_period;
68 input <= to_sfixed(16,input);
69 wait for clk_period;
70
71 wait;
72 END PROCESS tb;
73 -- End Test Bench
74
75 END;
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 17:26:48 03/19/2015
6 -- Design Name:
7 -- Module Name: integra_gain1 - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.std_logic_1164.all;
22 use IEEE.numeric_std.all;
23
24 use work.cic_utils.all;
25
26 -- entity declaration --------------------------------
27
28
29 entity integra_gain1 is
30 port (
31 clk : in std_logic;
32 N : in integer range 1 to MAX_M2_DEC;
33 input : in std_logic_vector(FIXWIDTH-1 downto 0);
34 output : out std_logic_vector(FIXWIDTH-1 downto 0)
35 );
36 end integra_gain1;
37
38 architecture Behavioral of integra_gain1 is
39 component integrator
40 port (
41 clk : in std_logic;
42 input : in std_logic_vector(FIXWIDTH-1 downto 0);
43 output : out std_logic_vector(FIXWIDTH-1 downto 0)
44 );
45 end component;
46 signal s1 ,s2: std_logic_vector(FIXWIDTH-1 downto 0);
47 begin
48 inte: integrator port map(
49 clk => clk,
50 input => input,
51 output => s1
52 );
53
54 s2 <= to_fix(ONE/N);
55 output <= s2*s1;
56 end Behavioral;
57
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