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1 [Dolphin]
2 Timestamp=2015,3,11,23,23,3
3 Version=3
4 ViewMode=1
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1 INCREMENT com.sigasi.hdt sigasi 2.0 08-sep-2015 uncounted \
2 VENDOR_STRING=company:pucp.edu.pe;id:16476;mac:d067e531aa88;name:a20032304;type:edu \
3 HOSTID=ANY ISSUER=Sigasi ISSUED=08-Mar-2015 START=08-Mar-2015 \
4 SIGN="1670 17B2 977C C947 45CA 966A C2BD 73B1 BD74 9AA7 F37F \
5 7ED5 C530 86CD D95C 11D8 112A FB74 6A16 4707 7ECB 1FBC 5B19 \
6 9570 1D03 9A3D AA88 4F2E EE58 6B44" No newline at end of file
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1 ---------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5
6 use work.cic_utils.all;
7
8 --**********************************************************************************
9
10 entity Hr is
11 Port ( clk : in std_logic;
12 reset: in std_logic;
13 N : in integer range 1 to MAX_M2_DEC;
14 input : in std_logic_vector(FIXWIDTH-1 downto 0);
15 output : out std_logic_vector(FIXWIDTH-1 downto 0)
16 );
17 end Hr;
18
19 --**********************************************************************************
20
21 architecture filter of Hr is
22
23 -------------------------------------------------------------
24 component hr_block
25 Port ( clk : in std_logic;
26 reset : in std_logic;
27 input : in std_logic_vector(FIXWIDTH-1 downto 0);
28 output : out std_logic_vector(FIXWIDTH-1 downto 0);
29 ka : in std_logic_vector(4 downto 0);
30 kb : in std_logic_vector(4 downto 0);
31 enb : in std_logic);
32 end component hr_block;
33 -------------------------------------------------------------
34 component clk_div
35 Port ( clkin : in STD_LOGIC;
36 clkout: out STD_LOGIC;
37 reset : in std_logic;
38 N : in integer range 1 to 19);
39 end component clk_div;
40 -------------------------------------------------------------
41 type conn is array (0 to MAX_M2_DEC-1) of std_logic_vector(FIXWIDTH-1 downto 0);
42 signal s1,s2,s3: conn;
43 signal s4:std_logic_vector(FIXWIDTH-1 downto 0);
44 signal clkd: std_logic;
45 type enab is array (0 to MAX_M2_DEC-1) of std_logic;
46 signal enb: enab;
47 type k is array (0 to MAX_M2_DEC-1) of std_logic_vector(4 downto 0);
48 constant ka:k := ("00000","00001","00010","00011",
49 "00100","00101","00110","00111",
50 "01000","01001","01010","01011",
51 "01100","01101","01110","01111",
52 "10000","10001","10010");
53 signal kb:k;
54
55 begin
56 s1(0) <= input;
57 output <= s4;
58
59 clkdiv: clk_div port map(
60 clkin => clk,
61 clkout => clkd,
62 reset => reset,
63 N => N
64 );
65
66 --/////////////////////////////////////////////////////////////////////////////////
67 hr_filter: for i in 0 to MAX_M2_DEC-1 generate
68 begin
69 -------------------------------------------------------------
70
71 Gk: component hr_block
72 -- (clk,reset,input,output,ka,kb,encb)
73 port map (clkd,reset,s2(i),s3(i),ka(i),kb(i),enb(i));
74 -------------------------------------------------------------
75 end generate hr_filter;
76 --/////////////////////////////////////////////////////////////////////////////////
77
78
79 -- shift registers --
80 process(clk,reset)
81 begin
82 if reset='1' then
83 for i in 1 to MAX_M2_DEC-1 loop
84 s1(i) <= (others=>'0');
85 end loop;
86 elsif clk'event and clk='1' then
87 for i in MAX_M2_DEC-1 downto 1 loop
88 s1(i) <= s1(i-1);
89 end loop;
90 end if;
91 end process;
92
93
94
95 -- implementa a los decimadores, cada vez que haya un flanco de subida
96 -- en el clock clkd (clkd = clk / N), pasa una muestra al lado de baja
97 -- frecuencia del filtro.
98 -- la salida final del filtro es la suma de las salidas de los bloques.
99 process(clkd,reset)
100 begin
101 if reset='1' then
102 for i in 0 to MAX_M2_DEC-1 loop
103 s2(i) <= (others=>'0');
104 end loop;
105 elsif clkd'event and clkd='1' then
106 for i in 0 to MAX_M2_DEC-1 loop
107 s2(i) <= s1(i);
108 end loop;
109 end if;
110 end process;
111
112
113 -- process(s3)
114 -- variable acum : std_logic_vector(FIXWIDTH-1 downto 0);
115 -- begin
116 -- acum := s3(0);
117 -- for i in 1 to MAX_M2_DEC-1 loop
118 -- acum := acum+s3(i);
119 -- end loop;
120 -- s4 <= acum;
121 -- end process;
122
123 s4 <= s3(0)+s3(1)+s3(2)+s3(3)+s3(4)+s3(5)+
124 s3(6)+s3(7)+s3(8)+s3(9)+s3(10)+s3(11)+
125 s3(12)+s3(13)+s3(14)+s3(15)+s3(16)+s3(17)+s3(18);
126
127 process(N)
128 begin
129 for i in 0 to MAX_M2_DEC-1 loop
130 if N-1 > i then
131 kb(i) <= std_logic_vector(to_unsigned(N-i-2,kb(i)'length));
132 else
133 kb(i) <= std_logic_vector(to_unsigned(19,kb(i)'length));
134 end if;
135
136 if N-1 >= i then
137 enb(i) <= '1';
138 else
139 enb(i) <= '0';
140 end if;
141 end loop;
142 end process;
143
144 end filter;
145
146 --********************************************************************************** No newline at end of file
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1 ----------------------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5
6 use work.cic_utils.all;
7
8 -- Este modulo implementa el bloque Gk del filtro Hr
9
10 entity hr_block is
11 Port ( clk : in std_logic;
12 reset : in std_logic;
13 input : in std_logic_vector(FIXWIDTH-1 downto 0);
14 output : out std_logic_vector(FIXWIDTH-1 downto 0);
15 ka : in std_logic_vector(4 downto 0);
16 kb : in std_logic_vector(4 downto 0);
17 enb : in std_logic);
18 end hr_block;
19
20
21
22 architecture simple_block of Hr_block is
23 signal s1,s2,s3 : std_logic_vector(FIXWIDTH-1 downto 0);
24 signal Ca,Cb : std_logic_vector(FIXWIDTH-1 downto 0);
25 type ROM is array (0 to 19) of std_logic_vector(FIXWIDTH-1 downto 0);
26 constant coeffs : ROM:= ( to_fix(2**MANTISSA_BITS),
27 to_fix((196875 *(2**MANTISSA_BITS))/100000),
28 to_fix((284375 *(2**MANTISSA_BITS))/100000),
29 to_fix((362500 *(2**MANTISSA_BITS))/100000),
30 to_fix((425000 *(2**MANTISSA_BITS))/100000),
31 to_fix((475000 *(2**MANTISSA_BITS))/100000),
32 to_fix((503125 *(2**MANTISSA_BITS))/100000),
33 to_fix((512500 *(2**MANTISSA_BITS))/100000),
34 to_fix((503125 *(2**MANTISSA_BITS))/100000),
35 to_fix((475000 *(2**MANTISSA_BITS))/100000),
36 to_fix((425000 *(2**MANTISSA_BITS))/100000),
37 to_fix((362500 *(2**MANTISSA_BITS))/100000),
38 to_fix((284375 *(2**MANTISSA_BITS))/100000),
39 to_fix((196875 *(2**MANTISSA_BITS))/100000),
40 to_fix(2**MANTISSA_BITS),
41 to_fix(0),
42 to_fix((-100000 *(2**MANTISSA_BITS))/100000),
43 to_fix((-196875 *(2**MANTISSA_BITS))/100000),
44 to_fix((-284375 *(2**MANTISSA_BITS))/100000),
45 to_fix(0));-- el coeficieente 19 no existe, solo es para anular un tap
46
47
48 begin
49 Ca <= coeffs(to_integer(unsigned(ka)));
50 Cb <= coeffs(to_integer(unsigned(kb)));
51
52 process (clk,enb,reset)
53 begin
54 if (enb = '0') or (reset='1') then
55 s2 <= (others =>'0');
56 elsif clk'event and clk='1' then
57 s2 <= s1;
58 end if;
59
60 end process;
61 s1 <= input*Cb;
62 with enb select
63 s3 <= input*Ca when '1',
64 (others=>'0') when others;
65
66 output <= s2+s3;
67
68 end simple_block; No newline at end of file
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1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 15:48:08 03/12/2015
6 -- Design Name:
7 -- Module Name: cic - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22 library IEEE_proposed;
23 use IEEE_proposed.fixed_pkg.all;
24 use work.cic_utils.all;
25
26
27 entity cic is
28 Port ( clk : in STD_LOGIC;
29 M1 : in integer(8 downto 0); -- factor de decimacion
30 M2 : in integer(8 downto 0);
31 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
32 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
33 end cic;
34
35
36 architecture Behavioral of cic is
37 -- componentes del cic
38 COMPONENT integrator
39 PORT(
40 clk : IN std_logic;
41 input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
42 output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
43 );
44 END COMPONENT;
45
46 COMPONENT comb
47 PORT(
48 clk : in std_logic;
49 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
50 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
51 );
52 END COMPONENT;
53
54 constant K: integer := 3;-- numero de etapas del filtro CIC
55 type conn is array (2*(K+1)-1 downto 0) of sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
56 signal connector : conn;
57 begin
58 cic_arc: for i in 0 to (K-1) generate
59 int: integrator port map(clk=>clk, input=>connector(i), output=>connector(i+1) );
60 cmb: comb port map(clk=>clk, input=>connector(i+K), output=>connector(i+K+1) );
61 end generate cic_arc;
62
63
64 end Behavioral;
65
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1
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.all;
4 use IEEE.numeric_std.all;
5
6 package cic_utils is
7 -- parametros de diseΓ±o del filtro CIC ----------------------------------------
8 constant MANTISSA_BITS : integer := 24;
9 constant NUMBER_BITS : integer := 32; -- incluye bit de signo
10 constant FIXWIDTH : integer := NUMBER_BITS + MANTISSA_BITS;
11 constant STAGES : integer := 5; -- orden del filtro CIC (numero de etapas)
12
13 -- no modificar ---------------------------------------------------------------
14 subtype fixpoint is std_logic_vector(FIXWIDTH-1 downto 0);
15 function "*"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector;
16 function "/"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector;
17 function "+"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector;
18 function "-"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector;
19 function to_fix(a: integer) return std_logic_vector;
20 constant MAX_M2_DEC : integer := 19;
21 constant ONE: integer := 2**MANTISSA_BITS;
22
23 end cic_utils;
24
25
26
27
28 package body cic_utils is
29 -- operaciones aritmeticas de punto fijo
30 function "*" ( a: std_logic_vector ; b: std_logic_vector)
31 return std_logic_vector is
32 variable ret : std_logic_vector(2*FIXWIDTH-1 downto 0);
33 begin
34 ret := std_logic_vector(signed(a)*signed(b));
35 return ret(a'length+MANTISSA_BITS-1 downto MANTISSA_BITS);
36 end "*";
37
38
39 function "/" (a: std_logic_vector ; b: std_logic_vector)
40 return std_logic_vector is
41 variable ret : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0);
42 variable tmp : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0):=(others=>'0');
43 begin
44 for i in 0 to a'length-1 loop
45 tmp(i+MANTISSA_BITS ) := a(i);
46 end loop;
47 ret := std_logic_vector(signed(tmp)/signed(b));
48 return ret(a'length-1 downto 0);
49 end "/";
50
51
52 function "+" (a: std_logic_vector ; b: std_logic_vector)
53 return std_logic_vector is
54 variable ret : std_logic_vector(a'length-1 downto 0);
55 begin
56 ret := std_logic_vector(signed(a)+signed(b));
57 return ret;
58 end "+";
59
60
61 function "-" (a: std_logic_vector ; b: std_logic_vector)
62 return std_logic_vector is
63 variable ret : std_logic_vector(a'length-1 downto 0);
64 begin
65 ret := std_logic_vector(signed(a)-signed(b));
66 return ret;
67 end "-";
68
69 --
70
71 function to_fix(a: integer)
72 return std_logic_vector is
73 variable ret : std_logic_vector(FIXWIDTH-1 downto 0);
74 begin
75 ret := std_logic_vector(to_signed(a,FIXWIDTH));
76 return ret;
77 end to_fix;
78
79 end cic_utils;
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1 ----------------------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5 use work.cic_utils.all;
6
7
8
9 entity clk_div is
10 Port ( clkin : in STD_LOGIC;
11 clkout: out STD_LOGIC;
12 reset : in std_logic;
13 N : in integer range 0 to 19);
14 end clk_div;
15
16
17 architecture Behavioral of clk_div is
18 signal clktmp: STD_LOGIC := '0';
19 signal cnt1: integer range 0 to 19 := 0;
20 begin
21 process(clkin,reset)
22 begin
23 if reset = '1' then
24 cnt1 <= 0;
25 clktmp <= '0';
26 elsif clkin'event and clkin = '1' then
27 if cnt1 < N then
28 if cnt1 >= N/2 then
29 clktmp <= '0';
30 end if;
31 cnt1 <= cnt1 +1;
32 else
33 clktmp <= '1';
34 cnt1 <= 0;
35 end if;
36 end if;
37 end process;
38
39 clkout <= clktmp;
40 end Behavioral;
41
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1 NO CONTENT: new file 10644
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1 ----------------------------------------------------------------------------------
2 -- Company: company
3 -- Engineer: shinobi
4 --
5 -- Create Date: Mar 9, 2015 - 5:10:57 PM
6 -- Design Name: modulename
7 -- Module Name: comb
8 -- Project Name: projectname
9 -- Description:
10 --
11 --
12 --
13 ----------------------------------------------------------------------------------
14 library IEEE;
15 use IEEE.std_logic_1164.all;
16 use IEEE.numeric_std.all;
17 library IEEE_proposed;
18 use IEEE_proposed.fixed_pkg.all;
19
20 use work.cic_utils.all;
21
22 -- entity declaration --------------------------------
23 entity comb is
24 port (
25 clk : in std_logic;
26 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
27 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
28 );
29 end entity comb;
30
31
32 -- architecture declaration------------------------
33 architecture simple of comb is
34 signal s_in_1 : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
35 signal s_in : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
36 begin
37 process(clk)
38 begin
39 if clk'event and clk = '1' then
40 s_in_1 <= s_in;
41 end if;
42 end process;
43 output <= sust(input ,s_in_1);
44 s_in <= input;
45
46
47 end architecture simple;
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1 ----------------------------------------------------------------------------------
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.numeric_std.all;
5 library IEEE_proposed;
6 use IEEE_proposed.fixed_pkg.all;
7 use work.cic_utils.all;
8
9
10
11 entity decimator is
12 Port ( clkin : in STD_LOGIC;
13 clkout: out STD_LOGIC;
14 reset : in std_logic;
15 N : in integer range 0 to 19;
16 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
17 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS));
18 end decimator;
19
20
21 architecture Behavioral of decimator is
22 signal clktmp: STD_LOGIC := '0';
23 signal cnt1: integer range 0 to 19 := 0;
24 signal tmp: sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
25 begin
26
27
28 process(clkin,reset)
29 begin
30 if reset = '1' then
31 cnt1 <= 0;
32 clktmp <= '0';
33 elsif clkin'event and clkin = '1' then
34 if cnt1 < N then
35 if cnt1 >= N/2 then
36 clktmp <= '0';
37 end if;
38 cnt1 <= cnt1 +1;
39 else
40 clktmp <= '1';
41 cnt1 <= 0;
42 tmp <= input;
43 end if;
44 end if;
45 end process;
46
47
48 clkout <= clktmp;
49 output <= tmp;
50
51 end Behavioral;
52
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1 ----------------------------------------------------------------------------------
2 -- Company: company
3 -- Engineer: shinobi
4 --
5 -- Create Date: Mar 9, 2015 - 5:10:57 PM
6 -- Design Name: modulename
7 -- Module Name: integrator
8 -- Project Name: projectname
9 -- Description:
10 --
11 --
12 --
13 ----------------------------------------------------------------------------------
14 library IEEE;
15 use IEEE.std_logic_1164.all;
16 use IEEE.numeric_std.all;
17
18 use work.cic_utils.all;
19
20 -- entity declaration --------------------------------
21 entity integrator is
22 port (
23 clk : in std_logic;
24 input : in std_logic_vector(FIXWIDTH-1 downto 0);
25 output : out std_logic_vector(FIXWIDTH-1 downto 0)
26 );
27 end entity integrator;
28
29
30 -- architecture declaration------------------------
31 architecture simple of integrator is
32
33 signal s_out : std_logic_vector(FIXWIDTH-1 downto 0);
34 signal s_out_1: std_logic_vector(FIXWIDTH-1 downto 0);
35
36 begin
37 process(clk)
38 begin
39 if clk'event and clk = '1' then
40 s_out_1 <= s_out;
41 end if;
42 end process;
43 output <= s_out;
44 s_out <= input+s_out_1;
45
46
47 end architecture simple;
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1 -- test_comb Template
2
3 LIBRARY ieee;
4 USE ieee.std_logic_1164.ALL;
5 USE ieee.numeric_std.ALL;
6 library IEEE_proposed;
7 use IEEE_proposed.fixed_pkg.all;
8
9 use work.cic_utils.all;
10
11
12 ENTITY test_comb IS
13 END test_comb;
14
15 ARCHITECTURE behavior OF test_comb IS
16
17 -- Component Declaration
18 COMPONENT comb
19 PORT(
20 clk : in std_logic;
21 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
22 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
23 );
24 END COMPONENT;
25
26 --Inputs
27 signal clk : std_logic := '0';
28 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
29
30 --Outputs
31 signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
32
33 -- Clock period definitions
34 constant clk_period : time := 1 ms;
35 BEGIN
36
37 -- Instantiate the Unit Under Test (UUT)
38 uut: comb PORT MAP(
39 clk => clk,
40 input => input,
41 output => output
42 );
43
44 -- Clock process definitions
45 clk_process :process
46 begin
47 clk <= '1';
48 wait for clk_period/2;
49 clk <= '0';
50 wait for clk_period/2;
51 end process;
52
53 -- Stimulus process
54 stim_proc: process
55 begin
56 -- hold reset state for 1 ms.
57 wait for 1 ms;
58 input <= to_sfixed(1,input);
59 wait for clk_period;
60 input <= to_sfixed(2,input);
61 wait for clk_period;
62 input <= to_sfixed(3,input);
63 wait for clk_period;
64 input <= to_sfixed(5,input);
65 wait for clk_period;
66 input <= to_sfixed(8,input);
67 wait for clk_period;
68 input <= to_sfixed(13,input);
69 wait for clk_period;
70 input <= to_sfixed(21,input);
71 wait for clk_period;
72 input <= to_sfixed(34,input);
73 wait for clk_period;
74 input <= to_sfixed(55,input);
75 wait for clk_period;
76 input <= to_sfixed(89,input);
77 wait;
78 end process;
79
80
81 END;
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1 --------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:55:16 03/12/2015
6 -- Design Name:
7 -- Module Name: /home/shinobi/workspaces/roj/trunk/firmware/sources/processingEngine/cic/tb_int.vhd
8 -- Project Name: cic
9 -- Target Device:
10 -- Tool versions:
11 -- Description:
12 --
13 -- VHDL Test Bench Created by ISE for module: integrator
14 --
15 -- Dependencies:
16 --
17 -- Revision:
18 -- Revision 0.01 - File Created
19 -- Additional Comments:
20 --
21 -- Notes:
22 -- This testbench has been automatically generated using types std_logic and
23 -- std_logic_vector for the ports of the unit under test. Xilinx recommends
24 -- that these types always be used for the top-level I/O of a design in order
25 -- to guarantee that the testbench will bind correctly to the post-implementation
26 -- simulation model.
27 --------------------------------------------------------------------------------
28 LIBRARY ieee;
29 USE ieee.std_logic_1164.ALL;
30 USE ieee.numeric_std.ALL;
31 library IEEE_proposed;
32 use IEEE_proposed.fixed_pkg.all;
33
34 use work.fix_arith.all;
35 -- Uncomment the following library declaration if using
36 -- arithmetic functions with Signed or Unsigned values
37 --USE ieee.numeric_std.ALL;
38
39 ENTITY tb_int IS
40 END tb_int;
41
42 ARCHITECTURE behavior OF tb_int IS
43
44 -- Component Declaration for the Unit Under Test (UUT)
45
46 COMPONENT integrator
47 PORT(
48 clk : IN std_logic;
49 input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
50 output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
51 );
52 END COMPONENT;
53
54
55 --Inputs
56 signal clk : std_logic := '0';
57 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
58
59 --Outputs
60 signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
61
62 -- Clock period definitions
63 constant clk_period : time := 1 ms;
64
65 BEGIN
66
67 -- Instantiate the Unit Under Test (UUT)
68 uut: integrator PORT MAP (
69 clk => clk,
70 input => input,
71 output => output
72 );
73
74 -- Clock process definitions
75 clk_process :process
76 begin
77 clk <= '1';
78 wait for clk_period/2;
79 clk <= '0';
80 wait for clk_period/2;
81 end process;
82
83
84 -- Stimulus process
85 stim_proc: process
86 begin
87 -- hold reset state for 100 ns.
88 wait for 1 ms;
89 input <= to_sfixed(1,input);
90 wait for clk_period;
91 input <= to_sfixed(1,input);
92 wait for clk_period;
93 input <= to_sfixed(1,input);
94 wait for clk_period;
95 input <= to_sfixed(1,input);
96 wait for clk_period;
97 input <= to_sfixed(1,input);
98 wait for clk_period;
99 input <= to_sfixed(1,input);
100 wait for clk_period;
101 input <= to_sfixed(1,input);
102 wait for clk_period;
103 input <= to_sfixed(1,input);
104 wait for clk_period;
105 input <= to_sfixed(1,input);
106 wait for clk_period;
107 input <= to_sfixed(1,input);
108 wait;
109 end process;
110
111 END;
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1 -- test_comb Template
2
3 LIBRARY ieee;
4 USE ieee.std_logic_1164.ALL;
5 USE ieee.numeric_std.ALL;
6 library IEEE_proposed;
7 use IEEE_proposed.fixed_pkg.all;
8 use work.cic_utils.all;
9
10
11 ENTITY test_decim IS
12 END test_decim;
13
14 ARCHITECTURE behavior OF test_decim IS
15
16 -- Component Declaration
17 COMPONENT decimator
18 Port ( clkin : in STD_LOGIC;
19 clkout: out STD_LOGIC;
20 reset : in std_logic;
21 N : in integer range 0 to 19;
22 input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
23 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS));
24 END COMPONENT;
25
26 --Inputs
27 signal clkin : std_logic := '0';
28 signal reset : std_logic := '0';
29 signal N : integer range 0 to 19:= 11;
30 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
31
32 --Outputs
33 signal clkout : std_logic := '0';
34 signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
35
36 -- Clock period definitions
37 constant clk_period : time := 1 ms;
38 BEGIN
39
40 -- Instantiate the Unit Under Test (UUT)
41 uut: decimator PORT MAP(
42 clkin => clkin,
43 clkout => clkout,
44 reset => reset,
45 N => N,
46 input => input,
47 output => output
48 );
49
50 -- Clock process definitions
51 clk_process :process
52 begin
53 clkin <= '1';
54 wait for clk_period/2;
55 clkin <= '0';
56 wait for clk_period/2;
57 end process;
58
59 -- Stimulus process
60 stim_proc: process
61 begin
62 -- hold reset state for 1 ms.
63 wait for clk_period;
64 input <= to_sfixed(1,input);
65 wait for clk_period;
66 input <= to_sfixed(2,input);
67 wait for clk_period;
68 input <= to_sfixed(3,input);
69 wait for clk_period;
70 input <= to_sfixed(4,input);
71 wait for clk_period;
72 input <= to_sfixed(5,input);
73 wait for clk_period;
74 input <= to_sfixed(6,input);
75 wait for clk_period;
76 input <= to_sfixed(7,input);
77 wait for clk_period;
78 input <= to_sfixed(8,input);
79 wait for clk_period;
80 input <= to_sfixed(9,input);
81 wait for clk_period;
82 input <= to_sfixed(10,input);
83 wait for clk_period;
84 input <= to_sfixed(11,input);
85 wait for clk_period;
86 input <= to_sfixed(12,input);
87 wait for clk_period;
88 input <= to_sfixed(13,input);
89 wait for clk_period;
90 input <= to_sfixed(14,input);
91 wait for clk_period;
92 input <= to_sfixed(15,input);
93 wait for clk_period;
94 input <= to_sfixed(16,input);
95 wait for clk_period;
96 input <= to_sfixed(17,input);
97 wait for clk_period;
98 input <= to_sfixed(18,input);
99 wait for clk_period;
100 input <= to_sfixed(19,input);
101 wait for clk_period;
102 input <= to_sfixed(20,input);
103 end process;
104
105
106 END;
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1 -- test_hr Template
2
3 LIBRARY ieee;
4 USE ieee.std_logic_1164.ALL;
5 USE ieee.numeric_std.ALL;
6 library IEEE_proposed;
7 use IEEE_proposed.fixed_pkg.all;
8 use work.cic_utils.all;
9
10
11 ENTITY test_hr IS
12 END test_hr;
13
14 ARCHITECTURE behavior OF test_hr IS
15
16 -- Component Declaration
17 COMPONENT Hr_block
18 Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
19 output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
20 Cb : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
21 Ca : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
22 acum : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
23 clk : in std_logic;
24 last : in std_logic);
25 END COMPONENT;
26
27 signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
28 signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
29 signal Cb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
30 signal Ca : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
31 signal acum : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
32 signal clk : std_logic;
33 signal last : std_logic;
34
35 -- Clock period definitions
36 constant clk_period : time := 1 ms;
37
38 BEGIN
39
40 -- Component Instantiation
41 uut: Hr_block PORT MAP(
42 input => input,
43 output => output,
44 Cb => Cb,
45 Ca => Ca,
46 acum => acum,
47 clk => clk,
48 last => last
49 );
50
51 Cb <= to_sfixed(2,Cb);
52 Ca <= to_sfixed(3,Ca);
53 acum <= to_sfixed(10,Ca);
54
55
56 -- Clock process definitions
57 clk_process :process
58 begin
59 clk <= '1';
60 wait for clk_period/2;
61 clk <= '0';
62 wait for clk_period/2;
63 end process;
64
65
66 -- Test Bench Statements
67 tb : PROCESS
68 BEGIN
69
70 -- hold reset state for 1 ms.
71 last <= '1';
72 input <= to_sfixed(100,input);
73 wait for clk_period;
74 last <= '0';
75 input <= to_sfixed(100,input);
76 wait for clk_period;
77
78 wait;
79 END PROCESS tb;
80 -- End Test Bench
81
82 END;
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