# SVN changeset patch # User lgonzales # Date 2016-01-05 16:49:48.322647 # Revision 221 Index: trunk/firmware/sources/acquisitiond/.cproject =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/.cproject b/trunk/firmware/sources/acquisitiond/.cproject deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/.cproject (revision 220) +++ /dev/null (revision 221) @@ -1,74 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Index: trunk/firmware/sources/acquisitiond/.project =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/.project b/trunk/firmware/sources/acquisitiond/.project deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/.project (revision 220) +++ /dev/null (revision 221) @@ -1,28 +0,0 @@ - - - acquisitiond - - - - - - org.eclipse.cdt.managedbuilder.core.genmakebuilder - clean,full,incremental, - - - - - org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder - full,incremental, - - - - - - org.eclipse.cdt.core.cnature - org.eclipse.cdt.core.ccnature - org.eclipse.cdt.managedbuilder.core.managedBuildNature - org.eclipse.cdt.managedbuilder.core.ScannerConfigNature - de.innot.avreclipse.core.avrnature - - Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/.cproject =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/.cproject b/trunk/firmware/sources/acquisitiond/Primera_Etapa/.cproject new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/.cproject (revision 221) @@ -0,0 +1,74 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/.project =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/.project b/trunk/firmware/sources/acquisitiond/Primera_Etapa/.project new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/.project (revision 221) @@ -0,0 +1,28 @@ + + + acquisitiond + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.core.ccnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + de.innot.avreclipse.core.avrnature + + Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.c b/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.c (revision 221) @@ -0,0 +1,261 @@ +/* + * acquisitiond.c + * + * Created on: Mar 24, 2015 + * Author: shinobi + */ + +#include "acquisitiond.h" +#include "fpgaport.h" + +volatile uint8_t is_acquiring = 0; +volatile uint8_t send_flg = 0; + +// Comandos para el ADC +#define CMD_ACTV 0 +#define CMD_DACTV 1 +#define CMD_RATE 2 +#define CMD_RPARAM 3 +#define CMD_WPARAM 4 +#define CMD_START 5 +#define CMD_STOP 6 +#define CMD_INFO 7 +#define CMD_GAIN 8 +#define CMD_ID 9 +#define CMD_STATUS 10 +#define CMD_PPS 11 + + +/*! + * \fn acq_chn_activate + * \breif activa la comunicacion con el IC ADC + * \see acq_chn_deactivate + */ +void acq_chn_activate(){ + adcport_open(); +} + + +/*! + * \fn acq_chn_deactivate + * \breif desactiva la comunicacion con el IC ADC + * \see acq_chn_activate + */ +void acq_chn_deactivate(){ + adcport_close(); +} + + +/*! + * \fn acq_chn_datarate + * \breif Configura el datarate del ADC + * \param datarate El datarate deseado + */ +void acq_chn_datarate(uint16_t datarate){ + if(is_acquiring==1){ + acq_stop_acquisiton(); + } + acq_set_param_to_adc(CMD_RATE,datarate); +} + + +/*! + * \fn acq_send_information + * \breif Envia informacion relevante al Embebido (a traves de FPGA) + */ +void acq_send_information(){ + if(is_acquiring==1){ + acq_stop_acquisiton(); + } + acq_send_param(CMD_RATE); + acq_send_param(CMD_GAIN); + acq_send_param(CMD_ID); + acq_send_param(CMD_STATUS); + acq_send_param(CMD_PPS); +} + + +/*! + * \fn acq_chn_datarate + * \breif Envia parametros al embebido a traves del FPGA (este se debe encargar + * de hacer el puente al embebido) + * \param param El parametro que se quiere enviar al embebido + */ +void acq_send_param(uint8_t param){ + uint8_t data; + fpgaport_open(); + fpgaport_write(param); + switch(param){ + case CMD_RATE: + // TODO secuencia de comandos para obtener el datarate del ADC + break; + case CMD_GAIN: + data=adcport_get_param(GAIN0); + break; + case CMD_ID: + data=adcport_get_param(ID); + break; + case CMD_STATUS: + data=adcport_get_param(STATUS); + break; + case CMD_PPS: + break;// TODO + default: + // con esta opcion se puede leer los registros del ADC definidos en + // "adcpot.h" y enviarlos al embebido + data= adcport_get_param(param); + break; + } + + fpgaport_write(data); + fpgaport_close(); +} + + +/*! + * \fn acq_send_buff + * \breif Envia el contenido de un buffer de datos hacia el + * FPGA para que sean pre-procesados. + */ +/* + * Esta funcion debe ser ejecutada con la señal de una interrupcion externa + * manejada por software, que le indicara que hay un buffer lleno listo + * para pre-procesar (vea adcport.c ). + */ +void acq_send_buff(){ + uint8_t i=0; + uint32_t* pbuff = adcport_getbuff(); + fpgaport_open(); + while(!(i==BUFF_SIZE)){ + fpgaport_write(pbuff[i]); + i++; + } + fpgaport_close(); +} + + +/*! + * \fn acq_chn_set_datarate + * \breif configura edl datarate del ADC + * \param datarate + */ +void acq_chn_set_datarate(uint8_t datarate){ + // TODO secuencia de comandos para configurar el data rate +} + + +/*! + * \fn acq_process_cmd + * \breif Procesa todos los comandos enviados desde el FPGA. + * \param cmd Comando a procesar. + */ +/* + * Esta funcion debe ejecutarse al haber una interrupcion en el puerto que + * conecta al FPGA + */ +void acq_process_cmd(uint8_t cmd){ + static uint8_t param; + static uint8_t data; + cli();// desactiva interrupciones + fpgaport_open(); + switch(cmd){ + case CMD_ACTV: acq_chn_activate(); + break; + case CMD_DACTV:acq_chn_deactivate(); + break; + case CMD_RATE: + param=fpgaport_read(); + acq_chn_set_datarate(param); + break; + case CMD_RPARAM: + param=fpgaport_read(); + acq_send_param(param); + break; + case CMD_WPARAM: + cmd=fpgaport_read();//lee + data=fpgaport_read();//lee valor + acq_set_param_to_adc(cmd,data); + break; + case CMD_START: + acq_start_acquisition(); + break; + case CMD_STOP: + acq_stop_acquisition(); + break; + case CMD_INFO: + acq_send_information(); + break; + default: break; + } + fpgaport_close(); + sei();//acvtiva interrupciones +} + + +/*! + * \fn acq_set_param + * \breif Procesa todos los comandos enviados desde el FPGA. + * \param param Parametro a configurar. + * \param value Valor del parametro + */ +void acq_set_param(uint8_t param, uint8_t value){ + adcport_tranceiv(param); + adcport_tranceiv(value); +} + + +/*! + * \fn acq_start_acquisition + * \breif Inicia la adquisicion de datos, esta se hara a traves de interrupciones + * "software" (ver adcport.c) + */ +void acq_start_acquisition(){ + is_acquiring = 1; + adcport_start(); +} + +/*! + * \fn acq_stop_acquisition + * \breif Para la adquisicion de datos. Las interrupciones utilizadas para + * este fin son desactivadas. + */ +void acq_stop_acquisition(){ + is_acquiring=0; + adcport_stop(); +} + + +/* + * interrupcion en algun pin que no se este usdando. + * Interrupcion software. No puede ser PORTC_INT0_vect + * Se usara para le indiquen que ya hay un buffer lleno + * (ver adcport.c) + */ +ISR(PORTx_INTx_vect){ // FIXME + send_flg=1; +} + + + +/* + * interrupcion en algun pin que no se este usdando. + * Interrupcion software. No puede ser PORTC_INT0_vect + * Se usara para le indiquen que ya hay un buffer lleno + * (ver adcport.c) + */ +ISR(PORTx_INTx_vect){ // FIXME + send_flg=1; +} + +/*! + * \brief Espera que un buffer este lleno para enviarlo al fpga + */ +int main(){ + do{ + if(send_flg==1){ + send_flg=0; + acq_send_buff(); + } + }while(1); + return 0; +} Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.h b/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/acquisitiond.h (revision 221) @@ -0,0 +1,35 @@ +/* + * acquisitiond.h + * + * Created on: Mar 24, 2015 + * Author: shinobi + */ + +#ifndef ACQUISITIOND_H_ +#define ACQUISITIOND_H_ + +#include +#include +#include "adcport.h" + +void acq_chn_activate(); +void acq_chn_deactivate(); +void acq_chn_datarate(uint16_t datarate); + + +void acq_send_information(); +void acq_send_param(uint8_t param); +void acq_send_buff(); + + +void acq_process_cmd(uint8_t cmd); + +void acq_set_param_to_adc(uint8_t cmd, uint8_t data); + + +void acq_start_acquisition(); +void acq_stop_acquisition(); + + + +#endif /* ACQUISITIOND_H_ */ Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.c b/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.c (revision 221) @@ -0,0 +1,266 @@ +/* + * adcport.c + * + * Created on: Mar 25, 2015 + * Author: shinobi + */ + +#include "adcport.h" +#include +#include + + +#define SPI_SS_bm PIN4_bm /*!< \brief Bit mask para el pin SS. */ +#define SPI_MOSI_bm PIN5_bm /*!< \brief Bit mask para el pin MOSI. */ +#define SPI_MISO_bm PIN6_bm /*!< \brief Bit mask para el pin MISO. */ +#define SPI_SCK_bm PIN7_bm /*!< \brief Bit mask para el pin SCK. */ + + +#define SS_OFF PORTC.OUTSET=PIN4_bm;/*!< \brief Deselecciona el ADC (puerto SPI) */ +#define SS_ON PORTC.OUTCLR=PIN4_bm;/*!< \brief Selecciona el ADC (puerto SPI) */ + + +/* + * Al iniciar la adquisicion se debe activar la interrupcion del pin RDY a + * traves del PINC6 del XMEGA. + * Luego al leer los datos digitalizados, se debe desactivar. Al terminar + * se reactiva para esperar la siguiente interrupcion. + * Esto se debe a que el DOUT y el RDY del ADC comparten el pin. Si se dejara + * activa la interrupcion al leer, se generarian interrupciones e los flancos + * de bajada generados por la transferencia de las muestras + */ +#define WAIT_DATA PORTC.INT0MASK=PIN6_bm/*!< \brief Activa interrupcion que indica dato nuevo */ +#define GET_DATA PORTC.INT0MASK=0/*!< \brief Desactiva iterrupcion que indica dato nuevo */ + + +volatile uint8_t buff_idx; +uint32_t * pfull_buff; +uint32_t * pread_buff; +volatile uint8_t buff_full_flg = 0; + +/*! + * \fn adcport_ready_interrupt_config + * \brief configura el pin de MISO (conectado a DOUT del ADC), para que dispare + * una interrupcion por flanco de bajada. + * una vez disparada la interrupcion, se puede leer el pin; sin embargo, debe + * desactivarse antes de leer la interrupcion por flanco (con GET_DATA). De lo + * contrario se disparara la interrupcion varias veces al leer los datos, ya + * que ese el pin RDY y DOUT es el mismo en el ADC. + */ +inline void adcport_ready_interrupt_config(){ + // pin6: MISO(xmega) --> DOUT/RDY(ADC) => pin6 entrada + PORTC.DIRCLR=PIN6_bm; + // El ADC llevara a "low" RDY cuando la conversion de un dato haya concluido + // Se debe leer el dato generado luego. Se espera una interrupcion de flanco + // de bajada para manejar esto + PORTC.PIN6CTRL=PORT_ISC_FALLING_gc; + // Se mapea la interrupcion externa INT0 de PORTC a PINC6 + PORTC.INT0MASK=PIN6_bm; + // Debido a que esta interrupcion va a manejar la adquisicion de datos, se + // le da maxima prioridad (nivel alto) + PORTC.INTCTRL=PORT_INT0LVL_HI_gc; + // Se habilita la atencion de interrupciones de nivel alto + PMIC.CTRL|= PMIC_HILVLEN_bm; +} + + +/*! + * \fn adcport_spi_config + * \brief configura el puerto SPI para que coincida con el requerimiento del ADC + * AD7178-2 + */ +inline void adcport_spi_config(){ + PORTC.DIRSET = SPI_MOSI_bm | SPI_SCK_bm | SPI_SS_bm; + // Preescaler: clkper/2 (con clk2x). Maestro. CPOL=1,CPHA=1 + // MSB primero + SPIC.CTRL = SPI_CLK2X_bm|SPI_ENABLE_bm|SPI_MASTER_bm| + SPI_MODE1_bm|SPI_MODE0_bm; +} + + +/*! + * \fn adcport_config + * \brief Configura el microcontrolador para darle servicio a la interrupcion + * del pin "RDY" del ADC, que reacciona con un flanco de bajada cuando se ha + * terminado de digitalar una muestra nueva. + * Tambien configura el puerto SPI que servira para comunicarse con el ADC. + * \see adcport_ready_interrupt_config + * \see adcport_spi_config + */ +inline void adcport_config(){ + adcport_ready_interrupt_config(); + adcport_spi_config(); + // TODO configurar ADC: datarate, ganancia, desactivar CRC, formato numerico + // de muestras debe ser "bipolar offset binary"(canales diferenciales). +} + + +/*! + * \fn adcport_open + * \brief Inicializa el buffer de entrada (para datos de 24bits del ADC) y + * activa la comunicacion a traves del pin "SS" del puerto SPI. + * \see adcport_close + */ +inline void adcport_open(){ + buff_idx=0; + // TODO configurar interrupcion externa PPS (pin 6) + // TODO configurar interrupcion externa LOCK (pin 21) + pfull_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); + pread_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); + adcport_config(); + SS_ON; +} + + +/*! + * \fn adcport_close + * \brief Desactiva la comunicacion con el ADC a traves del pin "SS" del puerto + * SPI. + * \see adcport_open + */ +inline void adcport_close(){ + SS_OFF; + free(pfull_buff); + free(pread_buff); +} + + +/*! + * \fn adcport_start + * \brief Inicia la digitalizacion de muestras del sensor. + * SPI. + * \see adcport_stop + * \see adcport_open + * \see adcport_close + */ +inline void adcport_start(){ + // necesario para darle servicio con interrupciones al flanco de bajada + // del pin "RDY" + WAIT_DATA; + // TODO enviar comandos al ADC para que inicie la adquisicion. +} + + +/*! + * \fn adcport_stop + * \brief Pausa la digitalizacion de muestras del sensor. + * SPI. + * \see adcport_start + * \see adcport_open + * \see adcport_close + */ +inline void adcport_stop(){ + // TODO enviar comandos al ADC para que deje de adquirir. + // necesario para cortar el servicio interrupcion del pin "RDY" + GET_DATA; +} + + +/*! + * \fn adcport_tranceiv + * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + + //Wait until transmission complete + while(!(SPIC.STATUS)&SPI_IF_bm); + + // Return received data + return SPIC.DATA; +} + + +/*! + * \fn adcport_start + * \brief Inicia la digitalizacion de muestras del sensor. + * SPI. + * \see adcport_open + */ +void adcport_read_sample(){ + uint32_t aux; + GET_DATA; // desactiva interrupciones de flaco de bajada + // Se le indica al adc que se va a leer el registro de data. + adcport_tranceiv(0x44); + // El byte mas significativo de la variable de 32bits es cero + // La codificacion de los numeros es "bipolar offset binary" y + // la transmision es MSB first + aux = adcport_tranceiv(0); + aux = (aux<<8)|adcport_tranceiv(0); + aux = (aux<<8)|adcport_tranceiv(0); + aux = (aux<<8)|adcport_tranceiv(0); + pread_buff[buff_idx]=aux; + + WAIT_DATA; // reactiva interrupciones de flanco de bajada +} + + +/*! + * \fn adcport_getbuff + * \brief Devuelve la direccion del buffer lleno + * \return Direccion del buffer lleno. 0 si no esta lleno aun + */ +inline uint32_t* adcport_getbuff(){ + if(buff_full_flg==1){ + buff_full_flg=0; + return pfull_buff; + } + return 0; +} + + +uint8_t adcport_get_param(uint8_t data){ + adcport_tranceiv(data); + return adcport_tranceiv(0); +} + + +/*! + * \brief interrupcion externa debe dispararse en flanco de bajada en PC6 (RDY del ADC). + * Cuando el ADC lleva este pin a "low", se debe leer el dato nuevo + */ +ISR(PORTC_INT0_vect){ + adcport_read_sample(); + buff_idx++; + if(buff_idx>=100){ + uint32_t* paux = pread_buff; + pread_buff = pfull_buff; + pfull_buff = paux; + buff_full_flg=1; + // TODO dar aviso al programa principal que el buffer esta lleno. + // Puede ser a traves de una interrupcion "externa" en un pin que no se + // use, para lo cual debe estar configurado como salida y para recibir + // interrupciones de IO. + // para hacer que funcione como una interrupcion software, solo escribir + // en ese pin un valor segun se configure la interrupcion + } +} + + +/* TODO + * interrupcion del LOCK del GNSS (pin numero 21 del xmega) + * servira para indicar que el GNSS esta sincronizado con satelites y la hora y + * PPS son correctos, a partir de ese momento se pueden contar los PPS y + * identificarlos en el header. + */ +ISR(PORTx_INTx_vect){ // FIXME + +} + + +/* TODO + * interrupcion del PPS del GNSS (pin numero 6 del xmega) + * servira para sincronizar la hora. Debe agregar un numero de serie entre 0 y 255 + * a la cabecera del buffer que indentifique al PPS; y el numero de muestra que se adquirio + * en el momento de la llegada de esta interrupcion. + */ +ISR(PORTx_INTx_vect){ // FIXME + +} + Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.h b/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/adcport.h (revision 221) @@ -0,0 +1,60 @@ +/* + * adcport.h + * + * Created on: Mar 25, 2015 + * Author: shinobi + */ + +#ifndef ADCPORT_H_ +#define ADCPORT_H_ + +#include + +#define BUFF_SIZE 100 + +/* Direcciones de registros del ADC */ + +#define COMMS 0x00 +#define STATUS 0x00 +#define ADCMODE 0x01 +#define IFMODE 0x02 +#define REGCHECK 0x03 +#define DATA 0X04 +#define GPIOCON 0x06 +#define ID 0x07 + +#define CHMAP0 0x10 +#define CHMAP1 0x11 +#define CHMAP2 0x12 +#define CHMAP3 0x13 + +#define SETUPCON0 0x20 +#define SETUPCON1 0x21 +#define SETUPCON2 0x22 +#define SETUPCON3 0x23 + +#define FILTCON0 0x28 +#define FILTCON1 0x29 +#define FILTCON2 0x2A +#define FILTCON3 0x2B + +#define OFFSET0 0x30 +#define OFFSET1 0x31 +#define OFFSET2 0x32 +#define OFFSET3 0x33 + +#define GAIN0 0x38 +#define GAIN1 0x39 +#define GAIN2 0x2A +#define GAIN3 0x2B + + +void adcport_open(); +void adcport_close(); +void adcport_start(); +void adcport_stop(); +uint32_t* adcport_getbuff(); +uint8_t adcport_tranceiv(uint8_t data); +uint8_t adcport_get_param(uint8_t data); + +#endif /* ADCPORT_H_ */ Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.c b/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.c (revision 221) @@ -0,0 +1,57 @@ +/* + * fpgaport.c + * + * Created on: Mar 26, 2015 + * Author: shinobi + */ + + +/*! + * \fn fpgaport_open + * \brief actima la comunicacion con el FPGA + */ +inline void fpgaport_open(){ + // TODO configurar puerto pfga e interrupcion externa (pin 22) + // TODO configurar interrupcion externa PPS (pin 6) + // TODO configurar interrupcion externa LOCK (pin 21) +} + + +/*! + * \fn fpgaport_close + * \brief Desactiva la comunicacion con el FPGA + */ +inline void fpgaport_close(){ + // TODO configurar puerto pfga e interrupcion externa (pin 22) para + // clock +} + + +/*! + * \fn fpgaport_write + * \breif activa la comunicacion con el IC ADC + * \see acq_chn_deactivate + */ +inline void fpgaport_write(uint8_t data){ + // TODO +} + + +/*! + * \fn fpgaport_read + * \breif activa la comunicacion con el IC ADC + * \see acq_chn_deactivate + */ +inline uint8_t fpgaport_read(){ + // TODO +} + + +/* + * Interrupcion de dato entrante por el puerto FPGA. El pin debe ser alguno de los + * que estan conectatos al FPGA (el bus) + */ +ISR(PORTx_INTx_vect){ + // TODO debe idicar que se ejecute la funcion que procesa los comandos + // que bienen del FPGA +} Index: trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.h b/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Primera_Etapa/fpgaport.h (revision 221) @@ -0,0 +1,19 @@ +/* + * fpgaport.h + * + * Created on: Mar 26, 2015 + * Author: shinobi + */ + +#ifndef FPGAPORT_H_ +#define FPGAPORT_H_ + +#include + +void fpgaport_open(); +void fpgaport_close(); +void fpgaport_write(uint8_t data); +uint8_t fpgaport_read(); + + +#endif /* FPGAPORT_H_ */ =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/.vs/ADCSPI_ver01/v14/.atsuo =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/.vs/ADCSPI_ver01/v14/.atsuo b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/.vs/ADCSPI_ver01/v14/.atsuo new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/.vs/ADCSPI_ver01/v14/.atsuo (revision 221) Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01.atsln =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01.atsln b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01.atsln new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01.atsln (revision 221) @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_ver01", "ADCSPI_ver01\ADCSPI_ver01.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.ActiveCfg = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.Build.0 = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.ActiveCfg = Release|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml (revision 221) @@ -0,0 +1,86 @@ + + + + + + + Device + Startup + + + Atmel + 1.0.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include + + include + C + + + include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include\avr\iox32d4.h + + header + C + Fb3v/Gsyx/fNhVPcSy4byA== + + include/avr/iox32d4.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.c + template + source + C Exe + 8XJjXFQBySw6iim2xAnW5g== + + templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.cpp + template + source + C Exe + YXFphlh0CtZJU+ebktABgQ== + + templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4 + + libraryPrefix + GCC + + + gcc/dev/atxmega32d4 + + + + + XMEGAD_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/Atmel.XMEGAD_DFP.pdsc + 1.0.29 + true + ATxmega32D4 + + + + Resolved + Fixed + true + + + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.cproj =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.cproj b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.cproj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADCSPI_ver01.cproj (revision 221) @@ -0,0 +1,161 @@ + + + + 2.0 + 7.0 + com.Atmel.AVRGCC8.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATxmega32D4 + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + ADCSPI_ver01 + ADCSPI_ver01 + ADCSPI_ver01 + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + + + + + + + + + + + + + + com.atmel.avrdbg.tool.simulator + + 0x1E9542 + + + + + + com.atmel.avrdbg.tool.simulator + + + Simulator + + + + + + + -mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + True + True + True + True + False + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + + + + + -mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + True + True + True + True + False + True + True + + + DEBUG + + + + + %24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\include + + + Optimize (-O1) + True + True + Default (-g2) + True + + + libm + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADC_7176_2.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADC_7176_2.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADC_7176_2.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/ADC_7176_2.c (revision 221) @@ -0,0 +1,103 @@ +/* + * ADC_7176_2.c + * + * Created: 23/11/15 14:01:02 + * Author: Francisco + */ + +/*! + * \fn test_adc + * \brief Lectura de ID del adc + * + * Lectura esperada: 0x0C94 + * + * Esta funci�n tiene como fin probar la comunicaci�n on el ADC + * +#define ADC_WENbar_bm (1<<7) +#define ADC_RWbar_bm (1<<6) +#define ADC_ADDR_READ_ID 0x07 + * \ +*/ + +#define F_CPU 32000000UL +#include +#include "ADC_7176_2.h" + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + return aux; +} + +inline void test_adc_2(uint8_t* dato){ + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_read_data(dato,ADC_DATASZ); + PORTSPI.OUTSET = SPI_SS_bm; +} +/*! + * \fn adcport_tranceiv + * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + + // Return received data + + return SPIC.DATA; +} + +/*! + * \fn adcport_readdata + * \brief Realiza la lectura de datos en modo de conversi�n continua + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param La direcci�n del puntero a dato + * \return Ninguno s�lo se llena el puntero al dato + */ +inline void adcport_read_data(uint8_t* dato,int j) +{ + + //Env�o del comando de lectura de datos 0x44 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i +#include "Ports.h" +#include "commSPI_ADC.h" + +//ID esperada +//tama�o 16 bits +//Valor 0x0C94 +#define ADC_ID 0x0C94 +#define ADC_RD 0x04 +#define ADC_FILTCON0 0x28 +#define ADC_INTERFMODE 0x02 +#define ADC_DATASZ 3 + +//Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n +#define ADC_WENbar_bm (1<<7) +#define ADC_RWbar_bm (1<<6) +#define ADC_ADDR_READ_ID (0x07) +#define ADC_FILT0_ORDER0_bp 5 +#define ADC_FILT0_ODR0_bp 0 +#define ADC_CONTREAD_bp 7 +#define ADC_WL16_bp 0 + +uint8_t adcport_tranceiv(uint8_t data); +void adcport_read_data(uint8_t* dato,int j); + +void adcport_write_filtcon0(void); +void adcport_write_interfmode(void); + +uint16_t test_adc(void); +void test_adc_2(uint8_t* dato); +void config_adc(void); + +#endif /* ADC_7176_2_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.eep =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.eep b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.eep new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.eep (revision 221) @@ -0,0 +1 @@ +:00000001FF =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.elf =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.elf b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.elf new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.elf (revision 221) Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.hex =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.hex b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.hex new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.hex (revision 221) @@ -0,0 +1,87 @@ +:100000000C94B6000C94C0000C94F1010C94C00048 +:100010000C94C0000C94C0000C94C0000C94C00060 +:100020000C94C0000C94C0000C94C0000C94C00050 +:100030000C94C0000C94C0000C94C0000C94C00040 +:100040000C94C0000C94C0000C94C0000C94C00030 +:100050000C94C0000C94C0000C94C0000C94C00020 +:100060000C94C0000C94C0000C94C0000C94C00010 +:100070000C94C0000C94C0000C94C0000C94C00000 +:100080000C94C0000C94C0000C94C0000C94D201DD +:100090000C94C0000C94C0000C94C0000C94C000E0 +:1000A0000C94C0000C94C0000C94C0000C94C000D0 +:1000B0000C94C0000C94C0000C94C0000C94C000C0 +:1000C0000C94C0000C94C0000C94C0000C94C000B0 +:1000D0000C94C0000C94C0000C94C0000C94C000A0 +:1000E0000C94C0000C94C0000C94C0000C94C00090 +:1000F0000C94C0000C94C0000C94C0000C94C00080 +:100100000C94AD010C94C0000C94C0000C94C00081 +:100110000C94C0000C94C0000C94C0000C94C0005F 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+:1005400090936000E0E5F0E08681168280818E7FE6 +:0E055000808324BF909353000895F894FFCF4A +:00000001FF Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.lss =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.lss b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.lss new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.lss (revision 221) @@ -0,0 +1,1012 @@ + +ADCSPI_ver01.elf: file format elf32-avr + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 0000055e 00000000 00000000 00000054 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .data 00000000 00802000 00802000 000005b2 2**0 + CONTENTS, ALLOC, LOAD, DATA + 2 .comment 00000030 00000000 00000000 000005b2 2**0 + CONTENTS, READONLY + 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 000005e4 2**2 + CONTENTS, READONLY + 4 .debug_aranges 00000138 00000000 00000000 00000624 2**0 + CONTENTS, READONLY, DEBUGGING + 5 .debug_info 000014b5 00000000 00000000 0000075c 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_abbrev 00000644 00000000 00000000 00001c11 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_line 00000827 00000000 00000000 00002255 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_frame 00000278 00000000 00000000 00002a7c 2**2 + CONTENTS, READONLY, DEBUGGING + 9 .debug_str 000007d6 00000000 00000000 00002cf4 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_loc 000003d0 00000000 00000000 000034ca 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_ranges 000000d8 00000000 00000000 0000389a 2**0 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00000000 <__vectors>: + 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end> + 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 8: 0c 94 f1 01 jmp 0x3e2 ; 0x3e2 <__vector_2> + c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 2c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 30: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 44: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 48: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 4c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 50: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 60: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 64: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 8c: 0c 94 d2 01 jmp 0x3a4 ; 0x3a4 <__vector_35> + 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 100: 0c 94 ad 01 jmp 0x35a ; 0x35a <__vector_64> + 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + +0000016c <__ctors_end>: + 16c: 11 24 eor r1, r1 + 16e: 1f be out 0x3f, r1 ; 63 + 170: cf ef ldi r28, 0xFF ; 255 + 172: cd bf out 0x3d, r28 ; 61 + 174: df e2 ldi r29, 0x2F ; 47 + 176: de bf out 0x3e, r29 ; 62 + 178: 0e 94 95 01 call 0x32a ; 0x32a
+ 17c: 0c 94 ad 02 jmp 0x55a ; 0x55a <_exit> + +00000180 <__bad_interrupt>: + 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> + +00000184 : +#include +#include "ADC_7176_2.h" + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + 184: 80 e1 ldi r24, 0x10 ; 16 + 186: 80 93 46 06 sts 0x0646, r24 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 18a: 87 e4 ldi r24, 0x47 ; 71 + 18c: 80 93 c3 08 sts 0x08C3, r24 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 190: e0 ec ldi r30, 0xC0 ; 192 + 192: f8 e0 ldi r31, 0x08 ; 8 + 194: 82 81 ldd r24, Z+2 ; 0x02 + 196: 88 23 and r24, r24 + 198: ec f7 brge .-6 ; 0x194 + + // Return received data + + return SPIC.DATA; + 19a: e0 ec ldi r30, 0xC0 ; 192 + 19c: f8 e0 ldi r31, 0x08 ; 8 + 19e: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1a0: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1a2: 82 81 ldd r24, Z+2 ; 0x02 + 1a4: 88 23 and r24, r24 + 1a6: ec f7 brge .-6 ; 0x1a2 + + // Return received data + + return SPIC.DATA; + 1a8: e0 ec ldi r30, 0xC0 ; 192 + 1aa: f8 e0 ldi r31, 0x08 ; 8 + 1ac: 23 81 ldd r18, Z+3 ; 0x03 + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + 1ae: 30 e0 ldi r19, 0x00 ; 0 + aux = (aux << 8) | adcport_tranceiv(0); + 1b0: 32 2f mov r19, r18 + 1b2: 22 27 eor r18, r18 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1b4: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1b6: 92 81 ldd r25, Z+2 ; 0x02 + 1b8: 99 23 and r25, r25 + 1ba: ec f7 brge .-6 ; 0x1b6 + + // Return received data + + return SPIC.DATA; + 1bc: 80 91 c3 08 lds r24, 0x08C3 + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + 1c0: 90 e1 ldi r25, 0x10 ; 16 + 1c2: 90 93 45 06 sts 0x0645, r25 + return aux; +} + 1c6: a9 01 movw r20, r18 + 1c8: 48 2b or r20, r24 + 1ca: ca 01 movw r24, r20 + 1cc: 08 95 ret + +000001ce : + * transmision genera clock en el pin "sclk" + * \param La direcci�n del puntero a dato + * \return Ninguno s�lo se llena el puntero al dato + */ +inline void adcport_read_data(uint8_t* dato,int j) +{ + 1ce: 9c 01 movw r18, r24 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1d0: 84 e4 ldi r24, 0x44 ; 68 + 1d2: 80 93 c3 08 sts 0x08C3, r24 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1d6: e0 ec ldi r30, 0xC0 ; 192 + 1d8: f8 e0 ldi r31, 0x08 ; 8 + 1da: 92 81 ldd r25, Z+2 ; 0x02 + 1dc: 99 23 and r25, r25 + 1de: ec f7 brge .-6 ; 0x1da + + // Return received data + + return SPIC.DATA; + 1e0: 80 91 c3 08 lds r24, 0x08C3 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 1ea: d9 01 movw r26, r18 + 1ec: a6 0f add r26, r22 + 1ee: b7 1f adc r27, r23 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1f0: e0 ec ldi r30, 0xC0 ; 192 + 1f2: f8 e0 ldi r31, 0x08 ; 8 + 1f4: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1f6: 92 81 ldd r25, Z+2 ; 0x02 + 1f8: 99 23 and r25, r25 + 1fa: ec f7 brge .-6 ; 0x1f6 + + // Return received data + + return SPIC.DATA; + 1fc: 93 81 ldd r25, Z+3 ; 0x03 + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 206: 08 95 ret + +00000208 : +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | + 208: 8c ed ldi r24, 0xDC ; 220 + 20a: 80 93 c0 08 sts 0x08C0, r24 + 20e: 08 95 ret + +00000210 : +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + 210: cf 93 push r28 + 212: df 93 push r29 + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRCLR = LOCK_FPGA; + 214: e0 e6 ldi r30, 0x60 ; 96 + 216: f6 e0 ldi r31, 0x06 ; 6 + 218: 22 e0 ldi r18, 0x02 ; 2 + 21a: 22 83 std Z+2, r18 ; 0x02 + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + 21c: 80 e1 ldi r24, 0x10 ; 16 + 21e: 81 8b std Z+17, r24 ; 0x11 + PORT_FPGA.DIRSET = CLK_FPGA; + 220: 94 e0 ldi r25, 0x04 ; 4 + 222: 91 83 std Z+1, r25 ; 0x01 + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; + 224: 38 e1 ldi r19, 0x18 ; 24 + 226: 32 8b std Z+18, r19 ; 0x12 + PORT_FPGA.OUTSET = CLK_FPGA; + 228: 95 83 std Z+5, r25 ; 0x05 + + //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + 22a: 38 e7 ldi r19, 0x78 ; 120 + 22c: 31 83 std Z+1, r19 ; 0x01 + PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; + 22e: 13 8a std Z+19, r1 ; 0x13 + PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + 230: 35 83 std Z+5, r19 ; 0x05 + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + 232: a0 e2 ldi r26, 0x20 ; 32 + 234: b6 e0 ldi r27, 0x06 ; 6 + 236: 12 96 adiw r26, 0x02 ; 2 + 238: 9c 93 st X, r25 + 23a: 12 97 sbiw r26, 0x02 ; 2 + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + 23c: 52 96 adiw r26, 0x12 ; 18 + 23e: 8c 93 st X, r24 + 240: 52 97 sbiw r26, 0x12 ; 18 + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + 242: c0 e0 ldi r28, 0x00 ; 0 + 244: d6 e0 ldi r29, 0x06 ; 6 + 246: 81 e0 ldi r24, 0x01 ; 1 + 248: 89 83 std Y+1, r24 ; 0x01 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 24a: 8e 83 std Y+6, r24 ; 0x06 + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + 24c: 81 85 ldd r24, Z+9 ; 0x09 + 24e: 83 60 ori r24, 0x03 ; 3 + 250: 81 87 std Z+9, r24 ; 0x09 + PORT_FPGA.INT0MASK = LOCK_FPGA; + 252: 22 87 std Z+10, r18 ; 0x0a + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + 254: 81 89 ldd r24, Z+17 ; 0x11 + 256: 88 7f andi r24, 0xF8 ; 248 + 258: 81 8b std Z+17, r24 ; 0x11 + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + 25a: 81 85 ldd r24, Z+9 ; 0x09 + 25c: 83 7f andi r24, 0xF3 ; 243 + 25e: 88 60 ori r24, 0x08 ; 8 + 260: 19 96 adiw r26, 0x09 ; 9 + 262: 8c 93 st X, r24 + 264: 19 97 sbiw r26, 0x09 ; 9 + PORT_PPS.INT1MASK = PPS_FPGA; + 266: 1b 96 adiw r26, 0x0b ; 11 + 268: 9c 93 st X, r25 + 26a: 1b 97 sbiw r26, 0x0b ; 11 + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; + 26c: 52 96 adiw r26, 0x12 ; 18 + 26e: 8c 91 ld r24, X + 270: 52 97 sbiw r26, 0x12 ; 18 + 272: 88 7f andi r24, 0xF8 ; 248 + 274: 81 60 ori r24, 0x01 ; 1 + 276: 52 96 adiw r26, 0x12 ; 18 + 278: 8c 93 st X, r24 +} + 27a: df 91 pop r29 + 27c: cf 91 pop r28 + 27e: 08 95 ret + +00000280 : + PMIC.CTRL = level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); + 280: 78 94 sei + 282: 08 95 ret + +00000284 : + cli(); +} + +void envio_nibble(uint8_t fpga_dato) +{ + PORT_FPGA.OUTCLR = CLK_FPGA; + 284: e0 e6 ldi r30, 0x60 ; 96 + 286: f6 e0 ldi r31, 0x06 ; 6 + 288: 24 e0 ldi r18, 0x04 ; 4 + 28a: 26 83 std Z+6, r18 ; 0x06 + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); + 28c: 94 81 ldd r25, Z+4 ; 0x04 + 28e: 38 2f mov r19, r24 + 290: 30 7f andi r19, 0xF0 ; 240 + 292: 33 0f add r19, r19 + 294: 33 0f add r19, r19 + 296: 33 0f add r19, r19 + 298: 98 73 andi r25, 0x38 ; 56 + 29a: 93 2b or r25, r19 + 29c: 94 83 std Z+4, r25 ; 0x04 + PORT_FPGA.OUTSET = CLK_FPGA; + 29e: 25 83 std Z+5, r18 ; 0x05 + //asm("nop"); + PORT_FPGA.OUTCLR = CLK_FPGA; + 2a0: 26 83 std Z+6, r18 ; 0x06 + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); + 2a2: 94 81 ldd r25, Z+4 ; 0x04 + 2a4: 8f 70 andi r24, 0x0F ; 15 + 2a6: 88 0f add r24, r24 + 2a8: 88 0f add r24, r24 + 2aa: 88 0f add r24, r24 + 2ac: 98 73 andi r25, 0x38 ; 56 + 2ae: 89 2b or r24, r25 + 2b0: 84 83 std Z+4, r24 ; 0x04 + PORT_FPGA.OUTSET = CLK_FPGA; + 2b2: 25 83 std Z+5, r18 ; 0x05 + 2b4: 08 95 ret + +000002b6 : + envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + 2b6: 0f 93 push r16 + 2b8: 1f 93 push r17 + 2ba: cf 93 push r28 + 2bc: df 93 push r29 + 2be: ec 01 movw r28, r24 + 2c0: 8c 01 movw r16, r24 + 2c2: 0d 5f subi r16, 0xFD ; 253 + 2c4: 1f 4f sbci r17, 0xFF ; 255 + for(int i=0; i<3 ; i++) + envio_nibble(dato_adc[i]); + 2c6: 89 91 ld r24, Y+ + 2c8: 0e 94 42 01 call 0x284 ; 0x284 + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + for(int i=0; i<3 ; i++) + 2cc: c0 17 cp r28, r16 + 2ce: d1 07 cpc r29, r17 + 2d0: d1 f7 brne .-12 ; 0x2c6 + envio_nibble(dato_adc[i]); +} + 2d2: df 91 pop r29 + 2d4: cf 91 pop r28 + 2d6: 1f 91 pop r17 + 2d8: 0f 91 pop r16 + 2da: 08 95 ret + +000002dc : + PORT_FPGA.OUTSET = CLK_FPGA; + +} + +void envio_datos_fpga(void) +{ + 2dc: cf 93 push r28 + 2de: df 93 push r29 + 2e0: cd b7 in r28, 0x3d ; 61 + 2e2: de b7 in r29, 0x3e ; 62 + 2e4: 26 97 sbiw r28, 0x06 ; 6 + 2e6: cd bf out 0x3d, r28 ; 61 + 2e8: de bf out 0x3e, r29 ; 62 + uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; + adcport_read_data(fpga_dato,ADC_DATASZ); + 2ea: 63 e0 ldi r22, 0x03 ; 3 + 2ec: 70 e0 ldi r23, 0x00 ; 0 + 2ee: ce 01 movw r24, r28 + 2f0: 01 96 adiw r24, 0x01 ; 1 + 2f2: 0e 94 e7 00 call 0x1ce ; 0x1ce + aux_dato[0] = fpga_dato[0]; + 2f6: 89 81 ldd r24, Y+1 ; 0x01 + 2f8: 8c 83 std Y+4, r24 ; 0x04 + aux_dato[1] = fpga_dato[1]; + 2fa: 8a 81 ldd r24, Y+2 ; 0x02 + 2fc: 8d 83 std Y+5, r24 ; 0x05 + aux_dato[2] = fpga_dato[2]; + 2fe: 8b 81 ldd r24, Y+3 ; 0x03 + 300: 8e 83 std Y+6, r24 ; 0x06 + adcport_read_data(fpga_dato,ADC_DATASZ); + 302: 63 e0 ldi r22, 0x03 ; 3 + 304: 70 e0 ldi r23, 0x00 ; 0 + 306: ce 01 movw r24, r28 + 308: 01 96 adiw r24, 0x01 ; 1 + 30a: 0e 94 e7 00 call 0x1ce ; 0x1ce + + envio_dato_adc(aux_dato); + 30e: ce 01 movw r24, r28 + 310: 04 96 adiw r24, 0x04 ; 4 + 312: 0e 94 5b 01 call 0x2b6 ; 0x2b6 + envio_dato_adc(fpga_dato); + 316: ce 01 movw r24, r28 + 318: 01 96 adiw r24, 0x01 ; 1 + 31a: 0e 94 5b 01 call 0x2b6 ; 0x2b6 +} + 31e: 26 96 adiw r28, 0x06 ; 6 + 320: cd bf out 0x3d, r28 ; 61 + 322: de bf out 0x3e, r29 ; 62 + 324: df 91 pop r29 + 326: cf 91 pop r28 + 328: 08 95 ret + +0000032a
: + + +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + 32a: 0e 94 15 02 call 0x42a ; 0x42a + config_sysclock(); + 32e: 0e 94 8b 02 call 0x516 ; 0x516 + config_spiparm(); + 332: 0e 94 04 01 call 0x208 ; 0x208 + config_fpgaport(); + 336: 0e 94 08 01 call 0x210 ; 0x210 + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + 33a: 84 e0 ldi r24, 0x04 ; 4 + 33c: 80 93 a2 00 sts 0x00A2, r24 + habilitar_interrupciones_globales(); + 340: 0e 94 40 01 call 0x280 ; 0x280 + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + PORTD.OUTSET = PIN6_bm | PIN5_bm; + 344: 00 e6 ldi r16, 0x60 ; 96 + 346: 16 e0 ldi r17, 0x06 ; 6 + 348: c0 e6 ldi r28, 0x60 ; 96 + habilitar_interrupciones_globales(); + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + 34a: 0e 94 c2 00 call 0x184 ; 0x184 + 34e: 84 39 cpi r24, 0x94 ; 148 + 350: 9c 40 sbci r25, 0x0C ; 12 + 352: d9 f7 brne .-10 ; 0x34a + PORTD.OUTSET = PIN6_bm | PIN5_bm; + 354: f8 01 movw r30, r16 + 356: c5 83 std Z+5, r28 ; 0x05 + 358: f8 cf rjmp .-16 ; 0x34a + +0000035a <__vector_64>: + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + 35a: 1f 92 push r1 + 35c: 0f 92 push r0 + 35e: 0f b6 in r0, 0x3f ; 63 + 360: 0f 92 push r0 + 362: 11 24 eor r1, r1 + 364: 8f 93 push r24 + 366: ef 93 push r30 + 368: ff 93 push r31 + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + 36a: 80 91 68 06 lds r24, 0x0668 + 36e: 81 ff sbrs r24, 1 + 370: 09 c0 rjmp .+18 ; 0x384 <__vector_64+0x2a> + { + PMIC.CTRL |= hab_prioridad_media; + 372: e0 ea ldi r30, 0xA0 ; 160 + 374: f0 e0 ldi r31, 0x00 ; 0 + 376: 82 81 ldd r24, Z+2 ; 0x02 + 378: 82 60 ori r24, 0x02 ; 2 + 37a: 82 83 std Z+2, r24 ; 0x02 + PORT_LOCKOUT.OUTSET = LOCK_OUT; + 37c: 81 e0 ldi r24, 0x01 ; 1 + 37e: 80 93 05 06 sts 0x0605, r24 + 382: 08 c0 rjmp .+16 ; 0x394 <__vector_64+0x3a> + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + 384: e0 ea ldi r30, 0xA0 ; 160 + 386: f0 e0 ldi r31, 0x00 ; 0 + 388: 82 81 ldd r24, Z+2 ; 0x02 + 38a: 8d 7f andi r24, 0xFD ; 253 + 38c: 82 83 std Z+2, r24 ; 0x02 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 38e: 81 e0 ldi r24, 0x01 ; 1 + 390: 80 93 06 06 sts 0x0606, r24 + } +} + 394: ff 91 pop r31 + 396: ef 91 pop r30 + 398: 8f 91 pop r24 + 39a: 0f 90 pop r0 + 39c: 0f be out 0x3f, r0 ; 63 + 39e: 0f 90 pop r0 + 3a0: 1f 90 pop r1 + 3a2: 18 95 reti + +000003a4 <__vector_35>: + +ISR(INT_PPS) +{ + 3a4: 1f 92 push r1 + 3a6: 0f 92 push r0 + 3a8: 0f b6 in r0, 0x3f ; 63 + 3aa: 0f 92 push r0 + 3ac: 11 24 eor r1, r1 + 3ae: 8f 93 push r24 + 3b0: ef 93 push r30 + 3b2: ff 93 push r31 + if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA) + 3b4: 80 91 28 06 lds r24, 0x0628 + 3b8: 82 ff sbrs r24, 2 + 3ba: 06 c0 rjmp .+12 ; 0x3c8 <__vector_35+0x24> + PMIC.CTRL |= hab_prioridad_baja; + 3bc: e0 ea ldi r30, 0xA0 ; 160 + 3be: f0 e0 ldi r31, 0x00 ; 0 + 3c0: 82 81 ldd r24, Z+2 ; 0x02 + 3c2: 81 60 ori r24, 0x01 ; 1 + 3c4: 82 83 std Z+2, r24 ; 0x02 + 3c6: 05 c0 rjmp .+10 ; 0x3d2 <__vector_35+0x2e> + else + PMIC.CTRL &= ~hab_prioridad_baja; + 3c8: e0 ea ldi r30, 0xA0 ; 160 + 3ca: f0 e0 ldi r31, 0x00 ; 0 + 3cc: 82 81 ldd r24, Z+2 ; 0x02 + 3ce: 8e 7f andi r24, 0xFE ; 254 + 3d0: 82 83 std Z+2, r24 ; 0x02 +} + 3d2: ff 91 pop r31 + 3d4: ef 91 pop r30 + 3d6: 8f 91 pop r24 + 3d8: 0f 90 pop r0 + 3da: 0f be out 0x3f, r0 ; 63 + 3dc: 0f 90 pop r0 + 3de: 1f 90 pop r1 + 3e0: 18 95 reti + +000003e2 <__vector_2>: + +ISR(INT_RDY) +{ + 3e2: 1f 92 push r1 + 3e4: 0f 92 push r0 + 3e6: 0f b6 in r0, 0x3f ; 63 + 3e8: 0f 92 push r0 + 3ea: 11 24 eor r1, r1 + 3ec: 2f 93 push r18 + 3ee: 3f 93 push r19 + 3f0: 4f 93 push r20 + 3f2: 5f 93 push r21 + 3f4: 6f 93 push r22 + 3f6: 7f 93 push r23 + 3f8: 8f 93 push r24 + 3fa: 9f 93 push r25 + 3fc: af 93 push r26 + 3fe: bf 93 push r27 + 400: ef 93 push r30 + 402: ff 93 push r31 + envio_datos_fpga(); + 404: 0e 94 6e 01 call 0x2dc ; 0x2dc +} + 408: ff 91 pop r31 + 40a: ef 91 pop r30 + 40c: bf 91 pop r27 + 40e: af 91 pop r26 + 410: 9f 91 pop r25 + 412: 8f 91 pop r24 + 414: 7f 91 pop r23 + 416: 6f 91 pop r22 + 418: 5f 91 pop r21 + 41a: 4f 91 pop r20 + 41c: 3f 91 pop r19 + 41e: 2f 91 pop r18 + 420: 0f 90 pop r0 + 422: 0f be out 0x3f, r0 ; 63 + 424: 0f 90 pop r0 + 426: 1f 90 pop r1 + 428: 18 95 reti + +0000042a : +#include "commSPI_ADC.h" + +inline void config_puertos(void){ + //Configuracion pines del puerto A: PA7-PA0 + //Pines de entrada y totem_pullup + PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + 42a: e0 e0 ldi r30, 0x00 ; 0 + 42c: f6 e0 ldi r31, 0x06 ; 6 + 42e: 8e ef ldi r24, 0xFE ; 254 + 430: 82 83 std Z+2, r24 ; 0x02 + PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; + 432: 88 e1 ldi r24, 0x18 ; 24 + 434: 87 8b std Z+23, r24 ; 0x17 + PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; + 436: 86 8b std Z+22, r24 ; 0x16 + PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; + 438: 85 8b std Z+21, r24 ; 0x15 + PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; + 43a: 84 8b std Z+20, r24 ; 0x14 + PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; + 43c: 83 8b std Z+19, r24 ; 0x13 + PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; + 43e: 82 8b std Z+18, r24 ; 0x12 + PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; + 440: 81 8b std Z+17, r24 ; 0x11 + //Pin de salida A0 + //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n + //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta + //Valor por defecto salida: PA0 = low + PORTA.DIRSET = PIN0_bm; + 442: 21 e0 ldi r18, 0x01 ; 1 + 444: 21 83 std Z+1, r18 ; 0x01 + PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; + 446: 98 e3 ldi r25, 0x38 ; 56 + 448: 90 8b std Z+16, r25 ; 0x10 + PORTA.OUTCLR = PIN0_bm; + 44a: 26 83 std Z+6, r18 ; 0x06 + + //Configuracion pines del puerto B: PB3-PB0 + //Pines de entrada y totem_pullup + PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + 44c: e0 e2 ldi r30, 0x20 ; 32 + 44e: f6 e0 ldi r31, 0x06 ; 6 + 450: 3f e0 ldi r19, 0x0F ; 15 + 452: 32 83 std Z+2, r19 ; 0x02 + PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; + 454: 83 8b std Z+19, r24 ; 0x13 + PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; + 456: 82 8b std Z+18, r24 ; 0x12 + PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; + 458: 81 8b std Z+17, r24 ; 0x11 + PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; + 45a: 80 8b std Z+16, r24 ; 0x10 + + //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI + //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 + //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. + PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + 45c: e0 e4 ldi r30, 0x40 ; 64 + 45e: f6 e0 ldi r31, 0x06 ; 6 + 460: 2f e4 ldi r18, 0x4F ; 79 + 462: 22 83 std Z+2, r18 ; 0x02 + PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; + 464: 86 8b std Z+22, r24 ; 0x16 + PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; + 466: 83 8b std Z+19, r24 ; 0x13 + PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; + 468: 82 8b std Z+18, r24 ; 0x12 + PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; + 46a: 81 8b std Z+17, r24 ; 0x11 + PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; + 46c: 80 8b std Z+16, r24 ; 0x10 + //Pines de salida wiredand-pull + //Valor por defecto salida: PC4,PC7 = low + //Valor por defecto salida: PC5 = set + PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; + 46e: 20 eb ldi r18, 0xB0 ; 176 + 470: 21 83 std Z+1, r18 ; 0x01 + PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; + 472: 15 8a std Z+21, r1 ; 0x15 + PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; + 474: 17 8a std Z+23, r1 ; 0x17 + PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; + 476: 14 8a std Z+20, r1 ; 0x14 + PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; + 478: 20 e9 ldi r18, 0x90 ; 144 + 47a: 25 83 std Z+5, r18 ; 0x05 + PORTSPI.OUTCLR = SPI_MOSI_bm; + 47c: 20 e2 ldi r18, 0x20 ; 32 + 47e: 26 83 std Z+6, r18 ; 0x06 + //Configuracion pines del puerto D: PD7-PD0 + //Pines de entrada y totem_pullup: PIN7 y PIN0 + //NOTA + //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO + //NOTA FIN + PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; + 480: a0 e6 ldi r26, 0x60 ; 96 + 482: b6 e0 ldi r27, 0x06 ; 6 + 484: 27 e8 ldi r18, 0x87 ; 135 + 486: 12 96 adiw r26, 0x02 ; 2 + 488: 2c 93 st X, r18 + 48a: 12 97 sbiw r26, 0x02 ; 2 + PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; + 48c: 57 96 adiw r26, 0x17 ; 23 + 48e: 8c 93 st X, r24 + 490: 57 97 sbiw r26, 0x17 ; 23 + PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; + 492: 50 96 adiw r26, 0x10 ; 16 + 494: 8c 93 st X, r24 + 496: 50 97 sbiw r26, 0x10 ; 16 + //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga + PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + 498: 20 e1 ldi r18, 0x10 ; 16 + 49a: 52 96 adiw r26, 0x12 ; 18 + 49c: 2c 93 st X, r18 + 49e: 52 97 sbiw r26, 0x12 ; 18 + PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 4a0: 51 96 adiw r26, 0x11 ; 17 + 4a2: 2c 93 st X, r18 + 4a4: 51 97 sbiw r26, 0x11 ; 17 + //Pines de salida tipo wired-and-pull + //Valor por defecto PD6, PD5, PD4, PD3 = low + PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 4a6: 48 e7 ldi r20, 0x78 ; 120 + 4a8: 11 96 adiw r26, 0x01 ; 1 + 4aa: 4c 93 st X, r20 + 4ac: 11 97 sbiw r26, 0x01 ; 1 + PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; + 4ae: 56 96 adiw r26, 0x16 ; 22 + 4b0: 9c 93 st X, r25 + 4b2: 56 97 sbiw r26, 0x16 ; 22 + PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; + 4b4: 55 96 adiw r26, 0x15 ; 21 + 4b6: 9c 93 st X, r25 + 4b8: 55 97 sbiw r26, 0x15 ; 21 + PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; + 4ba: 54 96 adiw r26, 0x14 ; 20 + 4bc: 9c 93 st X, r25 + 4be: 54 97 sbiw r26, 0x14 ; 20 + PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; + 4c0: 53 96 adiw r26, 0x13 ; 19 + 4c2: 9c 93 st X, r25 + 4c4: 53 97 sbiw r26, 0x13 ; 19 + PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 4c6: 16 96 adiw r26, 0x06 ; 6 + 4c8: 4c 93 st X, r20 + + //Configuracion pines del puerto E: PE3-PE0 + //Pines de entrada y totem_pullup: PIN3 - PIN0 + PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + 4ca: a0 e8 ldi r26, 0x80 ; 128 + 4cc: b6 e0 ldi r27, 0x06 ; 6 + 4ce: 12 96 adiw r26, 0x02 ; 2 + 4d0: 3c 93 st X, r19 + 4d2: 12 97 sbiw r26, 0x02 ; 2 + PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; + 4d4: 53 96 adiw r26, 0x13 ; 19 + 4d6: 8c 93 st X, r24 + 4d8: 53 97 sbiw r26, 0x13 ; 19 + PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; + 4da: 52 96 adiw r26, 0x12 ; 18 + 4dc: 8c 93 st X, r24 + 4de: 52 97 sbiw r26, 0x12 ; 18 + PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; + 4e0: 51 96 adiw r26, 0x11 ; 17 + 4e2: 8c 93 st X, r24 + 4e4: 51 97 sbiw r26, 0x11 ; 17 + PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; + 4e6: 50 96 adiw r26, 0x10 ; 16 + 4e8: 8c 93 st X, r24 + + //Configuracion pines del puerto R: PR1-PR0 + //Pines de entrada y totem_pulldown: PIN0 + PORTR.DIRCLR = PIN1_bm| PIN0_bm; + 4ea: a0 ee ldi r26, 0xE0 ; 224 + 4ec: b7 e0 ldi r27, 0x07 ; 7 + 4ee: 93 e0 ldi r25, 0x03 ; 3 + 4f0: 12 96 adiw r26, 0x02 ; 2 + 4f2: 9c 93 st X, r25 + 4f4: 12 97 sbiw r26, 0x02 ; 2 + PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 4f6: 51 96 adiw r26, 0x11 ; 17 + 4f8: 2c 93 st X, r18 + 4fa: 51 97 sbiw r26, 0x11 ; 17 + //Pines de entrada y totem_pulldup:PIN1 + PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + 4fc: 50 96 adiw r26, 0x10 ; 16 + 4fe: 8c 93 st X, r24 + + //Configuraci�n como interrupci�n del pin SPI_MISO_RDY + + PORTSPI.INT0MASK = SPI_MISO_bm; + 500: 80 e4 ldi r24, 0x40 ; 64 + 502: 82 87 std Z+10, r24 ; 0x0a + PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; + 504: 81 85 ldd r24, Z+9 ; 0x09 + 506: 8c 7f andi r24, 0xFC ; 252 + 508: 81 60 ori r24, 0x01 ; 1 + 50a: 81 87 std Z+9, r24 ; 0x09 + PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + 50c: 86 89 ldd r24, Z+22 ; 0x16 + 50e: 88 7f andi r24, 0xF8 ; 248 + 510: 82 60 ori r24, 0x02 ; 2 + 512: 86 8b std Z+22, r24 ; 0x16 + 514: 08 95 ret + +00000516 : +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + + OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz + 516: e0 e5 ldi r30, 0x50 ; 80 + 518: f0 e0 ldi r31, 0x00 ; 0 + 51a: 80 81 ld r24, Z + 51c: 86 60 ori r24, 0x06 ; 6 + 51e: 80 83 st Z, r24 + do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj + 520: 81 81 ldd r24, Z+1 ; 0x01 + 522: 81 ff sbrs r24, 1 + 524: fd cf rjmp .-6 ; 0x520 + do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj + 526: e0 e5 ldi r30, 0x50 ; 80 + 528: f0 e0 ldi r31, 0x00 ; 0 + 52a: 81 81 ldd r24, Z+1 ; 0x01 + 52c: 82 ff sbrs r24, 2 + 52e: fd cf rjmp .-6 ; 0x52a + CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla + 530: 28 ed ldi r18, 0xD8 ; 216 + 532: 24 bf out 0x34, r18 ; 52 + //con instrucciones en assembler + CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler + 534: e0 e4 ldi r30, 0x40 ; 64 + 536: f0 e0 ldi r31, 0x00 ; 0 + 538: 80 81 ld r24, Z + 53a: 81 60 ori r24, 0x01 ; 1 + 53c: 80 83 st Z, r24 + DFLLRC32M.CTRL = DFLL_ENABLE_bm; + 53e: 91 e0 ldi r25, 0x01 ; 1 + 540: 90 93 60 00 sts 0x0060, r25 + OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K + 544: e0 e5 ldi r30, 0x50 ; 80 + 546: f0 e0 ldi r31, 0x00 ; 0 + 548: 86 81 ldd r24, Z+6 ; 0x06 + 54a: 16 82 std Z+6, r1 ; 0x06 + OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno + 54c: 80 81 ld r24, Z + 54e: 8e 7f andi r24, 0xFE ; 254 + 550: 80 83 st Z, r24 + CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro + 552: 24 bf out 0x34, r18 ; 52 + OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de + 554: 90 93 53 00 sts 0x0053, r25 + 558: 08 95 ret + +0000055a <_exit>: + 55a: f8 94 cli + +0000055c <__stop_program>: + 55c: ff cf rjmp .-2 ; 0x55c <__stop_program> Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.map =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.map b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.map new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.map (revision 221) @@ -0,0 +1,590 @@ +Archive member included to satisfy reference by file (symbol) + +c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o (exit) + +Discarded input sections + + .data 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + .bss 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + .text 0x00000000 0x0 ADC_7176_2.o + .data 0x00000000 0x0 ADC_7176_2.o + .bss 0x00000000 0x0 ADC_7176_2.o + .text.test_adc_2 + 0x00000000 0x3e ADC_7176_2.o + .text.adcport_tranceiv + 0x00000000 0x14 ADC_7176_2.o + .text.adcport_write_filtcon0 + 0x00000000 0x34 ADC_7176_2.o + .text.config_adc + 0x00000000 0x6 ADC_7176_2.o + .text.adcport_write_interfmode + 0x00000000 0x34 ADC_7176_2.o + .text 0x00000000 0x0 commSPI_ADC.o + .data 0x00000000 0x0 commSPI_ADC.o + .bss 0x00000000 0x0 commSPI_ADC.o + .text 0x00000000 0x0 fpga_port.o + .data 0x00000000 0x0 fpga_port.o + .bss 0x00000000 0x0 fpga_port.o + .text.habilitar_interrupciones + 0x00000000 0x6 fpga_port.o + .text.deshabilitar_interrupciones_globales + 0x00000000 0x4 fpga_port.o + .text 0x00000000 0x0 main.o + .data 0x00000000 0x0 main.o + .bss 0x00000000 0x0 main.o + .text 0x00000000 0x0 Ports.o + .data 0x00000000 0x0 Ports.o + .bss 0x00000000 0x0 Ports.o + .text 0x00000000 0x0 sys_clock.o + .data 0x00000000 0x0 sys_clock.o + .bss 0x00000000 0x0 sys_clock.o + .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.mul + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.div + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.prologue + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.builtins + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.fmul + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.fixed + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + +Memory Configuration + +Name Origin Length Attributes +text 0x00000000 0x00100000 xr +data 0x00802000 0x0000ffa0 rw !x +eeprom 0x00810000 0x00010000 rw !x +fuse 0x00820000 0x00000400 rw !x +lock 0x00830000 0x00000400 rw !x +signature 0x00840000 0x00000400 rw !x +user_signatures 0x00850000 0x00000400 rw !x +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o +LOAD ADC_7176_2.o +LOAD commSPI_ADC.o +LOAD fpga_port.o +LOAD main.o +LOAD Ports.o +LOAD sys_clock.o +START GROUP +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a +END GROUP +START GROUP +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libc.a +LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2\libatxmega32d4.a +END GROUP + +.hash + *(.hash) + +.dynsym + *(.dynsym) + +.dynstr + *(.dynstr) + +.gnu.version + *(.gnu.version) + +.gnu.version_d + *(.gnu.version_d) + +.gnu.version_r + *(.gnu.version_r) + +.rel.init + *(.rel.init) + +.rela.init + *(.rela.init) + +.rel.text + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + +.rela.text + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + +.rel.fini + *(.rel.fini) + +.rela.fini + *(.rela.fini) + +.rel.rodata + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + +.rela.rodata + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + +.rel.data + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + +.rela.data + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + +.rel.ctors + *(.rel.ctors) + +.rela.ctors + *(.rela.ctors) + +.rel.dtors + *(.rel.dtors) + +.rela.dtors + *(.rela.dtors) + +.rel.got + *(.rel.got) + +.rela.got + *(.rela.got) + +.rel.bss + *(.rel.bss) + +.rela.bss + *(.rela.bss) + +.rel.plt + *(.rel.plt) + +.rela.plt + *(.rela.plt) + +.text 0x00000000 0x55e + *(.vectors) + .vectors 0x00000000 0x16c C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x00000000 __vector_default + 0x00000000 __vectors + *(.vectors) + *(.progmem.gcc*) + 0x0000016c . = ALIGN (0x2) + 0x0000016c __trampolines_start = . + *(.trampolines) + .trampolines 0x0000016c 0x0 linker stubs + *(.trampolines*) + 0x0000016c __trampolines_end = . + *(.progmem*) + 0x0000016c . = ALIGN (0x2) + *(.jumptables) + *(.jumptables*) + *(.lowtext) + *(.lowtext*) + 0x0000016c __ctors_start = . + *(.ctors) + 0x0000016c __ctors_end = . + 0x0000016c __dtors_start = . + *(.dtors) + 0x0000016c __dtors_end = . + SORT(*)(.ctors) + SORT(*)(.dtors) + *(.init0) + .init0 0x0000016c 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x0000016c __init + *(.init0) + *(.init1) + *(.init1) + *(.init2) + .init2 0x0000016c 0xc C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + *(.init2) + *(.init3) + *(.init3) + *(.init4) + *(.init4) + *(.init5) + *(.init5) + *(.init6) + *(.init6) + *(.init7) + *(.init7) + *(.init8) + *(.init8) + *(.init9) + .init9 0x00000178 0x8 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + *(.init9) + *(.text) + .text 0x00000180 0x4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x00000180 __vector_38 + 0x00000180 __vector_22 + 0x00000180 __vector_63 + 0x00000180 __vector_28 + 0x00000180 __vector_67 + 0x00000180 __vector_1 + 0x00000180 __vector_32 + 0x00000180 __vector_75 + 0x00000180 __vector_71 + 0x00000180 __vector_34 + 0x00000180 __vector_62 + 0x00000180 __vector_77 + 0x00000180 __vector_24 + 0x00000180 __vector_12 + 0x00000180 __vector_55 + 0x00000180 __vector_69 + 0x00000180 __vector_81 + 0x00000180 __vector_90 + 0x00000180 __vector_46 + 0x00000180 __bad_interrupt + 0x00000180 __vector_72 + 0x00000180 __vector_6 + 0x00000180 __vector_31 + 0x00000180 __vector_78 + 0x00000180 __vector_74 + 0x00000180 __vector_39 + 0x00000180 __vector_3 + 0x00000180 __vector_23 + 0x00000180 __vector_68 + 0x00000180 __vector_30 + 0x00000180 __vector_73 + 0x00000180 __vector_45 + 0x00000180 __vector_25 + 0x00000180 __vector_61 + 0x00000180 __vector_11 + 0x00000180 __vector_54 + 0x00000180 __vector_13 + 0x00000180 __vector_17 + 0x00000180 __vector_19 + 0x00000180 __vector_56 + 0x00000180 __vector_7 + 0x00000180 __vector_49 + 0x00000180 __vector_41 + 0x00000180 __vector_86 + 0x00000180 __vector_88 + 0x00000180 __vector_43 + 0x00000180 __vector_27 + 0x00000180 __vector_5 + 0x00000180 __vector_33 + 0x00000180 __vector_76 + 0x00000180 __vector_47 + 0x00000180 __vector_52 + 0x00000180 __vector_37 + 0x00000180 __vector_89 + 0x00000180 __vector_4 + 0x00000180 __vector_44 + 0x00000180 __vector_82 + 0x00000180 __vector_51 + 0x00000180 __vector_9 + 0x00000180 __vector_21 + 0x00000180 __vector_15 + 0x00000180 __vector_66 + 0x00000180 __vector_36 + 0x00000180 __vector_79 + 0x00000180 __vector_58 + 0x00000180 __vector_70 + 0x00000180 __vector_83 + 0x00000180 __vector_29 + 0x00000180 __vector_60 + 0x00000180 __vector_40 + 0x00000180 __vector_85 + 0x00000180 __vector_8 + 0x00000180 __vector_26 + 0x00000180 __vector_48 + 0x00000180 __vector_80 + 0x00000180 __vector_14 + 0x00000180 __vector_84 + 0x00000180 __vector_57 + 0x00000180 __vector_53 + 0x00000180 __vector_10 + 0x00000180 __vector_50 + 0x00000180 __vector_16 + 0x00000180 __vector_59 + 0x00000180 __vector_18 + 0x00000180 __vector_20 + 0x00000180 __vector_42 + 0x00000180 __vector_87 + 0x00000180 __vector_65 + 0x00000184 . = ALIGN (0x2) + *(.text.*) + .text.test_adc + 0x00000184 0x4a ADC_7176_2.o + 0x00000184 test_adc + .text.adcport_read_data + 0x000001ce 0x3a ADC_7176_2.o + 0x000001ce adcport_read_data + .text.config_spiparm + 0x00000208 0x8 commSPI_ADC.o + 0x00000208 config_spiparm + .text.config_fpgaport + 0x00000210 0x70 fpga_port.o + 0x00000210 config_fpgaport + .text.habilitar_interrupciones_globales + 0x00000280 0x4 fpga_port.o + 0x00000280 habilitar_interrupciones_globales + .text.envio_nibble + 0x00000284 0x32 fpga_port.o + 0x00000284 envio_nibble + .text.envio_dato_adc + 0x000002b6 0x26 fpga_port.o + 0x000002b6 envio_dato_adc + .text.envio_datos_fpga + 0x000002dc 0x4e fpga_port.o + 0x000002dc envio_datos_fpga + .text.main 0x0000032a 0x30 main.o + 0x0000032a main + .text.__vector_64 + 0x0000035a 0x4a main.o + 0x0000035a __vector_64 + .text.__vector_35 + 0x000003a4 0x3e main.o + 0x000003a4 __vector_35 + .text.__vector_2 + 0x000003e2 0x48 main.o + 0x000003e2 __vector_2 + .text.config_puertos + 0x0000042a 0xec Ports.o + 0x0000042a config_puertos + .text.config_sysclock + 0x00000516 0x44 sys_clock.o + 0x00000516 config_sysclock + 0x0000055a . = ALIGN (0x2) + *(.fini9) + .fini9 0x0000055a 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + 0x0000055a _exit + 0x0000055a exit + *(.fini9) + *(.fini8) + *(.fini8) + *(.fini7) + *(.fini7) + *(.fini6) + *(.fini6) + *(.fini5) + *(.fini5) + *(.fini4) + *(.fini4) + *(.fini3) + *(.fini3) + *(.fini2) + *(.fini2) + *(.fini1) + *(.fini1) + *(.fini0) + .fini0 0x0000055a 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + *(.fini0) + 0x0000055e _etext = . + +.data 0x00802000 0x0 load address 0x0000055e + 0x00802000 PROVIDE (__data_start, .) + *(.data) + *(.data*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.d*) + 0x00802000 . = ALIGN (0x2) + 0x00802000 _edata = . + 0x00802000 PROVIDE (__data_end, .) + +.bss 0x00802000 0x0 + 0x00802000 PROVIDE (__bss_start, .) + *(.bss) + *(.bss*) + *(COMMON) + 0x00802000 PROVIDE (__bss_end, .) + 0x0000055e __data_load_start = LOADADDR (.data) + 0x0000055e __data_load_end = (__data_load_start + SIZEOF (.data)) + +.noinit 0x00802000 0x0 + 0x00802000 PROVIDE (__noinit_start, .) + *(.noinit*) + 0x00802000 PROVIDE (__noinit_end, .) + 0x00802000 _end = . + 0x00802000 PROVIDE (__heap_start, .) + +.eeprom 0x00810000 0x0 + *(.eeprom*) + 0x00810000 __eeprom_end = . + +.fuse + *(.fuse) + *(.lfuse) + *(.hfuse) + *(.efuse) + +.lock + *(.lock*) + +.signature + *(.signature*) + +.user_signatures + *(.user_signatures*) + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.stab.excl + *(.stab.excl) + +.stab.exclstr + *(.stab.exclstr) + +.stab.index + *(.stab.index) + +.stab.indexstr + *(.stab.indexstr) + +.comment 0x00000000 0x30 + *(.comment) + .comment 0x00000000 0x30 ADC_7176_2.o + 0x31 (size before relaxing) + .comment 0x00000030 0x31 commSPI_ADC.o + .comment 0x00000030 0x31 fpga_port.o + .comment 0x00000030 0x31 main.o + .comment 0x00000030 0x31 Ports.o + .comment 0x00000030 0x31 sys_clock.o + +.note.gnu.avr.deviceinfo + 0x00000000 0x40 + .note.gnu.avr.deviceinfo + 0x00000000 0x40 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + +.note.gnu.build-id + *(.note.gnu.build-id) + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x138 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x50 ADC_7176_2.o + .debug_aranges + 0x00000050 0x20 commSPI_ADC.o + .debug_aranges + 0x00000070 0x50 fpga_port.o + .debug_aranges + 0x000000c0 0x38 main.o + .debug_aranges + 0x000000f8 0x20 Ports.o + .debug_aranges + 0x00000118 0x20 sys_clock.o + +.debug_pubnames + *(.debug_pubnames) + +.debug_info 0x00000000 0x14b5 + *(.debug_info .gnu.linkonce.wi.*) + .debug_info 0x00000000 0x53c ADC_7176_2.o + .debug_info 0x0000053c 0xf0 commSPI_ADC.o + .debug_info 0x0000062c 0x578 fpga_port.o + .debug_info 0x00000ba4 0x413 main.o + .debug_info 0x00000fb7 0x2ab Ports.o + .debug_info 0x00001262 0x253 sys_clock.o + +.debug_abbrev 0x00000000 0x644 + *(.debug_abbrev) + .debug_abbrev 0x00000000 0x1b6 ADC_7176_2.o + .debug_abbrev 0x000001b6 0x83 commSPI_ADC.o + .debug_abbrev 0x00000239 0x19b fpga_port.o + .debug_abbrev 0x000003d4 0x10d main.o + .debug_abbrev 0x000004e1 0xaa Ports.o + .debug_abbrev 0x0000058b 0xb9 sys_clock.o + +.debug_line 0x00000000 0x827 + *(.debug_line .debug_line.* .debug_line_end) + .debug_line 0x00000000 0x1c9 ADC_7176_2.o + .debug_line 0x000001c9 0x101 commSPI_ADC.o + .debug_line 0x000002ca 0x19c fpga_port.o + .debug_line 0x00000466 0x185 main.o + .debug_line 0x000005eb 0x12c Ports.o + .debug_line 0x00000717 0x110 sys_clock.o + +.debug_frame 0x00000000 0x278 + *(.debug_frame) + .debug_frame 0x00000000 0x84 ADC_7176_2.o + .debug_frame 0x00000084 0x24 commSPI_ADC.o + .debug_frame 0x000000a8 0xb4 fpga_port.o + .debug_frame 0x0000015c 0xd4 main.o + .debug_frame 0x00000230 0x24 Ports.o + .debug_frame 0x00000254 0x24 sys_clock.o + +.debug_str 0x00000000 0x7d6 + *(.debug_str) + .debug_str 0x00000000 0x2c0 ADC_7176_2.o + 0x303 (size before relaxing) + .debug_str 0x000002c0 0x22 commSPI_ADC.o + 0x1cc (size before relaxing) + .debug_str 0x000002e2 0x34d fpga_port.o + 0x5e0 (size before relaxing) + .debug_str 0x0000062f 0x53 main.o + 0x3c1 (size before relaxing) + .debug_str 0x00000682 0xd Ports.o + 0x3f5 (size before relaxing) + .debug_str 0x0000068f 0x147 sys_clock.o + 0x2ff (size before relaxing) + +.debug_loc 0x00000000 0x3d0 + *(.debug_loc) + .debug_loc 0x00000000 0xfc ADC_7176_2.o + .debug_loc 0x000000fc 0x15d fpga_port.o + .debug_loc 0x00000259 0x177 main.o + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_pubtypes + *(.debug_pubtypes) + +.debug_ranges 0x00000000 0xd8 + *(.debug_ranges) + .debug_ranges 0x00000000 0x40 ADC_7176_2.o + .debug_ranges 0x00000040 0x10 commSPI_ADC.o + .debug_ranges 0x00000050 0x40 fpga_port.o + .debug_ranges 0x00000090 0x28 main.o + .debug_ranges 0x000000b8 0x10 Ports.o + .debug_ranges 0x000000c8 0x10 sys_clock.o + +.debug_macro + *(.debug_macro) +OUTPUT(ADCSPI_ver01.elf elf32-avr) +LOAD linker stubs Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.srec =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.srec b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.srec new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADCSPI_ver01.srec (revision 221) @@ -0,0 +1,88 @@ +S01400004144435350495F76657230312E737265634F +S11300000C94B6000C94C0000C94F1010C94C00044 +S11300100C94C0000C94C0000C94C0000C94C0005C +S11300200C94C0000C94C0000C94C0000C94C0004C +S11300300C94C0000C94C0000C94C0000C94C0003C +S11300400C94C0000C94C0000C94C0000C94C0002C +S11300500C94C0000C94C0000C94C0000C94C0001C +S11300600C94C0000C94C0000C94C0000C94C0000C +S11300700C94C0000C94C0000C94C0000C94C000FC +S11300800C94C0000C94C0000C94C0000C94D201D9 +S11300900C94C0000C94C0000C94C0000C94C000DC +S11300A00C94C0000C94C0000C94C0000C94C000CC +S11300B00C94C0000C94C0000C94C0000C94C000BC +S11300C00C94C0000C94C0000C94C0000C94C000AC +S11300D00C94C0000C94C0000C94C0000C94C0009C +S11300E00C94C0000C94C0000C94C0000C94C0008C +S11300F00C94C0000C94C0000C94C0000C94C0007C +S11301000C94AD010C94C0000C94C0000C94C0007D +S11301100C94C0000C94C0000C94C0000C94C0005B +S11301200C94C0000C94C0000C94C0000C94C0004B +S11301300C94C0000C94C0000C94C0000C94C0003B +S11301400C94C0000C94C0000C94C0000C94C0002B +S11301500C94C0000C94C0000C94C0000C94C0001B +S11301600C94C0000C94C0000C94C00011241FBE59 +S1130170CFEFCDBFDFE2DEBF0E9495010C94AD024C +S11301800C94000080E18093460687E48093C308C2 +S1130190E0ECF8E082818823ECF7E0ECF8E083817E +S11301A0138282818823ECF7E0ECF8E0238130E0CD +S11301B0322F2227138292819923ECF78091C3086E +S11301C090E190934506A901482BCA0108959C012A +S11301D084E48093C308E0ECF8E092819923ECF77F +S11301E08091C3081616170674F4D901A60FB71F19 +S11301F0E0ECF8E0138292819923ECF793819E93CB +S1130200A217B307B9F708958CED8093C008089539 +S1130210CF93DF93E0E6F6E022E0228380E1818B56 +S113022094E0918338E1328B958338E73183138AE4 +S11302303583A0E2B6E012969C93129752968C9363 +S11302405297C0E0D6E081E089838E838185836004 +S1130250818722878189887F818B8185837F8860DC +S113026019968C9319971B969C931B9752968C9175 +S11302705297887F816052968C93DF91CF91089535 +S113028078940895E0E6F6E024E026839481382FFC +S1130290307F330F330F330F9873932B948325835D +S11302A0268394818F70880F880F880F9873892B09 +S11302B08483258308950F931F93CF93DF93EC01D9 +S11302C08C010D5F1F4F89910E944201C017D10715 +S11302D0D1F7DF91CF911F910F910895CF93DF93C1 +S11302E0CDB7DEB72697CDBFDEBF63E070E0CE01A9 +S11302F001960E94E70089818C838A818D838B819A +S11303008E8363E070E0CE0101960E94E700CE0187 +S113031004960E945B01CE0101960E945B01269621 +S1130320CDBFDEBFDF91CF9108950E9415020E94D8 +S11303308B020E9404010E94080184E08093A200C1 +S11303400E94400100E616E0C0E60E94C200843923 +S11303509C40D9F7F801C583F8CF1F920F920FB6CE +S11303600F9211248F93EF93FF938091680681FF7E +S113037009C0E0EAF0E082818260828381E08093B8 +S1130380050608C0E0EAF0E082818D7F828381E087 +S113039080930606FF91EF918F910F900FBE0F90FF +S11303A01F9018951F920F920FB60F9211248F93DE +S11303B0EF93FF938091280682FF06C0E0EAF0E005 +S11303C082818160828305C0E0EAF0E082818E7FD1 +S11303D08283FF91EF918F910F900FBE0F901F902A +S11303E018951F920F920FB60F9211242F933F93DB +S11303F04F935F936F937F938F939F93AF93BF9329 +S1130400EF93FF930E946E01FF91EF91BF91AF9123 +S11304109F918F917F916F915F914F913F912F9118 +S11304200F900FBE0F901F901895E0E0F6E08EEF4E +S1130430828388E1878B868B858B848B838B828BED +S1130440818B21E0218398E3908B2683E0E2F6E020 +S11304503FE03283838B828B818B808BE0E4F6E0F8 +S11304602FE42283868B838B828B818B808B20EB82 +S11304702183158A178A148A20E9258320E226839A +S1130480A0E6B6E027E812962C93129757968C9321 +S1130490579750968C93509720E152962C935297ED +S11304A051962C93519748E711964C931197569671 +S11304B09C93569755969C93559754969C93549712 +S11304C053969C93539716964C93A0E8B6E01296D5 +S11304D03C93129753968C93539752968C935297BE +S11304E051968C93519750968C93A0EEB7E093E07D +S11304F012969C93129751962C93519750968C93E5 +S113050080E4828781858C7F816081878689887F6A +S11305108260868B0895E0E5F0E0808186608083C8 +S1130520818181FFFDCFE0E5F0E0818182FFFDCF95 +S113053028ED24BFE0E4F0E080818160808391E0D5 +S113054090936000E0E5F0E08681168280818E7FE2 +S1110550808324BF909353000895F894FFCF46 +S9030000FC Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADC_7176_2.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADC_7176_2.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADC_7176_2.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/ADC_7176_2.d (revision 221) @@ -0,0 +1,44 @@ +ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Makefile =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Makefile b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Makefile new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Makefile (revision 221) @@ -0,0 +1,164 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../ADC_7176_2.c \ +../commSPI_ADC.c \ +../fpga_port.c \ +../main.c \ +../Ports.c \ +../sys_clock.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +ADC_7176_2.o \ +commSPI_ADC.o \ +fpga_port.o \ +main.o \ +Ports.o \ +sys_clock.o + +OBJS_AS_ARGS += \ +ADC_7176_2.o \ +commSPI_ADC.o \ +fpga_port.o \ +main.o \ +Ports.o \ +sys_clock.o + +C_DEPS += \ +ADC_7176_2.d \ +commSPI_ADC.d \ +fpga_port.d \ +main.d \ +Ports.d \ +sys_clock.d + +C_DEPS_AS_ARGS += \ +ADC_7176_2.d \ +commSPI_ADC.d \ +fpga_port.d \ +main.d \ +Ports.d \ +sys_clock.d + +OUTPUT_FILE_PATH +=ADCSPI_ver01.elf + +OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= + + +# AVR32/GNU C Compiler + + + + + + + + + + + + + +./%.o: .././%.c + @echo Building file: $< + @echo Invoking: AVR/GNU C Compiler : 4.9.2 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: AVR/GNU Linker : 4.9.2 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + @echo Finished building target: $@ + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0 + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures" + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Ports.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Ports.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Ports.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/Ports.d (revision 221) @@ -0,0 +1,42 @@ +Ports.d Ports.o: .././Ports.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/commSPI_ADC.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/commSPI_ADC.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/commSPI_ADC.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/commSPI_ADC.d (revision 221) @@ -0,0 +1,42 @@ +commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././commSPI_ADC.h .././Ports.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././commSPI_ADC.h: + +.././Ports.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/fpga_port.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/fpga_port.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/fpga_port.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/fpga_port.d (revision 221) @@ -0,0 +1,50 @@ +fpga_port.d fpga_port.o: .././fpga_port.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/main.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/main.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/main.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/main.d (revision 221) @@ -0,0 +1,52 @@ +main.d main.o: .././main.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././commSPI_ADC.h .././sys_clock.h .././ADC_7176_2.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././commSPI_ADC.h: + +.././sys_clock.h: + +.././ADC_7176_2.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/makedep.mk =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/makedep.mk b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/makedep.mk new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/makedep.mk (revision 221) @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit or delete the file +################################################################################ + +ADC_7176_2.c + +commSPI_ADC.c + +fpga_port.c + +main.c + +Ports.c + +sys_clock.c + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/sys_clock.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/sys_clock.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/sys_clock.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Debug/sys_clock.d (revision 221) @@ -0,0 +1,37 @@ +sys_clock.d sys_clock.o: .././sys_clock.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.c (revision 221) @@ -0,0 +1,116 @@ +/* + * Ports.c + * + * Created: 23/11/15 13:57:48 + * Author: Francisco + */ + +/*! + * \fn config_puertos + * \brief Configuraci�n de todos los pines de I/O a usarse + * para la prueba. Para el firmware final se deben dejar de configurar en este segmento + * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo. + * Los criterios de asignaci�n de control: + * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si + * Se sabe que la entrada ser� casi siempre alta. + * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si + * Se sabe que la entrada ser� casi siempre baja. + * WiredAndpull: Para evitar cortos de una salida al exterior del board. + * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board). + * \ +*/ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" +#include "commSPI_ADC.h" + +inline void config_puertos(void){ + //Configuracion pines del puerto A: PA7-PA0 + //Pines de entrada y totem_pullup + PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; + //Pin de salida A0 + //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n + //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta + //Valor por defecto salida: PA0 = low + PORTA.DIRSET = PIN0_bm; + PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTA.OUTCLR = PIN0_bm; + + //Configuracion pines del puerto B: PB3-PB0 + //Pines de entrada y totem_pullup + PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI + //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 + //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. + PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; + //Pines de salida wiredand-pull + //Valor por defecto salida: PC4,PC7 = low + //Valor por defecto salida: PC5 = set + PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; + PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; + PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; + PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; + PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; + PORTSPI.OUTCLR = SPI_MOSI_bm; + + //Configuracion pines del puerto D: PD7-PD0 + //Pines de entrada y totem_pullup: PIN7 y PIN0 + //NOTA + //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO + //NOTA FIN + PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; + PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; + PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; + //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga + PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + //Pines de salida tipo wired-and-pull + //Valor por defecto PD6, PD5, PD4, PD3 = low + PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + + //Configuracion pines del puerto E: PE3-PE0 + //Pines de entrada y totem_pullup: PIN3 - PIN0 + PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuracion pines del puerto R: PR1-PR0 + //Pines de entrada y totem_pulldown: PIN0 + PORTR.DIRCLR = PIN1_bm| PIN0_bm; + PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + //Pines de entrada y totem_pulldup:PIN1 + PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuraci�n como interrupci�n del pin SPI_MISO_RDY + + PORTSPI.INT0MASK = SPI_MISO_bm; + PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; + PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + +} \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.h b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/Ports.h (revision 221) @@ -0,0 +1,21 @@ +/* + * Ports.h + * + * Created: 23/11/15 13:55:28 + * Author: Francisco + */ + + +#ifndef PORTS_H_ +#define PORTS_H_ + +#define F_CPU 32000000UL +#include + +#define INT_RDY PORTC_INT0_vect + +void config_puertos(void); + + + +#endif /* PORTS_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.c (revision 221) @@ -0,0 +1,31 @@ +/* + * commSPI_ADC.c + * + * Created: 23/11/15 14:08:25 + * Author: Francisco + */ + + +#define F_CPU 32000000UL +#include +#include "commSPI_ADC.h" + +/*! + * \fn config_spiparm + * \brief Configuraci�n de los par�metros de reloj SPI + * + * fspi = fper/2 = fcpu/2 = 16MHz + * + * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una + * nueva evaluaci�n + * \ +*/ +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | + SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm; +} + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.h b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/commSPI_ADC.h (revision 221) @@ -0,0 +1,32 @@ +/* + * commSPI_ADC.h + * + * Created: 23/11/15 14:06:45 + * Author: Francisco + */ + + +#ifndef COMMSPI_ADC_H_ +#define COMMSPI_ADC_H_ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" + +#define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI + +#define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS +#define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI +#define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO +#define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK + +#define SPI_SS_bm PIN4_bm // Pin de entrada - Totem +#define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem +#define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem +#define SPI_SCK_bm PIN7_bm // Pin de salida - Totem + +void config_spiparm(void); + + +#endif /* COMMSPI_ADC_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.c (revision 221) @@ -0,0 +1,111 @@ +/* + * fpga_port.c + * + * Created: 23/11/15 14:33:16 + * Author: Francisco + */ + +#define F_CPU 32000000UL +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRCLR = LOCK_FPGA; + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + PORT_FPGA.DIRSET = CLK_FPGA; + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; + PORT_FPGA.OUTSET = CLK_FPGA; + + //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; + PORT_FPGA.OUTSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + PORT_FPGA.INT0MASK = LOCK_FPGA; + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + + //Configuracion de interrupciones de CLK + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + PORT_PPS.INT1MASK = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; +} + +void habilitar_interrupciones( uint8_t level_mask ) +{ + PMIC.CTRL = level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); +} + +void deshabilitar_interrupciones_globales( void ) +{ + cli(); +} + +void envio_nibble(uint8_t fpga_dato) +{ + PORT_FPGA.OUTCLR = CLK_FPGA; + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); + PORT_FPGA.OUTSET = CLK_FPGA; + //asm("nop"); + PORT_FPGA.OUTCLR = CLK_FPGA; + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); + PORT_FPGA.OUTSET = CLK_FPGA; + +} + +void envio_datos_fpga(void) +{ + uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; + adcport_read_data(fpga_dato,ADC_DATASZ); + aux_dato[0] = fpga_dato[0]; + aux_dato[1] = fpga_dato[1]; + aux_dato[2] = fpga_dato[2]; + adcport_read_data(fpga_dato,ADC_DATASZ); + + envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + for(int i=0; i<3 ; i++) + envio_nibble(dato_adc[i]); +} +/* +__attribute__((noinline)) void delay_nop(void) +{ + asm("nop"); +} +*/ + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.h b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/fpga_port.h (revision 221) @@ -0,0 +1,68 @@ +/* + * fpga_port.h + * + * Created: 23/11/15 14:20:25 + * Author: Francisco + */ + + +#ifndef FPGA_PORT_H_ +#define FPGA_PORT_H_ + +#define F_CPU 32000000UL +#include +#include +#include "ADC_7176_2.h" + +//Port B +#define PORT_PPS PORTB +#define PPS_FPGA PIN2_bm +#define PPS_FPGA_CTRL PIN2CTRL +#define INT_PPS PORTB_INT1_vect + +//Port A +#define PORT_LOCKOUT PORTA +#define LOCK_OUT PIN0_bm + + +//Port D +#define PORT_FPGA PORTD +#define LOCK_FPGA PIN1_bm +#define CLK_FPGA PIN2_bm +#define CH_BIT0_FPGA PIN3_bm +#define CH_BIT1_FPGA PIN4_bm +#define CH_BIT2_FPGA PIN5_bm +#define CH_BIT3_FPGA PIN6_bm +#define INT_LOCK_FPGA PORTD_INT0_vect + +#define LOCK_FPGA_CTRL PIN1CTRL +#define CLK_FPGA_CTRL PIN2CTRL +#define CH_BIT0_FPGA_CTRL PIN3CTRL +#define CH_BIT1_FPGA_CTRL PIN4CTRL +#define CH_BIT2_FPGA_CTRL PIN5CTRL +#define CH_BIT3_FPGA_CTRL PIN6CTRL + +void config_fpgaport(); +void habilitar_interrupciones( uint8_t level_mask ); +void habilitar_interrupciones_globales( ); +void deshabilitar_interrupciones_globales( ); + +//Habilitar +#define hab_prioridad_alta PMIC_HILVLEN_bm +#define hab_prioridad_media PMIC_MEDLVLEN_bm +#define hab_prioridad_baja PMIC_LOLVLEN_bm + +//M�scara de nibbles +#define nibble_alto_bm 0xF0 +#define nibble_bajo_bm 0x0F +#define fpga_salidas_bp 3 +#define fpga_salidas_bm 0x38 + +//funciones de env�o de datos +void envio_nibble(uint8_t fpga_dato); + +//funcion interrupcion por flanco de subida de RDY +void envio_datos_fpga(void); +void envio_dato_adc(uint8_t* dato_adc); + +#endif /* FPGA_PORT_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/main.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/main.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/main.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/main.c (revision 221) @@ -0,0 +1,77 @@ +/* + * ADCSPI_ver01.c + * + * Created: 26/10/15 12:02:22 + * Author : Francisco + */ + +#define F_CPU 32000000UL +#include +#include "Ports.h" +#include "commSPI_ADC.h" +#include "sys_clock.h" +#include "ADC_7176_2.h" +#include "fpga_port.h" + + +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + config_sysclock(); + config_spiparm(); + config_fpgaport(); + + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + habilitar_interrupciones_globales(); + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + PORTD.OUTSET = PIN6_bm | PIN5_bm; + } + //test_adc_2(datos_adc); + //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){ + //PORTD.OUTSET = PIN4_bm; + //} + } + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + { + PMIC.CTRL |= hab_prioridad_media; + PORT_LOCKOUT.OUTSET = LOCK_OUT; + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + PMIC.CTRL &= ~hab_prioridad_baja; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + } +} + +ISR(INT_PPS) +{ + if((PORT_PPS.IN & PPS_FPGA) == PPS_FPGA) + PMIC.CTRL |= hab_prioridad_baja; + else + PMIC.CTRL &= ~hab_prioridad_baja; +} + +ISR(INT_RDY) +{ + envio_datos_fpga(); +} + + + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/sys_clock.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/sys_clock.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/sys_clock.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/ADCSPI_ver01/ADCSPI_ver01/sys_clock.c (revision 221) @@ -0,0 +1,55 @@ +/* + * sys_clock.c + * + * Created: 23/11/15 14:04:36 + * Author: Francisco + */ + + +/*! + * \fn config_sysclock + * \brief Configuraci�n del reloj interno del sistema + * Reloj interno + * fsys = 32MHz + * + * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL + * \ +*/ + +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + + OSC.CTRL |= OSC_RC32MEN_bm | OSC_RC32KEN_bm; //Habilito reloj interno de 32MHz + do{}while((OSC.STATUS & OSC_RC32MRDY_bm) == 0); //Se espera estabilidad del reloj + do{}while((OSC.STATUS & OSC_RC32KRDY_bm) == 0); //Se espera estabilidad del reloj + CCP = CCP_IOREG_gc ; //Activo por 4 ciclos de reloj la escritura en el registro de control de reloj //Si no funciona con esta intrucci�n optimizarla + //con instrucciones en assembler + CLK.CTRL |= (CLK_SCLKSEL_RC32M_gc); //Selecciono el reloj de 32MHz //Si no hace efecto con esta implementaci�n cambiarla por instrucciones en assembler + DFLLRC32M.CTRL = DFLL_ENABLE_bm; + OSC.DFLLCTRL &= (0b00<<1); //Habilito calibraci�n interna mediante reloj de 32K + OSC.CTRL &= ~OSC_RC2MEN_bm; //Deshabilito el reloj interno de 2MHz para evitar consumo o lo comentamos para evitar quedarnos sin reloj de 2MHz interno + CPU_CCP = CCP_IOREG_gc; //Levantar protecci�n de registro + OSC_XOSCFAIL = (OSC_XOSCFDEN_bm); // Detecci�n de error de XOSC y de + + /* +CLK_PSCTRL = ((0< + +void config_sysclock(void); + + + +#endif /* SYS_CLOCK_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/NotaVersión1.txt =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/NotaVersión1.txt b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/NotaVersión1.txt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_1/NotaVersión1.txt (revision 221) @@ -0,0 +1,4 @@ +En esta primera versi�n los activadores de interrupciones son LOCK y PPS. +LOCK activa la interrupci�n deprioridad media. +PPS activa la interrupci�n de prioridad baja. + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01.atsln =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01.atsln b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01.atsln new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01.atsln (revision 221) @@ -0,0 +1,22 @@ + +Microsoft Visual Studio Solution File, Format Version 12.00 +# Atmel Studio Solution File, Format Version 11.00 +VisualStudioVersion = 14.0.23107.0 +MinimumVisualStudioVersion = 10.0.40219.1 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_ver01", "ADCSPI_ver01\ADCSPI_ver01.cproj", "{DCE6C7E3-EE26-4D79-826B-08594B9AD897}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.ActiveCfg = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Debug|AVR.Build.0 = Debug|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.ActiveCfg = Release|AVR + {DCE6C7E3-EE26-4D79-826B-08594B9AD897}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.componentinfo.xml (revision 221) @@ -0,0 +1,86 @@ + + + + + + + Device + Startup + + + Atmel + 1.0.0 + C:/Program Files (x86)\Atmel\Studio\7.0\Packs + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include + + include + C + + + include + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include\avr\iox32d4.h + + header + C + Fb3v/Gsyx/fNhVPcSy4byA== + + include/avr/iox32d4.h + + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.c + template + source + C Exe + 8XJjXFQBySw6iim2xAnW5g== + + templates/main.c + Main file (.c) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\templates\main.cpp + template + source + C Exe + YXFphlh0CtZJU+ebktABgQ== + + templates/main.cpp + Main file (.cpp) + + + + C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4 + + libraryPrefix + GCC + + + gcc/dev/atxmega32d4 + + + + + XMEGAD_DFP + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/Atmel.XMEGAD_DFP.pdsc + 1.0.29 + true + ATxmega32D4 + + + + Resolved + Fixed + true + + + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.cproj =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.cproj b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.cproj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADCSPI_ver01.cproj (revision 221) @@ -0,0 +1,161 @@ + + + + 2.0 + 7.0 + com.Atmel.AVRGCC8.C + dce6c7e3-ee26-4d79-826b-08594b9ad897 + ATxmega32D4 + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + ADCSPI_ver01 + ADCSPI_ver01 + ADCSPI_ver01 + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + + + + + + + + + + + + + + com.atmel.avrdbg.tool.simulator + + 0x1E9542 + + + + + + com.atmel.avrdbg.tool.simulator + + + Simulator + + + + + + + -mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + True + True + True + True + False + True + True + + + NDEBUG + + + + + %24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\include + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + + + + + -mmcu=atxmega32d4 -B "%24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + True + True + True + True + False + True + True + + + DEBUG + + + + + %24(PackRepoDir)\atmel\XMEGAD_DFP\1.0.29\include + + + Optimize (-O1) + True + True + Default (-g2) + True + + + libm + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADC_7176_2.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADC_7176_2.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADC_7176_2.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/ADC_7176_2.c (revision 221) @@ -0,0 +1,106 @@ +/* + * ADC_7176_2.c + * + * Created: 23/11/15 14:01:02 + * Author: Francisco + */ + +/*! + * \fn test_adc + * \brief Lectura de ID del adc + * + * Lectura esperada: 0x0C94 + * + * Esta funci�n tiene como fin probar la comunicaci�n on el ADC + * +#define ADC_WENbar_bm (1<<7) +#define ADC_RWbar_bm (1<<6) +#define ADC_ADDR_READ_ID 0x07 + * \ +*/ + +#define F_CPU 32000000UL +#include +#include "ADC_7176_2.h" + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + return aux; +} + +inline void test_adc_2(uint8_t* dato){ + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_read_data(dato,ADC_DATASZ); + PORTSPI.OUTSET = SPI_SS_bm; +} +/*! + * \fn adcport_tranceiv + * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + + // Return received data + + return SPIC.DATA; +} + +/*! + * \fn adcport_readdata + * \brief Realiza la lectura de datos en modo de conversi�n continua + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param La direcci�n del puntero a dato + * \return Ninguno s�lo se llena el puntero al dato + */ +inline void adcport_read_data(uint8_t* dato,int j) +{ + + //Env�o del comando de lectura de datos 0x44 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i +#include "Ports.h" +#include "commSPI_ADC.h" + +//ID esperada +//tama�o 16 bits +//Valor 0x0C94 +#define ADC_ID 0x0C94 +#define ADC_RD 0x04 +#define ADC_FILTCON0 0x28 +#define ADC_INTERFMODE 0x02 +#define ADC_DATASZ 3 + +//Definici�n de orden de los bits de habilitaci�n, escritura lectura y direcci�n +#define ADC_WENbar_bm (1<<7) +#define ADC_RWbar_bm (1<<6) +#define ADC_ADDR_READ_ID (0x07) +#define ADC_FILT0_ORDER0_bp 5 +#define ADC_FILT0_ODR0_bp 0 +#define ADC_CONTREAD_bp 7 +#define ADC_WL16_bp 0 + +uint8_t adcport_tranceiv(uint8_t data); +void adcport_read_data(uint8_t* dato,int j); + +void adcport_write_filtcon0(void); +void adcport_write_interfmode(void); + +uint16_t test_adc(void); +void test_adc_2(uint8_t* dato); +void config_adc(void); + +#endif /* ADC_7176_2_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.eep =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.eep b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.eep new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.eep (revision 221) @@ -0,0 +1 @@ +:00000001FF =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.elf =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.elf b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.elf new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.elf (revision 221) Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.hex =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.hex b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.hex new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.hex (revision 221) @@ -0,0 +1,92 @@ +:100000000C94B6000C94C0000C941A020C94C0001E +:100010000C94C0000C94C0000C94C0000C94C00060 +:100020000C94C0000C94C0000C94C0000C94C00050 +:100030000C94C0000C94C0000C94C0000C94C00040 +:100040000C94C0000C94C0000C94C0000C94C00030 +:100050000C94C0000C94C0000C94C0000C94C00020 +:100060000C94C0000C94C0000C94C0000C94C00010 +:100070000C94C0000C94C0000C94C0000C94C00000 +:100080000C94C0000C94C0000C94C0000C940202AC +:100090000C94C0000C94C0000C94C0000C94C000E0 +:1000A0000C94C0000C94C0000C94C0000C94C000D0 +:1000B0000C94C0000C94C0000C94C0000C94C000C0 +:1000C0000C94C0000C94C0000C94C0000C94C000B0 +:1000D0000C94C0000C94C0000C94C0000C94C000A0 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+:1005000056969C93569755969C93559754969C93C4 +:10051000549753969C93539716964C93A0E8B6E045 +:1005200012963C93129753968C93539752968C93B2 +:10053000529751968C93519750968C93A0EEB7E0BA +:1005400093E012969C93129751962C935197509644 +:100550008C9380E4828781858C7F81608187868906 +:10056000887F8260868B089510924100E0E5F0E07C +:10057000808186608083818182FFFDCFE0E5F0E0AD +:10058000818181FFFDCF91E090936000E0E5F0E094 +:1005900086818D7F868388ED84BF90934000808123 +:0A05A0008E7F80830895F894FFCF4A +:00000001FF Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.lss =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.lss b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.lss new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.lss (revision 221) @@ -0,0 +1,1099 @@ + +ADCSPI_ver01.elf: file format elf32-avr + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000005aa 00000000 00000000 00000054 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .data 00000000 00802000 00802000 000005fe 2**0 + CONTENTS, ALLOC, LOAD, DATA + 2 .comment 00000030 00000000 00000000 000005fe 2**0 + CONTENTS, READONLY + 3 .note.gnu.avr.deviceinfo 00000040 00000000 00000000 00000630 2**2 + CONTENTS, READONLY + 4 .debug_aranges 00000138 00000000 00000000 00000670 2**0 + CONTENTS, READONLY, DEBUGGING + 5 .debug_info 000014ca 00000000 00000000 000007a8 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_abbrev 0000064f 00000000 00000000 00001c72 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_line 0000082c 00000000 00000000 000022c1 2**0 + CONTENTS, READONLY, DEBUGGING + 8 .debug_frame 00000288 00000000 00000000 00002af0 2**2 + CONTENTS, READONLY, DEBUGGING + 9 .debug_str 000007d6 00000000 00000000 00002d78 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_loc 0000042d 00000000 00000000 0000354e 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_ranges 000000d8 00000000 00000000 0000397b 2**0 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00000000 <__vectors>: + 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end> + 4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 8: 0c 94 1a 02 jmp 0x434 ; 0x434 <__vector_2> + c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 10: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 14: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 18: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 1c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 20: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 24: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 28: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 2c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 30: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 34: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 38: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 3c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 40: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 44: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 48: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 4c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 50: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 54: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 58: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 5c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 60: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 64: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 68: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 6c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 70: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 74: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 78: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 7c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 80: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 84: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 88: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 8c: 0c 94 02 02 jmp 0x404 ; 0x404 <__vector_35> + 90: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 94: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 98: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 9c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + a8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + ac: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + b8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + bc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + c8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + cc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + d8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + dc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + e8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + ec: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f0: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f4: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + f8: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + fc: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 100: 0c 94 d7 01 jmp 0x3ae ; 0x3ae <__vector_64> + 104: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 108: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 10c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 110: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 114: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 118: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 11c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 120: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 124: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 128: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 12c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 130: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 134: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 138: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 13c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 140: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 144: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 148: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 14c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 150: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 154: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 158: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 15c: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 160: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 164: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + 168: 0c 94 c0 00 jmp 0x180 ; 0x180 <__bad_interrupt> + +0000016c <__ctors_end>: + 16c: 11 24 eor r1, r1 + 16e: 1f be out 0x3f, r1 ; 63 + 170: cf ef ldi r28, 0xFF ; 255 + 172: cd bf out 0x3d, r28 ; 61 + 174: df e2 ldi r29, 0x2F ; 47 + 176: de bf out 0x3e, r29 ; 62 + 178: 0e 94 bd 01 call 0x37a ; 0x37a
+ 17c: 0c 94 d3 02 jmp 0x5a6 ; 0x5a6 <_exit> + +00000180 <__bad_interrupt>: + 180: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> + +00000184 : +#include +#include "ADC_7176_2.h" + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + 184: 80 e1 ldi r24, 0x10 ; 16 + 186: 80 93 46 06 sts 0x0646, r24 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 18a: 87 e4 ldi r24, 0x47 ; 71 + 18c: 80 93 c3 08 sts 0x08C3, r24 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 190: e0 ec ldi r30, 0xC0 ; 192 + 192: f8 e0 ldi r31, 0x08 ; 8 + 194: 82 81 ldd r24, Z+2 ; 0x02 + 196: 88 23 and r24, r24 + 198: ec f7 brge .-6 ; 0x194 + + // Return received data + + return SPIC.DATA; + 19a: e0 ec ldi r30, 0xC0 ; 192 + 19c: f8 e0 ldi r31, 0x08 ; 8 + 19e: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1a0: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1a2: 82 81 ldd r24, Z+2 ; 0x02 + 1a4: 88 23 and r24, r24 + 1a6: ec f7 brge .-6 ; 0x1a2 + + // Return received data + + return SPIC.DATA; + 1a8: e0 ec ldi r30, 0xC0 ; 192 + 1aa: f8 e0 ldi r31, 0x08 ; 8 + 1ac: 23 81 ldd r18, Z+3 ; 0x03 + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + 1ae: 30 e0 ldi r19, 0x00 ; 0 + aux = (aux << 8) | adcport_tranceiv(0); + 1b0: 32 2f mov r19, r18 + 1b2: 22 27 eor r18, r18 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1b4: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1b6: 92 81 ldd r25, Z+2 ; 0x02 + 1b8: 99 23 and r25, r25 + 1ba: ec f7 brge .-6 ; 0x1b6 + + // Return received data + + return SPIC.DATA; + 1bc: 80 91 c3 08 lds r24, 0x08C3 + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + 1c0: 90 e1 ldi r25, 0x10 ; 16 + 1c2: 90 93 45 06 sts 0x0645, r25 + return aux; +} + 1c6: a9 01 movw r20, r18 + 1c8: 48 2b or r20, r24 + 1ca: ca 01 movw r24, r20 + 1cc: 08 95 ret + +000001ce : + * transmision genera clock en el pin "sclk" + * \param La direcci�n del puntero a dato + * \return Ninguno s�lo se llena el puntero al dato + */ +inline void adcport_read_data(uint8_t* dato,int j) +{ + 1ce: 9c 01 movw r18, r24 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1d0: 84 e4 ldi r24, 0x44 ; 68 + 1d2: 80 93 c3 08 sts 0x08C3, r24 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1d6: e0 ec ldi r30, 0xC0 ; 192 + 1d8: f8 e0 ldi r31, 0x08 ; 8 + 1da: 92 81 ldd r25, Z+2 ; 0x02 + 1dc: 99 23 and r25, r25 + 1de: ec f7 brge .-6 ; 0x1da + + // Return received data + + return SPIC.DATA; + 1e0: 80 91 c3 08 lds r24, 0x08C3 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 1ea: d9 01 movw r26, r18 + 1ec: a6 0f add r26, r22 + 1ee: b7 1f adc r27, r23 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1f0: e0 ec ldi r30, 0xC0 ; 192 + 1f2: f8 e0 ldi r31, 0x08 ; 8 + 1f4: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1f6: 92 81 ldd r25, Z+2 ; 0x02 + 1f8: 99 23 and r25, r25 + 1fa: ec f7 brge .-6 ; 0x1f6 + + // Return received data + + return SPIC.DATA; + 1fc: 93 81 ldd r25, Z+3 ; 0x03 + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 206: 08 95 ret + +00000208 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 208: 88 e2 ldi r24, 0x28 ; 40 + 20a: 80 93 c3 08 sts 0x08C3, r24 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 20e: e0 ec ldi r30, 0xC0 ; 192 + 210: f8 e0 ldi r31, 0x08 ; 8 + 212: 82 81 ldd r24, Z+2 ; 0x02 + 214: 88 23 and r24, r24 + 216: ec f7 brge .-6 ; 0x212 + + // Return received data + + return SPIC.DATA; + 218: e0 ec ldi r30, 0xC0 ; 192 + 21a: f8 e0 ldi r31, 0x08 ; 8 + 21c: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 21e: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 220: 82 81 ldd r24, Z+2 ; 0x02 + 222: 88 23 and r24, r24 + 224: ec f7 brge .-6 ; 0x220 + + // Return received data + + return SPIC.DATA; + 226: e0 ec ldi r30, 0xC0 ; 192 + 228: f8 e0 ldi r31, 0x08 ; 8 + 22a: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 22c: 8a e0 ldi r24, 0x0A ; 10 + 22e: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 230: 82 81 ldd r24, Z+2 ; 0x02 + 232: 88 23 and r24, r24 + 234: ec f7 brge .-6 ; 0x230 + + // Return received data + + return SPIC.DATA; + 236: 80 91 c3 08 lds r24, 0x08C3 + 23a: 08 95 ret + +0000023c : + for(int i=0; i + //adcport_write_interfmode(); + PORTSPI.OUTSET = SPI_SS_bm; + 24e: 1d 83 std Y+5, r17 ; 0x05 + +} + 250: df 91 pop r29 + 252: cf 91 pop r28 + 254: 1f 91 pop r17 + 256: 08 95 ret + +00000258 : +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | + 258: 8c ed ldi r24, 0xDC ; 220 + 25a: 80 93 c0 08 sts 0x08C0, r24 + 25e: 08 95 ret + +00000260 : +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + 260: cf 93 push r28 + 262: df 93 push r29 + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRCLR = LOCK_FPGA; + 264: e0 e6 ldi r30, 0x60 ; 96 + 266: f6 e0 ldi r31, 0x06 ; 6 + 268: 22 e0 ldi r18, 0x02 ; 2 + 26a: 22 83 std Z+2, r18 ; 0x02 + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; + 26c: 11 8a std Z+17, r1 ; 0x11 + PORT_FPGA.DIRSET = CLK_FPGA; + 26e: 94 e0 ldi r25, 0x04 ; 4 + 270: 91 83 std Z+1, r25 ; 0x01 + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; + 272: 88 e1 ldi r24, 0x18 ; 24 + 274: 82 8b std Z+18, r24 ; 0x12 + PORT_FPGA.OUTSET = CLK_FPGA; + 276: 95 83 std Z+5, r25 ; 0x05 + + //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + 278: 88 e7 ldi r24, 0x78 ; 120 + 27a: 81 83 std Z+1, r24 ; 0x01 + PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; + 27c: 13 8a std Z+19, r1 ; 0x13 + PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + 27e: 86 83 std Z+6, r24 ; 0x06 + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + 280: a0 e2 ldi r26, 0x20 ; 32 + 282: b6 e0 ldi r27, 0x06 ; 6 + 284: 12 96 adiw r26, 0x02 ; 2 + 286: 9c 93 st X, r25 + 288: 12 97 sbiw r26, 0x02 ; 2 + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + 28a: 80 e1 ldi r24, 0x10 ; 16 + 28c: 52 96 adiw r26, 0x12 ; 18 + 28e: 8c 93 st X, r24 + 290: 52 97 sbiw r26, 0x12 ; 18 + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + 292: c0 e0 ldi r28, 0x00 ; 0 + 294: d6 e0 ldi r29, 0x06 ; 6 + 296: 81 e0 ldi r24, 0x01 ; 1 + 298: 89 83 std Y+1, r24 ; 0x01 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 29a: 8e 83 std Y+6, r24 ; 0x06 + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + 29c: 81 85 ldd r24, Z+9 ; 0x09 + 29e: 83 60 ori r24, 0x03 ; 3 + 2a0: 81 87 std Z+9, r24 ; 0x09 + PORT_FPGA.INT0MASK = LOCK_FPGA; + 2a2: 22 87 std Z+10, r18 ; 0x0a + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + 2a4: 81 89 ldd r24, Z+17 ; 0x11 + 2a6: 88 7f andi r24, 0xF8 ; 248 + 2a8: 81 8b std Z+17, r24 ; 0x11 + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + 2aa: 81 85 ldd r24, Z+9 ; 0x09 + 2ac: 83 7f andi r24, 0xF3 ; 243 + 2ae: 88 60 ori r24, 0x08 ; 8 + 2b0: 19 96 adiw r26, 0x09 ; 9 + 2b2: 8c 93 st X, r24 + 2b4: 19 97 sbiw r26, 0x09 ; 9 + PORT_PPS.INT1MASK = PPS_FPGA; + 2b6: 1b 96 adiw r26, 0x0b ; 11 + 2b8: 9c 93 st X, r25 + 2ba: 1b 97 sbiw r26, 0x0b ; 11 + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; + 2bc: 52 96 adiw r26, 0x12 ; 18 + 2be: 8c 91 ld r24, X + 2c0: 52 97 sbiw r26, 0x12 ; 18 + 2c2: 88 7f andi r24, 0xF8 ; 248 + 2c4: 81 60 ori r24, 0x01 ; 1 + 2c6: 52 96 adiw r26, 0x12 ; 18 + 2c8: 8c 93 st X, r24 +} + 2ca: df 91 pop r29 + 2cc: cf 91 pop r28 + 2ce: 08 95 ret + +000002d0 : + PMIC.CTRL |= level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); + 2d0: 78 94 sei + 2d2: 08 95 ret + +000002d4 : + cli(); +} + +void envio_nibble(uint8_t fpga_dato) +{ + PORT_FPGA.OUTCLR = CLK_FPGA; + 2d4: e0 e6 ldi r30, 0x60 ; 96 + 2d6: f6 e0 ldi r31, 0x06 ; 6 + 2d8: 24 e0 ldi r18, 0x04 ; 4 + 2da: 26 83 std Z+6, r18 ; 0x06 + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) << fpga_salidas_bp); + 2dc: 94 81 ldd r25, Z+4 ; 0x04 + 2de: 38 2f mov r19, r24 + 2e0: 30 7f andi r19, 0xF0 ; 240 + 2e2: 33 0f add r19, r19 + 2e4: 33 0f add r19, r19 + 2e6: 33 0f add r19, r19 + 2e8: 98 73 andi r25, 0x38 ; 56 + 2ea: 93 2b or r25, r19 + 2ec: 94 83 std Z+4, r25 ; 0x04 + PORT_FPGA.OUTSET = CLK_FPGA; + 2ee: 25 83 std Z+5, r18 ; 0x05 + //asm("nop"); + PORT_FPGA.OUTCLR = CLK_FPGA; + 2f0: 26 83 std Z+6, r18 ; 0x06 + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_bp); + 2f2: 94 81 ldd r25, Z+4 ; 0x04 + 2f4: 8f 70 andi r24, 0x0F ; 15 + 2f6: 88 0f add r24, r24 + 2f8: 88 0f add r24, r24 + 2fa: 88 0f add r24, r24 + 2fc: 98 73 andi r25, 0x38 ; 56 + 2fe: 89 2b or r24, r25 + 300: 84 83 std Z+4, r24 ; 0x04 + PORT_FPGA.OUTSET = CLK_FPGA; + 302: 25 83 std Z+5, r18 ; 0x05 + 304: 08 95 ret + +00000306 : + envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + 306: 0f 93 push r16 + 308: 1f 93 push r17 + 30a: cf 93 push r28 + 30c: df 93 push r29 + 30e: ec 01 movw r28, r24 + 310: 8c 01 movw r16, r24 + 312: 0d 5f subi r16, 0xFD ; 253 + 314: 1f 4f sbci r17, 0xFF ; 255 + for(int i=0; i<3 ; i++) + envio_nibble(dato_adc[i]); + 316: 89 91 ld r24, Y+ + 318: 0e 94 6a 01 call 0x2d4 ; 0x2d4 + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + for(int i=0; i<3 ; i++) + 31c: c0 17 cp r28, r16 + 31e: d1 07 cpc r29, r17 + 320: d1 f7 brne .-12 ; 0x316 + envio_nibble(dato_adc[i]); +} + 322: df 91 pop r29 + 324: cf 91 pop r28 + 326: 1f 91 pop r17 + 328: 0f 91 pop r16 + 32a: 08 95 ret + +0000032c : + PORT_FPGA.OUTSET = CLK_FPGA; + +} + +void envio_datos_fpga(void) +{ + 32c: cf 93 push r28 + 32e: df 93 push r29 + 330: cd b7 in r28, 0x3d ; 61 + 332: de b7 in r29, 0x3e ; 62 + 334: 26 97 sbiw r28, 0x06 ; 6 + 336: cd bf out 0x3d, r28 ; 61 + 338: de bf out 0x3e, r29 ; 62 + uint8_t fpga_dato[ADC_DATASZ], aux_dato[ADC_DATASZ] ; + + adcport_read_data(fpga_dato,ADC_DATASZ); + 33a: 63 e0 ldi r22, 0x03 ; 3 + 33c: 70 e0 ldi r23, 0x00 ; 0 + 33e: ce 01 movw r24, r28 + 340: 01 96 adiw r24, 0x01 ; 1 + 342: 0e 94 e7 00 call 0x1ce ; 0x1ce + aux_dato[0] = fpga_dato[0]; + 346: 89 81 ldd r24, Y+1 ; 0x01 + 348: 8c 83 std Y+4, r24 ; 0x04 + aux_dato[1] = fpga_dato[1]; + 34a: 8a 81 ldd r24, Y+2 ; 0x02 + 34c: 8d 83 std Y+5, r24 ; 0x05 + aux_dato[2] = fpga_dato[2]; + 34e: 8b 81 ldd r24, Y+3 ; 0x03 + 350: 8e 83 std Y+6, r24 ; 0x06 + adcport_read_data(fpga_dato,ADC_DATASZ); + 352: 63 e0 ldi r22, 0x03 ; 3 + 354: 70 e0 ldi r23, 0x00 ; 0 + 356: ce 01 movw r24, r28 + 358: 01 96 adiw r24, 0x01 ; 1 + 35a: 0e 94 e7 00 call 0x1ce ; 0x1ce + + envio_dato_adc(aux_dato); + 35e: ce 01 movw r24, r28 + 360: 04 96 adiw r24, 0x04 ; 4 + 362: 0e 94 83 01 call 0x306 ; 0x306 + envio_dato_adc(fpga_dato); + 366: ce 01 movw r24, r28 + 368: 01 96 adiw r24, 0x01 ; 1 + 36a: 0e 94 83 01 call 0x306 ; 0x306 +} + 36e: 26 96 adiw r28, 0x06 ; 6 + 370: cd bf out 0x3d, r28 ; 61 + 372: de bf out 0x3e, r29 ; 62 + 374: df 91 pop r29 + 376: cf 91 pop r28 + 378: 08 95 ret + +0000037a
: + + +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + 37a: 0e 94 3e 02 call 0x47c ; 0x47c + config_sysclock(); + 37e: 0e 94 b4 02 call 0x568 ; 0x568 + config_spiparm(); + 382: 0e 94 2c 01 call 0x258 ; 0x258 + config_fpgaport(); + 386: 0e 94 30 01 call 0x260 ; 0x260 + config_adc(); + 38a: 0e 94 1e 01 call 0x23c ; 0x23c + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + 38e: 84 e0 ldi r24, 0x04 ; 4 + 390: 80 93 a2 00 sts 0x00A2, r24 + habilitar_interrupciones_globales(); + 394: 0e 94 68 01 call 0x2d0 ; 0x2d0 + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + PORTD.OUTSET = PIN6_bm | PIN5_bm; + 398: 00 e6 ldi r16, 0x60 ; 96 + 39a: 16 e0 ldi r17, 0x06 ; 6 + 39c: c0 e6 ldi r28, 0x60 ; 96 + habilitar_interrupciones_globales(); + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + 39e: 0e 94 c2 00 call 0x184 ; 0x184 + 3a2: 84 39 cpi r24, 0x94 ; 148 + 3a4: 9c 40 sbci r25, 0x0C ; 12 + 3a6: d9 f7 brne .-10 ; 0x39e + PORTD.OUTSET = PIN6_bm | PIN5_bm; + 3a8: f8 01 movw r30, r16 + 3aa: c5 83 std Z+5, r28 ; 0x05 + 3ac: f8 cf rjmp .-16 ; 0x39e + +000003ae <__vector_64>: + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + 3ae: 1f 92 push r1 + 3b0: 0f 92 push r0 + 3b2: 0f b6 in r0, 0x3f ; 63 + 3b4: 0f 92 push r0 + 3b6: 11 24 eor r1, r1 + 3b8: 8f 93 push r24 + 3ba: ef 93 push r30 + 3bc: ff 93 push r31 + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + 3be: 80 91 68 06 lds r24, 0x0668 + 3c2: 81 ff sbrs r24, 1 + 3c4: 0c c0 rjmp .+24 ; 0x3de <__vector_64+0x30> + { + PMIC.CTRL |= hab_prioridad_media; + 3c6: e0 ea ldi r30, 0xA0 ; 160 + 3c8: f0 e0 ldi r31, 0x00 ; 0 + 3ca: 82 81 ldd r24, Z+2 ; 0x02 + 3cc: 82 60 ori r24, 0x02 ; 2 + 3ce: 82 83 std Z+2, r24 ; 0x02 + PORT_LOCKOUT.OUTSET = LOCK_OUT; + 3d0: 81 e0 ldi r24, 0x01 ; 1 + 3d2: 80 93 05 06 sts 0x0605, r24 + PORTD.OUTSET = PIN4_bm; + 3d6: 80 e1 ldi r24, 0x10 ; 16 + 3d8: 80 93 65 06 sts 0x0665, r24 + 3dc: 0b c0 rjmp .+22 ; 0x3f4 <__vector_64+0x46> + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + 3de: e0 ea ldi r30, 0xA0 ; 160 + 3e0: f0 e0 ldi r31, 0x00 ; 0 + 3e2: 82 81 ldd r24, Z+2 ; 0x02 + 3e4: 8d 7f andi r24, 0xFD ; 253 + 3e6: 82 83 std Z+2, r24 ; 0x02 + PMIC.CTRL &= ~hab_prioridad_baja; + 3e8: 82 81 ldd r24, Z+2 ; 0x02 + 3ea: 8e 7f andi r24, 0xFE ; 254 + 3ec: 82 83 std Z+2, r24 ; 0x02 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 3ee: 81 e0 ldi r24, 0x01 ; 1 + 3f0: 80 93 06 06 sts 0x0606, r24 + } +} + 3f4: ff 91 pop r31 + 3f6: ef 91 pop r30 + 3f8: 8f 91 pop r24 + 3fa: 0f 90 pop r0 + 3fc: 0f be out 0x3f, r0 ; 63 + 3fe: 0f 90 pop r0 + 400: 1f 90 pop r1 + 402: 18 95 reti + +00000404 <__vector_35>: + +ISR(INT_PPS) +{ + 404: 1f 92 push r1 + 406: 0f 92 push r0 + 408: 0f b6 in r0, 0x3f ; 63 + 40a: 0f 92 push r0 + 40c: 11 24 eor r1, r1 + 40e: 8f 93 push r24 + 410: ef 93 push r30 + 412: ff 93 push r31 + PMIC.CTRL |= hab_prioridad_baja; + 414: e0 ea ldi r30, 0xA0 ; 160 + 416: f0 e0 ldi r31, 0x00 ; 0 + 418: 82 81 ldd r24, Z+2 ; 0x02 + 41a: 81 60 ori r24, 0x01 ; 1 + 41c: 82 83 std Z+2, r24 ; 0x02 + PORTSPI.OUTCLR = SPI_SS_bm; + 41e: 80 e1 ldi r24, 0x10 ; 16 + 420: 80 93 46 06 sts 0x0646, r24 +} + 424: ff 91 pop r31 + 426: ef 91 pop r30 + 428: 8f 91 pop r24 + 42a: 0f 90 pop r0 + 42c: 0f be out 0x3f, r0 ; 63 + 42e: 0f 90 pop r0 + 430: 1f 90 pop r1 + 432: 18 95 reti + +00000434 <__vector_2>: + +ISR(INT_RDY) +{ + 434: 1f 92 push r1 + 436: 0f 92 push r0 + 438: 0f b6 in r0, 0x3f ; 63 + 43a: 0f 92 push r0 + 43c: 11 24 eor r1, r1 + 43e: 2f 93 push r18 + 440: 3f 93 push r19 + 442: 4f 93 push r20 + 444: 5f 93 push r21 + 446: 6f 93 push r22 + 448: 7f 93 push r23 + 44a: 8f 93 push r24 + 44c: 9f 93 push r25 + 44e: af 93 push r26 + 450: bf 93 push r27 + 452: ef 93 push r30 + 454: ff 93 push r31 + envio_datos_fpga(); + 456: 0e 94 96 01 call 0x32c ; 0x32c +} + 45a: ff 91 pop r31 + 45c: ef 91 pop r30 + 45e: bf 91 pop r27 + 460: af 91 pop r26 + 462: 9f 91 pop r25 + 464: 8f 91 pop r24 + 466: 7f 91 pop r23 + 468: 6f 91 pop r22 + 46a: 5f 91 pop r21 + 46c: 4f 91 pop r20 + 46e: 3f 91 pop r19 + 470: 2f 91 pop r18 + 472: 0f 90 pop r0 + 474: 0f be out 0x3f, r0 ; 63 + 476: 0f 90 pop r0 + 478: 1f 90 pop r1 + 47a: 18 95 reti + +0000047c : +#include "commSPI_ADC.h" + +inline void config_puertos(void){ + //Configuracion pines del puerto A: PA7-PA0 + //Pines de entrada y totem_pullup + PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + 47c: e0 e0 ldi r30, 0x00 ; 0 + 47e: f6 e0 ldi r31, 0x06 ; 6 + 480: 8e ef ldi r24, 0xFE ; 254 + 482: 82 83 std Z+2, r24 ; 0x02 + PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; + 484: 88 e1 ldi r24, 0x18 ; 24 + 486: 87 8b std Z+23, r24 ; 0x17 + PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; + 488: 86 8b std Z+22, r24 ; 0x16 + PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; + 48a: 85 8b std Z+21, r24 ; 0x15 + PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; + 48c: 84 8b std Z+20, r24 ; 0x14 + PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; + 48e: 83 8b std Z+19, r24 ; 0x13 + PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; + 490: 82 8b std Z+18, r24 ; 0x12 + PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; + 492: 81 8b std Z+17, r24 ; 0x11 + //Pin de salida A0 + //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n + //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta + //Valor por defecto salida: PA0 = low + PORTA.DIRSET = PIN0_bm; + 494: 21 e0 ldi r18, 0x01 ; 1 + 496: 21 83 std Z+1, r18 ; 0x01 + PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; + 498: 98 e3 ldi r25, 0x38 ; 56 + 49a: 90 8b std Z+16, r25 ; 0x10 + PORTA.OUTCLR = PIN0_bm; + 49c: 26 83 std Z+6, r18 ; 0x06 + + //Configuracion pines del puerto B: PB3-PB0 + //Pines de entrada y totem_pullup + PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + 49e: e0 e2 ldi r30, 0x20 ; 32 + 4a0: f6 e0 ldi r31, 0x06 ; 6 + 4a2: 3f e0 ldi r19, 0x0F ; 15 + 4a4: 32 83 std Z+2, r19 ; 0x02 + PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; + 4a6: 83 8b std Z+19, r24 ; 0x13 + PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; + 4a8: 82 8b std Z+18, r24 ; 0x12 + PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; + 4aa: 81 8b std Z+17, r24 ; 0x11 + PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; + 4ac: 80 8b std Z+16, r24 ; 0x10 + + //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI + //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 + //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. + PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + 4ae: e0 e4 ldi r30, 0x40 ; 64 + 4b0: f6 e0 ldi r31, 0x06 ; 6 + 4b2: 2f e4 ldi r18, 0x4F ; 79 + 4b4: 22 83 std Z+2, r18 ; 0x02 + PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; + 4b6: 86 8b std Z+22, r24 ; 0x16 + PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; + 4b8: 83 8b std Z+19, r24 ; 0x13 + PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; + 4ba: 82 8b std Z+18, r24 ; 0x12 + PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; + 4bc: 81 8b std Z+17, r24 ; 0x11 + PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; + 4be: 80 8b std Z+16, r24 ; 0x10 + //Pines de salida wiredand-pull + //Valor por defecto salida: PC4,PC7 = low + //Valor por defecto salida: PC5 = set + PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; + 4c0: 20 eb ldi r18, 0xB0 ; 176 + 4c2: 21 83 std Z+1, r18 ; 0x01 + PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; + 4c4: 15 8a std Z+21, r1 ; 0x15 + PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; + 4c6: 17 8a std Z+23, r1 ; 0x17 + PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; + 4c8: 14 8a std Z+20, r1 ; 0x14 + PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; + 4ca: 20 e9 ldi r18, 0x90 ; 144 + 4cc: 25 83 std Z+5, r18 ; 0x05 + PORTSPI.OUTCLR = SPI_MOSI_bm; + 4ce: 20 e2 ldi r18, 0x20 ; 32 + 4d0: 26 83 std Z+6, r18 ; 0x06 + //Configuracion pines del puerto D: PD7-PD0 + //Pines de entrada y totem_pullup: PIN7 y PIN0 + //NOTA + //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO + //NOTA FIN + PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; + 4d2: a0 e6 ldi r26, 0x60 ; 96 + 4d4: b6 e0 ldi r27, 0x06 ; 6 + 4d6: 27 e8 ldi r18, 0x87 ; 135 + 4d8: 12 96 adiw r26, 0x02 ; 2 + 4da: 2c 93 st X, r18 + 4dc: 12 97 sbiw r26, 0x02 ; 2 + PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; + 4de: 57 96 adiw r26, 0x17 ; 23 + 4e0: 8c 93 st X, r24 + 4e2: 57 97 sbiw r26, 0x17 ; 23 + PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; + 4e4: 50 96 adiw r26, 0x10 ; 16 + 4e6: 8c 93 st X, r24 + 4e8: 50 97 sbiw r26, 0x10 ; 16 + //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga + PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + 4ea: 20 e1 ldi r18, 0x10 ; 16 + 4ec: 52 96 adiw r26, 0x12 ; 18 + 4ee: 2c 93 st X, r18 + 4f0: 52 97 sbiw r26, 0x12 ; 18 + PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 4f2: 51 96 adiw r26, 0x11 ; 17 + 4f4: 2c 93 st X, r18 + 4f6: 51 97 sbiw r26, 0x11 ; 17 + //Pines de salida tipo wired-and-pull + //Valor por defecto PD6, PD5, PD4, PD3 = low + PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 4f8: 48 e7 ldi r20, 0x78 ; 120 + 4fa: 11 96 adiw r26, 0x01 ; 1 + 4fc: 4c 93 st X, r20 + 4fe: 11 97 sbiw r26, 0x01 ; 1 + PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; + 500: 56 96 adiw r26, 0x16 ; 22 + 502: 9c 93 st X, r25 + 504: 56 97 sbiw r26, 0x16 ; 22 + PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; + 506: 55 96 adiw r26, 0x15 ; 21 + 508: 9c 93 st X, r25 + 50a: 55 97 sbiw r26, 0x15 ; 21 + PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; + 50c: 54 96 adiw r26, 0x14 ; 20 + 50e: 9c 93 st X, r25 + 510: 54 97 sbiw r26, 0x14 ; 20 + PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; + 512: 53 96 adiw r26, 0x13 ; 19 + 514: 9c 93 st X, r25 + 516: 53 97 sbiw r26, 0x13 ; 19 + PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 518: 16 96 adiw r26, 0x06 ; 6 + 51a: 4c 93 st X, r20 + + //Configuracion pines del puerto E: PE3-PE0 + //Pines de entrada y totem_pullup: PIN3 - PIN0 + PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + 51c: a0 e8 ldi r26, 0x80 ; 128 + 51e: b6 e0 ldi r27, 0x06 ; 6 + 520: 12 96 adiw r26, 0x02 ; 2 + 522: 3c 93 st X, r19 + 524: 12 97 sbiw r26, 0x02 ; 2 + PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; + 526: 53 96 adiw r26, 0x13 ; 19 + 528: 8c 93 st X, r24 + 52a: 53 97 sbiw r26, 0x13 ; 19 + PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; + 52c: 52 96 adiw r26, 0x12 ; 18 + 52e: 8c 93 st X, r24 + 530: 52 97 sbiw r26, 0x12 ; 18 + PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; + 532: 51 96 adiw r26, 0x11 ; 17 + 534: 8c 93 st X, r24 + 536: 51 97 sbiw r26, 0x11 ; 17 + PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; + 538: 50 96 adiw r26, 0x10 ; 16 + 53a: 8c 93 st X, r24 + + //Configuracion pines del puerto R: PR1-PR0 + //Pines de entrada y totem_pulldown: PIN0 + PORTR.DIRCLR = PIN1_bm| PIN0_bm; + 53c: a0 ee ldi r26, 0xE0 ; 224 + 53e: b7 e0 ldi r27, 0x07 ; 7 + 540: 93 e0 ldi r25, 0x03 ; 3 + 542: 12 96 adiw r26, 0x02 ; 2 + 544: 9c 93 st X, r25 + 546: 12 97 sbiw r26, 0x02 ; 2 + PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 548: 51 96 adiw r26, 0x11 ; 17 + 54a: 2c 93 st X, r18 + 54c: 51 97 sbiw r26, 0x11 ; 17 + //Pines de entrada y totem_pulldup:PIN1 + PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + 54e: 50 96 adiw r26, 0x10 ; 16 + 550: 8c 93 st X, r24 + + //Configuraci�n como interrupci�n del pin SPI_MISO_RDY + + PORTSPI.INT0MASK = SPI_MISO_bm; + 552: 80 e4 ldi r24, 0x40 ; 64 + 554: 82 87 std Z+10, r24 ; 0x0a + PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; + 556: 81 85 ldd r24, Z+9 ; 0x09 + 558: 8c 7f andi r24, 0xFC ; 252 + 55a: 81 60 ori r24, 0x01 ; 1 + 55c: 81 87 std Z+9, r24 ; 0x09 + PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + 55e: 86 89 ldd r24, Z+22 ; 0x16 + 560: 88 7f andi r24, 0xF8 ; 248 + 562: 82 60 ori r24, 0x02 ; 2 + 564: 86 8b std Z+22, r24 ; 0x16 + 566: 08 95 ret + +00000568 : +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + +CLK_PSCTRL = ((0< +while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */ + 57c: e0 e5 ldi r30, 0x50 ; 80 + 57e: f0 e0 ldi r31, 0x00 ; 0 + 580: 81 81 ldd r24, Z+1 ; 0x01 + 582: 81 ff sbrs r24, 1 + 584: fd cf rjmp .-6 ; 0x580 +DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ + 586: 91 e0 ldi r25, 0x01 ; 1 + 588: 90 93 60 00 sts 0x0060, r25 +OSC.DFLLCTRL &= 0xFD; //Habilito calibraci�n interna mediante reloj de 32K + 58c: e0 e5 ldi r30, 0x50 ; 80 + 58e: f0 e0 ldi r31, 0x00 ; 0 + 590: 86 81 ldd r24, Z+6 ; 0x06 + 592: 8d 7f andi r24, 0xFD ; 253 + 594: 86 83 std Z+6, r24 ; 0x06 +CCP = CCP_IOREG_gc; /* Disable register security for clock update */ + 596: 88 ed ldi r24, 0xD8 ; 216 + 598: 84 bf out 0x34, r24 ; 52 +CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */ + 59a: 90 93 40 00 sts 0x0040, r25 +OSC.CTRL &= ~OSC_RC2MEN_bm; + 59e: 80 81 ld r24, Z + 5a0: 8e 7f andi r24, 0xFE ; 254 + 5a2: 80 83 st Z, r24 + 5a4: 08 95 ret + +000005a6 <_exit>: + 5a6: f8 94 cli + +000005a8 <__stop_program>: + 5a8: ff cf rjmp .-2 ; 0x5a8 <__stop_program> Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.map =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.map b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.map new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.map (revision 221) @@ -0,0 +1,592 @@ +Archive member included to satisfy reference by file (symbol) + +c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o (exit) + +Discarded input sections + + .data 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + .bss 0x00000000 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + .text 0x00000000 0x0 ADC_7176_2.o + .data 0x00000000 0x0 ADC_7176_2.o + .bss 0x00000000 0x0 ADC_7176_2.o + .text.test_adc_2 + 0x00000000 0x3e ADC_7176_2.o + .text.adcport_tranceiv + 0x00000000 0x14 ADC_7176_2.o + .text.adcport_write_interfmode + 0x00000000 0x34 ADC_7176_2.o + .text 0x00000000 0x0 commSPI_ADC.o + .data 0x00000000 0x0 commSPI_ADC.o + .bss 0x00000000 0x0 commSPI_ADC.o + .text 0x00000000 0x0 fpga_port.o + .data 0x00000000 0x0 fpga_port.o + .bss 0x00000000 0x0 fpga_port.o + .text.habilitar_interrupciones + 0x00000000 0xc fpga_port.o + .text.deshabilitar_interrupciones_globales + 0x00000000 0x4 fpga_port.o + .text 0x00000000 0x0 main.o + .data 0x00000000 0x0 main.o + .bss 0x00000000 0x0 main.o + .text 0x00000000 0x0 Ports.o + .data 0x00000000 0x0 Ports.o + .bss 0x00000000 0x0 Ports.o + .text 0x00000000 0x0 sys_clock.o + .data 0x00000000 0x0 sys_clock.o + .bss 0x00000000 0x0 sys_clock.o + .text 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .data 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .bss 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.mul + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.div + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.prologue + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.builtins + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.fmul + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + .text.libgcc.fixed + 0x00000000 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + +Memory Configuration + +Name Origin Length Attributes +text 0x00000000 0x00100000 xr +data 0x00802000 0x0000ffa0 rw !x +eeprom 0x00810000 0x00010000 rw !x +fuse 0x00820000 0x00000400 rw !x +lock 0x00830000 0x00000400 rw !x +signature 0x00840000 0x00000400 rw !x +user_signatures 0x00850000 0x00000400 rw !x +*default* 0x00000000 0xffffffff + +Linker script and memory map + +LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o +LOAD ADC_7176_2.o +LOAD commSPI_ADC.o +LOAD fpga_port.o +LOAD main.o +LOAD Ports.o +LOAD sys_clock.o +START GROUP +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a +END GROUP +START GROUP +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libm.a +LOAD c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/../../../../avr/lib/avrxmega2\libc.a +LOAD C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2\libatxmega32d4.a +END GROUP + +.hash + *(.hash) + +.dynsym + *(.dynsym) + +.dynstr + *(.dynstr) + +.gnu.version + *(.gnu.version) + +.gnu.version_d + *(.gnu.version_d) + +.gnu.version_r + *(.gnu.version_r) + +.rel.init + *(.rel.init) + +.rela.init + *(.rela.init) + +.rel.text + *(.rel.text) + *(.rel.text.*) + *(.rel.gnu.linkonce.t*) + +.rela.text + *(.rela.text) + *(.rela.text.*) + *(.rela.gnu.linkonce.t*) + +.rel.fini + *(.rel.fini) + +.rela.fini + *(.rela.fini) + +.rel.rodata + *(.rel.rodata) + *(.rel.rodata.*) + *(.rel.gnu.linkonce.r*) + +.rela.rodata + *(.rela.rodata) + *(.rela.rodata.*) + *(.rela.gnu.linkonce.r*) + +.rel.data + *(.rel.data) + *(.rel.data.*) + *(.rel.gnu.linkonce.d*) + +.rela.data + *(.rela.data) + *(.rela.data.*) + *(.rela.gnu.linkonce.d*) + +.rel.ctors + *(.rel.ctors) + +.rela.ctors + *(.rela.ctors) + +.rel.dtors + *(.rel.dtors) + +.rela.dtors + *(.rela.dtors) + +.rel.got + *(.rel.got) + +.rela.got + *(.rela.got) + +.rel.bss + *(.rel.bss) + +.rela.bss + *(.rela.bss) + +.rel.plt + *(.rel.plt) + +.rela.plt + *(.rela.plt) + +.text 0x00000000 0x5aa + *(.vectors) + .vectors 0x00000000 0x16c C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x00000000 __vector_default + 0x00000000 __vectors + *(.vectors) + *(.progmem.gcc*) + 0x0000016c . = ALIGN (0x2) + 0x0000016c __trampolines_start = . + *(.trampolines) + .trampolines 0x0000016c 0x0 linker stubs + *(.trampolines*) + 0x0000016c __trampolines_end = . + *(.progmem*) + 0x0000016c . = ALIGN (0x2) + *(.jumptables) + *(.jumptables*) + *(.lowtext) + *(.lowtext*) + 0x0000016c __ctors_start = . + *(.ctors) + 0x0000016c __ctors_end = . + 0x0000016c __dtors_start = . + *(.dtors) + 0x0000016c __dtors_end = . + SORT(*)(.ctors) + SORT(*)(.dtors) + *(.init0) + .init0 0x0000016c 0x0 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x0000016c __init + *(.init0) + *(.init1) + *(.init1) + *(.init2) + .init2 0x0000016c 0xc C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + *(.init2) + *(.init3) + *(.init3) + *(.init4) + *(.init4) + *(.init5) + *(.init5) + *(.init6) + *(.init6) + *(.init7) + *(.init7) + *(.init8) + *(.init8) + *(.init9) + .init9 0x00000178 0x8 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + *(.init9) + *(.text) + .text 0x00000180 0x4 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + 0x00000180 __vector_38 + 0x00000180 __vector_22 + 0x00000180 __vector_63 + 0x00000180 __vector_28 + 0x00000180 __vector_67 + 0x00000180 __vector_1 + 0x00000180 __vector_32 + 0x00000180 __vector_75 + 0x00000180 __vector_71 + 0x00000180 __vector_34 + 0x00000180 __vector_62 + 0x00000180 __vector_77 + 0x00000180 __vector_24 + 0x00000180 __vector_12 + 0x00000180 __vector_55 + 0x00000180 __vector_69 + 0x00000180 __vector_81 + 0x00000180 __vector_90 + 0x00000180 __vector_46 + 0x00000180 __bad_interrupt + 0x00000180 __vector_72 + 0x00000180 __vector_6 + 0x00000180 __vector_31 + 0x00000180 __vector_78 + 0x00000180 __vector_74 + 0x00000180 __vector_39 + 0x00000180 __vector_3 + 0x00000180 __vector_23 + 0x00000180 __vector_68 + 0x00000180 __vector_30 + 0x00000180 __vector_73 + 0x00000180 __vector_45 + 0x00000180 __vector_25 + 0x00000180 __vector_61 + 0x00000180 __vector_11 + 0x00000180 __vector_54 + 0x00000180 __vector_13 + 0x00000180 __vector_17 + 0x00000180 __vector_19 + 0x00000180 __vector_56 + 0x00000180 __vector_7 + 0x00000180 __vector_49 + 0x00000180 __vector_41 + 0x00000180 __vector_86 + 0x00000180 __vector_88 + 0x00000180 __vector_43 + 0x00000180 __vector_27 + 0x00000180 __vector_5 + 0x00000180 __vector_33 + 0x00000180 __vector_76 + 0x00000180 __vector_47 + 0x00000180 __vector_52 + 0x00000180 __vector_37 + 0x00000180 __vector_89 + 0x00000180 __vector_4 + 0x00000180 __vector_44 + 0x00000180 __vector_82 + 0x00000180 __vector_51 + 0x00000180 __vector_9 + 0x00000180 __vector_21 + 0x00000180 __vector_15 + 0x00000180 __vector_66 + 0x00000180 __vector_36 + 0x00000180 __vector_79 + 0x00000180 __vector_58 + 0x00000180 __vector_70 + 0x00000180 __vector_83 + 0x00000180 __vector_29 + 0x00000180 __vector_60 + 0x00000180 __vector_40 + 0x00000180 __vector_85 + 0x00000180 __vector_8 + 0x00000180 __vector_26 + 0x00000180 __vector_48 + 0x00000180 __vector_80 + 0x00000180 __vector_14 + 0x00000180 __vector_84 + 0x00000180 __vector_57 + 0x00000180 __vector_53 + 0x00000180 __vector_10 + 0x00000180 __vector_50 + 0x00000180 __vector_16 + 0x00000180 __vector_59 + 0x00000180 __vector_18 + 0x00000180 __vector_20 + 0x00000180 __vector_42 + 0x00000180 __vector_87 + 0x00000180 __vector_65 + 0x00000184 . = ALIGN (0x2) + *(.text.*) + .text.test_adc + 0x00000184 0x4a ADC_7176_2.o + 0x00000184 test_adc + .text.adcport_read_data + 0x000001ce 0x3a ADC_7176_2.o + 0x000001ce adcport_read_data + .text.adcport_write_filtcon0 + 0x00000208 0x34 ADC_7176_2.o + 0x00000208 adcport_write_filtcon0 + .text.config_adc + 0x0000023c 0x1c ADC_7176_2.o + 0x0000023c config_adc + .text.config_spiparm + 0x00000258 0x8 commSPI_ADC.o + 0x00000258 config_spiparm + .text.config_fpgaport + 0x00000260 0x70 fpga_port.o + 0x00000260 config_fpgaport + .text.habilitar_interrupciones_globales + 0x000002d0 0x4 fpga_port.o + 0x000002d0 habilitar_interrupciones_globales + .text.envio_nibble + 0x000002d4 0x32 fpga_port.o + 0x000002d4 envio_nibble + .text.envio_dato_adc + 0x00000306 0x26 fpga_port.o + 0x00000306 envio_dato_adc + .text.envio_datos_fpga + 0x0000032c 0x4e fpga_port.o + 0x0000032c envio_datos_fpga + .text.main 0x0000037a 0x34 main.o + 0x0000037a main + .text.__vector_64 + 0x000003ae 0x56 main.o + 0x000003ae __vector_64 + .text.__vector_35 + 0x00000404 0x30 main.o + 0x00000404 __vector_35 + .text.__vector_2 + 0x00000434 0x48 main.o + 0x00000434 __vector_2 + .text.config_puertos + 0x0000047c 0xec Ports.o + 0x0000047c config_puertos + .text.config_sysclock + 0x00000568 0x3e sys_clock.o + 0x00000568 config_sysclock + 0x000005a6 . = ALIGN (0x2) + *(.fini9) + .fini9 0x000005a6 0x0 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + 0x000005a6 _exit + 0x000005a6 exit + *(.fini9) + *(.fini8) + *(.fini8) + *(.fini7) + *(.fini7) + *(.fini6) + *(.fini6) + *(.fini5) + *(.fini5) + *(.fini4) + *(.fini4) + *(.fini3) + *(.fini3) + *(.fini2) + *(.fini2) + *(.fini1) + *(.fini1) + *(.fini0) + .fini0 0x000005a6 0x4 c:/program files (x86)/atmel/studio/7.0/toolchain/avr8/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.9.2/avrxmega2\libgcc.a(_exit.o) + *(.fini0) + 0x000005aa _etext = . + +.data 0x00802000 0x0 load address 0x000005aa + 0x00802000 PROVIDE (__data_start, .) + *(.data) + *(.data*) + *(.rodata) + *(.rodata*) + *(.gnu.linkonce.d*) + 0x00802000 . = ALIGN (0x2) + 0x00802000 _edata = . + 0x00802000 PROVIDE (__data_end, .) + +.bss 0x00802000 0x0 + 0x00802000 PROVIDE (__bss_start, .) + *(.bss) + *(.bss*) + *(COMMON) + 0x00802000 PROVIDE (__bss_end, .) + 0x000005aa __data_load_start = LOADADDR (.data) + 0x000005aa __data_load_end = (__data_load_start + SIZEOF (.data)) + +.noinit 0x00802000 0x0 + 0x00802000 PROVIDE (__noinit_start, .) + *(.noinit*) + 0x00802000 PROVIDE (__noinit_end, .) + 0x00802000 _end = . + 0x00802000 PROVIDE (__heap_start, .) + +.eeprom 0x00810000 0x0 + *(.eeprom*) + 0x00810000 __eeprom_end = . + +.fuse + *(.fuse) + *(.lfuse) + *(.hfuse) + *(.efuse) + +.lock + *(.lock*) + +.signature + *(.signature*) + +.user_signatures + *(.user_signatures*) + +.stab + *(.stab) + +.stabstr + *(.stabstr) + +.stab.excl + *(.stab.excl) + +.stab.exclstr + *(.stab.exclstr) + +.stab.index + *(.stab.index) + +.stab.indexstr + *(.stab.indexstr) + +.comment 0x00000000 0x30 + *(.comment) + .comment 0x00000000 0x30 ADC_7176_2.o + 0x31 (size before relaxing) + .comment 0x00000030 0x31 commSPI_ADC.o + .comment 0x00000030 0x31 fpga_port.o + .comment 0x00000030 0x31 main.o + .comment 0x00000030 0x31 Ports.o + .comment 0x00000030 0x31 sys_clock.o + +.note.gnu.avr.deviceinfo + 0x00000000 0x40 + .note.gnu.avr.deviceinfo + 0x00000000 0x40 C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/XMEGAD_DFP/1.0.29/gcc/dev/atxmega32d4/avrxmega2/crtatxmega32d4.o + +.note.gnu.build-id + *(.note.gnu.build-id) + +.debug + *(.debug) + +.line + *(.line) + +.debug_srcinfo + *(.debug_srcinfo) + +.debug_sfnames + *(.debug_sfnames) + +.debug_aranges 0x00000000 0x138 + *(.debug_aranges) + .debug_aranges + 0x00000000 0x50 ADC_7176_2.o + .debug_aranges + 0x00000050 0x20 commSPI_ADC.o + .debug_aranges + 0x00000070 0x50 fpga_port.o + .debug_aranges + 0x000000c0 0x38 main.o + .debug_aranges + 0x000000f8 0x20 Ports.o + .debug_aranges + 0x00000118 0x20 sys_clock.o + +.debug_pubnames + *(.debug_pubnames) + +.debug_info 0x00000000 0x14ca + *(.debug_info .gnu.linkonce.wi.*) + .debug_info 0x00000000 0x53c ADC_7176_2.o + .debug_info 0x0000053c 0xf0 commSPI_ADC.o + .debug_info 0x0000062c 0x57a fpga_port.o + .debug_info 0x00000ba6 0x426 main.o + .debug_info 0x00000fcc 0x2ab Ports.o + .debug_info 0x00001277 0x253 sys_clock.o + +.debug_abbrev 0x00000000 0x64f + *(.debug_abbrev) + .debug_abbrev 0x00000000 0x1d0 ADC_7176_2.o + .debug_abbrev 0x000001d0 0x83 commSPI_ADC.o + .debug_abbrev 0x00000253 0x18c fpga_port.o + .debug_abbrev 0x000003df 0x10d main.o + .debug_abbrev 0x000004ec 0xaa Ports.o + .debug_abbrev 0x00000596 0xb9 sys_clock.o + +.debug_line 0x00000000 0x82c + *(.debug_line .debug_line.* .debug_line_end) + .debug_line 0x00000000 0x1cc ADC_7176_2.o + .debug_line 0x000001cc 0x101 commSPI_ADC.o + .debug_line 0x000002cd 0x19c fpga_port.o + .debug_line 0x00000469 0x188 main.o + .debug_line 0x000005f1 0x12c Ports.o + .debug_line 0x0000071d 0x10f sys_clock.o + +.debug_frame 0x00000000 0x288 + *(.debug_frame) + .debug_frame 0x00000000 0x94 ADC_7176_2.o + .debug_frame 0x00000094 0x24 commSPI_ADC.o + .debug_frame 0x000000b8 0xb4 fpga_port.o + .debug_frame 0x0000016c 0xd4 main.o + .debug_frame 0x00000240 0x24 Ports.o + .debug_frame 0x00000264 0x24 sys_clock.o + +.debug_str 0x00000000 0x7d6 + *(.debug_str) + .debug_str 0x00000000 0x2c0 ADC_7176_2.o + 0x303 (size before relaxing) + .debug_str 0x000002c0 0x22 commSPI_ADC.o + 0x1cc (size before relaxing) + .debug_str 0x000002e2 0x34d fpga_port.o + 0x5e0 (size before relaxing) + .debug_str 0x0000062f 0x53 main.o + 0x3cc (size before relaxing) + .debug_str 0x00000682 0xd Ports.o + 0x3f5 (size before relaxing) + .debug_str 0x0000068f 0x147 sys_clock.o + 0x2ff (size before relaxing) + +.debug_loc 0x00000000 0x42d + *(.debug_loc) + .debug_loc 0x00000000 0x138 ADC_7176_2.o + .debug_loc 0x00000138 0x17e fpga_port.o + .debug_loc 0x000002b6 0x177 main.o + +.debug_macinfo + *(.debug_macinfo) + +.debug_weaknames + *(.debug_weaknames) + +.debug_funcnames + *(.debug_funcnames) + +.debug_typenames + *(.debug_typenames) + +.debug_varnames + *(.debug_varnames) + +.debug_pubtypes + *(.debug_pubtypes) + +.debug_ranges 0x00000000 0xd8 + *(.debug_ranges) + .debug_ranges 0x00000000 0x40 ADC_7176_2.o + .debug_ranges 0x00000040 0x10 commSPI_ADC.o + .debug_ranges 0x00000050 0x40 fpga_port.o + .debug_ranges 0x00000090 0x28 main.o + .debug_ranges 0x000000b8 0x10 Ports.o + .debug_ranges 0x000000c8 0x10 sys_clock.o + +.debug_macro + *(.debug_macro) +OUTPUT(ADCSPI_ver01.elf elf32-avr) +LOAD linker stubs Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.srec =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.srec b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.srec new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADCSPI_ver01.srec (revision 221) @@ -0,0 +1,93 @@ +S01400004144435350495F76657230312E737265634F +S11300000C94B6000C94C0000C941A020C94C0001A +S11300100C94C0000C94C0000C94C0000C94C0005C +S11300200C94C0000C94C0000C94C0000C94C0004C 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+S1130450BF93EF93FF930E949601FF91EF91BF9199 +S1130460AF919F918F917F916F915F914F913F9148 +S11304702F910F900FBE0F901F901895E0E0F6E0BB +S11304808EEF828388E1878B868B858B848B838B2D +S1130490828B818B21E0218398E3908B2683E0E299 +S11304A0F6E03FE03283838B828B818B808BE0E4A8 +S11304B0F6E02FE42283868B838B828B818B808B67 +S11304C020EB2183158A178A148A20E9258320E2E8 +S11304D02683A0E6B6E027E812962C931297579647 +S11304E08C93579750968C93509720E152962C9367 +S11304F0529751962C93519748E711964C93119724 +S113050056969C93569755969C93559754969C93C0 +S1130510549753969C93539716964C93A0E8B6E041 +S113052012963C93129753968C93539752968C93AE +S1130530529751968C93519750968C93A0EEB7E0B6 +S113054093E012969C93129751962C935197509640 +S11305508C9380E4828781858C7F81608187868902 +S1130560887F8260868B089510924100E0E5F0E078 +S1130570808186608083818182FFFDCFE0E5F0E0A9 +S1130580818181FFFDCF91E090936000E0E5F0E090 +S113059086818D7F868388ED84BF9093400080811F +S10D05A08E7F80830895F894FFCF46 +S9030000FC Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADC_7176_2.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADC_7176_2.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADC_7176_2.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/ADC_7176_2.d (revision 221) @@ -0,0 +1,44 @@ +ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Makefile =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Makefile b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Makefile new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Makefile (revision 221) @@ -0,0 +1,164 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../ADC_7176_2.c \ +../commSPI_ADC.c \ +../fpga_port.c \ +../main.c \ +../Ports.c \ +../sys_clock.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +ADC_7176_2.o \ +commSPI_ADC.o \ +fpga_port.o \ +main.o \ +Ports.o \ +sys_clock.o + +OBJS_AS_ARGS += \ +ADC_7176_2.o \ +commSPI_ADC.o \ +fpga_port.o \ +main.o \ +Ports.o \ +sys_clock.o + +C_DEPS += \ +ADC_7176_2.d \ +commSPI_ADC.d \ +fpga_port.d \ +main.d \ +Ports.d \ +sys_clock.d + +C_DEPS_AS_ARGS += \ +ADC_7176_2.d \ +commSPI_ADC.d \ +fpga_port.d \ +main.d \ +Ports.d \ +sys_clock.d + +OUTPUT_FILE_PATH +=ADCSPI_ver01.elf + +OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_ver01.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= + + +# AVR32/GNU C Compiler + + + + + + + + + + + + + +./%.o: .././%.c + @echo Building file: $< + @echo Invoking: AVR/GNU C Compiler : 4.9.2 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include" -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: AVR/GNU Linker : 4.9.2 + $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_ver01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\gcc\dev\atxmega32d4" + @echo Finished building target: $@ + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.hex" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_ver01.elf" "ADCSPI_ver01.eep" || exit 0 + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_ver01.elf" > "ADCSPI_ver01.lss" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_ver01.elf" "ADCSPI_ver01.srec" + "C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_ver01.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "ADCSPI_ver01.elf" "ADCSPI_ver01.a" "ADCSPI_ver01.hex" "ADCSPI_ver01.lss" "ADCSPI_ver01.eep" "ADCSPI_ver01.map" "ADCSPI_ver01.srec" "ADCSPI_ver01.usersignatures" + \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Ports.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Ports.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Ports.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/Ports.d (revision 221) @@ -0,0 +1,42 @@ +Ports.d Ports.o: .././Ports.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/commSPI_ADC.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/commSPI_ADC.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/commSPI_ADC.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/commSPI_ADC.d (revision 221) @@ -0,0 +1,42 @@ +commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././commSPI_ADC.h .././Ports.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././commSPI_ADC.h: + +.././Ports.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/fpga_port.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/fpga_port.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/fpga_port.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/fpga_port.d (revision 221) @@ -0,0 +1,50 @@ +fpga_port.d fpga_port.o: .././fpga_port.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/main.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/main.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/main.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/main.d (revision 221) @@ -0,0 +1,52 @@ +main.d main.o: .././main.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././sys_clock.h .././ADC_7176_2.h .././commSPI_ADC.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././sys_clock.h: + +.././ADC_7176_2.h: + +.././commSPI_ADC.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\interrupt.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/makedep.mk =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/makedep.mk b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/makedep.mk new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/makedep.mk (revision 221) @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit or delete the file +################################################################################ + +ADC_7176_2.c + +commSPI_ADC.c + +fpga_port.c + +main.c + +Ports.c + +sys_clock.c + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/sys_clock.d =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/sys_clock.d b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/sys_clock.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Debug/sys_clock.d (revision 221) @@ -0,0 +1,37 @@ +sys_clock.d sys_clock.o: .././sys_clock.c \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h \ + C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\lib\gcc\avr\4.9.2\include\stdint.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\stdint.h: + +C:\Program\ Files\ (x86)\Atmel\Studio\7.0\Packs\atmel\XMEGAD_DFP\1.0.29\include/avr/iox32d4.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\studio\7.0\toolchain\avr8\avr8-gnu-toolchain\avr\include\avr\lock.h: Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.c (revision 221) @@ -0,0 +1,116 @@ +/* + * Ports.c + * + * Created: 23/11/15 13:57:48 + * Author: Francisco + */ + +/*! + * \fn config_puertos + * \brief Configuraci�n de todos los pines de I/O a usarse + * para la prueba. Para el firmware final se deben dejar de configurar en este segmento + * los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo. + * Los criterios de asignaci�n de control: + * Pullup: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si + * Se sabe que la entrada ser� casi siempre alta. + * Pulldown: Para evitar ruido se env�a a una tensi�n conocida. De preferencia si + * Se sabe que la entrada ser� casi siempre baja. + * WiredAndpull: Para evitar cortos de una salida al exterior del board. + * Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board). + * \ +*/ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" +#include "commSPI_ADC.h" + +inline void config_puertos(void){ + //Configuracion pines del puerto A: PA7-PA0 + //Pines de entrada y totem_pullup + PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; + //Pin de salida A0 + //Wired AND. Esto pues podr� irse a alta por defecto y si existe una tensi�n + //La l�nea tendr� el valor de tensi�n externa pero si es entrada con impedancia alta leer� el valor en alta + //Valor por defecto salida: PA0 = low + PORTA.DIRSET = PIN0_bm; + PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTA.OUTCLR = PIN0_bm; + + //Configuracion pines del puerto B: PB3-PB0 + //Pines de entrada y totem_pullup + PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI + //Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 + //Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. + PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; + //Pines de salida wiredand-pull + //Valor por defecto salida: PC4,PC7 = low + //Valor por defecto salida: PC5 = set + PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; + PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; + PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; + PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; + PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; + PORTSPI.OUTCLR = SPI_MOSI_bm; + + //Configuracion pines del puerto D: PD7-PD0 + //Pines de entrada y totem_pullup: PIN7 y PIN0 + //NOTA + //PARA EL FW FINAL REVISAR SI PD2 SER� ENTRADA O NO + //NOTA FIN + PORTD.DIRCLR = PIN7_bm | PIN2_bm | PIN1_bm| PIN0_bm; + PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; + PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; + //Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas ser�n entradas provenientes de la fpga + PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + //Pines de salida tipo wired-and-pull + //Valor por defecto PD6, PD5, PD4, PD3 = low + PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + PORTD.PIN6CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN5CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.PIN3CTRL = PORT_OPC_WIREDANDPULL_gc; + PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + + //Configuracion pines del puerto E: PE3-PE0 + //Pines de entrada y totem_pullup: PIN3 - PIN0 + PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; + PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuracion pines del puerto R: PR1-PR0 + //Pines de entrada y totem_pulldown: PIN0 + PORTR.DIRCLR = PIN1_bm| PIN0_bm; + PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + //Pines de entrada y totem_pulldup:PIN1 + PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + + //Configuraci�n como interrupci�n del pin SPI_MISO_RDY + + PORTSPI.INT0MASK = SPI_MISO_bm; + PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; + PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + +} \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.h b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/Ports.h (revision 221) @@ -0,0 +1,21 @@ +/* + * Ports.h + * + * Created: 23/11/15 13:55:28 + * Author: Francisco + */ + + +#ifndef PORTS_H_ +#define PORTS_H_ + +#define F_CPU 32000000UL +#include + +#define INT_RDY PORTC_INT0_vect + +void config_puertos(void); + + + +#endif /* PORTS_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.c (revision 221) @@ -0,0 +1,31 @@ +/* + * commSPI_ADC.c + * + * Created: 23/11/15 14:08:25 + * Author: Francisco + */ + + +#define F_CPU 32000000UL +#include +#include "commSPI_ADC.h" + +/*! + * \fn config_spiparm + * \brief Configuraci�n de los par�metros de reloj SPI + * + * fspi = fper/2 = fcpu/2 = 16MHz + * + * En nuestra aplicaci�n final el reloj ser� externo, de 16MHz. Por lo que se tendr� que realizar una + * nueva evaluaci�n + * \ +*/ +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_CLK2X_bm | SPI_ENABLE_bm | SPI_MASTER_bm | + SPI_MODE1_bm | SPI_MODE0_bm) & ~SPI_DORD_bm; +} + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.h b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/commSPI_ADC.h (revision 221) @@ -0,0 +1,32 @@ +/* + * commSPI_ADC.h + * + * Created: 23/11/15 14:06:45 + * Author: Francisco + */ + + +#ifndef COMMSPI_ADC_H_ +#define COMMSPI_ADC_H_ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" + +#define PORTSPI PORTC //Puerto en el que se defini� el puerto SPI + +#define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS +#define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI +#define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO +#define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK + +#define SPI_SS_bm PIN4_bm // Pin de entrada - Totem +#define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem +#define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem +#define SPI_SCK_bm PIN7_bm // Pin de salida - Totem + +void config_spiparm(void); + + +#endif /* COMMSPI_ADC_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/fpga_port.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/fpga_port.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/fpga_port.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/fpga_port.c (revision 221) @@ -0,0 +1,115 @@ +/* + * fpga_port.c + * + * Created: 23/11/15 14:33:16 + * Author: Francisco + */ + +#define F_CPU 32000000UL +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRCLR = LOCK_FPGA; + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; + PORT_FPGA.DIRSET = CLK_FPGA; + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLUP_gc; + PORT_FPGA.OUTSET = CLK_FPGA; + + //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; + PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + PORT_FPGA.INT0MASK = LOCK_FPGA; + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + + //Configuracion de interrupciones de CLK + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + PORT_PPS.INT1MASK = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; +} + +void habilitar_interrupciones( uint8_t level_mask ) +{ + PMIC.CTRL |= level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); +} + +void deshabilitar_interrupciones_globales( void ) +{ + cli(); +} + +void envio_nibble(uint8_t fpga_dato) +{ + //Nibble superior 8 a 4 + PORT_FPGA.OUTCLR = CLK_FPGA; + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_alto_bm) >> fpga_salidas_nibblealto_bp); + PORT_FPGA.OUTSET = CLK_FPGA; + //asm("nop"); + //Nibble inferior 3 a 0 + PORT_FPGA.OUTCLR = CLK_FPGA; + PORT_FPGA.OUT = (PORT_FPGA.OUT & fpga_salidas_bm) | ((fpga_dato & nibble_bajo_bm) << fpga_salidas_nibblebajo_bp); + PORT_FPGA.OUTSET = CLK_FPGA; + +} + +void envio_datos_fpga(void) +{ + uint8_t fpga_dato[ADC_DATASZ] ; + //uint8_t aux_dato[ADC_DATASZ] ; + + adcport_read_data(fpga_dato,ADC_DATASZ); + //aux_dato[0] = fpga_dato[0]; + //aux_dato[1] = fpga_dato[1]; + //aux_dato[2] = fpga_dato[2]; + //adcport_read_data(fpga_dato,ADC_DATASZ); + + //envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + for(int i=0; i +#include +#include "ADC_7176_2.h" + +//Port B +#define PORT_PPS PORTB +#define PPS_FPGA PIN2_bm +#define PPS_FPGA_CTRL PIN2CTRL +#define INT_PPS PORTB_INT1_vect + +//Port A +#define PORT_LOCKOUT PORTA +#define LOCK_OUT PIN0_bm + + +//Port D +#define PORT_FPGA PORTD +#define LOCK_FPGA PIN1_bm +#define CLK_FPGA PIN2_bm +#define CH_BIT0_FPGA PIN3_bm +#define CH_BIT1_FPGA PIN4_bm +#define CH_BIT2_FPGA PIN5_bm +#define CH_BIT3_FPGA PIN6_bm +#define INT_LOCK_FPGA PORTD_INT0_vect + +#define LOCK_FPGA_CTRL PIN1CTRL +#define CLK_FPGA_CTRL PIN2CTRL +#define CH_BIT0_FPGA_CTRL PIN3CTRL +#define CH_BIT1_FPGA_CTRL PIN4CTRL +#define CH_BIT2_FPGA_CTRL PIN5CTRL +#define CH_BIT3_FPGA_CTRL PIN6CTRL + +void config_fpgaport(); +void habilitar_interrupciones( uint8_t level_mask ); +void habilitar_interrupciones_globales( ); +void deshabilitar_interrupciones_globales( ); + +//Habilitar +#define hab_prioridad_alta PMIC_HILVLEN_bm +#define hab_prioridad_media PMIC_MEDLVLEN_bm +#define hab_prioridad_baja PMIC_LOLVLEN_bm + +//M�scara de nibbles +#define nibble_alto_bm 0xF0 +#define nibble_bajo_bm 0x0F +#define fpga_salidas_nibblealto_bp 1 +#define fpga_salidas_nibblebajo_bp 3 +#define fpga_salidas_bm 0x87 + +//funciones de env�o de datos +void envio_nibble(uint8_t fpga_dato); + +//funcion interrupcion por flanco de subida de RDY +void envio_datos_fpga(void); +void envio_dato_adc(uint8_t* dato_adc); + +#endif /* FPGA_PORT_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/main.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/main.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/main.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/main.c (revision 221) @@ -0,0 +1,83 @@ +/* + * ADCSPI_ver01.c + * + * Created: 26/10/15 12:02:22 + * Author : Francisco + */ + +#define F_CPU 32000000UL +#include +#include "Ports.h" +//#include "commSPI_ADC.h" +#include "sys_clock.h" +#include "ADC_7176_2.h" +#include "fpga_port.h" + + +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + config_sysclock(); + config_spiparm(); + config_fpgaport(); + config_adc(); + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + habilitar_interrupciones_globales(); + + /* Replace with your application code */ + while (1) + { + if (test_adc() == ADC_ID){ + PORTD.OUTSET = PIN6_bm | PIN5_bm; + } + + //test_adc_2(datos_adc); + //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){ + //PORTD.OUTSET = PIN4_bm; + //} + } + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + { + PMIC.CTRL |= hab_prioridad_media; + PORT_LOCKOUT.OUTSET = LOCK_OUT; + PORTD.OUTSET = PIN4_bm; + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + PMIC.CTRL &= ~hab_prioridad_baja; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + PORTSPI.OUTSET = SPI_SS_bm; + } +} + +//Interrupcion por flanco de subida de PPS +//Habilito interrupciones de prioridad baja +//Selecciono el chip del ADC para iniciar comunicaci�n. +//Al iniciar esta comunicaci�n se indicar� al ADC que use el RDYbar +//Esta ser� nuestra interrupci�n para lectura del ADC y env�o de dato a la FPGA +ISR(INT_PPS) +{ + PMIC.CTRL |= hab_prioridad_baja; + PORTSPI.OUTCLR = SPI_SS_bm; +} + +ISR(INT_RDY) +{ + envio_datos_fpga(); +} + + + Index: trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/sys_clock.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/sys_clock.c b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/sys_clock.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/acquisitiond/Segunda_Etapa/Ver_2/ADCSPI_ver01/sys_clock.c (revision 221) @@ -0,0 +1,53 @@ +/* + * sys_clock.c + * + * Created: 23/11/15 14:04:36 + * Author: Francisco + */ + + +/*! + * \fn config_sysclock + * \brief Configuraci�n del reloj interno del sistema + * Reloj interno + * fsys = 32MHz + * + * En nuestra aplicaci�n final el reloj ser� externo de 16MHz por lo que se tendr� que usar el PLL + * \ +*/ + +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + +CLK_PSCTRL = ((0< + +void config_sysclock(void); + + + +#endif /* SYS_CLOCK_H_ */ \ No newline at end of file Index: trunk/firmware/sources/acquisitiond/Ver1 =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/Ver1 b/trunk/firmware/sources/acquisitiond/Ver1 deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/Ver1 (revision 220) +++ /dev/null (revision 221) Index: trunk/firmware/sources/acquisitiond/acquisitiond.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/acquisitiond.c b/trunk/firmware/sources/acquisitiond/acquisitiond.c deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/acquisitiond.c (revision 220) +++ /dev/null (revision 221) @@ -1,261 +0,0 @@ -/* - * acquisitiond.c - * - * Created on: Mar 24, 2015 - * Author: shinobi - */ - -#include "acquisitiond.h" -#include "fpgaport.h" - -volatile uint8_t is_acquiring = 0; -volatile uint8_t send_flg = 0; - -// Comandos para el ADC -#define CMD_ACTV 0 -#define CMD_DACTV 1 -#define CMD_RATE 2 -#define CMD_RPARAM 3 -#define CMD_WPARAM 4 -#define CMD_START 5 -#define CMD_STOP 6 -#define CMD_INFO 7 -#define CMD_GAIN 8 -#define CMD_ID 9 -#define CMD_STATUS 10 -#define CMD_PPS 11 - - -/*! - * \fn acq_chn_activate - * \breif activa la comunicacion con el IC ADC - * \see acq_chn_deactivate - */ -void acq_chn_activate(){ - adcport_open(); -} - - -/*! - * \fn acq_chn_deactivate - * \breif desactiva la comunicacion con el IC ADC - * \see acq_chn_activate - */ -void acq_chn_deactivate(){ - adcport_close(); -} - - -/*! - * \fn acq_chn_datarate - * \breif Configura el datarate del ADC - * \param datarate El datarate deseado - */ -void acq_chn_datarate(uint16_t datarate){ - if(is_acquiring==1){ - acq_stop_acquisiton(); - } - acq_set_param_to_adc(CMD_RATE,datarate); -} - - -/*! - * \fn acq_send_information - * \breif Envia informacion relevante al Embebido (a traves de FPGA) - */ -void acq_send_information(){ - if(is_acquiring==1){ - acq_stop_acquisiton(); - } - acq_send_param(CMD_RATE); - acq_send_param(CMD_GAIN); - acq_send_param(CMD_ID); - acq_send_param(CMD_STATUS); - acq_send_param(CMD_PPS); -} - - -/*! - * \fn acq_chn_datarate - * \breif Envia parametros al embebido a traves del FPGA (este se debe encargar - * de hacer el puente al embebido) - * \param param El parametro que se quiere enviar al embebido - */ -void acq_send_param(uint8_t param){ - uint8_t data; - fpgaport_open(); - fpgaport_write(param); - switch(param){ - case CMD_RATE: - // TODO secuencia de comandos para obtener el datarate del ADC - break; - case CMD_GAIN: - data=adcport_get_param(GAIN0); - break; - case CMD_ID: - data=adcport_get_param(ID); - break; - case CMD_STATUS: - data=adcport_get_param(STATUS); - break; - case CMD_PPS: - break;// TODO - default: - // con esta opcion se puede leer los registros del ADC definidos en - // "adcpot.h" y enviarlos al embebido - data= adcport_get_param(param); - break; - } - - fpgaport_write(data); - fpgaport_close(); -} - - -/*! - * \fn acq_send_buff - * \breif Envia el contenido de un buffer de datos hacia el - * FPGA para que sean pre-procesados. - */ -/* - * Esta funcion debe ser ejecutada con la señal de una interrupcion externa - * manejada por software, que le indicara que hay un buffer lleno listo - * para pre-procesar (vea adcport.c ). - */ -void acq_send_buff(){ - uint8_t i=0; - uint32_t* pbuff = adcport_getbuff(); - fpgaport_open(); - while(!(i==BUFF_SIZE)){ - fpgaport_write(pbuff[i]); - i++; - } - fpgaport_close(); -} - - -/*! - * \fn acq_chn_set_datarate - * \breif configura edl datarate del ADC - * \param datarate - */ -void acq_chn_set_datarate(uint8_t datarate){ - // TODO secuencia de comandos para configurar el data rate -} - - -/*! - * \fn acq_process_cmd - * \breif Procesa todos los comandos enviados desde el FPGA. - * \param cmd Comando a procesar. - */ -/* - * Esta funcion debe ejecutarse al haber una interrupcion en el puerto que - * conecta al FPGA - */ -void acq_process_cmd(uint8_t cmd){ - static uint8_t param; - static uint8_t data; - cli();// desactiva interrupciones - fpgaport_open(); - switch(cmd){ - case CMD_ACTV: acq_chn_activate(); - break; - case CMD_DACTV:acq_chn_deactivate(); - break; - case CMD_RATE: - param=fpgaport_read(); - acq_chn_set_datarate(param); - break; - case CMD_RPARAM: - param=fpgaport_read(); - acq_send_param(param); - break; - case CMD_WPARAM: - cmd=fpgaport_read();//lee - data=fpgaport_read();//lee valor - acq_set_param_to_adc(cmd,data); - break; - case CMD_START: - acq_start_acquisition(); - break; - case CMD_STOP: - acq_stop_acquisition(); - break; - case CMD_INFO: - acq_send_information(); - break; - default: break; - } - fpgaport_close(); - sei();//acvtiva interrupciones -} - - -/*! - * \fn acq_set_param - * \breif Procesa todos los comandos enviados desde el FPGA. - * \param param Parametro a configurar. - * \param value Valor del parametro - */ -void acq_set_param(uint8_t param, uint8_t value){ - adcport_tranceiv(param); - adcport_tranceiv(value); -} - - -/*! - * \fn acq_start_acquisition - * \breif Inicia la adquisicion de datos, esta se hara a traves de interrupciones - * "software" (ver adcport.c) - */ -void acq_start_acquisition(){ - is_acquiring = 1; - adcport_start(); -} - -/*! - * \fn acq_stop_acquisition - * \breif Para la adquisicion de datos. Las interrupciones utilizadas para - * este fin son desactivadas. - */ -void acq_stop_acquisition(){ - is_acquiring=0; - adcport_stop(); -} - - -/* - * interrupcion en algun pin que no se este usdando. - * Interrupcion software. No puede ser PORTC_INT0_vect - * Se usara para le indiquen que ya hay un buffer lleno - * (ver adcport.c) - */ -ISR(PORTx_INTx_vect){ // FIXME - send_flg=1; -} - - - -/* - * interrupcion en algun pin que no se este usdando. - * Interrupcion software. No puede ser PORTC_INT0_vect - * Se usara para le indiquen que ya hay un buffer lleno - * (ver adcport.c) - */ -ISR(PORTx_INTx_vect){ // FIXME - send_flg=1; -} - -/*! - * \brief Espera que un buffer este lleno para enviarlo al fpga - */ -int main(){ - do{ - if(send_flg==1){ - send_flg=0; - acq_send_buff(); - } - }while(1); - return 0; -} Index: trunk/firmware/sources/acquisitiond/acquisitiond.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/acquisitiond.h b/trunk/firmware/sources/acquisitiond/acquisitiond.h deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/acquisitiond.h (revision 220) +++ /dev/null (revision 221) @@ -1,35 +0,0 @@ -/* - * acquisitiond.h - * - * Created on: Mar 24, 2015 - * Author: shinobi - */ - -#ifndef ACQUISITIOND_H_ -#define ACQUISITIOND_H_ - -#include -#include -#include "adcport.h" - -void acq_chn_activate(); -void acq_chn_deactivate(); -void acq_chn_datarate(uint16_t datarate); - - -void acq_send_information(); -void acq_send_param(uint8_t param); -void acq_send_buff(); - - -void acq_process_cmd(uint8_t cmd); - -void acq_set_param_to_adc(uint8_t cmd, uint8_t data); - - -void acq_start_acquisition(); -void acq_stop_acquisition(); - - - -#endif /* ACQUISITIOND_H_ */ Index: trunk/firmware/sources/acquisitiond/adcport.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/adcport.c b/trunk/firmware/sources/acquisitiond/adcport.c deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/adcport.c (revision 220) +++ /dev/null (revision 221) @@ -1,266 +0,0 @@ -/* - * adcport.c - * - * Created on: Mar 25, 2015 - * Author: shinobi - */ - -#include "adcport.h" -#include -#include - - -#define SPI_SS_bm PIN4_bm /*!< \brief Bit mask para el pin SS. */ -#define SPI_MOSI_bm PIN5_bm /*!< \brief Bit mask para el pin MOSI. */ -#define SPI_MISO_bm PIN6_bm /*!< \brief Bit mask para el pin MISO. */ -#define SPI_SCK_bm PIN7_bm /*!< \brief Bit mask para el pin SCK. */ - - -#define SS_OFF PORTC.OUTSET=PIN4_bm;/*!< \brief Deselecciona el ADC (puerto SPI) */ -#define SS_ON PORTC.OUTCLR=PIN4_bm;/*!< \brief Selecciona el ADC (puerto SPI) */ - - -/* - * Al iniciar la adquisicion se debe activar la interrupcion del pin RDY a - * traves del PINC6 del XMEGA. - * Luego al leer los datos digitalizados, se debe desactivar. Al terminar - * se reactiva para esperar la siguiente interrupcion. - * Esto se debe a que el DOUT y el RDY del ADC comparten el pin. Si se dejara - * activa la interrupcion al leer, se generarian interrupciones e los flancos - * de bajada generados por la transferencia de las muestras - */ -#define WAIT_DATA PORTC.INT0MASK=PIN6_bm/*!< \brief Activa interrupcion que indica dato nuevo */ -#define GET_DATA PORTC.INT0MASK=0/*!< \brief Desactiva iterrupcion que indica dato nuevo */ - - -volatile uint8_t buff_idx; -uint32_t * pfull_buff; -uint32_t * pread_buff; -volatile uint8_t buff_full_flg = 0; - -/*! - * \fn adcport_ready_interrupt_config - * \brief configura el pin de MISO (conectado a DOUT del ADC), para que dispare - * una interrupcion por flanco de bajada. - * una vez disparada la interrupcion, se puede leer el pin; sin embargo, debe - * desactivarse antes de leer la interrupcion por flanco (con GET_DATA). De lo - * contrario se disparara la interrupcion varias veces al leer los datos, ya - * que ese el pin RDY y DOUT es el mismo en el ADC. - */ -inline void adcport_ready_interrupt_config(){ - // pin6: MISO(xmega) --> DOUT/RDY(ADC) => pin6 entrada - PORTC.DIRCLR=PIN6_bm; - // El ADC llevara a "low" RDY cuando la conversion de un dato haya concluido - // Se debe leer el dato generado luego. Se espera una interrupcion de flanco - // de bajada para manejar esto - PORTC.PIN6CTRL=PORT_ISC_FALLING_gc; - // Se mapea la interrupcion externa INT0 de PORTC a PINC6 - PORTC.INT0MASK=PIN6_bm; - // Debido a que esta interrupcion va a manejar la adquisicion de datos, se - // le da maxima prioridad (nivel alto) - PORTC.INTCTRL=PORT_INT0LVL_HI_gc; - // Se habilita la atencion de interrupciones de nivel alto - PMIC.CTRL|= PMIC_HILVLEN_bm; -} - - -/*! - * \fn adcport_spi_config - * \brief configura el puerto SPI para que coincida con el requerimiento del ADC - * AD7178-2 - */ -inline void adcport_spi_config(){ - PORTC.DIRSET = SPI_MOSI_bm | SPI_SCK_bm | SPI_SS_bm; - // Preescaler: clkper/2 (con clk2x). Maestro. CPOL=1,CPHA=1 - // MSB primero - SPIC.CTRL = SPI_CLK2X_bm|SPI_ENABLE_bm|SPI_MASTER_bm| - SPI_MODE1_bm|SPI_MODE0_bm; -} - - -/*! - * \fn adcport_config - * \brief Configura el microcontrolador para darle servicio a la interrupcion - * del pin "RDY" del ADC, que reacciona con un flanco de bajada cuando se ha - * terminado de digitalar una muestra nueva. - * Tambien configura el puerto SPI que servira para comunicarse con el ADC. - * \see adcport_ready_interrupt_config - * \see adcport_spi_config - */ -inline void adcport_config(){ - adcport_ready_interrupt_config(); - adcport_spi_config(); - // TODO configurar ADC: datarate, ganancia, desactivar CRC, formato numerico - // de muestras debe ser "bipolar offset binary"(canales diferenciales). -} - - -/*! - * \fn adcport_open - * \brief Inicializa el buffer de entrada (para datos de 24bits del ADC) y - * activa la comunicacion a traves del pin "SS" del puerto SPI. - * \see adcport_close - */ -inline void adcport_open(){ - buff_idx=0; - // TODO configurar interrupcion externa PPS (pin 6) - // TODO configurar interrupcion externa LOCK (pin 21) - pfull_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); - pread_buff = malloc(sizeof(uint32_t)*BUFF_SIZE); - adcport_config(); - SS_ON; -} - - -/*! - * \fn adcport_close - * \brief Desactiva la comunicacion con el ADC a traves del pin "SS" del puerto - * SPI. - * \see adcport_open - */ -inline void adcport_close(){ - SS_OFF; - free(pfull_buff); - free(pread_buff); -} - - -/*! - * \fn adcport_start - * \brief Inicia la digitalizacion de muestras del sensor. - * SPI. - * \see adcport_stop - * \see adcport_open - * \see adcport_close - */ -inline void adcport_start(){ - // necesario para darle servicio con interrupciones al flanco de bajada - // del pin "RDY" - WAIT_DATA; - // TODO enviar comandos al ADC para que inicie la adquisicion. -} - - -/*! - * \fn adcport_stop - * \brief Pausa la digitalizacion de muestras del sensor. - * SPI. - * \see adcport_start - * \see adcport_open - * \see adcport_close - */ -inline void adcport_stop(){ - // TODO enviar comandos al ADC para que deje de adquirir. - // necesario para cortar el servicio interrupcion del pin "RDY" - GET_DATA; -} - - -/*! - * \fn adcport_tranceiv - * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y - * el microcontrolador. - * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la - * transmision genera clock en el pin "sclk" - * \param El dato a transmitir - * \return El dato leido del ADC - */ -inline uint8_t adcport_tranceiv(uint8_t data){ - // - SPIC.DATA = data; - - //Wait until transmission complete - while(!(SPIC.STATUS)&SPI_IF_bm); - - // Return received data - return SPIC.DATA; -} - - -/*! - * \fn adcport_start - * \brief Inicia la digitalizacion de muestras del sensor. - * SPI. - * \see adcport_open - */ -void adcport_read_sample(){ - uint32_t aux; - GET_DATA; // desactiva interrupciones de flaco de bajada - // Se le indica al adc que se va a leer el registro de data. - adcport_tranceiv(0x44); - // El byte mas significativo de la variable de 32bits es cero - // La codificacion de los numeros es "bipolar offset binary" y - // la transmision es MSB first - aux = adcport_tranceiv(0); - aux = (aux<<8)|adcport_tranceiv(0); - aux = (aux<<8)|adcport_tranceiv(0); - aux = (aux<<8)|adcport_tranceiv(0); - pread_buff[buff_idx]=aux; - - WAIT_DATA; // reactiva interrupciones de flanco de bajada -} - - -/*! - * \fn adcport_getbuff - * \brief Devuelve la direccion del buffer lleno - * \return Direccion del buffer lleno. 0 si no esta lleno aun - */ -inline uint32_t* adcport_getbuff(){ - if(buff_full_flg==1){ - buff_full_flg=0; - return pfull_buff; - } - return 0; -} - - -uint8_t adcport_get_param(uint8_t data){ - adcport_tranceiv(data); - return adcport_tranceiv(0); -} - - -/*! - * \brief interrupcion externa debe dispararse en flanco de bajada en PC6 (RDY del ADC). - * Cuando el ADC lleva este pin a "low", se debe leer el dato nuevo - */ -ISR(PORTC_INT0_vect){ - adcport_read_sample(); - buff_idx++; - if(buff_idx>=100){ - uint32_t* paux = pread_buff; - pread_buff = pfull_buff; - pfull_buff = paux; - buff_full_flg=1; - // TODO dar aviso al programa principal que el buffer esta lleno. - // Puede ser a traves de una interrupcion "externa" en un pin que no se - // use, para lo cual debe estar configurado como salida y para recibir - // interrupciones de IO. - // para hacer que funcione como una interrupcion software, solo escribir - // en ese pin un valor segun se configure la interrupcion - } -} - - -/* TODO - * interrupcion del LOCK del GNSS (pin numero 21 del xmega) - * servira para indicar que el GNSS esta sincronizado con satelites y la hora y - * PPS son correctos, a partir de ese momento se pueden contar los PPS y - * identificarlos en el header. - */ -ISR(PORTx_INTx_vect){ // FIXME - -} - - -/* TODO - * interrupcion del PPS del GNSS (pin numero 6 del xmega) - * servira para sincronizar la hora. Debe agregar un numero de serie entre 0 y 255 - * a la cabecera del buffer que indentifique al PPS; y el numero de muestra que se adquirio - * en el momento de la llegada de esta interrupcion. - */ -ISR(PORTx_INTx_vect){ // FIXME - -} - Index: trunk/firmware/sources/acquisitiond/adcport.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/adcport.h b/trunk/firmware/sources/acquisitiond/adcport.h deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/adcport.h (revision 220) +++ /dev/null (revision 221) @@ -1,60 +0,0 @@ -/* - * adcport.h - * - * Created on: Mar 25, 2015 - * Author: shinobi - */ - -#ifndef ADCPORT_H_ -#define ADCPORT_H_ - -#include - -#define BUFF_SIZE 100 - -/* Direcciones de registros del ADC */ - -#define COMMS 0x00 -#define STATUS 0x00 -#define ADCMODE 0x01 -#define IFMODE 0x02 -#define REGCHECK 0x03 -#define DATA 0X04 -#define GPIOCON 0x06 -#define ID 0x07 - -#define CHMAP0 0x10 -#define CHMAP1 0x11 -#define CHMAP2 0x12 -#define CHMAP3 0x13 - -#define SETUPCON0 0x20 -#define SETUPCON1 0x21 -#define SETUPCON2 0x22 -#define SETUPCON3 0x23 - -#define FILTCON0 0x28 -#define FILTCON1 0x29 -#define FILTCON2 0x2A -#define FILTCON3 0x2B - -#define OFFSET0 0x30 -#define OFFSET1 0x31 -#define OFFSET2 0x32 -#define OFFSET3 0x33 - -#define GAIN0 0x38 -#define GAIN1 0x39 -#define GAIN2 0x2A -#define GAIN3 0x2B - - -void adcport_open(); -void adcport_close(); -void adcport_start(); -void adcport_stop(); -uint32_t* adcport_getbuff(); -uint8_t adcport_tranceiv(uint8_t data); -uint8_t adcport_get_param(uint8_t data); - -#endif /* ADCPORT_H_ */ Index: trunk/firmware/sources/acquisitiond/fpgaport.c =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/fpgaport.c b/trunk/firmware/sources/acquisitiond/fpgaport.c deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/fpgaport.c (revision 220) +++ /dev/null (revision 221) @@ -1,57 +0,0 @@ -/* - * fpgaport.c - * - * Created on: Mar 26, 2015 - * Author: shinobi - */ - - -/*! - * \fn fpgaport_open - * \brief actima la comunicacion con el FPGA - */ -inline void fpgaport_open(){ - // TODO configurar puerto pfga e interrupcion externa (pin 22) - // TODO configurar interrupcion externa PPS (pin 6) - // TODO configurar interrupcion externa LOCK (pin 21) -} - - -/*! - * \fn fpgaport_close - * \brief Desactiva la comunicacion con el FPGA - */ -inline void fpgaport_close(){ - // TODO configurar puerto pfga e interrupcion externa (pin 22) para - // clock -} - - -/*! - * \fn fpgaport_write - * \breif activa la comunicacion con el IC ADC - * \see acq_chn_deactivate - */ -inline void fpgaport_write(uint8_t data){ - // TODO -} - - -/*! - * \fn fpgaport_read - * \breif activa la comunicacion con el IC ADC - * \see acq_chn_deactivate - */ -inline uint8_t fpgaport_read(){ - // TODO -} - - -/* - * Interrupcion de dato entrante por el puerto FPGA. El pin debe ser alguno de los - * que estan conectatos al FPGA (el bus) - */ -ISR(PORTx_INTx_vect){ - // TODO debe idicar que se ejecute la funcion que procesa los comandos - // que bienen del FPGA -} Index: trunk/firmware/sources/acquisitiond/fpgaport.h =================================================================== diff --git a/trunk/firmware/sources/acquisitiond/fpgaport.h b/trunk/firmware/sources/acquisitiond/fpgaport.h deleted file mode 10644 --- a/trunk/firmware/sources/acquisitiond/fpgaport.h (revision 220) +++ /dev/null (revision 221) @@ -1,19 +0,0 @@ -/* - * fpgaport.h - * - * Created on: Mar 26, 2015 - * Author: shinobi - */ - -#ifndef FPGAPORT_H_ -#define FPGAPORT_H_ - -#include - -void fpgaport_open(); -void fpgaport_close(); -void fpgaport_write(uint8_t data); -uint8_t fpgaport_read(); - - -#endif /* FPGAPORT_H_ */