Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsln =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsln b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsln new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsln (revision 224) @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Atmel Studio Solution File, Format Version 11.00 +Project("{54F91283-7BC4-4236-8FF9-10F437C3AD48}") = "ADCSPI_v01", "ADCSPI_v01\ADCSPI_v01.cproj", "{7024C456-574A-4FD1-BAA2-1F09B3D11566}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Debug|AVR.ActiveCfg = Debug|AVR + {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Debug|AVR.Build.0 = Debug|AVR + {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Release|AVR.ActiveCfg = Release|AVR + {7024C456-574A-4FD1-BAA2-1F09B3D11566}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsuo =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsuo b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsuo new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.atsuo (revision 224) Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.cproj =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.cproj b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.cproj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADCSPI_v01.cproj (revision 224) @@ -0,0 +1,147 @@ + + + + 2.0 + 6.2 + com.Atmel.AVRGCC8.C + {7024c456-574a-4fd1-baa2-1f09b3d11566} + ATxmega32D4 + none + Executable + C + $(MSBuildProjectName) + .elf + $(MSBuildProjectDirectory)\$(Configuration) + ADCSPI_v01 + ADCSPI_v01 + ADCSPI_v01 + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + + + + + + + + + + + + + com.atmel.avrdbg.tool.atmelice + PDI + + + + 4000000 + + PDI + + com.atmel.avrdbg.tool.atmelice + J41800030896 + Atmel-ICE + + + + + + True + True + True + True + False + True + True + + + NDEBUG + + + Optimize for size (-Os) + True + True + True + + + libm + + + + + + + + + True + True + True + True + False + True + True + + + DEBUG + + + Optimize (-O1) + True + True + Default (-g2) + True + + + libm + + + Default (-Wa,-g) + + + + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + compile + + + + \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADC_7176_2.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADC_7176_2.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADC_7176_2.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/ADC_7176_2.c (revision 224) @@ -0,0 +1,257 @@ +/* + * ADC_7176_2.c + * + * Created: 26/04/16 11:46:48 + * Author: Francisco + */ + +/*! + * \fn test_adc + * \brief Lectura de ID del adc + * + * Lectura esperada: 0x0C94 + * + * Esta función tiene como fin probar la comunicación on el ADC + * +#define ADC_WENbar_bm (1<<7) +#define ADC_RWbar_bm (1<<6) +#define ADC_ADDR_READ_ID 0x07 + * \ +*/ + +#define F_CPU 32000000UL +#include +#include "ADC_7176_2.h" +#include + +inline uint16_t test_adc(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_ADDR_READ_ID|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + return aux; +} + +inline void test_adc_2(uint8_t* dato){ + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_read_data(dato,ADC_DATASZ); + PORTSPI.OUTSET = SPI_SS_bm; +} + +inline uint16_t test_adc_3(void){ + uint16_t aux; + PORTSPI.OUTCLR = SPI_SS_bm; + adcport_tranceiv((ADC_FILTCON0|ADC_RWbar_bm)&(~ADC_WENbar_bm)); + aux = adcport_tranceiv(0); + aux = (aux << 8) | adcport_tranceiv(0); + PORTSPI.OUTSET = SPI_SS_bm; + return aux; +} + +/*! + * \fn adcport_tranceiv + * \brief Realiza la transmision y recepcion simultanea de datos entre el ADC y + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + + // Return received data + + return SPIC.DATA; +} + +/*! + * \fn adcport_readdata + * \brief Realiza la lectura de datos en modo de conversión continua + * el microcontrolador. + * Incluso en para leer un dato del ADC se debe transmitir, ya que solo la + * transmision genera clock en el pin "sclk" + * \param La dirección del puntero a dato + * \return Ninguno sólo se llena el puntero al dato + */ +inline void adcport_read_data(uint8_t* dato,int j) +{ + + //Envío del comando de lectura de datos 0x44 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i +#include "Ports.h" +#include "commSPI_ADC.h" + +//ID esperada +//tamaño 16 bits +//Valor 0x0C94 +#define ADC_VALFIL0 0x0013 +//#define ADC_VALFIL0 0x8000 +#define ADC_ID 0x0C94 +#define ADC_RD 0x04 + +#define ADC_MODREG 0x01 +#define ADC_DATREG 0x04 +#define ADC_FILTCON0 0x28 +#define ADC_INTERFMODE_REG 0x02 + +#define ADC_ADDR_READ_ID (0x07) +#define ADC_CHMAPREG0 0x10 +#define ADC_CHMAPREG1 0x11 +#define ADC_CHMAPREG2 0x12 +#define ADC_CHMAPREG3 0x13 +#define ADC_SETUPCON0 0x20 + +#define ADC_DATASZ 3 //Numero de bytes + +//Definición de orden de los bits de habilitación, escritura lectura y dirección +#define ADC_WENbar_bm 0b10000000 +#define ADC_RWbar_bm 0b01000000 +#define ADC_FILT0_ORDER0_bp 5 +#define ADC_FILT0_ODR0_bp 0 + +#define ADC_CONTREAD_bp 7 +#define ADC_WL16_bp 0 +#define ADC_IOSTRENGTH_bp 3 +#define ADC_IOSTRENGTH_E 0b1 +#define ADC_IOSTRENGTH_NE 0b0 + +#define ADC_SYNCYC_bp 5 +#define ADC_REFOUT_bp 7 +#define ADC_MODECONV_bp 4 +#define ADC_SINGLECONV 0b001 +#define ADC_CONTCONV 0b000 + +#define ADC_SINC5SINC1 0b00 +#define ADC_CONTREAD_E 0b1 +#define ADC_CONTREAD_NE 0b0 + +#define ADC_REFEN_bm 0b1 +#define ADC_REFNEN_bm 0b0 + +#define ADC_SINGLECONV_EN_bm 0b1 +#define ADC_SINGLECONV_NEN_bm 0b0 + +#define ADC_CHMAPEN_bp 7 +#define ADC_CHMAPEN_E 1 +#define ADC_CHMAPEN_NE 0 + + +#define ADC_CHSETSEL_bp 4 +#define ADC_SET0_bm 0b000 + +#define ADC_AINPOSUB_bp 0 +#define ADC_AINPOSLB_bp 5 +#define ADC_AINNEG_bp 0 + +#define ADC_AINPOSUB0_bm 0b00 +#define ADC_AINPOSLB0_bm 0b000 +#define ADC_AINEG1_bm 0b00001 + +#define ADC_AINPOSUB1_bm 0b00 +#define ADC_AINPOSLB1_bm 0b001 +#define ADC_AINEG0_bm 0b00000 + + +#define ADC_BI_UNIPOLAR_bp 4 +#define ADC_OFFSETBIP_bm 0b1 +#define ADC_REFSEL_bp 4 +#define ADC_INT25V_bm 0b10 + + + + +#define ADC_250000S 0b00000 +#define ADC_125000S 0b00001 +#define ADC_62500S 0b00010 +#define ADC_50000S 0b00011 +#define ADC_31250S 0b00100 +#define ADC_25000S 0b00101 +#define ADC_15625S 0b00110 +#define ADC_10000S 0b00111 +#define ADC_5000S 0b01000 +#define ADC_2500S 0b01001 +#define ADC_1000S 0b01010 +#define ADC_500S 0b01011 +#define ADC_3975S 0b01100 +#define ADC_200S 0b01101 +#define ADC_100S 0b01110 +#define ADC_5994S 0b01111 +#define ADC_4996S 0b10000 +#define ADC_20S 0b10001 +#define ADC_166S 0b10010 +#define ADC_10S 0b10011 +#define ADC_5S 0b10100 + +#define ADC_24b 0b0 +#define ADC_16b 0b1 + +uint8_t adcport_tranceiv(uint8_t data); +void adcport_read_data(uint8_t* dato,int j); + +uint16_t adcport_read_filtcon0(void); + +void adcport_write_filtcon0(void); +void adcport_write_interfmode(void); +void adcport_write_adcmode(void); +void adcport_write_reset(void); +void adcport_write_chmapreg0(void); +void adcport_write_chmapreg1(void); +void adcport_write_chmapreg2(void); +void adcport_write_chmapreg3(void); +void adcport_write_setupcon0(void); +void adcport_write_adcmode_2(void); +void adcport_read_data_synconv(uint8_t* dato,int j); +void adcport_read_data_contread(uint8_t* dato,int j); + + +uint16_t test_adc(void); +void test_adc_2(uint8_t* dato); +uint16_t test_adc_3(void); + +void config_adc(void); + +#endif /* ADC_7176_2_H_ */ \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.eep =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.eep b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.eep new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.eep (revision 224) @@ -0,0 +1 @@ +:00000001FF =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.elf =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.elf b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.elf new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.elf (revision 224) Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.hex =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.hex b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.hex new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.hex (revision 224) @@ -0,0 +1,143 @@ +:100000000C94B6000C94C8000C94AC020C94C8007C +:100010000C94C8000C94C8000C94C8000C94C80040 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+:10086000509712962C93A0EEB7E051969C93519717 +:1008700093E012969C93129750968C9380E4828713 +:1008800081858C7F816081878689887F8260868B65 +:10089000089510924100E0E5F0E080818660808359 +:1008A000818182FFFDCFE0E5F0E0818181FFFDCF16 +:1008B00081E080936000E0E5F0E096819D7F968383 +:1008C00098ED94BF8093400080818E7F808308954F +:0408D000F894FFCFCA +:00000001FF Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.lss =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.lss b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.lss new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.lss (revision 224) @@ -0,0 +1,1825 @@ + +ADCSPI_v01.elf: file format elf32-avr + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000008d4 00000000 00000000 00000074 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .bss 00000002 00802000 00802000 00000948 2**0 + ALLOC + 2 .comment 00000030 00000000 00000000 00000948 2**0 + CONTENTS, READONLY + 3 .debug_aranges 00000198 00000000 00000000 00000978 2**0 + CONTENTS, READONLY, DEBUGGING + 4 .debug_info 00001a04 00000000 00000000 00000b10 2**0 + CONTENTS, READONLY, DEBUGGING + 5 .debug_abbrev 00000726 00000000 00000000 00002514 2**0 + CONTENTS, READONLY, DEBUGGING + 6 .debug_line 00000c70 00000000 00000000 00002c3a 2**0 + CONTENTS, READONLY, DEBUGGING + 7 .debug_frame 0000034c 00000000 00000000 000038ac 2**2 + CONTENTS, READONLY, DEBUGGING + 8 .debug_str 000008ad 00000000 00000000 00003bf8 2**0 + CONTENTS, READONLY, DEBUGGING + 9 .debug_loc 00000564 00000000 00000000 000044a5 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_ranges 00000138 00000000 00000000 00004a09 2**0 + CONTENTS, READONLY, DEBUGGING + +Disassembly of section .text: + +00000000 <__vectors>: + 0: 0c 94 b6 00 jmp 0x16c ; 0x16c <__ctors_end> + 4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 8: 0c 94 ac 02 jmp 0x558 ; 0x558 <__vector_2> + c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 10: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 14: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 18: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 1c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 20: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 24: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 28: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 2c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 30: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 34: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 38: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 3c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 40: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 44: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 48: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 4c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 50: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 54: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 58: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 5c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 60: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 64: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 68: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 6c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 70: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 74: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 78: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 7c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 80: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 84: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 88: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 8c: 0c 94 63 02 jmp 0x4c6 ; 0x4c6 <__vector_35> + 90: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 94: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 98: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 9c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + a0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + a4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + a8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + ac: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + b0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + b4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + b8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + bc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + c0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + c4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + c8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + cc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + d0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + d4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + d8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + dc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + e0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + e4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + e8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + ec: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + f0: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + f4: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + f8: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + fc: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 100: 0c 94 2f 02 jmp 0x45e ; 0x45e <__vector_64> + 104: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 108: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 10c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 110: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 114: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 118: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 11c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 120: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 124: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 128: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 12c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 130: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 134: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 138: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 13c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 140: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 144: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 148: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 14c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 150: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 154: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 158: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 15c: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 160: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 164: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + 168: 0c 94 c8 00 jmp 0x190 ; 0x190 <__bad_interrupt> + +0000016c <__ctors_end>: + 16c: 11 24 eor r1, r1 + 16e: 1f be out 0x3f, r1 ; 63 + 170: cf ef ldi r28, 0xFF ; 255 + 172: cd bf out 0x3d, r28 ; 61 + 174: df e2 ldi r29, 0x2F ; 47 + 176: de bf out 0x3e, r29 ; 62 + +00000178 <__do_clear_bss>: + 178: 20 e2 ldi r18, 0x20 ; 32 + 17a: a0 e0 ldi r26, 0x00 ; 0 + 17c: b0 e2 ldi r27, 0x20 ; 32 + 17e: 01 c0 rjmp .+2 ; 0x182 <.do_clear_bss_start> + +00000180 <.do_clear_bss_loop>: + 180: 1d 92 st X+, r1 + +00000182 <.do_clear_bss_start>: + 182: a2 30 cpi r26, 0x02 ; 2 + 184: b2 07 cpc r27, r18 + 186: e1 f7 brne .-8 ; 0x180 <.do_clear_bss_loop> + 188: 0e 94 1e 02 call 0x43c ; 0x43c
+ 18c: 0c 94 68 04 jmp 0x8d0 ; 0x8d0 <_exit> + +00000190 <__bad_interrupt>: + 190: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> + +00000194 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 194: 24 e4 ldi r18, 0x44 ; 68 + 196: e0 ec ldi r30, 0xC0 ; 192 + 198: f8 e0 ldi r31, 0x08 ; 8 + 19a: 23 83 std Z+3, r18 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 19c: 22 81 ldd r18, Z+2 ; 0x02 + 19e: 22 23 and r18, r18 + 1a0: ec f7 brge .-6 ; 0x19c + + // Return received data + + return SPIC.DATA; + 1a2: e0 ec ldi r30, 0xC0 ; 192 + 1a4: f8 e0 ldi r31, 0x08 ; 8 + 1a6: 23 81 ldd r18, Z+3 ; 0x03 + adcport_tranceiv((ADC_RD | ADC_RWbar_bm)&(~ADC_WENbar_bm)); + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 1ae: dc 01 movw r26, r24 + 1b0: 86 0f add r24, r22 + 1b2: 97 1f adc r25, r23 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1b4: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1b6: 22 81 ldd r18, Z+2 ; 0x02 + 1b8: 22 23 and r18, r18 + 1ba: ec f7 brge .-6 ; 0x1b6 + + // Return received data + + return SPIC.DATA; + 1bc: 23 81 ldd r18, Z+3 ; 0x03 + + //x = (i2 >> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i> 16) & (i1 >> 8) & (i0 >>0) + + // Save received data + for(int i=0; i + 1c6: 08 95 ret + +000001c8 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1c8: 81 e0 ldi r24, 0x01 ; 1 + 1ca: e0 ec ldi r30, 0xC0 ; 192 + 1cc: f8 e0 ldi r31, 0x08 ; 8 + 1ce: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1d0: 82 81 ldd r24, Z+2 ; 0x02 + 1d2: 88 23 and r24, r24 + 1d4: ec f7 brge .-6 ; 0x1d0 + + // Return received data + + return SPIC.DATA; + 1d6: e0 ec ldi r30, 0xC0 ; 192 + 1d8: f8 e0 ldi r31, 0x08 ; 8 + 1da: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1dc: 80 e8 ldi r24, 0x80 ; 128 + 1de: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1e0: 82 81 ldd r24, Z+2 ; 0x02 + 1e2: 88 23 and r24, r24 + 1e4: ec f7 brge .-6 ; 0x1e0 + + // Return received data + + return SPIC.DATA; + 1e6: e0 ec ldi r30, 0xC0 ; 192 + 1e8: f8 e0 ldi r31, 0x08 ; 8 + 1ea: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1ec: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 1ee: 82 81 ldd r24, Z+2 ; 0x02 + 1f0: 88 23 and r24, r24 + 1f2: ec f7 brge .-6 ; 0x1ee + + // Return received data + + return SPIC.DATA; + 1f4: e0 ec ldi r30, 0xC0 ; 192 + 1f6: f8 e0 ldi r31, 0x08 ; 8 + 1f8: 83 81 ldd r24, Z+3 ; 0x03 + 1fa: 08 95 ret + +000001fc : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 1fc: 88 e2 ldi r24, 0x28 ; 40 + 1fe: e0 ec ldi r30, 0xC0 ; 192 + 200: f8 e0 ldi r31, 0x08 ; 8 + 202: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 204: 82 81 ldd r24, Z+2 ; 0x02 + 206: 88 23 and r24, r24 + 208: ec f7 brge .-6 ; 0x204 + + // Return received data + + return SPIC.DATA; + 20a: e0 ec ldi r30, 0xC0 ; 192 + 20c: f8 e0 ldi r31, 0x08 ; 8 + 20e: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 210: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 212: 82 81 ldd r24, Z+2 ; 0x02 + 214: 88 23 and r24, r24 + 216: ec f7 brge .-6 ; 0x212 + + // Return received data + + return SPIC.DATA; + 218: e0 ec ldi r30, 0xC0 ; 192 + 21a: f8 e0 ldi r31, 0x08 ; 8 + 21c: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 21e: 83 e0 ldi r24, 0x03 ; 3 + 220: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 222: 82 81 ldd r24, Z+2 ; 0x02 + 224: 88 23 and r24, r24 + 226: ec f7 brge .-6 ; 0x222 + + // Return received data + + return SPIC.DATA; + 228: e0 ec ldi r30, 0xC0 ; 192 + 22a: f8 e0 ldi r31, 0x08 ; 8 + 22c: 83 81 ldd r24, Z+3 ; 0x03 + 22e: 08 95 ret + +00000230 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 230: 82 e0 ldi r24, 0x02 ; 2 + 232: e0 ec ldi r30, 0xC0 ; 192 + 234: f8 e0 ldi r31, 0x08 ; 8 + 236: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 238: 82 81 ldd r24, Z+2 ; 0x02 + 23a: 88 23 and r24, r24 + 23c: ec f7 brge .-6 ; 0x238 + + // Return received data + + return SPIC.DATA; + 23e: e0 ec ldi r30, 0xC0 ; 192 + 240: f8 e0 ldi r31, 0x08 ; 8 + 242: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 244: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 246: 82 81 ldd r24, Z+2 ; 0x02 + 248: 88 23 and r24, r24 + 24a: ec f7 brge .-6 ; 0x246 + + // Return received data + + return SPIC.DATA; + 24c: e0 ec ldi r30, 0xC0 ; 192 + 24e: f8 e0 ldi r31, 0x08 ; 8 + 250: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 252: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 254: 82 81 ldd r24, Z+2 ; 0x02 + 256: 88 23 and r24, r24 + 258: ec f7 brge .-6 ; 0x254 + + // Return received data + + return SPIC.DATA; + 25a: e0 ec ldi r30, 0xC0 ; 192 + 25c: f8 e0 ldi r31, 0x08 ; 8 + 25e: 83 81 ldd r24, Z+3 ; 0x03 + 260: 08 95 ret + +00000262 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 262: 80 e1 ldi r24, 0x10 ; 16 + 264: e0 ec ldi r30, 0xC0 ; 192 + 266: f8 e0 ldi r31, 0x08 ; 8 + 268: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 26a: 82 81 ldd r24, Z+2 ; 0x02 + 26c: 88 23 and r24, r24 + 26e: ec f7 brge .-6 ; 0x26a + + // Return received data + + return SPIC.DATA; + 270: e0 ec ldi r30, 0xC0 ; 192 + 272: f8 e0 ldi r31, 0x08 ; 8 + 274: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 276: 80 e8 ldi r24, 0x80 ; 128 + 278: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 27a: 82 81 ldd r24, Z+2 ; 0x02 + 27c: 88 23 and r24, r24 + 27e: ec f7 brge .-6 ; 0x27a + + // Return received data + + return SPIC.DATA; + 280: e0 ec ldi r30, 0xC0 ; 192 + 282: f8 e0 ldi r31, 0x08 ; 8 + 284: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 286: 80 e2 ldi r24, 0x20 ; 32 + 288: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 28a: 82 81 ldd r24, Z+2 ; 0x02 + 28c: 88 23 and r24, r24 + 28e: ec f7 brge .-6 ; 0x28a + + // Return received data + + return SPIC.DATA; + 290: e0 ec ldi r30, 0xC0 ; 192 + 292: f8 e0 ldi r31, 0x08 ; 8 + 294: 83 81 ldd r24, Z+3 ; 0x03 + 296: 08 95 ret + +00000298 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 298: 81 e1 ldi r24, 0x11 ; 17 + 29a: e0 ec ldi r30, 0xC0 ; 192 + 29c: f8 e0 ldi r31, 0x08 ; 8 + 29e: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2a0: 82 81 ldd r24, Z+2 ; 0x02 + 2a2: 88 23 and r24, r24 + 2a4: ec f7 brge .-6 ; 0x2a0 + + // Return received data + + return SPIC.DATA; + 2a6: e0 ec ldi r30, 0xC0 ; 192 + 2a8: f8 e0 ldi r31, 0x08 ; 8 + 2aa: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 2ac: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2ae: 82 81 ldd r24, Z+2 ; 0x02 + 2b0: 88 23 and r24, r24 + 2b2: ec f7 brge .-6 ; 0x2ae + + // Return received data + + return SPIC.DATA; + 2b4: e0 ec ldi r30, 0xC0 ; 192 + 2b6: f8 e0 ldi r31, 0x08 ; 8 + 2b8: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 2ba: 81 e0 ldi r24, 0x01 ; 1 + 2bc: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2be: 82 81 ldd r24, Z+2 ; 0x02 + 2c0: 88 23 and r24, r24 + 2c2: ec f7 brge .-6 ; 0x2be + + // Return received data + + return SPIC.DATA; + 2c4: e0 ec ldi r30, 0xC0 ; 192 + 2c6: f8 e0 ldi r31, 0x08 ; 8 + 2c8: 83 81 ldd r24, Z+3 ; 0x03 + 2ca: 08 95 ret + +000002cc : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 2cc: 82 e1 ldi r24, 0x12 ; 18 + 2ce: e0 ec ldi r30, 0xC0 ; 192 + 2d0: f8 e0 ldi r31, 0x08 ; 8 + 2d2: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2d4: 82 81 ldd r24, Z+2 ; 0x02 + 2d6: 88 23 and r24, r24 + 2d8: ec f7 brge .-6 ; 0x2d4 + + // Return received data + + return SPIC.DATA; + 2da: e0 ec ldi r30, 0xC0 ; 192 + 2dc: f8 e0 ldi r31, 0x08 ; 8 + 2de: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 2e0: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2e2: 82 81 ldd r24, Z+2 ; 0x02 + 2e4: 88 23 and r24, r24 + 2e6: ec f7 brge .-6 ; 0x2e2 + + // Return received data + + return SPIC.DATA; + 2e8: e0 ec ldi r30, 0xC0 ; 192 + 2ea: f8 e0 ldi r31, 0x08 ; 8 + 2ec: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 2ee: 81 e0 ldi r24, 0x01 ; 1 + 2f0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 2f2: 82 81 ldd r24, Z+2 ; 0x02 + 2f4: 88 23 and r24, r24 + 2f6: ec f7 brge .-6 ; 0x2f2 + + // Return received data + + return SPIC.DATA; + 2f8: e0 ec ldi r30, 0xC0 ; 192 + 2fa: f8 e0 ldi r31, 0x08 ; 8 + 2fc: 83 81 ldd r24, Z+3 ; 0x03 + 2fe: 08 95 ret + +00000300 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 300: 83 e1 ldi r24, 0x13 ; 19 + 302: e0 ec ldi r30, 0xC0 ; 192 + 304: f8 e0 ldi r31, 0x08 ; 8 + 306: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 308: 82 81 ldd r24, Z+2 ; 0x02 + 30a: 88 23 and r24, r24 + 30c: ec f7 brge .-6 ; 0x308 + + // Return received data + + return SPIC.DATA; + 30e: e0 ec ldi r30, 0xC0 ; 192 + 310: f8 e0 ldi r31, 0x08 ; 8 + 312: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 314: 13 82 std Z+3, r1 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 316: 82 81 ldd r24, Z+2 ; 0x02 + 318: 88 23 and r24, r24 + 31a: ec f7 brge .-6 ; 0x316 + + // Return received data + + return SPIC.DATA; + 31c: e0 ec ldi r30, 0xC0 ; 192 + 31e: f8 e0 ldi r31, 0x08 ; 8 + 320: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 322: 81 e0 ldi r24, 0x01 ; 1 + 324: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 326: 82 81 ldd r24, Z+2 ; 0x02 + 328: 88 23 and r24, r24 + 32a: ec f7 brge .-6 ; 0x326 + + // Return received data + + return SPIC.DATA; + 32c: e0 ec ldi r30, 0xC0 ; 192 + 32e: f8 e0 ldi r31, 0x08 ; 8 + 330: 83 81 ldd r24, Z+3 ; 0x03 + 332: 08 95 ret + +00000334 : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 334: 80 e2 ldi r24, 0x20 ; 32 + 336: e0 ec ldi r30, 0xC0 ; 192 + 338: f8 e0 ldi r31, 0x08 ; 8 + 33a: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 33c: 82 81 ldd r24, Z+2 ; 0x02 + 33e: 88 23 and r24, r24 + 340: ec f7 brge .-6 ; 0x33c + + // Return received data + + return SPIC.DATA; + 342: e0 ec ldi r30, 0xC0 ; 192 + 344: f8 e0 ldi r31, 0x08 ; 8 + 346: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 348: 80 e1 ldi r24, 0x10 ; 16 + 34a: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 34c: 82 81 ldd r24, Z+2 ; 0x02 + 34e: 88 23 and r24, r24 + 350: ec f7 brge .-6 ; 0x34c + + // Return received data + + return SPIC.DATA; + 352: e0 ec ldi r30, 0xC0 ; 192 + 354: f8 e0 ldi r31, 0x08 ; 8 + 356: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 358: 80 e2 ldi r24, 0x20 ; 32 + 35a: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 35c: 82 81 ldd r24, Z+2 ; 0x02 + 35e: 88 23 and r24, r24 + 360: ec f7 brge .-6 ; 0x35c + + // Return received data + + return SPIC.DATA; + 362: e0 ec ldi r30, 0xC0 ; 192 + 364: f8 e0 ldi r31, 0x08 ; 8 + 366: 83 81 ldd r24, Z+3 ; 0x03 + 368: 08 95 ret + +0000036a : + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 36a: 8f ef ldi r24, 0xFF ; 255 + 36c: e0 ec ldi r30, 0xC0 ; 192 + 36e: f8 e0 ldi r31, 0x08 ; 8 + 370: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 372: 82 81 ldd r24, Z+2 ; 0x02 + 374: 88 23 and r24, r24 + 376: ec f7 brge .-6 ; 0x372 + + // Return received data + + return SPIC.DATA; + 378: e0 ec ldi r30, 0xC0 ; 192 + 37a: f8 e0 ldi r31, 0x08 ; 8 + 37c: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 37e: 8f ef ldi r24, 0xFF ; 255 + 380: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 382: 82 81 ldd r24, Z+2 ; 0x02 + 384: 88 23 and r24, r24 + 386: ec f7 brge .-6 ; 0x382 + + // Return received data + + return SPIC.DATA; + 388: e0 ec ldi r30, 0xC0 ; 192 + 38a: f8 e0 ldi r31, 0x08 ; 8 + 38c: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 38e: 8f ef ldi r24, 0xFF ; 255 + 390: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 392: 82 81 ldd r24, Z+2 ; 0x02 + 394: 88 23 and r24, r24 + 396: ec f7 brge .-6 ; 0x392 + + // Return received data + + return SPIC.DATA; + 398: e0 ec ldi r30, 0xC0 ; 192 + 39a: f8 e0 ldi r31, 0x08 ; 8 + 39c: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 39e: 8f ef ldi r24, 0xFF ; 255 + 3a0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 3a2: 82 81 ldd r24, Z+2 ; 0x02 + 3a4: 88 23 and r24, r24 + 3a6: ec f7 brge .-6 ; 0x3a2 + + // Return received data + + return SPIC.DATA; + 3a8: e0 ec ldi r30, 0xC0 ; 192 + 3aa: f8 e0 ldi r31, 0x08 ; 8 + 3ac: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 3ae: 8f ef ldi r24, 0xFF ; 255 + 3b0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 3b2: 82 81 ldd r24, Z+2 ; 0x02 + 3b4: 88 23 and r24, r24 + 3b6: ec f7 brge .-6 ; 0x3b2 + + // Return received data + + return SPIC.DATA; + 3b8: e0 ec ldi r30, 0xC0 ; 192 + 3ba: f8 e0 ldi r31, 0x08 ; 8 + 3bc: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 3be: 8f ef ldi r24, 0xFF ; 255 + 3c0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 3c2: 82 81 ldd r24, Z+2 ; 0x02 + 3c4: 88 23 and r24, r24 + 3c6: ec f7 brge .-6 ; 0x3c2 + + // Return received data + + return SPIC.DATA; + 3c8: e0 ec ldi r30, 0xC0 ; 192 + 3ca: f8 e0 ldi r31, 0x08 ; 8 + 3cc: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 3ce: 8f ef ldi r24, 0xFF ; 255 + 3d0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 3d2: 82 81 ldd r24, Z+2 ; 0x02 + 3d4: 88 23 and r24, r24 + 3d6: ec f7 brge .-6 ; 0x3d2 + + // Return received data + + return SPIC.DATA; + 3d8: e0 ec ldi r30, 0xC0 ; 192 + 3da: f8 e0 ldi r31, 0x08 ; 8 + 3dc: 83 81 ldd r24, Z+3 ; 0x03 + * \param El dato a transmitir + * \return El dato leido del ADC + */ +inline uint8_t adcport_tranceiv(uint8_t data){ + // + SPIC.DATA = data; + 3de: 8f ef ldi r24, 0xFF ; 255 + 3e0: 83 83 std Z+3, r24 ; 0x03 + + //Wait until transmission complete + while( !(SPIC.STATUS & SPI_IF_bm)); + 3e2: 82 81 ldd r24, Z+2 ; 0x02 + 3e4: 88 23 and r24, r24 + 3e6: ec f7 brge .-6 ; 0x3e2 + + // Return received data + + return SPIC.DATA; + 3e8: e0 ec ldi r30, 0xC0 ; 192 + 3ea: f8 e0 ldi r31, 0x08 ; 8 + 3ec: 83 81 ldd r24, Z+3 ; 0x03 + 3ee: 08 95 ret + +000003f0 : + dato[i] = adcport_tranceiv(0); //Escribo el bit más significativo en el byte de orden 0 y el menos significativo en el orden (ADC_DATASZ-1) + //Si se desease almacenar el dato de byte menos significativo a más signficativo: dato[j-i-1] = adcport_tranceiv(0); +} + +void config_adc(void) +{ + 3f0: 1f 93 push r17 + 3f2: cf 93 push r28 + 3f4: df 93 push r29 + PORTSPI.OUTCLR = SPI_SS_bm; + 3f6: c0 e4 ldi r28, 0x40 ; 64 + 3f8: d6 e0 ldi r29, 0x06 ; 6 + 3fa: 10 e1 ldi r17, 0x10 ; 16 + 3fc: 1e 83 std Y+6, r17 ; 0x06 + adcport_write_reset(); + 3fe: 0e 94 b5 01 call 0x36a ; 0x36a + PORTSPI.OUTSET = SPI_SS_bm; + 402: 1d 83 std Y+5, r17 ; 0x05 + #else + //round up by default + __ticks_dc = (uint32_t)(ceil(fabs(__tmp))); + #endif + + __builtin_avr_delay_cycles(__ticks_dc); + 404: 8f e5 ldi r24, 0x5F ; 95 + 406: 99 e0 ldi r25, 0x09 ; 9 + 408: 01 97 sbiw r24, 0x01 ; 1 + 40a: f1 f7 brne .-4 ; 0x408 + 40c: 00 c0 rjmp .+0 ; 0x40e + 40e: 00 00 nop + + _delay_us(300); + + PORTSPI.OUTCLR = SPI_SS_bm; + 410: 1e 83 std Y+6, r17 ; 0x06 + adcport_write_adcmode(); + 412: 0e 94 e4 00 call 0x1c8 ; 0x1c8 + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_interfmode(); + 416: 0e 94 18 01 call 0x230 ; 0x230 + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_filtcon0(); + 41a: 0e 94 fe 00 call 0x1fc ; 0x1fc + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_setupcon0(); + 41e: 0e 94 9a 01 call 0x334 ; 0x334 + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_chmapreg0(); + 422: 0e 94 31 01 call 0x262 ; 0x262 + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_chmapreg1(); + 426: 0e 94 4c 01 call 0x298 ; 0x298 + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_chmapreg2(); + 42a: 0e 94 66 01 call 0x2cc ; 0x2cc + //PORTSPI.OUTSET = SPI_SS_bm; + + //PORTSPI.OUTCLR = SPI_SS_bm; + adcport_write_chmapreg3(); + 42e: 0e 94 80 01 call 0x300 ; 0x300 + PORTSPI.OUTSET = SPI_SS_bm; + 432: 1d 83 std Y+5, r17 ; 0x05 + +} + 434: df 91 pop r29 + 436: cf 91 pop r28 + 438: 1f 91 pop r17 + 43a: 08 95 ret + +0000043c
: + +int aux = 0; +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + 43c: 0e 94 cf 03 call 0x79e ; 0x79e + config_sysclock(); + 440: 0e 94 49 04 call 0x892 ; 0x892 + config_spiparm(); + 444: 0e 94 e4 02 call 0x5c8 ; 0x5c8 + config_fpgaport(); + 448: 0e 94 e8 02 call 0x5d0 ; 0x5d0 + config_adc(); + 44c: 0e 94 f8 01 call 0x3f0 ; 0x3f0 + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + 450: 84 e0 ldi r24, 0x04 ; 4 + 452: e0 ea ldi r30, 0xA0 ; 160 + 454: f0 e0 ldi r31, 0x00 ; 0 + 456: 82 83 std Z+2, r24 ; 0x02 + habilitar_interrupciones_globales(); + 458: 0e 94 1b 03 call 0x636 ; 0x636 + 45c: ff cf rjmp .-2 ; 0x45c + +0000045e <__vector_64>: + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + 45e: 1f 92 push r1 + 460: 0f 92 push r0 + 462: 0f b6 in r0, 0x3f ; 63 + 464: 0f 92 push r0 + 466: 11 24 eor r1, r1 + 468: 8f 93 push r24 + 46a: 9f 93 push r25 + 46c: ef 93 push r30 + 46e: ff 93 push r31 + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + 470: e0 e6 ldi r30, 0x60 ; 96 + 472: f6 e0 ldi r31, 0x06 ; 6 + 474: 80 85 ldd r24, Z+8 ; 0x08 + 476: 81 ff sbrs r24, 1 + 478: 11 c0 rjmp .+34 ; 0x49c <__vector_64+0x3e> + { + PORTSPI.SPI_INTFLAGS =0b00000001; + 47a: 81 e0 ldi r24, 0x01 ; 1 + 47c: e0 e4 ldi r30, 0x40 ; 64 + 47e: f6 e0 ldi r31, 0x06 ; 6 + 480: 84 87 std Z+12, r24 ; 0x0c + PORT_PPS.PPS_FPGA_INTFLAGS =0b00000010; + 482: 92 e0 ldi r25, 0x02 ; 2 + 484: e0 e2 ldi r30, 0x20 ; 32 + 486: f6 e0 ldi r31, 0x06 ; 6 + 488: 94 87 std Z+12, r25 ; 0x0c + PMIC.CTRL |= hab_prioridad_media; + 48a: e0 ea ldi r30, 0xA0 ; 160 + 48c: f0 e0 ldi r31, 0x00 ; 0 + 48e: 92 81 ldd r25, Z+2 ; 0x02 + 490: 92 60 ori r25, 0x02 ; 2 + 492: 92 83 std Z+2, r25 ; 0x02 + PORT_LOCKOUT.OUTSET = LOCK_OUT; + 494: e0 e0 ldi r30, 0x00 ; 0 + 496: f6 e0 ldi r31, 0x06 ; 6 + 498: 85 83 std Z+5, r24 ; 0x05 + 49a: 0c c0 rjmp .+24 ; 0x4b4 <__vector_64+0x56> + //PORTD.OUTSET = PIN4_bm; + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + 49c: e0 ea ldi r30, 0xA0 ; 160 + 49e: f0 e0 ldi r31, 0x00 ; 0 + 4a0: 82 81 ldd r24, Z+2 ; 0x02 + 4a2: 8d 7f andi r24, 0xFD ; 253 + 4a4: 82 83 std Z+2, r24 ; 0x02 + PMIC.CTRL &= ~hab_prioridad_baja; + 4a6: 82 81 ldd r24, Z+2 ; 0x02 + 4a8: 8e 7f andi r24, 0xFE ; 254 + 4aa: 82 83 std Z+2, r24 ; 0x02 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 4ac: 81 e0 ldi r24, 0x01 ; 1 + 4ae: e0 e0 ldi r30, 0x00 ; 0 + 4b0: f6 e0 ldi r31, 0x06 ; 6 + 4b2: 86 83 std Z+6, r24 ; 0x06 + //PORTSPI.OUTSET = SPI_SS_bm; + //PORTD.OUTCLR = PIN4_bm; + } +} + 4b4: ff 91 pop r31 + 4b6: ef 91 pop r30 + 4b8: 9f 91 pop r25 + 4ba: 8f 91 pop r24 + 4bc: 0f 90 pop r0 + 4be: 0f be out 0x3f, r0 ; 63 + 4c0: 0f 90 pop r0 + 4c2: 1f 90 pop r1 + 4c4: 18 95 reti + +000004c6 <__vector_35>: +//Habilito interrupciones de prioridad baja +//Selecciono el chip del ADC para iniciar comunicación. +//Al iniciar esta comunicación se indicará al ADC que use el RDYbar +//Esta será nuestra interrupción para lectura del ADC y envío de dato a la FPGA +ISR(INT_PPS) +{ + 4c6: 1f 92 push r1 + 4c8: 0f 92 push r0 + 4ca: 0f b6 in r0, 0x3f ; 63 + 4cc: 0f 92 push r0 + 4ce: 11 24 eor r1, r1 + 4d0: 8f 93 push r24 + 4d2: ef 93 push r30 + 4d4: ff 93 push r31 + PMIC.CTRL &= ~hab_prioridad_baja; + 4d6: e0 ea ldi r30, 0xA0 ; 160 + 4d8: f0 e0 ldi r31, 0x00 ; 0 + 4da: 82 81 ldd r24, Z+2 ; 0x02 + 4dc: 8e 7f andi r24, 0xFE ; 254 + 4de: 82 83 std Z+2, r24 ; 0x02 + PORTSPI.SPI_INTFLAGS =0b00000001; + 4e0: e0 e4 ldi r30, 0x40 ; 64 + 4e2: f6 e0 ldi r31, 0x06 ; 6 + 4e4: 81 e0 ldi r24, 0x01 ; 1 + 4e6: 84 87 std Z+12, r24 ; 0x0c + PORTSPI.SPI_INTFLAGS =0b00000001; + 4e8: 84 87 std Z+12, r24 ; 0x0c + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + aux = 0; + 4f2: 10 92 00 20 sts 0x2000, r1 + 4f6: 10 92 01 20 sts 0x2001, r1 + //if(aux==0) + PMIC.CTRL |= hab_prioridad_baja; + 4fa: e0 ea ldi r30, 0xA0 ; 160 + 4fc: f0 e0 ldi r31, 0x00 ; 0 + 4fe: 82 81 ldd r24, Z+2 ; 0x02 + 500: 81 60 ori r24, 0x01 ; 1 + 502: 82 83 std Z+2, r24 ; 0x02 + PORTSPI.SPI_INTFLAGS =0b00000001; + 504: e0 e4 ldi r30, 0x40 ; 64 + 506: f6 e0 ldi r31, 0x06 ; 6 + 508: 81 e0 ldi r24, 0x01 ; 1 + 50a: 84 87 std Z+12, r24 ; 0x0c + PORTSPI.OUTSET = SPI_SS_bm; + 50c: 80 e1 ldi r24, 0x10 ; 16 + 50e: 85 83 std Z+5, r24 ; 0x05 + asm("nop"); + 510: 00 00 nop + PORT_FPGA.OUTSET = CLK_FPGA; + 512: 84 e0 ldi r24, 0x04 ; 4 + 514: e0 e6 ldi r30, 0x60 ; 96 + 516: f6 e0 ldi r31, 0x06 ; 6 + 518: 85 83 std Z+5, r24 ; 0x05 + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + 532: 00 00 nop + PORTSPI.OUTCLR = SPI_SS_bm; + 534: 80 e1 ldi r24, 0x10 ; 16 + 536: e0 e4 ldi r30, 0x40 ; 64 + 538: f6 e0 ldi r31, 0x06 ; 6 + 53a: 86 83 std Z+6, r24 ; 0x06 + 53c: 8a e6 ldi r24, 0x6A ; 106 + 53e: 8a 95 dec r24 + 540: f1 f7 brne .-4 ; 0x53e <__vector_35+0x78> + 542: 00 c0 rjmp .+0 ; 0x544 <__vector_35+0x7e> + + _delay_us(10); + PORTSPI.SPI_INTFLAGS =0b00000001; + 544: 81 e0 ldi r24, 0x01 ; 1 + 546: 84 87 std Z+12, r24 ; 0x0c + //envio_datos_fpga(); + //PORTSPI.OUTSET = SPI_SS_bm; + +} + 548: ff 91 pop r31 + 54a: ef 91 pop r30 + 54c: 8f 91 pop r24 + 54e: 0f 90 pop r0 + 550: 0f be out 0x3f, r0 ; 63 + 552: 0f 90 pop r0 + 554: 1f 90 pop r1 + 556: 18 95 reti + +00000558 <__vector_2>: + +ISR(INT_RDY) +{ + 558: 1f 92 push r1 + 55a: 0f 92 push r0 + 55c: 0f b6 in r0, 0x3f ; 63 + 55e: 0f 92 push r0 + 560: 11 24 eor r1, r1 + 562: 2f 93 push r18 + 564: 3f 93 push r19 + 566: 4f 93 push r20 + 568: 5f 93 push r21 + 56a: 6f 93 push r22 + 56c: 7f 93 push r23 + 56e: 8f 93 push r24 + 570: 9f 93 push r25 + 572: af 93 push r26 + 574: bf 93 push r27 + 576: ef 93 push r30 + 578: ff 93 push r31 + //PMIC.CTRL &= ~hab_prioridad_media; + //PMIC.CTRL &= ~hab_prioridad_alta; + if(aux < 20000){ + 57a: 80 91 00 20 lds r24, 0x2000 + 57e: 90 91 01 20 lds r25, 0x2001 + 582: 80 32 cpi r24, 0x20 ; 32 + 584: 9e 44 sbci r25, 0x4E ; 78 + 586: 5c f4 brge .+22 ; 0x59e <__vector_2+0x46> + envio_datos_fpga(); + 588: 0e 94 b9 03 call 0x772 ; 0x772 + aux = aux+1; + 58c: 80 91 00 20 lds r24, 0x2000 + 590: 90 91 01 20 lds r25, 0x2001 + 594: 01 96 adiw r24, 0x01 ; 1 + 596: 80 93 00 20 sts 0x2000, r24 + 59a: 90 93 01 20 sts 0x2001, r25 + } + //PORTSPI.OUTCLR = SPI_SS_bm; + //adcport_read_filtcon0(); + //PMIC.CTRL |= hab_prioridad_media; + //PMIC.CTRL |= hab_prioridad_alta; + PORTSPI.SPI_INTFLAGS =0b00000001; + 59e: 81 e0 ldi r24, 0x01 ; 1 + 5a0: e0 e4 ldi r30, 0x40 ; 64 + 5a2: f6 e0 ldi r31, 0x06 ; 6 + 5a4: 84 87 std Z+12, r24 ; 0x0c +} + 5a6: ff 91 pop r31 + 5a8: ef 91 pop r30 + 5aa: bf 91 pop r27 + 5ac: af 91 pop r26 + 5ae: 9f 91 pop r25 + 5b0: 8f 91 pop r24 + 5b2: 7f 91 pop r23 + 5b4: 6f 91 pop r22 + 5b6: 5f 91 pop r21 + 5b8: 4f 91 pop r20 + 5ba: 3f 91 pop r19 + 5bc: 2f 91 pop r18 + 5be: 0f 90 pop r0 + 5c0: 0f be out 0x3f, r0 ; 63 + 5c2: 0f 90 pop r0 + 5c4: 1f 90 pop r1 + 5c6: 18 95 reti + +000005c8 : +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE1_bm | SPI_MODE0_bm | SPI_CLK2X_bm);//SPI_PRESCALER1_bm | SPI_CLK2X_bm); + 5c8: 8c ed ldi r24, 0xDC ; 220 + 5ca: 80 93 c0 08 sts 0x08C0, r24 + 5ce: 08 95 ret + +000005d0 : +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + 5d0: cf 93 push r28 + 5d2: df 93 push r29 + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; + 5d4: e0 e6 ldi r30, 0x60 ; 96 + 5d6: f6 e0 ldi r31, 0x06 ; 6 + 5d8: 11 8a std Z+17, r1 ; 0x11 + PORT_FPGA.DIRCLR = LOCK_FPGA; + 5da: 92 e0 ldi r25, 0x02 ; 2 + 5dc: 92 83 std Z+2, r25 ; 0x02 + + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + 5de: 20 e1 ldi r18, 0x10 ; 16 + 5e0: 22 8b std Z+18, r18 ; 0x12 + PORT_FPGA.DIRSET = CLK_FPGA; + 5e2: 84 e0 ldi r24, 0x04 ; 4 + 5e4: 81 83 std Z+1, r24 ; 0x01 + PORT_FPGA.OUTCLR = CLK_FPGA; + 5e6: 86 83 std Z+6, r24 ; 0x06 + //PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + 5e8: a0 e2 ldi r26, 0x20 ; 32 + 5ea: b6 e0 ldi r27, 0x06 ; 6 + 5ec: 12 96 adiw r26, 0x02 ; 2 + 5ee: 8c 93 st X, r24 + 5f0: 12 97 sbiw r26, 0x02 ; 2 + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + 5f2: 52 96 adiw r26, 0x12 ; 18 + 5f4: 2c 93 st X, r18 + 5f6: 52 97 sbiw r26, 0x12 ; 18 + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + 5f8: c0 e0 ldi r28, 0x00 ; 0 + 5fa: d6 e0 ldi r29, 0x06 ; 6 + 5fc: 21 e0 ldi r18, 0x01 ; 1 + 5fe: 29 83 std Y+1, r18 ; 0x01 + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + 600: 2e 83 std Y+6, r18 ; 0x06 + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + 602: 21 85 ldd r18, Z+9 ; 0x09 + 604: 23 60 ori r18, 0x03 ; 3 + 606: 21 87 std Z+9, r18 ; 0x09 + PORT_FPGA.INT0MASK = LOCK_FPGA; + 608: 92 87 std Z+10, r25 ; 0x0a + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + 60a: 91 89 ldd r25, Z+17 ; 0x11 + 60c: 98 7f andi r25, 0xF8 ; 248 + 60e: 91 8b std Z+17, r25 ; 0x11 + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + 610: 91 85 ldd r25, Z+9 ; 0x09 + 612: 93 7f andi r25, 0xF3 ; 243 + 614: 98 60 ori r25, 0x08 ; 8 + 616: 19 96 adiw r26, 0x09 ; 9 + 618: 9c 93 st X, r25 + 61a: 19 97 sbiw r26, 0x09 ; 9 + PORT_PPS.INT1MASK = PPS_FPGA; + 61c: 1b 96 adiw r26, 0x0b ; 11 + 61e: 8c 93 st X, r24 + 620: 1b 97 sbiw r26, 0x0b ; 11 + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; + 622: 52 96 adiw r26, 0x12 ; 18 + 624: 8c 91 ld r24, X + 626: 52 97 sbiw r26, 0x12 ; 18 + 628: 88 7f andi r24, 0xF8 ; 248 + 62a: 81 60 ori r24, 0x01 ; 1 + 62c: 52 96 adiw r26, 0x12 ; 18 + 62e: 8c 93 st X, r24 +} + 630: df 91 pop r29 + 632: cf 91 pop r28 + 634: 08 95 ret + +00000636 : + PMIC.CTRL |= level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); + 636: 78 94 sei + 638: 08 95 ret + +0000063a : + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + 662: 84 e0 ldi r24, 0x04 ; 4 + 664: e0 e6 ldi r30, 0x60 ; 96 + 666: f6 e0 ldi r31, 0x06 ; 6 + 668: 85 83 std Z+5, r24 ; 0x05 + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTCLR = CLK_FPGA; + 692: 86 83 std Z+6, r24 ; 0x06 + //_delay_ms(100); + temp_regin = PORT_FPGA.OUTCLR; + 694: 86 81 ldd r24, Z+6 ; 0x06 + temp_dato = fpga_dato & nibble_alto_bm; + //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato >> fpga_salidas_nibblealto_bp); + PORT_FPGA.OUT = (0b01001000); + 696: 88 e4 ldi r24, 0x48 ; 72 + 698: 84 83 std Z+4, r24 ; 0x04 + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + 6c2: 84 e0 ldi r24, 0x04 ; 4 + 6c4: 85 83 std Z+5, r24 ; 0x05 + ... + asm("nop"); + asm("nop"); + asm("nop"); + //_delay_ms(200); + //Nibble inferior 3 a 0 + PORT_FPGA.OUTCLR = CLK_FPGA; + 6ee: 86 83 std Z+6, r24 ; 0x06 + temp_regin = PORT_FPGA.OUTCLR; + 6f0: 86 81 ldd r24, Z+6 ; 0x06 + temp_dato = fpga_dato & nibble_bajo_bm; + //_delay_ms(100); + //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato << fpga_salidas_nibblebajo_bp); + PORT_FPGA.OUT = (0b01100000); + 6f2: 80 e6 ldi r24, 0x60 ; 96 + 6f4: 84 83 std Z+4, r24 ; 0x04 + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + 71e: 84 e0 ldi r24, 0x04 ; 4 + 720: 85 83 std Z+5, r24 ; 0x05 + ... + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + 746: 08 95 ret + +00000748 : + //envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + 748: 0f 93 push r16 + 74a: 1f 93 push r17 + 74c: cf 93 push r28 + 74e: df 93 push r29 + 750: 8c 01 movw r16, r24 + //dato_adc[1] = 0b11111110; + //dato_adc[0] = 0b11111110; + //dato_adc[2] = 0b11111110; + //dato_adc[1] = 0b11111111; + //dato_adc[0] = 0b11111110; + for(int i=0; i + //dato_adc[1] = 0b11111110; + //dato_adc[0] = 0b11111110; + //dato_adc[2] = 0b11111110; + //dato_adc[1] = 0b11111111; + //dato_adc[0] = 0b11111110; + for(int i=0; i + envio_nibble(dato_adc[i]); + + //envio_nibble(dato_adc[0]); +} + 768: df 91 pop r29 + 76a: cf 91 pop r28 + 76c: 1f 91 pop r17 + 76e: 0f 91 pop r16 + 770: 08 95 ret + +00000772 : + asm("nop"); + //_delay_ms(200); +} + +void envio_datos_fpga(void) +{ + 772: cf 93 push r28 + 774: df 93 push r29 + 776: 00 d0 rcall .+0 ; 0x778 + 778: 1f 92 push r1 + 77a: cd b7 in r28, 0x3d ; 61 + 77c: de b7 in r29, 0x3e ; 62 + uint8_t fpga_dato[ADC_DATASZ] ; + //uint8_t aux_dato[ADC_DATASZ] ; + + adcport_read_data(fpga_dato,ADC_DATASZ); + 77e: 63 e0 ldi r22, 0x03 ; 3 + 780: 70 e0 ldi r23, 0x00 ; 0 + 782: ce 01 movw r24, r28 + 784: 01 96 adiw r24, 0x01 ; 1 + 786: 0e 94 ca 00 call 0x194 ; 0x194 + //aux_dato[1] = fpga_dato[1]; + //aux_dato[2] = fpga_dato[2]; + //adcport_read_data(fpga_dato,ADC_DATASZ); + + //envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); + 78a: ce 01 movw r24, r28 + 78c: 01 96 adiw r24, 0x01 ; 1 + 78e: 0e 94 a4 03 call 0x748 ; 0x748 +} + 792: 23 96 adiw r28, 0x03 ; 3 + 794: cd bf out 0x3d, r28 ; 61 + 796: de bf out 0x3e, r29 ; 62 + 798: df 91 pop r29 + 79a: cf 91 pop r28 + 79c: 08 95 ret + +0000079e : +#include "commSPI_ADC.h" + +inline void config_puertos(void){ +//Configuracion pines del puerto A: PA7-PA0 +//Pines de entrada y totem_pullup +PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; + 79e: e0 e0 ldi r30, 0x00 ; 0 + 7a0: f6 e0 ldi r31, 0x06 ; 6 + 7a2: 88 e1 ldi r24, 0x18 ; 24 + 7a4: 87 8b std Z+23, r24 ; 0x17 +PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; + 7a6: 86 8b std Z+22, r24 ; 0x16 +PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; + 7a8: 85 8b std Z+21, r24 ; 0x15 +PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; + 7aa: 84 8b std Z+20, r24 ; 0x14 +PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; + 7ac: 83 8b std Z+19, r24 ; 0x13 +PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; + 7ae: 82 8b std Z+18, r24 ; 0x12 +PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; + 7b0: 81 8b std Z+17, r24 ; 0x11 +PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + 7b2: 9e ef ldi r25, 0xFE ; 254 + 7b4: 92 83 std Z+2, r25 ; 0x02 +//Pin de salida A0 +//Wired AND. Esto pues podrá irse a alta por defecto y si existe una tensión +//La línea tendrá el valor de tensión externa pero si es entrada con impedancia alta leerá el valor en alta +//Valor por defecto salida: PA0 = low + +PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; + 7b6: 98 e3 ldi r25, 0x38 ; 56 + 7b8: 90 8b std Z+16, r25 ; 0x10 +PORTA.OUTCLR = PIN0_bm; + 7ba: 91 e0 ldi r25, 0x01 ; 1 + 7bc: 96 83 std Z+6, r25 ; 0x06 +PORTA.DIRSET = PIN0_bm; + 7be: 91 83 std Z+1, r25 ; 0x01 + +//Configuracion pines del puerto B: PB3-PB0 +//Pines de entrada y totem_pullup +PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; + 7c0: e0 e2 ldi r30, 0x20 ; 32 + 7c2: f6 e0 ldi r31, 0x06 ; 6 + 7c4: 83 8b std Z+19, r24 ; 0x13 +PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; + 7c6: 82 8b std Z+18, r24 ; 0x12 +PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; + 7c8: 81 8b std Z+17, r24 ; 0x11 +PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; + 7ca: 80 8b std Z+16, r24 ; 0x10 +PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + 7cc: 2f e0 ldi r18, 0x0F ; 15 + 7ce: 22 83 std Z+2, r18 ; 0x02 + +//Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI +//Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 +//Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. +PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; + 7d0: e0 e4 ldi r30, 0x40 ; 64 + 7d2: f6 e0 ldi r31, 0x06 ; 6 + 7d4: 86 8b std Z+22, r24 ; 0x16 +PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; + 7d6: 83 8b std Z+19, r24 ; 0x13 +PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; + 7d8: 82 8b std Z+18, r24 ; 0x12 +PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; + 7da: 81 8b std Z+17, r24 ; 0x11 +PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; + 7dc: 80 8b std Z+16, r24 ; 0x10 +PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + 7de: 9f e4 ldi r25, 0x4F ; 79 + 7e0: 92 83 std Z+2, r25 ; 0x02 + +//Pines de salida wiredand-pull +//Valor por defecto salida: PC4,PC7 = low +//Valor por defecto salida: PC5 = set + +PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; + 7e2: 15 8a std Z+21, r1 ; 0x15 +PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; + 7e4: 17 8a std Z+23, r1 ; 0x17 +PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; + 7e6: 14 8a std Z+20, r1 ; 0x14 +PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; + 7e8: 90 eb ldi r25, 0xB0 ; 176 + 7ea: 91 83 std Z+1, r25 ; 0x01 +PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; + 7ec: 90 e9 ldi r25, 0x90 ; 144 + 7ee: 95 83 std Z+5, r25 ; 0x05 +PORTSPI.OUTCLR = SPI_MOSI_bm; + 7f0: 90 e2 ldi r25, 0x20 ; 32 + 7f2: 96 83 std Z+6, r25 ; 0x06 +//Configuracion pines del puerto D: PD7-PD0 +//Pines de entrada y totem_pullup: PIN7 y PIN0 +//NOTA +//PARA EL FW FINAL REVISAR SI PD2 SERÁ ENTRADA O NO +//NOTA FIN +PORTD.DIRSET = PIN2_bm; + 7f4: a0 e6 ldi r26, 0x60 ; 96 + 7f6: b6 e0 ldi r27, 0x06 ; 6 + 7f8: 94 e0 ldi r25, 0x04 ; 4 + 7fa: 11 96 adiw r26, 0x01 ; 1 + 7fc: 9c 93 st X, r25 + 7fe: 11 97 sbiw r26, 0x01 ; 1 +PORTD.OUTCLR = PIN2_bm; + 800: 16 96 adiw r26, 0x06 ; 6 + 802: 9c 93 st X, r25 + 804: 16 97 sbiw r26, 0x06 ; 6 + + +PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; + 806: 57 96 adiw r26, 0x17 ; 23 + 808: 8c 93 st X, r24 + 80a: 57 97 sbiw r26, 0x17 ; 23 +PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; + 80c: 50 96 adiw r26, 0x10 ; 16 + 80e: 8c 93 st X, r24 + 810: 50 97 sbiw r26, 0x10 ; 16 +PORTD.DIRCLR = PIN7_bm | PIN1_bm| PIN0_bm; + 812: 93 e8 ldi r25, 0x83 ; 131 + 814: 12 96 adiw r26, 0x02 ; 2 + 816: 9c 93 st X, r25 + 818: 12 97 sbiw r26, 0x02 ; 2 +//Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas serán entradas provenientes de la fpga +//PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + +PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 81a: 90 e1 ldi r25, 0x10 ; 16 + 81c: 51 96 adiw r26, 0x11 ; 17 + 81e: 9c 93 st X, r25 + 820: 51 97 sbiw r26, 0x11 ; 17 +//Pines de salida tipo wired-and-pull +//Valor por defecto PD6, PD5, PD4, PD3 = low + +PORTD.PIN6CTRL = PORT_OPC_TOTEM_gc; + 822: 56 96 adiw r26, 0x16 ; 22 + 824: 1c 92 st X, r1 + 826: 56 97 sbiw r26, 0x16 ; 22 +PORTD.PIN5CTRL = PORT_OPC_TOTEM_gc; + 828: 55 96 adiw r26, 0x15 ; 21 + 82a: 1c 92 st X, r1 + 82c: 55 97 sbiw r26, 0x15 ; 21 +PORTD.PIN4CTRL = PORT_OPC_TOTEM_gc; + 82e: 54 96 adiw r26, 0x14 ; 20 + 830: 1c 92 st X, r1 + 832: 54 97 sbiw r26, 0x14 ; 20 +PORTD.PIN3CTRL = PORT_OPC_TOTEM_gc; + 834: 53 96 adiw r26, 0x13 ; 19 + 836: 1c 92 st X, r1 + 838: 53 97 sbiw r26, 0x13 ; 19 +PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 83a: 38 e7 ldi r19, 0x78 ; 120 + 83c: 11 96 adiw r26, 0x01 ; 1 + 83e: 3c 93 st X, r19 + 840: 11 97 sbiw r26, 0x01 ; 1 +PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + 842: 16 96 adiw r26, 0x06 ; 6 + 844: 3c 93 st X, r19 + +//Configuracion pines del puerto E: PE3-PE0 +//Pines de entrada y totem_pullup: PIN3 - PIN0 + +PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; + 846: a0 e8 ldi r26, 0x80 ; 128 + 848: b6 e0 ldi r27, 0x06 ; 6 + 84a: 53 96 adiw r26, 0x13 ; 19 + 84c: 8c 93 st X, r24 + 84e: 53 97 sbiw r26, 0x13 ; 19 +PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; + 850: 52 96 adiw r26, 0x12 ; 18 + 852: 8c 93 st X, r24 + 854: 52 97 sbiw r26, 0x12 ; 18 +PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; + 856: 51 96 adiw r26, 0x11 ; 17 + 858: 8c 93 st X, r24 + 85a: 51 97 sbiw r26, 0x11 ; 17 +PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; + 85c: 50 96 adiw r26, 0x10 ; 16 + 85e: 8c 93 st X, r24 + 860: 50 97 sbiw r26, 0x10 ; 16 +PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + 862: 12 96 adiw r26, 0x02 ; 2 + 864: 2c 93 st X, r18 + +//Configuracion pines del puerto R: PR1-PR0 +//Pines de entrada y totem_pulldown: PIN0 +PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; + 866: a0 ee ldi r26, 0xE0 ; 224 + 868: b7 e0 ldi r27, 0x07 ; 7 + 86a: 51 96 adiw r26, 0x11 ; 17 + 86c: 9c 93 st X, r25 + 86e: 51 97 sbiw r26, 0x11 ; 17 +PORTR.DIRCLR = PIN1_bm| PIN0_bm; + 870: 93 e0 ldi r25, 0x03 ; 3 + 872: 12 96 adiw r26, 0x02 ; 2 + 874: 9c 93 st X, r25 + 876: 12 97 sbiw r26, 0x02 ; 2 +//Pines de entrada y totem_pulldup:PIN1 +PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + 878: 50 96 adiw r26, 0x10 ; 16 + 87a: 8c 93 st X, r24 + +//Configuración como interrupción del pin SPI_MISO_RDY + +PORTSPI.INT0MASK = SPI_MISO_bm; + 87c: 80 e4 ldi r24, 0x40 ; 64 + 87e: 82 87 std Z+10, r24 ; 0x0a +PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; + 880: 81 85 ldd r24, Z+9 ; 0x09 + 882: 8c 7f andi r24, 0xFC ; 252 + 884: 81 60 ori r24, 0x01 ; 1 + 886: 81 87 std Z+9, r24 ; 0x09 +PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + 888: 86 89 ldd r24, Z+22 ; 0x16 + 88a: 88 7f andi r24, 0xF8 ; 248 + 88c: 82 60 ori r24, 0x02 ; 2 + 88e: 86 8b std Z+22, r24 ; 0x16 + 890: 08 95 ret + +00000892 : +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + +CLK_PSCTRL = ((0< +while(!(OSC.STATUS & OSC_RC32MRDY_bm)); /* Wait for 32MHz oscillator to stabilize */ + 8a6: e0 e5 ldi r30, 0x50 ; 80 + 8a8: f0 e0 ldi r31, 0x00 ; 0 + 8aa: 81 81 ldd r24, Z+1 ; 0x01 + 8ac: 81 ff sbrs r24, 1 + 8ae: fd cf rjmp .-6 ; 0x8aa +DFLLRC32M.CTRL = DFLL_ENABLE_bm ; /* Enable DFLL - defaults to calibrate against internal 32Khz clock */ + 8b0: 81 e0 ldi r24, 0x01 ; 1 + 8b2: 80 93 60 00 sts 0x0060, r24 +OSC.DFLLCTRL &= 0xFD; //Habilito calibración interna mediante reloj de 32K + 8b6: e0 e5 ldi r30, 0x50 ; 80 + 8b8: f0 e0 ldi r31, 0x00 ; 0 + 8ba: 96 81 ldd r25, Z+6 ; 0x06 + 8bc: 9d 7f andi r25, 0xFD ; 253 + 8be: 96 83 std Z+6, r25 ; 0x06 +CCP = CCP_IOREG_gc; /* Disable register security for clock update */ + 8c0: 98 ed ldi r25, 0xD8 ; 216 + 8c2: 94 bf out 0x34, r25 ; 52 +CLK.CTRL = CLK_SCLKSEL_RC32M_gc; /* Switch to 32MHz clock */ + 8c4: 80 93 40 00 sts 0x0040, r24 +OSC.CTRL &= ~OSC_RC2MEN_bm; + 8c8: 80 81 ld r24, Z + 8ca: 8e 7f andi r24, 0xFE ; 254 + 8cc: 80 83 st Z, r24 + 8ce: 08 95 ret + +000008d0 <_exit>: + 8d0: f8 94 cli + +000008d2 <__stop_program>: + 8d2: ff cf rjmp .-2 ; 0x8d2 <__stop_program> Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.map =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.map b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.map new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADCSPI_v01.map (revision 224) @@ -0,0 +1,639 @@ +Archive member included because of file (symbol) + +c:/program files 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.text.adcport_write_setupcon0 + 0x00000334 0x36 ADC_7176_2.o + 0x00000334 adcport_write_setupcon0 + .text.adcport_write_reset + 0x0000036a 0x86 ADC_7176_2.o + 0x0000036a adcport_write_reset + .text.config_adc + 0x000003f0 0x4c ADC_7176_2.o + 0x000003f0 config_adc + .text.main 0x0000043c 0x22 main.o + 0x0000043c main + .text.__vector_64 + 0x0000045e 0x68 main.o + 0x0000045e __vector_64 + .text.__vector_35 + 0x000004c6 0x92 main.o + 0x000004c6 __vector_35 + .text.__vector_2 + 0x00000558 0x70 main.o + 0x00000558 __vector_2 + .text.config_spiparm + 0x000005c8 0x8 commSPI_ADC.o + 0x000005c8 config_spiparm + .text.config_fpgaport + 0x000005d0 0x66 fpga_port.o + 0x000005d0 config_fpgaport + .text.habilitar_interrupciones_globales + 0x00000636 0x4 fpga_port.o + 0x00000636 habilitar_interrupciones_globales + .text.envio_nibble + 0x0000063a 0x10e fpga_port.o + 0x0000063a envio_nibble + .text.envio_dato_adc + 0x00000748 0x2a fpga_port.o + 0x00000748 envio_dato_adc + .text.envio_datos_fpga + 0x00000772 0x2c fpga_port.o + 0x00000772 envio_datos_fpga + .text.config_puertos + 0x0000079e 0xf4 Ports.o + 0x0000079e config_puertos + .text.config_sysclock + 0x00000892 0x3e sys_clock.o + 0x00000892 config_sysclock + 0x000008d0 . = ALIGN (0x2) + *(.fini9) + .fini9 0x000008d0 0x0 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o) + 0x000008d0 _exit + 0x000008d0 exit + *(.fini9) + *(.fini8) + *(.fini8) + *(.fini7) + *(.fini7) + *(.fini6) + *(.fini6) + *(.fini5) + *(.fini5) + *(.fini4) + *(.fini4) + *(.fini3) + *(.fini3) + *(.fini2) + *(.fini2) + *(.fini1) + *(.fini1) + *(.fini0) + .fini0 0x000008d0 0x4 c:/program files (x86)/atmel/atmel toolchain/avr8 gcc/native/3.4.1061/avr8-gnu-toolchain/bin/../lib/gcc/avr/4.8.1/avrxmega2\libgcc.a(_exit.o) + *(.fini0) + 0x000008d4 _etext = . + +.data 0x00802000 0x0 load address 0x000008d4 + 0x00802000 PROVIDE (__data_start, .) + *(.data) + *(.data*) + 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+S11308301C92549753961C92539738E711963C9305 +S1130840119716963C93A0E8B6E053968C93539771 +S113085052968C93529751968C93519750968C93B1 +S1130860509712962C93A0EEB7E051969C93519713 +S113087093E012969C93129750968C9380E482870F +S113088081858C7F816081878689887F8260868B61 +S1130890089510924100E0E5F0E080818660808355 +S11308A0818182FFFDCFE0E5F0E0818181FFFDCF12 +S11308B081E080936000E0E5F0E096819D7F96837F +S11308C098ED94BF8093400080818E7F808308954B +S10708D0F894FFCFC6 +S9030000FC Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADC_7176_2.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADC_7176_2.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADC_7176_2.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/ADC_7176_2.d (revision 224) @@ -0,0 +1,53 @@ +ADC_7176_2.d ADC_7176_2.o: .././ADC_7176_2.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Makefile =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Makefile b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Makefile new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Makefile (revision 224) @@ -0,0 +1,164 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +SHELL := cmd.exe +RM := rm -rf + +USER_OBJS := + +LIBS := +PROJ := + +O_SRCS := +C_SRCS := +S_SRCS := +S_UPPER_SRCS := +OBJ_SRCS := +ASM_SRCS := +PREPROCESSING_SRCS := +OBJS := +OBJS_AS_ARGS := +C_DEPS := +C_DEPS_AS_ARGS := +EXECUTABLES := +OUTPUT_FILE_PATH := +OUTPUT_FILE_PATH_AS_ARGS := +AVR_APP_PATH :=$$$AVR_APP_PATH$$$ +QUOTE := " +ADDITIONAL_DEPENDENCIES:= +OUTPUT_FILE_DEP:= +LIB_DEP:= +LINKER_SCRIPT_DEP:= + +# Every subdirectory with source files must be described here +SUBDIRS := + + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../ADC_7176_2.c \ +../main.c \ +../commSPI_ADC.c \ +../fpga_port.c \ +../Ports.c \ +../sys_clock.c + + +PREPROCESSING_SRCS += + + +ASM_SRCS += + + +OBJS += \ +ADC_7176_2.o \ +main.o \ +commSPI_ADC.o \ +fpga_port.o \ +Ports.o \ +sys_clock.o + +OBJS_AS_ARGS += \ +ADC_7176_2.o \ +main.o \ +commSPI_ADC.o \ +fpga_port.o \ +Ports.o \ +sys_clock.o + +C_DEPS += \ +ADC_7176_2.d \ +main.d \ +commSPI_ADC.d \ +fpga_port.d \ +Ports.d \ +sys_clock.d + +C_DEPS_AS_ARGS += \ +ADC_7176_2.d \ +main.d \ +commSPI_ADC.d \ +fpga_port.d \ +Ports.d \ +sys_clock.d + +OUTPUT_FILE_PATH +=ADCSPI_v01.elf + +OUTPUT_FILE_PATH_AS_ARGS +=ADCSPI_v01.elf + +ADDITIONAL_DEPENDENCIES:= + +OUTPUT_FILE_DEP:= ./makedep.mk + +LIB_DEP+= + +LINKER_SCRIPT_DEP+= + + +# AVR32/GNU C Compiler + + + + + + + + + + + + + +./%.o: .././%.c + @echo Building file: $< + @echo Invoking: AVR/GNU C Compiler : 4.8.1 + $(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -x c -funsigned-char -funsigned-bitfields -DDEBUG -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=atxmega32d4 -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + + + + +# AVR32/GNU Preprocessing Assembler + + + +# AVR32/GNU Assembler + + + + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +# Add inputs and outputs from these tool invocations to the build variables + +# All Target +all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES) + +$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP) + @echo Building target: $@ + @echo Invoking: AVR/GNU Linker : 4.8.1 + $(QUOTE)C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -Wl,-Map="ADCSPI_v01.map" -Wl,--start-group -Wl,-lm -Wl,--end-group -Wl,--gc-sections -mmcu=atxmega32d4 + @echo Finished building target: $@ + "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_v01.elf" "ADCSPI_v01.hex" + "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O ihex "ADCSPI_v01.elf" "ADCSPI_v01.eep" || exit 0 + "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objdump.exe" -h -S "ADCSPI_v01.elf" > "ADCSPI_v01.lss" + "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature -R .user_signatures "ADCSPI_v01.elf" "ADCSPI_v01.srec" + "C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR8 GCC\Native\3.4.1061\avr8-gnu-toolchain\bin\avr-size.exe" "ADCSPI_v01.elf" + + + + + + + +# Other Targets +clean: + -$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES) + -$(RM) $(C_DEPS_AS_ARGS) + rm -rf "ADCSPI_v01.elf" "ADCSPI_v01.a" "ADCSPI_v01.hex" "ADCSPI_v01.lss" "ADCSPI_v01.eep" "ADCSPI_v01.map" "ADCSPI_v01.srec" "ADCSPI_v01.usersignatures" + \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Ports.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Ports.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Ports.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/Ports.d (revision 224) @@ -0,0 +1,42 @@ +Ports.d Ports.o: .././Ports.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/commSPI_ADC.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/commSPI_ADC.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/commSPI_ADC.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/commSPI_ADC.d (revision 224) @@ -0,0 +1,42 @@ +commSPI_ADC.d commSPI_ADC.o: .././commSPI_ADC.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././commSPI_ADC.h .././Ports.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././commSPI_ADC.h: + +.././Ports.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/fpga_port.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/fpga_port.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/fpga_port.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/fpga_port.d (revision 224) @@ -0,0 +1,59 @@ +fpga_port.d fpga_port.o: .././fpga_port.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ + .././ADC_7176_2.h .././Ports.h .././commSPI_ADC.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h: + +.././ADC_7176_2.h: + +.././Ports.h: + +.././commSPI_ADC.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/main.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/main.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/main.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/main.d (revision 224) @@ -0,0 +1,61 @@ +main.d main.o: .././main.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h \ + .././Ports.h .././sys_clock.h .././ADC_7176_2.h .././commSPI_ADC.h \ + .././fpga_port.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: + +.././Ports.h: + +.././sys_clock.h: + +.././ADC_7176_2.h: + +.././commSPI_ADC.h: + +.././fpga_port.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\interrupt.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\util\delay_basic.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\math.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/makedep.mk =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/makedep.mk b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/makedep.mk new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/makedep.mk (revision 224) @@ -0,0 +1,16 @@ +################################################################################ +# Automatically-generated file. Do not edit or delete the file +################################################################################ + +ADC_7176_2.c + +main.c + +commSPI_ADC.c + +fpga_port.c + +Ports.c + +sys_clock.c + Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/sys_clock.d =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/sys_clock.d b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/sys_clock.d new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Debug/sys_clock.d (revision 224) @@ -0,0 +1,37 @@ +sys_clock.d sys_clock.o: .././sys_clock.c \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h \ + c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\io.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\sfr_defs.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\inttypes.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\lib\gcc\avr\4.8.1\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\stdint.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\iox32d4.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\portpins.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\common.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\version.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\xmega.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\fuse.h: + +c:\program\ files\ (x86)\atmel\atmel\ toolchain\avr8\ gcc\native\3.4.1061\avr8-gnu-toolchain\avr\include\avr\lock.h: Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.c (revision 224) @@ -0,0 +1,126 @@ +/* + * Ports.c + * + * Created: 26/04/16 11:39:52 + * Author: Francisco + */ +/*! +* \fn config_puertos +* \brief Configuración de todos los pines de I/O a usarse +* para la prueba. Para el firmware final se deben dejar de configurar en este segmento +* los pines PR0 y PR1 que corresponden a las entradas de tierra y reloj externo. +* Los criterios de asignación de control: +* Pullup: Para evitar ruido se envía a una tensión conocida. De preferencia si +* Se sabe que la entrada será casi siempre alta. +* Pulldown: Para evitar ruido se envía a una tensión conocida. De preferencia si +* Se sabe que la entrada será casi siempre baja. +* WiredAndpull: Para evitar cortos de una salida al exterior del board. +* Totem: Si se tiene certeza que el otro extremo es una salida o entrada con un valor predecible(Mismo board). +* \ +*/ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" +#include "commSPI_ADC.h" + +inline void config_puertos(void){ +//Configuracion pines del puerto A: PA7-PA0 +//Pines de entrada y totem_pullup +PORTA.PIN7CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN6CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN5CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN4CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN3CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN2CTRL = PORT_OPC_PULLUP_gc; +PORTA.PIN1CTRL = PORT_OPC_PULLUP_gc; +PORTA.DIRCLR = PIN7_bm | PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm | PIN2_bm | PIN1_bm; + +//Pin de salida A0 +//Wired AND. Esto pues podrá irse a alta por defecto y si existe una tensión +//La línea tendrá el valor de tensión externa pero si es entrada con impedancia alta leerá el valor en alta +//Valor por defecto salida: PA0 = low + +PORTA.PIN0CTRL = PORT_OPC_WIREDANDPULL_gc; +PORTA.OUTCLR = PIN0_bm; +PORTA.DIRSET = PIN0_bm; + +//Configuracion pines del puerto B: PB3-PB0 +//Pines de entrada y totem_pullup +PORTB.PIN3CTRL = PORT_OPC_PULLUP_gc; +PORTB.PIN2CTRL = PORT_OPC_PULLUP_gc; +PORTB.PIN1CTRL = PORT_OPC_PULLUP_gc; +PORTB.PIN0CTRL = PORT_OPC_PULLUP_gc; +PORTB.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; + +//Configuracion pines del puerto C: PC7-PC0 Con PC7-PC4:SPI +//Pines de entrada y totem_pullup: PC3, PC2, PC1, PC0, SPI_MISO PC6 +//Pines de salida y totem_wiredand-pull: SPI_MOSI, SCK, SS. Valores por defecto de 1's en SCK y SS. Por defecto 0 en MOSI. +PORTSPI.PINSPIMISOCTRL = PORT_OPC_PULLUP_gc; +PORTC.PIN3CTRL = PORT_OPC_PULLUP_gc; +PORTC.PIN2CTRL = PORT_OPC_PULLUP_gc; +PORTC.PIN1CTRL = PORT_OPC_PULLUP_gc; +PORTC.PIN0CTRL = PORT_OPC_PULLUP_gc; +PORTC.DIRCLR = SPI_MISO_bm | PIN3_bm | PIN2_bm | PIN1_bm | PIN0_bm; //En este paso ya se sabe que el puerto SPI es el C + +//Pines de salida wiredand-pull +//Valor por defecto salida: PC4,PC7 = low +//Valor por defecto salida: PC5 = set + +PORTSPI.PINSPIMOSICTRL = PORT_OPC_TOTEM_gc; +PORTSPI.PINSPISCKCTRL = PORT_OPC_TOTEM_gc; +PORTSPI.PINSPISSCTRL = PORT_OPC_TOTEM_gc; +PORTSPI.DIRSET = SPI_MOSI_bm | SPI_SS_bm |SPI_SCK_bm; +PORTSPI.OUTSET = SPI_SS_bm |SPI_SCK_bm; +PORTSPI.OUTCLR = SPI_MOSI_bm; + +//Configuracion pines del puerto D: PD7-PD0 +//Pines de entrada y totem_pullup: PIN7 y PIN0 +//NOTA +//PARA EL FW FINAL REVISAR SI PD2 SERÁ ENTRADA O NO +//NOTA FIN +PORTD.DIRSET = PIN2_bm; +PORTD.OUTCLR = PIN2_bm; + + +PORTD.PIN7CTRL = PORT_OPC_PULLUP_gc; +PORTD.PIN0CTRL = PORT_OPC_PULLUP_gc; +PORTD.DIRCLR = PIN7_bm | PIN1_bm| PIN0_bm; +//Pines de entrada y totem_pulldown: PIN2 y PIN1. Ambas serán entradas provenientes de la fpga +//PORTD.PIN2CTRL = PORT_OPC_PULLDOWN_gc; + +PORTD.PIN1CTRL = PORT_OPC_PULLDOWN_gc; +//Pines de salida tipo wired-and-pull +//Valor por defecto PD6, PD5, PD4, PD3 = low + +PORTD.PIN6CTRL = PORT_OPC_TOTEM_gc; +PORTD.PIN5CTRL = PORT_OPC_TOTEM_gc; +PORTD.PIN4CTRL = PORT_OPC_TOTEM_gc; +PORTD.PIN3CTRL = PORT_OPC_TOTEM_gc; +PORTD.DIRSET = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; +PORTD.OUTCLR = PIN6_bm | PIN5_bm | PIN4_bm | PIN3_bm; + +//Configuracion pines del puerto E: PE3-PE0 +//Pines de entrada y totem_pullup: PIN3 - PIN0 + +PORTE.PIN3CTRL = PORT_OPC_PULLUP_gc; +PORTE.PIN2CTRL = PORT_OPC_PULLUP_gc; +PORTE.PIN1CTRL = PORT_OPC_PULLUP_gc; +PORTE.PIN0CTRL = PORT_OPC_PULLUP_gc; +PORTE.DIRCLR = PIN3_bm | PIN2_bm | PIN1_bm| PIN0_bm; + +//Configuracion pines del puerto R: PR1-PR0 +//Pines de entrada y totem_pulldown: PIN0 +PORTR.PIN1CTRL = PORT_OPC_PULLDOWN_gc; +PORTR.DIRCLR = PIN1_bm| PIN0_bm; +//Pines de entrada y totem_pulldup:PIN1 +PORTR.PIN0CTRL = PORT_OPC_PULLUP_gc; + +//Configuración como interrupción del pin SPI_MISO_RDY + +PORTSPI.INT0MASK = SPI_MISO_bm; +PORTSPI.INTCTRL = ( PORTSPI.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_LO_gc; +PORTSPI.PINSPIMISOCTRL = ( PORTSPI.PINSPIMISOCTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + +} \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.h =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.h b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/Ports.h (revision 224) @@ -0,0 +1,22 @@ +/* + * Ports.h + * + * Created: 26/04/16 11:40:34 + * Author: Francisco + */ + + + +#ifndef PORTS_H_ +#define PORTS_H_ + +#define F_CPU 32000000UL +#include + +#define INT_RDY PORTC_INT0_vect + +void config_puertos(void); + + + +#endif /* PORTS_H_ */ \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.c (revision 224) @@ -0,0 +1,29 @@ +/* + * commSPI_ADC.c + * + * Created: 26/04/16 11:44:43 + * Author: Francisco + */ + +#define F_CPU 32000000UL +#include +#include "commSPI_ADC.h" + +/*! + * \fn config_spiparm + * \brief Configuración de los parámetros de reloj SPI + * + * fspi = fper/2 = fcpu/2 = 16MHz + * + * En nuestra aplicación final el reloj será externo, de 16MHz. Por lo que se tendrá que realizar una + * nueva evaluación + * \ +*/ +inline void config_spiparm(void){ + // Preescaler: clkper/2 = f_cpu/2. + // Master + // Mode 3: CPOL=1,CPHA=1 + // MSB --- LSB + SPIC.CTRL = (SPI_ENABLE_bm | SPI_MASTER_bm | SPI_MODE1_bm | SPI_MODE0_bm | SPI_CLK2X_bm);//SPI_PRESCALER1_bm | SPI_CLK2X_bm); +} + Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.h =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.h b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/commSPI_ADC.h (revision 224) @@ -0,0 +1,32 @@ +/* + * commSPI_ADC.h + * + * Created: 26/04/16 11:46:06 + * Author: Francisco + */ + + +#ifndef COMMSPI_ADC_H_ +#define COMMSPI_ADC_H_ + +#define F_CPU 32000000UL +#include + +#include "Ports.h" + +#define PORTSPI PORTC //Puerto en el que se definió el puerto SPI + +#define PINSPISSCTRL PIN4CTRL //Pin de control de salida SS +#define PINSPIMOSICTRL PIN5CTRL //Pin de control de salida MOSI +#define PINSPIMISOCTRL PIN6CTRL //Pin de control de entrada MISO +#define PINSPISCKCTRL PIN7CTRL //Pin de control de salida SCK + +#define SPI_SS_bm PIN4_bm // Pin de entrada - Totem +#define SPI_MOSI_bm PIN5_bm // Pin de salida - Totem +#define SPI_MISO_bm PIN6_bm // Pin de entrada - Totem +#define SPI_SCK_bm PIN7_bm // Pin de salida - Totem +#define SPI_INTFLAGS INTFLAGS +void config_spiparm(void); + + +#endif /* COMMSPI_ADC_H_ */ \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/fpga_port.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/fpga_port.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/fpga_port.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/fpga_port.c (revision 224) @@ -0,0 +1,259 @@ +/* + * fpga_port.c + * + * Created: 26/04/16 11:42:02 + * Author: Francisco + */ + +#define F_CPU 32000000UL +#include + +#include + +#include "fpga_port.h" + +inline void config_fpgaport() +{ + //Configuracion pines del puerto D: PD6-PA1 + //Pines de entrada CLK_FPGA, LOCK_FPGA + //Pines de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + + PORT_FPGA.LOCK_FPGA_CTRL = PORT_OPC_TOTEM_gc; + PORT_FPGA.DIRCLR = LOCK_FPGA; + + PORT_FPGA.CLK_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + PORT_FPGA.DIRSET = CLK_FPGA; + PORT_FPGA.OUTCLR = CLK_FPGA; + + //Pin de salida CH_BIT0_FPGA, CH_BIT1_FPGA,CH_BIT2_FPGA, CH_BIT3_FPGA + //PORT_FPGA.DIRSET = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + //PORT_FPGA.CH_BIT0_FPGA_CTRL = PORT_OPC_TOTEM_gc; //PORT_OPC_WIREDANDPULL_gc; + //PORT_FPGA.OUTCLR = CH_BIT3_FPGA | CH_BIT2_FPGA | CH_BIT1_FPGA | CH_BIT0_FPGA; + + //Configuracion pines del puerto B: PPS + //Pines de entrada PPS_FPGA + //Pines de entrada en pulldown + PORT_PPS.DIRCLR = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = PORT_OPC_PULLDOWN_gc; + + //Configuracion pines del puerto A: LOCKOUT + //Pines de salida LOCK_OUT + //Pines de salida en baja + PORT_LOCKOUT.DIRSET = LOCK_OUT; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + + + + //Configuracion de interrupciones de LOCK_FPGA + + PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT0LVL_gm ) | PORT_INT0LVL_HI_gc; + PORT_FPGA.INT0MASK = LOCK_FPGA; + PORT_FPGA.LOCK_FPGA_CTRL = ( PORT_FPGA.LOCK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_BOTHEDGES_gc; + + //Configuracion de interrupciones de CLK + //PORT_FPGA.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + //PORT_FPGA.INT1MASK = CLK_FPGA; + //PORT_FPGA.CLK_FPGA_CTRL = ( PORT_FPGA.CLK_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_FALLING_gc; + + //Configuracion de interrupciones de PPS + PORT_PPS.INTCTRL = ( PORT_FPGA.INTCTRL & ~PORT_INT1LVL_gm ) | PORT_INT1LVL_MED_gc; + PORT_PPS.INT1MASK = PPS_FPGA; + PORT_PPS.PPS_FPGA_CTRL = ( PORT_PPS.PPS_FPGA_CTRL & ~PORT_ISC_gm ) | PORT_ISC_RISING_gc; +} + +void habilitar_interrupciones( uint8_t level_mask ) +{ + PMIC.CTRL |= level_mask; +} + +void habilitar_interrupciones_globales( void ) +{ + sei(); +} + +void deshabilitar_interrupciones_globales( void ) +{ + cli(); +} + +void envio_nibble(uint8_t fpga_dato) +{ + uint8_t temp_regin; + uint8_t temp_dato; + //fpga_dato = 0b100000000000100001110000; + //Nibble superior 7 a 4 + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTCLR = CLK_FPGA; + //_delay_ms(100); + temp_regin = PORT_FPGA.OUTCLR; + temp_dato = fpga_dato & nibble_alto_bm; + //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato >> fpga_salidas_nibblealto_bp); + PORT_FPGA.OUT = (0b01001000); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + //_delay_ms(200); + //Nibble inferior 3 a 0 + PORT_FPGA.OUTCLR = CLK_FPGA; + temp_regin = PORT_FPGA.OUTCLR; + temp_dato = fpga_dato & nibble_bajo_bm; + //_delay_ms(100); + //PORT_FPGA.OUT = (temp_regin & fpga_salidas_bm) | (temp_dato << fpga_salidas_nibblebajo_bp); + PORT_FPGA.OUT = (0b01100000); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + //_delay_ms(200); +} + +void envio_datos_fpga(void) +{ + uint8_t fpga_dato[ADC_DATASZ] ; + //uint8_t aux_dato[ADC_DATASZ] ; + + adcport_read_data(fpga_dato,ADC_DATASZ); + //adcport_read_data_synconv(fpga_dato,ADC_DATASZ); + //adcport_read_data_contread(fpga_dato,ADC_DATASZ); + //aux_dato[0] = fpga_dato[0]; + //aux_dato[1] = fpga_dato[1]; + //aux_dato[2] = fpga_dato[2]; + //adcport_read_data(fpga_dato,ADC_DATASZ); + + //envio_dato_adc(aux_dato); + envio_dato_adc(fpga_dato); +} + +void envio_dato_adc(uint8_t* dato_adc) +{ + //fpga_dato = 0b100000000000100001110000; + //dato_adc[2] = 0b11111101; + //dato_adc[1] = 0b11111110; + //dato_adc[0] = 0b11111110; + //dato_adc[2] = 0b11111110; + //dato_adc[1] = 0b11111111; + //dato_adc[0] = 0b11111110; + for(int i=0; i +#include +#include "ADC_7176_2.h" + +//Port B +#define PORT_PPS PORTB +#define PPS_FPGA PIN2_bm +#define PPS_FPGA_CTRL PIN2CTRL +#define PPS_FPGA_INTFLAGS INTFLAGS +#define INT_PPS PORTB_INT1_vect + +//Port A +#define PORT_LOCKOUT PORTA +#define LOCK_OUT PIN0_bm + + +//Port D +#define PORT_FPGA PORTD +#define LOCK_FPGA PIN1_bm +#define CLK_FPGA PIN2_bm +#define CH_BIT0_FPGA PIN3_bm +#define CH_BIT1_FPGA PIN4_bm +#define CH_BIT2_FPGA PIN5_bm +#define CH_BIT3_FPGA PIN6_bm +#define INT_LOCK_FPGA PORTD_INT0_vect + +#define LOCK_FPGA_CTRL PIN1CTRL +#define CLK_FPGA_CTRL PIN2CTRL +#define CH_BIT0_FPGA_CTRL PIN3CTRL +#define CH_BIT1_FPGA_CTRL PIN4CTRL +#define CH_BIT2_FPGA_CTRL PIN5CTRL +#define CH_BIT3_FPGA_CTRL PIN6CTRL + +void config_fpgaport(); +void habilitar_interrupciones( uint8_t level_mask ); +void habilitar_interrupciones_globales( ); +void deshabilitar_interrupciones_globales( ); + +//Habilitar +#define hab_prioridad_alta PMIC_HILVLEN_bm +#define hab_prioridad_media PMIC_MEDLVLEN_bm +#define hab_prioridad_baja PMIC_LOLVLEN_bm + +//Máscara de nibbles +#define nibble_alto_bm 0xF0 +#define nibble_bajo_bm 0x0F +#define fpga_salidas_nibblealto_bp 1 +#define fpga_salidas_nibblebajo_bp 3 +#define fpga_salidas_bm 0x87 + +//funciones de envío de datos +void envio_nibble(uint8_t fpga_dato); + +//funcion interrupcion por flanco de subida de RDY +void envio_datos_fpga(void); +void envio_dato_adc(uint8_t* dato_adc); + +#endif /* FPGA_PORT_H_ */ \ No newline at end of file Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/main.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/main.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/main.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/main.c (revision 224) @@ -0,0 +1,149 @@ +/* + * ADCSPI_v01.c + * + * Created: 26/04/16 11:26:57 + * Author: Francisco + */ + +#define F_CPU 32000000UL +#include +#include "Ports.h" +//#include "commSPI_ADC.h" +#include "sys_clock.h" +#include "ADC_7176_2.h" +#include "fpga_port.h" +#include + +int aux = 0; +int main(void) +{ + //uint8_t datos_adc[3]; + config_puertos(); + config_sysclock(); + config_spiparm(); + config_fpgaport(); + config_adc(); + //datos_adc[0] = 0x00; + //datos_adc[1] = 0x00; + //datos_adc[2] = 0x00; + //PORTD.OUTSET = PIN5_bm; + + PMIC.CTRL = hab_prioridad_alta; + habilitar_interrupciones_globales(); + + /* Replace with your application code */ + //adcport_write_adcmode_2(); + while (1) + { + //PORTSPI.OUTCLR = SPI_SS_bm; + //if (adcport_read_filtcon0() == ADC_VALFIL0){ + // PORTD.OUTSET = PIN6_bm | PIN5_bm; + // adcport_write_adcmode_2(); + //while(1){ + // PORTSPI.OUTCLR = SPI_SS_bm; + //} + //} + //else{ + // PORTD.OUTCLR = PIN6_bm | PIN5_bm; + //} + //PORTD.OUTSET = PIN2_bm; + //_delay_ms(1000); + //PORTD.OUTCLR = PIN2_bm; + //_delay_ms(1000); + //if (test_adc() == ADC_ID){ + // PORTD.OUTSET = PIN6_bm | PIN5_bm; + // _delay_ms(1000); + //} + + //else{ + // PORTD.OUTCLR = PIN6_bm | PIN5_bm; + //} + //_delay_ms(10); + //test_adc_2(datos_adc); + //if (((datos_adc[0]<<16)+(datos_adc[1]<<8)+(datos_adc[2]<<0))!= 0x00){ + //PORTD.OUTSET = PIN4_bm; + //} + } + return 0; +} + + +ISR(INT_LOCK_FPGA) +{ + if((PORT_FPGA.IN & LOCK_FPGA) == LOCK_FPGA) + { + PORTSPI.SPI_INTFLAGS =0b00000001; + PORT_PPS.PPS_FPGA_INTFLAGS =0b00000010; + PMIC.CTRL |= hab_prioridad_media; + PORT_LOCKOUT.OUTSET = LOCK_OUT; + //PORTD.OUTSET = PIN4_bm; + } + else + { + PMIC.CTRL &= ~hab_prioridad_media; + PMIC.CTRL &= ~hab_prioridad_baja; + PORT_LOCKOUT.OUTCLR = LOCK_OUT; + //PORTSPI.OUTSET = SPI_SS_bm; + //PORTD.OUTCLR = PIN4_bm; + } +} + +//Interrupcion por flanco de subida de PPS +//Habilito interrupciones de prioridad baja +//Selecciono el chip del ADC para iniciar comunicación. +//Al iniciar esta comunicación se indicará al ADC que use el RDYbar +//Esta será nuestra interrupción para lectura del ADC y envío de dato a la FPGA +ISR(INT_PPS) +{ + PMIC.CTRL &= ~hab_prioridad_baja; + PORTSPI.SPI_INTFLAGS =0b00000001; + PORTSPI.SPI_INTFLAGS =0b00000001; + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + aux = 0; + //if(aux==0) + PMIC.CTRL |= hab_prioridad_baja; + PORTSPI.SPI_INTFLAGS =0b00000001; + PORTSPI.OUTSET = SPI_SS_bm; + asm("nop"); + PORT_FPGA.OUTSET = CLK_FPGA; + //PORT_FPGA.OUT = (0b01111000); + asm("nop"); + + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + asm("nop"); + PORTSPI.OUTCLR = SPI_SS_bm; + + _delay_us(10); + PORTSPI.SPI_INTFLAGS =0b00000001; + //envio_datos_fpga(); + //PORTSPI.OUTSET = SPI_SS_bm; + +} + +ISR(INT_RDY) +{ + //PMIC.CTRL &= ~hab_prioridad_media; + //PMIC.CTRL &= ~hab_prioridad_alta; + if(aux < 20000){ + envio_datos_fpga(); + aux = aux+1; + } + //PORTSPI.OUTCLR = SPI_SS_bm; + //adcport_read_filtcon0(); + //PMIC.CTRL |= hab_prioridad_media; + //PMIC.CTRL |= hab_prioridad_alta; + PORTSPI.SPI_INTFLAGS =0b00000001; +} Index: trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/sys_clock.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/sys_clock.c b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/sys_clock.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Acquisition/32d4_ADCSPI_v01/ADCSPI_v01/ADCSPI_v01/sys_clock.c (revision 224) @@ -0,0 +1,51 @@ +/* + * sys_clock.c + * + * Created: 26/04/16 11:32:16 + * Author: Francisco + */ +/*! + * \fn config_sysclock + * \brief Configuración del reloj interno del sistema + * Reloj interno + * fsys = 32MHz + * + * En nuestra aplicación final el reloj será externo de 16MHz por lo que se tendrá que usar el PLL + * \ +*/ + +#define F_CPU 32000000UL +#include + +void config_sysclock(void){ + +CLK_PSCTRL = ((0< + +void config_sysclock(void); + + + +#endif /* SYS_CLOCK_H_ */ \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.lso =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.lso b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.lso new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.lso (revision 224) @@ -0,0 +1 @@ +work Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.prj =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.prj b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.prj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.prj (revision 224) @@ -0,0 +1 @@ +vhdl work "DCM_fwd_int.vhd" Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.stx =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.stx b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.stx new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.stx (revision 224) @@ -0,0 +1,57 @@ +Release 14.7 - xst P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Reading design: DCM_fwd_int.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* HDL Parsing * +========================================================================= +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\DCM_fwd_int.vhd" into library work +Parsing entity . +Parsing architecture of entity . + + +Total REAL time to Xst completion: 5.00 secs +Total CPU time to Xst completion: 5.00 secs + +--> + +Total memory usage is 184976 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.vhd (revision 224) @@ -0,0 +1,160 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:23:06 02/16/2016 +-- Design Name: +-- Module Name: DCM_fwd_int - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity DCM_fwd_int is +PORT( + clk_main_io: IN std_logic; + c_16MHz_io: OUT std_logic; + c_200MHz_in: OUT std_logic +); +end DCM_fwd_int; + +architecture Behavioral of DCM_fwd_int is +SIGNAL clk_main: std_logic; +SIGNAL c_16MHz: std_logic; + +SIGNAL clk_fb_aux: std_logic; +SIGNAL clk_fb_aux_200MHz: std_logic; + +SIGNAL c_16MHz_inv: std_logic; + +begin + +c_16MHz_inv <= NOT(c_16MHz); + +ODDR2_inst : ODDR2 + generic map( + DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1" + INIT => '0', -- Sets initial state of the Q output to '0' or '1' + SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset + port map ( + Q => c_16MHz_io, -- 1-bit output data + C0 => c_16MHz, -- 1-bit clock input + C1 => c_16MHz_inv, -- 1-bit clock input + CE => '1', -- 1-bit clock enable input + D0 => '0', -- 1-bit data input (associated with C0) + D1 => '1', -- 1-bit data input (associated with C1) + R => '0', -- 1-bit reset input + S => '0' -- 1-bit set input + ); + +--IBUFG_inst : IBUFG +-- generic map ( +-- IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards +-- IOSTANDARD => "DEFAULT") +-- port map ( +-- O => clk_main, -- Clock buffer output +-- I => clk_main_io -- Clock buffer input (connect directly to top-level port) +-- ); + +DCM_SP_inst : DCM_SP + generic map ( + CLKDV_DIVIDE => 2.0, -- CLKDV divide value + -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). + CLKFX_DIVIDE => 15, -- Divide value on CLKFX outputs - D - (1-32) + CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32) + CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE) + CLKIN_PERIOD => 16.667, -- Input clock period specified in nS + CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE) + CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X) + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS + DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DSS_MODE => "NONE", -- Unsupported - Do not change value + DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value + FACTORY_JF => X"c080", -- Unsupported - Do not change value + PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255) + STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) + ) + port map ( + CLK0 => clk_fb_aux, -- 1-bit output: 0 degree clock output + CLK180 => open, -- 1-bit output: 180 degree clock output + CLK270 => open, -- 1-bit output: 270 degree clock output + CLK2X => open, -- 1-bit output: 2X clock frequency clock output + CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output + CLK90 => open, -- 1-bit output: 90 degree clock output + CLKDV => open, -- 1-bit output: Divided clock output + CLKFX => c_16MHz, -- 1-bit output: Digital Frequency Synthesizer output (DFS) + CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output + LOCKED => open, -- 1-bit output: DCM_SP Lock Output + PSDONE => open, -- 1-bit output: Phase shift done output + STATUS => open, -- 8-bit output: DCM_SP status output + CLKFB => clk_fb_aux, -- 1-bit input: Clock feedback input + CLKIN => clk_main_io, -- 1-bit input: Clock input + DSSEN => '0', -- 1-bit input: Unsupported, specify to GND. + PSCLK => '1', -- 1-bit input: Phase shift clock input + PSEN => '0', -- 1-bit input: Phase shift enable + PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input + RST => '0' -- 1-bit input: Active high reset input + ); + +DCM_SP_inst_int : DCM_SP + generic map ( + CLKDV_DIVIDE => 2.0, -- CLKDV divide value + -- (1.5,2,2.5,3,3.5,4,4.5,5,5.5,6,6.5,7,7.5,8,9,10,11,12,13,14,15,16). + CLKFX_DIVIDE => 1, -- Divide value on CLKFX outputs - D - (1-32) + CLKFX_MULTIPLY => 4, -- Multiply value on CLKFX outputs - M - (2-32) + CLKIN_DIVIDE_BY_2 => FALSE, -- CLKIN divide by two (TRUE/FALSE) + CLKIN_PERIOD => 16.667, -- Input clock period specified in nS + CLKOUT_PHASE_SHIFT => "NONE", -- Output phase shift (NONE, FIXED, VARIABLE) + CLK_FEEDBACK => "1X", -- Feedback source (NONE, 1X, 2X) + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SYSTEM_SYNCHRNOUS or SOURCE_SYNCHRONOUS + DFS_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DLL_FREQUENCY_MODE => "LOW", -- Unsupported - Do not change value + DSS_MODE => "NONE", -- Unsupported - Do not change value + DUTY_CYCLE_CORRECTION => TRUE, -- Unsupported - Do not change value + FACTORY_JF => X"c080", -- Unsupported - Do not change value + PHASE_SHIFT => 0, -- Amount of fixed phase shift (-255 to 255) + STARTUP_WAIT => FALSE -- Delay config DONE until DCM_SP LOCKED (TRUE/FALSE) + ) + port map ( + CLK0 => clk_fb_aux_200MHz, -- 1-bit output: 0 degree clock output + CLK180 => open, -- 1-bit output: 180 degree clock output + CLK270 => open, -- 1-bit output: 270 degree clock output + CLK2X => open, -- 1-bit output: 2X clock frequency clock output + CLK2X180 => open, -- 1-bit output: 2X clock frequency, 180 degree clock output + CLK90 => open, -- 1-bit output: 90 degree clock output + CLKDV => open, -- 1-bit output: Divided clock output + CLKFX => c_200MHz_in, -- 1-bit output: Digital Frequency Synthesizer output (DFS) + CLKFX180 => open, -- 1-bit output: 180 degree CLKFX output + LOCKED => open, -- 1-bit output: DCM_SP Lock Output + PSDONE => open, -- 1-bit output: Phase shift done output + STATUS => open, -- 8-bit output: DCM_SP status output + CLKFB => clk_fb_aux_200MHz, -- 1-bit input: Clock feedback input + CLKIN => clk_main_io, -- 1-bit input: Clock input + DSSEN => '0', -- 1-bit input: Unsupported, specify to GND. + PSCLK => '1', -- 1-bit input: Phase shift clock input + PSEN => '0', -- 1-bit input: Phase shift enable + PSINCDEC => '0', -- 1-bit input: Phase shift increment/decrement input + RST => '0' -- 1-bit input: Active high reset input + ); + +end Behavioral; \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.xst =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.xst b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.xst new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/DCM_fwd_int.xst (revision 224) @@ -0,0 +1,50 @@ +set -tmpdir "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst/projnav.tmp" +set -xsthdpdir "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/xst" +run -compileonly yes +-p xc6slx9-3-tqg144 +-top DCM_fwd_int +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 +-ifn DCM_fwd_int.prj Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SEL_WRbar.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SEL_WRbar.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SEL_WRbar.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SEL_WRbar.vhd (revision 224) @@ -0,0 +1,54 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:45:36 05/16/2016 +-- Design Name: +-- Module Name: SEL_OEbar - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SEL_WRbar is +GENERIC(RESUL_IOSEL_SZ: INTEGER :=16 + ); + +PORT( + DATA_W : IN std_logic_vector((RESUL_IOSEL_SZ-1) downto 0); + DATA_R : OUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0); + OEbar: IN std_logic; + DATA_INOUT: INOUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0) +); +end SEL_WRbar; + +architecture Behavioral of SEL_WRbar is + +begin + +DATA_INOUT <= DATA_W WHEN OEbar = '1' ELSE + (others => 'Z'); + +DATA_R <= DATA_INOUT; + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SPI_SLAVE.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SPI_SLAVE.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SPI_SLAVE.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/SPI_SLAVE.vhd (revision 224) @@ -0,0 +1,290 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 19:55:49 05/06/2016 +-- Design Name: +-- Module Name: spi_slave - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + + +entity SPI_SLAVE is +GENERIC( + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 +); + +PORT ( + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + data_in : IN std_logic_vector (SPI_DATA_WIDTH-1 downto 0); + clk_main : IN std_logic; + rst_bar : IN std_logic; + MISO : OUT std_logic; + data_out : OUT std_logic_vector (SPI_DATA_WIDTH-1 downto 0); + spi_ready : OUT std_logic; + + spi_free: OUT std_logic + --spi_ld_8_in: IN STD_LOGIC; + + --spi_req : OUT std_logic + + +); +end SPI_SLAVE; + +architecture Behavioral of SPI_SLAVE is +SIGNAL SCKr : std_logic_vector (1 downto 0) :=( OTHERS => '0'); +SIGNAL CSr : std_logic_vector (1 downto 0) :=( OTHERS => '0'); +SIGNAL MOSIr : std_logic_vector (1 downto 0) :=( OTHERS => '0'); +SIGNAL SCK_rise : std_logic := '0'; +SIGNAL SCK_fall : std_logic := '0'; +--SIGNAL CS_fall : std_logic := '0'; + +SIGNAL bit_counter : std_logic_vector (SPI_BIT_COUNT_WIDTH-1 downto 0) :=( OTHERS => '0'); +SIGNAL buffer_in : std_logic_vector (SPI_DATA_WIDTH-1 downto 0) :=( OTHERS => '0'); +SIGNAL buffer_out : std_logic_vector (SPI_DATA_WIDTH-1 downto 0) :=( OTHERS => '0'); + +TYPE spi_states IS ( + idle, + free, + busy + ); +SIGNAL spi_cur_state: spi_states := free; +SIGNAL spi_next_state: spi_states := free; +SIGNAL spi_ready_aux: std_logic := '0'; +--SIGNAL spi_req_aux: std_logic := '0'; + +SIGNAL MISO_int: std_logic :='1'; +begin + +-- Shifting the SCK line for synchronization purposes + SCK_shift_register: process (clk_main) + --VARIABLE SCKr : std_logic_vector (2 downto 0) :=( OTHERS => '0'); + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + SCKr <= (others => '1'); + else + SCKr <= SCKr(0) & SCK; + end if; + end if; + end process; + + -- Shifting the SCK line for edge detection + SCK_edge_det: process (clk_main) + --VARIABLE SCKr : std_logic_vector (2 downto 0) :=( OTHERS => '0'); + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + SCK_rise <= '0'; + SCK_fall <= '0'; + else + IF (SCKr(1 downto 0) = "01") THEN + SCK_rise <= '1'; + ELSE + SCK_rise <= '0'; + END IF; + + IF (SCKr(1 downto 0) = "10") THEN + SCK_fall <= '1'; + ELSE + SCK_fall <= '0'; + END IF; + end if; + end if; + end process; + + -- Shifting the CS line for synchronization purposes and edge detection + CS_shift_register: process (clk_main) + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + --CSr <= (others => '0'); + else + CSr <= CSr(0) & CS; + end if; + end if; + end process; + + -- Shifting the MOSI line for synchronization purposes + MOSI_shift_register: process (clk_main) + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + MOSIr <= (others => '0'); + else + MOSIr <= MOSIr(0) & MOSI; + end if; + end if; + end process; + + receive_process: process (clk_main) + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + bit_counter <= (others => '0'); + buffer_in <= (others => '0'); + spi_ready_aux <= '0'; + --spi_req_aux <= '0'; + else + if (CSr(1) = '1') then + bit_counter <= (others => '0'); + elsif (SCK_rise = '1') then + bit_counter <= std_logic_vector(unsigned(bit_counter) + 1); + buffer_in <= buffer_in(SPI_DATA_WIDTH-2 downto 0) & MOSIr(1); + IF((bit_counter = "111")) THEN + bit_counter <= (others => '0'); + END IF; + end if; + + IF((bit_counter = "111")) THEN + + IF(CSr(1) = '0') THEN + IF (SCK_rise = '1')THEN + spi_ready_aux <= '1'; + ELSE + spi_ready_aux <= '0'; + END IF; + ELSE + spi_ready_aux <= '0'; + END IF; + ELSE + spi_ready_aux <= '0'; + END IF; + + --IF((bit_counter = "000")) THEN + + --IF(CSr(1) = '0') THEN + -- IF (SCK_fall = '1')THEN + -- spi_req_aux <= '1'; + -- ELSE + -- spi_req_aux <= '0'; + -- END IF; + --ELSE + -- spi_req_aux <= '0'; + --END IF; + --ELSE + --spi_req_aux <= '0'; + --END IF; + end if; + end if; + end process; + + spi_ready <= spi_ready_aux; + --spi_req <= spi_req_aux; + + transmit_process: process (clk_main) + begin + if rising_edge (clk_main) then + if rst_bar = '0' then + buffer_out <= (others => '0'); + elsif (CSr(1) = '0') then + + if ((bit_counter = "000")) then + --IF (SCK_fall = '1') THEN + buffer_out <= data_in; + --buffer_out <= "01000000"; + --end if; + elsif (SCK_fall = '1') then + --if((bit_counter /= "000")) then + buffer_out <= buffer_out(6 downto 0) & '0'; + --buffer_out <= "10000000"; + end if; + --end if; + end if; + end if; + end process; + + --MISO_asignacion: PROCESS(clk_main) + -- BEGIN + -- IF(rising_edge(clk_main)) THEN + -- MISO_int <=buffer_out(7); + -- END iF; + -- END PROCESS; + + MISO <= buffer_out(7); + + data_out <= buffer_in; + + ----------------------------------- + + cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + spi_cur_state <= idle; + ELSE + spi_cur_state <= spi_next_state; + END IF; + END IF; + END PROCESS; + + salidas_estados: PROCESS(spi_cur_state,spi_ready_aux,bit_counter, + --spi_req_aux, + SCK_rise) + BEGIN + CASE spi_cur_state IS + WHEN idle => + spi_free <= '0'; --spi atendido por spi_controller + spi_next_state <= free; + + + WHEN free => + spi_free <= '1'; --spi atendido por spi_controller + IF (SCK_rise = '1') THEN + spi_next_state <= busy; + ELSE + spi_next_state <= free; + END IF; + + WHEN busy => + spi_free <= '0'; + IF (spi_ready_aux = '1') THEN + spi_next_state <= free; + ELSE + spi_next_state <= busy; + END IF; + + WHEN OTHERS => + spi_free <= '0'; + spi_next_state <= idle; + + END CASE; + END PROCESS; +end Behavioral; \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/W_R_RAM_CONTROLLER.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/W_R_RAM_CONTROLLER.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/W_R_RAM_CONTROLLER.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/W_R_RAM_CONTROLLER.vhd (revision 224) @@ -0,0 +1,1751 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:26:56 05/12/2016 +-- Design Name: +-- Module Name: W_R_RAM_CONTROLLER - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity W_R_RAM_CONTROLLER is +GENERIC( + ADDR_LENGTH: INTEGER := 19; + CHAN_NUM: INTEGER := 5 + +); + +PORT( + --Reset general + rst_bar: IN std_logic; + + --Entrada de reloj principal + clk_main: IN std_logic; + + --Entradas para indicar dato preparado por leer + --Desde los nibble to packets + wr_ch_vector: IN std_logic_vector((CHAN_NUM-1) downto 0); + + --Senhal para que indica que termino con una peticion + --Hacia los nibble to packets + ack_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0); + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req: IN std_logic; + --Hacia el SPI_Controller + ld_ram: OUT std_logic; + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + cs1_bar: OUT std_logic; + cs2: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Selector de canal de salida hacia RAM + --Hacia el multiplexor + oe_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0); + hb_lbbar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0) +); + +end W_R_RAM_CONTROLLER; + +architecture Behavioral of W_R_RAM_CONTROLLER is +--Estados del controlador de memoria +--Incluye el estado de espera, proceso de borrado, espera de "listos" para llenado de memoria +--espera de pedido y estados para proceder a una lectura +TYPE ram_cont_states IS (idle, + set_erase_ram, act_erase_ram,exe_erase_ram, + ------------------------------------------- + ------------------------------------------- + espera_rdy, + ------------------------------------------ + set_wrt_ch1_1, act_wrt_ch1_1,exe_wrt_ch1_1, + set_wrt_ch1_2, act_wrt_ch1_2,exe_wrt_ch1_2, + ------------------------------------------ + set_wrt_ch2_1, act_wrt_ch2_1,exe_wrt_ch2_1, + set_wrt_ch2_2, act_wrt_ch2_2,exe_wrt_ch2_2, + ------------------------------------------ + set_wrt_ch3_1, act_wrt_ch3_1,exe_wrt_ch3_1, + set_wrt_ch3_2, act_wrt_ch3_2,exe_wrt_ch3_2, + ------------------------------------------ + set_wrt_ch4_1, act_wrt_ch4_1,exe_wrt_ch4_1, + set_wrt_ch4_2, act_wrt_ch4_2,exe_wrt_ch4_2, + ------------------------------------------ + set_wrt_ch5_1, act_wrt_ch5_1,exe_wrt_ch5_1, + set_wrt_ch5_2, act_wrt_ch5_2,exe_wrt_ch5_2, + ------------------------------------------- + end_wrt_cycle_1,end_wrt_cycle_2, + ------------------------------------------- + ------------------------------------------- + espera_req, + set_rd, act_rd,exe_rd,end_rd + ); + +SIGNAL ram_contr_cur_state: ram_cont_states := idle; +SIGNAL ram_contr_next_state: ram_cont_states := idle; + +--Constante del tamanho maximo por canal +CONSTANT TOP_GL: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000100111000011"; --5000 bytes maximo direcciones /2=2500 = 1001 1100 0100. Se coloca el -1 +CONSTANT TOP_GL_2: std_logic_vector(11 downto 0) := "100111000011"; +CONSTANT TOP_CH: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000000111110011"; --500 "010 1010 1010 1010 1010" se coloca el -1 +CONSTANT TOP_CH_2: std_logic_vector(8 downto 0) := "111110011"; + +--Direcciones base por canal +CONSTANT BASE_ADD_CH1: std_logic_vector((ADDR_LENGTH-1) downto 0) := (OTHERS=>'0'); +CONSTANT BASE_ADD_CH2: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000000111110100"; --500 +CONSTANT BASE_ADD_CH3: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000001111101000"; --1000 +CONSTANT BASE_ADD_CH4: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000010111011100"; --1500 +CONSTANT BASE_ADD_CH5: std_logic_vector((ADDR_LENGTH-1) downto 0) := "0000000011111010000"; --2000 + +--Contador de número de ciclos de reloj en los estados de lectura-escritura +SIGNAL count_slw: std_logic_vector(3 downto 0) := "0000"; + +--Constantes de espera para el proceso de lectura-escritura +--Recordar para 200MHz->Periodo=5ns +--6ciclos=30ns y 12ciclos=60ns +--Para el 62WV51216BLL-55T los tiempos para preparar y escribir dato son: 20ns y 55ns resp. +CONSTANT ramwait_const1: std_logic_vector(3 downto 0) := "1000"; --3 6 +CONSTANT ramwait_const2: std_logic_vector(3 downto 0) := "1111"; --6 12 + +--Punteros de direccion para escritura por cada espacio de memoria asignado a canal +SIGNAL rel_pos_ch1: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch1_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch2: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch2_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch3: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch3_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch4: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch4_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch5: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL rel_pos_ch5_int: std_logic_vector(8 downto 0) :=(OTHERS=>'0'); + +--Senhal auxiliar de direccion a memoria para escritura +SIGNAL addr_wr_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); + +--Senhal auxiliar de direccion a memoria para lectura +SIGNAL addr_rd_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL addr_rd_aux_int: std_logic_vector(11 downto 0) :=(OTHERS=>'0'); + +--Senhal auxiliar de direccion a memoria para borrado +SIGNAL addr_erase_aux: std_logic_vector((ADDR_LENGTH-1) downto 0) :=(OTHERS=>'0'); +SIGNAL addr_erase_aux_int: std_logic_vector(11 downto 0) :=(OTHERS=>'0'); + +--Estados de la atencion a ready's +-- +TYPE chn_cont_states IS ( idle, + checking_ch1, attending_ch1, + checking_ch2, attending_ch2, + checking_ch3, attending_ch3, + checking_ch4, attending_ch4, + checking_ch5, attending_ch5 + ); + +SIGNAL ch_cont_cur_state: chn_cont_states := idle; +SIGNAL ch_cont_next_state: chn_cont_states := idle; + +--Senhal de reset interna formada de rst_bar y pps_r +--SIGNAL rst_bar_int: std_logic :='0'; + +--Registro para detección de flanco +--SIGNAL pps_r: std_logic_vector(1 downto 0) :="00"; +--SIGNAL pps_rst: std_logic :='0'; + +begin + + +--Deteccion de flanco de pps +--pps_bloco: PROCESS(clk_main) +-- BEGIN +-- IF (rising_edge(clk_main)) THEN +-- IF(rst_bar = '0') THEN +-- pps_rst <= '0'; +-- pps_r <= (OTHERS=>'0'); +-- pps_rst <= '0'; +-- ELSE +-- pps_r <= pps_r(0) & pps; +-- IF(pps_r(1 downto 0) = "01") THEN +-- pps_rst <= '0'; +-- ELSE +-- pps_rst <= '1'; +-- END IF; +-- END IF; +-- END IF; +-- END PROCESS; + +--Generacion de reset a partir del resetbar y flanco de subida del pps +--rst_bar_int <= rst_bar AND (pps_rst); + +--------------------- +--Estados para atencion de canales +ch_cont_cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + ch_cont_cur_state <= idle; + ELSE + ch_cont_cur_state <= ch_cont_next_state; + END IF; + END IF; + END PROCESS; + +ch_salidas_estados: PROCESS(ch_cont_cur_state, + wr_ch_vector, + ram_contr_cur_state + ) + BEGIN + + CASE ch_cont_cur_state IS + WHEN idle => + ch_cont_next_state <= checking_ch1; + + WHEN checking_ch1 => + IF(wr_ch_vector(0) = '1') THEN + ch_cont_next_state <= attending_ch1; + ELSE + ch_cont_next_state <= checking_ch2; + END IF; + + WHEN attending_ch1 => + IF(ram_contr_cur_state = end_wrt_cycle_2) THEN + ch_cont_next_state <= checking_ch2; + ELSE + ch_cont_next_state <= attending_ch1; + END IF; + + WHEN checking_ch2 => + IF(wr_ch_vector(1) = '1') THEN + ch_cont_next_state <= attending_ch2; + ELSE + ch_cont_next_state <= checking_ch3; + END IF; + + WHEN attending_ch2 => + IF(ram_contr_cur_state = end_wrt_cycle_2) THEN + ch_cont_next_state <= checking_ch3; + ELSE + ch_cont_next_state <= attending_ch2; + END IF; + + WHEN checking_ch3 => + IF(wr_ch_vector(2) = '1') THEN + ch_cont_next_state <= attending_ch3; + ELSE + ch_cont_next_state <= checking_ch4; + END IF; + + WHEN attending_ch3 => + IF(ram_contr_cur_state = end_wrt_cycle_2) THEN + ch_cont_next_state <= checking_ch4; + ELSE + ch_cont_next_state <= attending_ch3; + END IF; + + WHEN checking_ch4 => + IF(wr_ch_vector(3) = '1') THEN + ch_cont_next_state <= attending_ch4; + ELSE + ch_cont_next_state <= checking_ch5; + END IF; + + WHEN attending_ch4 => + IF(ram_contr_cur_state = end_wrt_cycle_2) THEN + ch_cont_next_state <= checking_ch5; + ELSE + ch_cont_next_state <= attending_ch4; + END IF; + + WHEN checking_ch5 => + IF(wr_ch_vector(4) = '1') THEN + ch_cont_next_state <= attending_ch5; + ELSE + ch_cont_next_state <= checking_ch1; + END IF; + + WHEN attending_ch5 => + IF(ram_contr_cur_state = end_wrt_cycle_2) THEN + ch_cont_next_state <= checking_ch1; + ELSE + ch_cont_next_state <= attending_ch5; + END IF; + + WHEN OTHERS => + + ch_cont_next_state <= idle; + + END CASE; + END PROCESS; + +----------------------------------------- +--Asignacion de direccion de escritura +asignacion_direccion_base_escritura: + PROCESS(ch_cont_cur_state,rel_pos_ch1,rel_pos_ch2,rel_pos_ch3,rel_pos_ch4,rel_pos_ch5) + BEGIN + CASE ch_cont_cur_state IS + WHEN idle => + addr_wr_aux <= (OTHERS => '0'); + WHEN attending_ch1 => + addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH1)+unsigned(rel_pos_ch1)); + WHEN attending_ch2 => + addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH2)+unsigned(rel_pos_ch2)); + WHEN attending_ch3 => + addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH3)+unsigned(rel_pos_ch3)); + WHEN attending_ch4 => + addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH4)+unsigned(rel_pos_ch4)); + WHEN attending_ch5 => + addr_wr_aux <= std_logic_vector(unsigned(BASE_ADD_CH5)+unsigned(rel_pos_ch5)); + WHEN OTHERS => + addr_wr_aux <= (OTHERS => '0'); + END CASE; + END PROCESS; + +--Asignacion de direccion de lectura +puntero_rd: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + addr_rd_aux_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + addr_rd_aux_int <= (OTHERS=>'0'); + END IF; + + --Cuentas de ram_ptr en proceso de lectura + IF(ram_contr_cur_state = end_rd) THEN + IF(addr_rd_aux_int = TOP_GL_2) THEN + addr_rd_aux_int <= addr_rd_aux_int; + ELSE + addr_rd_aux_int <= std_logic_vector(unsigned(addr_rd_aux_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +addr_rd_aux <= "0000000" & addr_rd_aux_int; + +--Asignacion de direccion de borrado +puntero_erase: PROCESS(clk_main) + --VARIABLE var_addr_erase_aux: std_logic_vector(11 downto 0) :=(OTHERS => '0'); + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + addr_erase_aux_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + addr_erase_aux_int <= (OTHERS=>'0'); + END IF; + + --Cuentas de ram_ptr en proceso de borrado + IF(ram_contr_cur_state = exe_erase_ram) THEN + IF(addr_erase_aux_int = TOP_GL_2) THEN + addr_erase_aux_int <= (OTHERS=>'0'); + ELSE + addr_erase_aux_int <= std_logic_vector(unsigned(addr_erase_aux_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +addr_erase_aux <= "0000000" & addr_erase_aux_int; + +--Asignación de salida addr_mem +addr_mem_asig: PROCESS(ram_contr_cur_state,addr_erase_aux,addr_rd_aux,addr_wr_aux) + BEGIN + CASE ram_contr_cur_state IS + WHEN idle | espera_rdy => + addr <= (OTHERS => '0'); + + WHEN set_erase_ram | act_erase_ram | exe_erase_ram => + addr <= addr_erase_aux; + + WHEN set_wrt_ch1_1 | act_wrt_ch1_1 | exe_wrt_ch1_1 | + set_wrt_ch1_2 | act_wrt_ch1_2 | exe_wrt_ch1_2 | + set_wrt_ch2_1 | act_wrt_ch2_1 | exe_wrt_ch2_1 | + set_wrt_ch2_2 | act_wrt_ch2_2 | exe_wrt_ch2_2 | + set_wrt_ch3_1 | act_wrt_ch3_1 | exe_wrt_ch3_1 | + set_wrt_ch3_2 | act_wrt_ch3_2 | exe_wrt_ch3_2 | + set_wrt_ch4_1 | act_wrt_ch4_1 | exe_wrt_ch4_1 | + set_wrt_ch4_2 | act_wrt_ch4_2 | exe_wrt_ch4_2 | + set_wrt_ch5_1 | act_wrt_ch5_1 | exe_wrt_ch5_1 | + set_wrt_ch5_2 | act_wrt_ch5_2 | exe_wrt_ch5_2 | + end_wrt_cycle_1 | end_wrt_cycle_2 => + addr <= addr_wr_aux; + + WHEN espera_req | set_rd | act_rd | exe_rd | end_rd => + addr <= addr_rd_aux; + + WHEN OTHERS => + addr <= (OTHERS => '0'); + END CASE; + + END PROCESS; + +--Avance de punteros de escritura +puntero_ch1: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rel_pos_ch1_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + rel_pos_ch1_int <= (OTHERS=>'0'); + END IF; + + IF(ram_contr_cur_state = exe_wrt_ch1_1 OR ram_contr_cur_state = exe_wrt_ch1_2) THEN + IF(rel_pos_ch1_int /= TOP_CH_2) THEN + rel_pos_ch1_int <= std_logic_vector(unsigned(rel_pos_ch1_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +rel_pos_ch1 <= "0000000000"& rel_pos_ch1_int; + +puntero_ch2: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rel_pos_ch2_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + rel_pos_ch2_int <= (OTHERS=>'0'); + END IF; + + IF(ram_contr_cur_state = exe_wrt_ch2_1 OR ram_contr_cur_state = exe_wrt_ch2_2) THEN + IF(rel_pos_ch2_int /= TOP_CH_2) THEN + rel_pos_ch2_int <= std_logic_vector(unsigned(rel_pos_ch2_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +rel_pos_ch2 <= "0000000000"& rel_pos_ch2_int; + +puntero_ch3: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rel_pos_ch3_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + rel_pos_ch3_int <= (OTHERS=>'0'); + END IF; + + IF(ram_contr_cur_state = exe_wrt_ch3_1 OR ram_contr_cur_state = exe_wrt_ch3_2) THEN + IF(rel_pos_ch3_int /= TOP_CH_2) THEN + rel_pos_ch3_int <= std_logic_vector(unsigned(rel_pos_ch3_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +rel_pos_ch3 <= "0000000000"& rel_pos_ch3_int; + +puntero_ch4: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rel_pos_ch4_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + rel_pos_ch4_int <= (OTHERS=>'0'); + END IF; + + IF(ram_contr_cur_state = exe_wrt_ch4_1 OR ram_contr_cur_state = exe_wrt_ch4_2) THEN + IF(rel_pos_ch4_int /= TOP_CH_2) THEN + rel_pos_ch4_int <= std_logic_vector(unsigned(rel_pos_ch4_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +rel_pos_ch4 <= "0000000000"& rel_pos_ch4_int; + +puntero_ch5: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rel_pos_ch5_int <= (OTHERS=>'0'); + ELSE + IF(ram_contr_cur_state = idle) THEN + rel_pos_ch5_int <= (OTHERS=>'0'); + END IF; + + IF(ram_contr_cur_state = exe_wrt_ch5_1 OR ram_contr_cur_state = exe_wrt_ch5_2) THEN + IF(rel_pos_ch5_int /= TOP_CH_2) THEN + rel_pos_ch5_int <= std_logic_vector(unsigned(rel_pos_ch5_int) + 1); + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +rel_pos_ch5 <= "0000000000"& rel_pos_ch5_int; + +-------------------------------------------------- +--Estados de máquina principal para control de RAM + +ctrl_cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + ram_contr_cur_state <= idle; + ELSE + ram_contr_cur_state <= ram_contr_next_state; + END IF; + END IF; + END PROCESS; + +--Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set sí. +ctrl_salidas_estados: PROCESS(ram_contr_cur_state, + count_slw, rd_req, + ch_cont_cur_state, + addr_erase_aux, + addr_rd_aux, + rel_pos_ch1,rel_pos_ch2,rel_pos_ch3,rel_pos_ch4,rel_pos_ch5) + BEGIN + + CASE ram_contr_cur_state IS + WHEN idle => + + --Senhales hacia memoria RAM + UB_bar <= '1'; + LB_bar <= '1'; + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'1'); + + --Senhales hacia SPI Controller o Cache + ld_ram <= '0'; + + ------------------------------------------ + --Siguiente estado + ram_contr_next_state <= set_erase_ram; + + + WHEN set_erase_ram => + + --Senhales hacia memoria RAM + UB_bar <= '0'; + LB_bar <= '0'; + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_erase_ram; + ELSE + ram_contr_next_state <= set_erase_ram; + END IF; + + WHEN act_erase_ram => + + --Senhales hacia memoria RAM + UB_bar <= '0'; + LB_bar <= '0'; + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_erase_ram; + ELSE + ram_contr_next_state <= act_erase_ram; + END IF; + + WHEN exe_erase_ram => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (addr_erase_aux = TOP_GL) THEN + ram_contr_next_state <= espera_rdy; + ELSE + ram_contr_next_state <= set_erase_ram; + END IF; + + WHEN espera_rdy => + + --Senhales hacia memoria RAM + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + UB_bar <= '1'; + LB_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + ------------------------------------------ + --Siguiente estado + IF(rd_req = '1') THEN + ram_contr_next_state <= set_rd; + ELSE + CASE ch_cont_cur_state IS + WHEN attending_ch1 => + ram_contr_next_state <= set_wrt_ch1_1; + WHEN attending_ch2 => + ram_contr_next_state <= set_wrt_ch2_1; + WHEN attending_ch3 => + ram_contr_next_state <= set_wrt_ch3_1; + WHEN attending_ch4 => + ram_contr_next_state <= set_wrt_ch4_1; + WHEN attending_ch5 => + ram_contr_next_state <= set_wrt_ch5_1; + WHEN OTHERS => + ram_contr_next_state <= espera_rdy; + END CASE; + END IF; + + --Inicio proceso de escritura en canal 1 + WHEN set_wrt_ch1_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001";--(OTHERS=>'0'); + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch1_1; + ELSE + ram_contr_next_state <= set_wrt_ch1_1; + END IF; + + WHEN act_wrt_ch1_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch1_1; + ELSE + ram_contr_next_state <= act_wrt_ch1_1; + END IF; + + WHEN exe_wrt_ch1_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_1; + + --Inicio proceso de escritura en canal 1 + WHEN set_wrt_ch1_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001";--(OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch1_2; + ELSE + ram_contr_next_state <= set_wrt_ch1_2; + END IF; + + WHEN act_wrt_ch1_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch1_2; + ELSE + ram_contr_next_state <= act_wrt_ch1_2; + END IF; + + WHEN exe_wrt_ch1_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00001"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= "00001"; + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_2; + + + --Inicio proceso de escritura en canal 2 + WHEN set_wrt_ch2_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010";--(OTHERS=>'0'); + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch2_1; + ELSE + ram_contr_next_state <= set_wrt_ch2_1; + END IF; + + WHEN act_wrt_ch2_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch2_1; + ELSE + ram_contr_next_state <= act_wrt_ch2_1; + END IF; + + WHEN exe_wrt_ch2_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_1; + + --Inicio proceso de escritura en canal 2 + WHEN set_wrt_ch2_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010";--(OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch2_2; + ELSE + ram_contr_next_state <= set_wrt_ch2_2; + END IF; + + WHEN act_wrt_ch2_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch2_2; + ELSE + ram_contr_next_state <= act_wrt_ch2_2; + END IF; + + WHEN exe_wrt_ch2_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00010"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= "00010"; + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_2; + + + --Inicio proceso de escritura en canal 3 + WHEN set_wrt_ch3_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100";--(OTHERS=>'0'); + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch3_1; + ELSE + ram_contr_next_state <= set_wrt_ch3_1; + END IF; + + WHEN act_wrt_ch3_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch3_1; + ELSE + ram_contr_next_state <= act_wrt_ch3_1; + END IF; + + WHEN exe_wrt_ch3_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_1; + + --Inicio proceso de escritura en canal 3 + WHEN set_wrt_ch3_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100";--(OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch3_2; + ELSE + ram_contr_next_state <= set_wrt_ch3_2; + END IF; + + WHEN act_wrt_ch3_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch3_2; + ELSE + ram_contr_next_state <= act_wrt_ch3_2; + END IF; + + WHEN exe_wrt_ch3_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "00100"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= "00100"; + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_2; + + --Inicio proceso de escritura en canal 4 + WHEN set_wrt_ch4_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch4_1; + ELSE + ram_contr_next_state <= set_wrt_ch4_1; + END IF; + + WHEN act_wrt_ch4_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch4_1; + ELSE + ram_contr_next_state <= act_wrt_ch4_1; + END IF; + + WHEN exe_wrt_ch4_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_1; + + --Inicio proceso de escritura en canal 4 + WHEN set_wrt_ch4_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch4_2; + ELSE + ram_contr_next_state <= set_wrt_ch4_2; + END IF; + + WHEN act_wrt_ch4_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch4_2; + ELSE + ram_contr_next_state <= act_wrt_ch4_2; + END IF; + + WHEN exe_wrt_ch4_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "01000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= "01000"; + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_2; + + --Inicio proceso de escritura en canal 5 + WHEN set_wrt_ch5_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch5_1; + ELSE + ram_contr_next_state <= set_wrt_ch5_1; + END IF; + + WHEN act_wrt_ch5_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch5_1; + ELSE + ram_contr_next_state <= act_wrt_ch5_1; + END IF; + + WHEN exe_wrt_ch5_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '1'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia el SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_1; + + --Inicio proceso de escritura en canal 5 + WHEN set_wrt_ch5_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const1) THEN + ram_contr_next_state <= act_wrt_ch5_2; + ELSE + ram_contr_next_state <= set_wrt_ch5_2; + END IF; + + WHEN act_wrt_ch5_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_wrt_ch5_2; + ELSE + ram_contr_next_state <= act_wrt_ch5_2; + END IF; + + WHEN exe_wrt_ch5_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '0'; + OE_RAM_bar <= '1'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= "10000"; + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= "10000"; + + --Senhales hacia el SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= end_wrt_cycle_2; + + --------------------------------- + + WHEN end_wrt_cycle_1 => + + --Senhales hacia memoria RAM + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + UB_bar <= '1'; + LB_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + CASE ch_cont_cur_state IS + WHEN attending_ch1 => + ram_contr_next_state <= set_wrt_ch1_2; + WHEN attending_ch2 => + ram_contr_next_state <= set_wrt_ch2_2; + WHEN attending_ch3 => + ram_contr_next_state <= set_wrt_ch3_2; + WHEN attending_ch4 => + ram_contr_next_state <= set_wrt_ch4_2; + WHEN attending_ch5 => + ram_contr_next_state <= set_wrt_ch5_2; + WHEN OTHERS => + ram_contr_next_state <= espera_rdy; + END CASE; + + + WHEN end_wrt_cycle_2 => + + --Senhales hacia memoria RAM + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + UB_bar <= '1'; + LB_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= espera_rdy; + + + --------------------------------- + + WHEN espera_req => + + --Senhales hacia memoria RAM + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + UB_bar <= '1'; + LB_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS => '0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS =>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (rd_req = '1') THEN + ram_contr_next_state <= set_rd; + ELSE + ram_contr_next_state <= espera_req; + END IF; + + WHEN set_rd => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '1'; + OE_RAM_bar <= '0'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS => '0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= act_rd; + + WHEN act_rd => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '1'; + OE_RAM_bar <= '0'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS => '0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS => '0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (count_slw = ramwait_const2) THEN + ram_contr_next_state <= exe_rd; + ELSE + ram_contr_next_state <= act_rd; + END IF; + + WHEN exe_rd => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '1'; + OE_RAM_bar <= '0'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '1'; + + + --Estado siguiente + IF (rd_req = '0') THEN + ram_contr_next_state <= end_rd; + ELSE + ram_contr_next_state <= exe_rd; + END IF; + + WHEN end_rd => + + --Senhales hacia memoria RAM + CS1_bar <= '0'; + CS2 <= '1'; + WE_bar <= '1'; + OE_RAM_bar <= '0'; + UB_bar <= '0'; + LB_bar <= '0'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + IF (addr_rd_aux = TOP_GL) THEN + ram_contr_next_state <= end_rd; + ELSE + ram_contr_next_state <= espera_req; + END IF; + + WHEN OTHERS => + + --Senhales hacia memoria RAM + CS1_bar <= '1'; + CS2 <= '0'; + WE_bar <= '1'; + OE_RAM_bar <= '1'; + UB_bar <= '1'; + LB_bar <= '1'; + + --Senhales hacia mutiplexor + oe_ch_vector <= (OTHERS=>'0'); + hb_lbbar <= '0'; + + --Senhales hacia canales + ack_ch_vector <= (OTHERS=>'0'); + + --Senhales hacia SPI Controller o cache + ld_ram <= '0'; + + --Estado siguiente + ram_contr_next_state <= idle; + + + END CASE; + END PROCESS; + + +contador_10ns: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + count_slw <= (OTHERS=>'0'); + ELSE + + CASE ram_contr_cur_state IS + WHEN set_wrt_ch1_1 | + set_wrt_ch1_2 | + set_wrt_ch2_1 | + set_wrt_ch2_2 | + set_wrt_ch3_1 | + set_wrt_ch3_2 | + set_wrt_ch4_1 | + set_wrt_ch4_2 | + set_wrt_ch5_1 | + set_wrt_ch5_2 | + set_erase_ram + => + + IF(count_slw = ramwait_const1) THEN + count_slw <= (OTHERS=>'0'); + ELSE + count_slw <= std_logic_vector(unsigned(count_slw) + 1); + END IF; + + WHEN act_wrt_ch1_1 | + act_wrt_ch1_2 | + act_wrt_ch2_1 | + act_wrt_ch2_2 | + act_wrt_ch3_1 | + act_wrt_ch3_2 | + act_wrt_ch4_1 | + act_wrt_ch4_2 | + act_wrt_ch5_1 | + act_wrt_ch5_2 | + act_erase_ram | + act_rd => + count_slw <= std_logic_vector(unsigned(count_slw) + 1); + IF(count_slw = ramwait_const2) THEN + count_slw <= (OTHERS=>'0'); + ELSE + count_slw <= std_logic_vector(unsigned(count_slw) + 1); + END IF; + + + WHEN OTHERS => + count_slw <= (OTHERS=>'0'); + + END CASE; + END IF; + END IF; + END PROCESS; + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_ngo/netlist.lst =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_ngo/netlist.lst b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_ngo/netlist.lst new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_ngo/netlist.lst (revision 224) @@ -0,0 +1,2 @@ +C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.ngc 1464025067 +OK Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/bitgen.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/bitgen.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/bitgen.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/bitgen.xmsgs (revision 224) @@ -0,0 +1,15 @@ + + + +To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int, consult the device Data Sheet. + + +To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst, consult the device Data Sheet. + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/map.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/map.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/map.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/map.xmsgs (revision 224) @@ -0,0 +1,33 @@ + + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. + + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) + + +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +The Interim Design Summary has been generated in the MAP Report (.mrp). + + +Map created a placed design. + + +To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int, consult the device Data Sheet. + + +To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst, consult the device Data Sheet. + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/netgen.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/netgen.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/netgen.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/netgen.xmsgs (revision 224) @@ -0,0 +1,18 @@ + + + +The generated VHDL netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM library for correct compilation and simulation. + + +Xilinx recommends running separate simulations to check for setup by specifying the MAX field in the SDF file and for hold by specifying the MIN field in the SDF file. Please refer to Simulator documentation for more details on specifying MIN and MAX field in the SDF. + + +For more information on how to pass the SDF switches to the simulator, see your Simulator tool documentation. + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/ngdbuild.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/ngdbuild.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/ngdbuild.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/ngdbuild.xmsgs (revision 224) @@ -0,0 +1,17 @@ + + + +TNM 'clk_main', used in period specification 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst_int. The following new TNM groups and period specifications were generated at the DCM_SP output(s): +CLKFX: <TIMESPEC TS_clk_u_proc = PERIOD "clk_u_proc" TS_clk_main / 4 HIGH 50%> + + +TNM 'clk_main', used in period specification 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst. The following new TNM groups and period specifications were generated at the DCM_SP output(s): +CLKFX: <TIMESPEC TS_clk_mang_c_16MHz = PERIOD "clk_mang_c_16MHz" TS_clk_main / 0.266666667 HIGH 50%> + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/par.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/par.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/par.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/par.xmsgs (revision 224) @@ -0,0 +1,9 @@ + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/pn_parser.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/pn_parser.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/pn_parser.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/pn_parser.xmsgs (revision 224) @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd" into library work + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/trce.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/trce.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/trce.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/trce.xmsgs (revision 224) @@ -0,0 +1,15 @@ + + + +To improve timing, see the Timing Closure User Guide (UG612). + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/xst.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/xst.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/xst.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/_xmsgs/xst.xmsgs (revision 224) @@ -0,0 +1,21 @@ + + + +"C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd" line 383: Output port <cs1_bar> of the instance <nb_mem_cont> is unconnected or connected to loadless signal. + + +"C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd" line 383: Output port <cs2> of the instance <nb_mem_cont> is unconnected or connected to loadless signal. + + +HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + + +The small RAM <Mram_data_header> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bgn =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bgn b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bgn new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bgn (revision 224) @@ -0,0 +1,141 @@ +Release 14.7 - Bitgen P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file '6slx9.nph' in environment +C:\Xilinx\14.7\ISE_DS\ISE\. + "chn5_mem_spi_joint" is an NCD, version 3.2, device xc6slx9, package tqg144, +speed -3 +Opened constraints file chn5_mem_spi_joint.pcf. + +Mon May 23 12:39:01 2016 + +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 chn5_mem_spi_joint.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| CRC | Enable** | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 2** | ++----------------------+----------------------+ +| StartupClk | Cclk** | ++----------------------+----------------------+ +| DonePin | Pullup* | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup** | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | Yes | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| Partial | (Not Specified)* | ++----------------------+----------------------+ +| Encrypt | No* | ++----------------------+----------------------+ +| Key0 | pick* | ++----------------------+----------------------+ +| StartCBC | pick* | ++----------------------+----------------------+ +| KeyFile | (Not Specified)* | ++----------------------+----------------------+ +| drive_awake | No** | ++----------------------+----------------------+ +| Reset_on_err | No** | ++----------------------+----------------------+ +| suspend_filter | Yes* | ++----------------------+----------------------+ +| en_sw_gsr | No** | ++----------------------+----------------------+ +| en_suspend | No* | ++----------------------+----------------------+ +| sw_clk | Startupclk** | ++----------------------+----------------------+ +| sw_gwe_cycle | 5** | ++----------------------+----------------------+ +| sw_gts_cycle | 4** | ++----------------------+----------------------+ +| multipin_wakeup | No** | ++----------------------+----------------------+ +| wakeup_mask | 0x00* | ++----------------------+----------------------+ +| ExtMasterCclk_en | No** | ++----------------------+----------------------+ +| ExtMasterCclk_divide | 1* | ++----------------------+----------------------+ +| CrcCoverage | No* | ++----------------------+----------------------+ +| glutmask | Yes* | ++----------------------+----------------------+ +| next_config_addr | 0x00000000* | ++----------------------+----------------------+ +| next_config_new_mode | No* | ++----------------------+----------------------+ +| next_config_boot_mode | 001* | ++----------------------+----------------------+ +| next_config_register_write | Enable* | ++----------------------+----------------------+ +| next_config_reboot | Enable* | ++----------------------+----------------------+ +| golden_config_addr | 0x00000000* | ++----------------------+----------------------+ +| failsafe_user | 0x0000* | ++----------------------+----------------------+ +| TIMER_CFG | 0xFFFF | ++----------------------+----------------------+ +| spi_buswidth | 1** | ++----------------------+----------------------+ +| TimeStamp | Default* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +There were 0 CONFIG constraint(s) processed from chn5_mem_spi_joint.pcf. + + +Running DRC. +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int, + consult the device Data Sheet. +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst, + consult the device Data Sheet. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "chn5_mem_spi_joint.bit". +Bitstream generation is complete. =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bit =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bit b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bit new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bit (revision 224) Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bld =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bld b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bld new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.bld (revision 224) @@ -0,0 +1,52 @@ +Release 14.7 ngdbuild P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe +-intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p +xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd + +Reading NGO file +"C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_s +pi_joint/chn5_mem_spi_joint.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "chn5_mem_spi_joint.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +INFO:ConstraintSystem:178 - TNM 'clk_main', used in period specification + 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst_int. The + following new TNM groups and period specifications were generated at the + DCM_SP output(s): + CLKFX: + +INFO:ConstraintSystem:178 - TNM 'clk_main', used in period specification + 'TS_clk_main', was traced into DCM_SP instance clk_mang/DCM_SP_inst. The + following new TNM groups and period specifications were generated at the + DCM_SP output(s): + CLKFX: + +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 174432 kilobytes + +Writing NGD file "chn5_mem_spi_joint.ngd" ... +Total REAL time to NGDBUILD completion: 4 sec +Total CPU time to NGDBUILD completion: 4 sec + +Writing NGDBUILD log file "chn5_mem_spi_joint.bld"... Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.cmd_log =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.cmd_log b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.cmd_log new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.cmd_log (revision 224) @@ -0,0 +1,315 @@ +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd +xst -intstyle ise -ifn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.xst" -ofn "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/chn5_mem_spi_joint.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc chn5_mem_spi_joint.ucf -p xc6slx9-tqg144-3 chn5_mem_spi_joint.ngc chn5_mem_spi_joint.ngd +map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd chn5_mem_spi_joint.pcf +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf +bitgen -intstyle ise -f chn5_mem_spi_joint.ut chn5_mem_spi_joint.ncd Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.drc =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.drc b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.drc new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.drc (revision 224) @@ -0,0 +1,14 @@ +Release 14.7 Drc P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Mon May 23 12:39:01 2016 + +drc -z chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf + +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int, + consult the device Data Sheet. +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst, + consult the device Data Sheet. +DRC detected 0 errors and 0 warnings. Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.gise =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.gise b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.gise new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.gise (revision 224) @@ -0,0 +1,201 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.lso =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.lso b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.lso new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.lso (revision 224) @@ -0,0 +1 @@ +work Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ncd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ncd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ncd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ncd (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###5304:XlxV32DM 3ff1 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f28eNrlWXtPI8kR/zrYlnbdr5nx+A7hxSY4azCxze6iKBoZMJdTdoEDTllFo/ns6fdrpsf0yPkr6Bamu6t+9ejq6qq+x9vix+5Hcff0+PbxZSs+Xp6+f3zZfS+en16Lu3/i4vfHt79n/ygapn78+bPISLG83vyCj4vn7d2/ihTfjh8PBUqOCTwkmlARHVLF5KAqJv8LFbODqpgpFeHovaDFEA3fT1u8vL49P70hEM0CEI7mKdZfIUrj2aJ9ACJ8AOJ9ALQP0mieeGNghDFQSomARxHwKN5XqIOvkOMrHGEMjjAGx/uKRMCTePgkAj6Jh08j4NP4nU477HTaeaezCGMy5avtO1gIY/llePwuyxWx0B924EkilAIxSgEpYBQhAMYIgFIAQDCeZxihFYrRCnXYC6Sv2fcrhY8jzFYFG4jRCnewRPGQCEtIjHuJ3vR4HtSBB3fgSTrwpBEOS2IclnRwWNLBYUkHhyke0oEnJq2kMQ5LO4RwFiMg67Ajige+q1cg9eqe2NX9KOHVPTwm6JBo0ixwSB3xQXXUeRAdUsd3dq7vRhM6ZodUMTmoG3VOGR5Sx+ygboxrXUlE60riW1fSoXUl3VpX0rl1JRGtK4lvXUmH1pU0tK4gwhgYYUxU60oiWlcS37qSDq0raWhdYYQxOMIYHO8rEgFP4uGTCPgkHj6NgE/jdzrtsNNdWlcS0boSp3Xdjp92BSO83b48WN/F8tP1GRo/PTyg8fP2hf56fs3Yr2JOF8TXC202H/SXPMVqCRyn4qsYqg8gP17fdupDMj14Y+ARQG+MvDH2xsQbZ8n45Z5eLH/cy79KTjZ+2b3u3orfdo8fmKsKOBxenP+HmkN1Ci0p5lGAAgyP4TC8Jk0Ady0kL29hdNCCrppzHEYH7eiwBd2UgnctJG3oqAVdd9hhdNSOjlvQ8X6/43Z00oJO9vudcPRQwIFwwAHtl9swRQs0DEND7ZTbMEULNApDI+2R2zBFCzQOQ+tqPwiNW6FJGJrs9XX7NiZh6GSvr5NW6DQMne71ddoKnYWhs72+zlqhR2Ho0V5fjzh02rxaDIMrwbxOO5vwUgsXDC+h8BIOL5Gg7jC4goIrOLgSlpMEV9LgShZcGaXj17vvxcvz7wCqr2LOaoiPrF4AyJtkvzaU536reMSXx+NMcp5s/ErLkbftY5KM3/74DWCcjP+8ZRXLrfzLK5dk/O+dmBR/+WQ6/nmXvH7/OWKtRnm6+Dz9UkznX+bTWQ4/DHM6Mb+UE8WnmwLmZ5PFesbmaeNZXJ1P1rNifT4/2+SXy0s+X5zNZtNPk9PPOfiWT2frz7OvxWT61+v1Jif59GxdnK1mf7ueXZ7eFBdLKmax/JpPF4vG6fVaDDj29HpzU5zenC5mxelytZqdbubLy3yzup7l681ktbm+Kr5O5hup4ZfZ6qY4n//l3ACLlZJZefZNWQlILsYX14vN/Gpxk2Np9dVsNV9Oc5B8SJI0t00dApj9fzqrg6/g/bjU7No5V5P1WqgzL+aXVP5GCWRx2ETGiSjt1fVmrWgRw17Nv8wmm83q0/JbDmC+Xsy+0l/UI+vr9dXscpojavGGUi/p38vpZDXNF19OL5ZrxHracjHZnJ4Xy1VxdpbT/9ar+SX1i/gzzNc3l6cFQ88n7JOq9/B+FsGxTwioC0GYstCQoQwXs4t8NeH/+O6uVwuQlMvk1+HPofdTQjAu9+o/bKGRJD5Mg4a0GynD/p3DU3ZCyiX59ejoqJrg/oT0BhPc67MR6E9gb3DE/qJer1eCe0U6ASeVWEP0Hx5QLra+ra1XE9SnsC4zUszAZoZ6nfQpxwmVWdLeSU4ybegv2Kfsfc7BFTuaQC5EgPRKNDIMkBuB+hKQa8sGzD7BD/tSQa4BixjFKwgZOicWrBWboriDSiCUEDscdHrAsaQk3JemZTbZBIh16gJXX9w/kiZxf2soMX+i/CnmKS++d3npPNMBKCooFCdyL+lkT85KVG6hoqTW3Bk8IqyR1gKNZMZmQ6XO2mvSOWBnrStEbR3Tf6QJBtKDkoRw5wglmdO10pKEr3A39KXuOnp4TNFdQ7bfZdgwYKU8dJYGIkSdSRGYJbizJ4kEAtpKWwa3km27OC6GcyB8jbm/uQa2NBkrsD4pVcjsSSFC2sGyhF6qhA7S3SpI9TZxvUpamsixAuKuSvWs1FP40GIn/EQCIsf6QEqAkZ5n504cUnFQjJLi/PIAxUpJEQvQsAfDoK8cR2zaSjmjfLCmWXCUAJsZblEl3GlkYbVn8ERYu7OWqHB3TJwx8481Jty70o1D9QFKuXcTqL9IifhqInIu6KtkpdJvIpMT+5D5N2GhTvHRtpHTeE3m7x7fPX5wWLxRfyS9kjzUmAXDkcwfCoqDKH6VaWvUho7+CAnQM4zRYGUDlEmEGSOTl0VJlN2uVXTS5O3E5G097PFAl8nE4FUqQ2hE5E4qh1UiTgUWz4Ul2jlYQgWllhgx9Qw7uzAVAr+2MguA5zvmSc+FnKGNlEhZ4vaipMglxTJKkPRrJRyLFZWx2wmNk0o6uiGZCgczH7DawsAYMfJcCt0tmhOutSwHzO6URNOIkBOaIOkCGRIDE+nq7CNnHtsbXpKhiykTqLDL3XQYWuZp/0RepXY4Nh+rSmyFdJTwnv6E5hOIzxI/BPFkWaBKCln/KJ1kzSAtUKKZ0bsQYiUiShZaKjq9FRmdJig8rl6Z3DYIkArr8DK+Mz7t1Y+tAe4bf4uqBAuHJ3cBaZUdYprTnlPSXB5rN+yx9F67uKpJXtUi0JNXE0dGjeLE4ai8VNacnFQkGFJxDZRp0oSt4vvICTSzbwN/y6w9s5lUQpCykUrtwQBxBPObwb4aGiJEu7jlImFmbhukWXVD4pTw/oq/ad66ScDm2CVi/3gZQBrCRSQtuY+61PeCn4e4cYek5FuuFeuV21p2wMZCZIXeQJeVOgqw6XlcWDt9mkClVZvFaechzTyoUcK+r3EGHY1N2LJbyOxz7fpuDEIvlxjCyqN09pMG4LauxH4h/v7IgqRmgWtyidOaMKfI0jGjO9HAagsSkZc4aUSqrfpZzE3Qg6ZcXL9y+IebKqxsbeFQcSQorgr5tzkP2XHm3Cai+G90kLrMgFVx4FGdEvdroWc34jrx9q3Ey58KdjUs7azEsqu2IA9+iYfNAFUQoapBJD6EXwQ7V8GRXc/ojeQu3IWBKscCWfAgP5QG5tnD3qyBHRHmEoJ1dnm01JZhK3JLcl8jd+5s4Kcm5ypsuI5lOaErwszHl+WqXylhH7LyMP1bxCrQ69BuLJfY34QT3fyY42Gi0ASnCgyrwuw1XEPyOmlwW23FcaVzn6C+Ns2Hx/rsVU78mkbHXCJy6FSa3g3ux6SniDwZ/FlKNDjIywPEPw1apv3s2JRB7GbSSvvMZreI8eryxA4553o3B0QkF/uI6B3zc4pzgpP6XbQ3pzhlajNC9R6IKqhEc2aDAYjGQryy6hHjjBIlNZBKHB0dlANTjFnJwuudqnpy0RrZl7l7wJ1Uj7ceIhrUuxoHt6npkU9VhNTBmk9l1XQsK33gnZcH9QSmcPWjg3lPwz399IuGIVprJ5z7zno54k/ExrMt70f0h78WlIkVEKascBlkPJ9wFZuqAKejR/y960S9d/lJvE0If6p4B771YoDRfmhdxTopxnl3uG1CcTsm/TBQ17Cqq1jZOo5cdP48gXtuZeu2i6FusSSJi+W8qtqnrnJiHJllv4WRgWd3ZV7g0CD0ntZUTzGoFX1+2GkHeinYvvXdk9dW+1e1DqNeBlemfHLK6vrFaSO7/4+soYux3gRDRZTz1uQGh+lAAg+UVmjqfWp2i93q1qtu2y36IcgPIjsPQ3+fGs7fScO7oqHliNn4v8s6TwQ=###4492:XlxV32DM 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1174eNrNWltv5bYR/jN+sM95Ee+6YAEbCYoESBu0G/QhDwF0oYC8JA2CFi18rN/e4U0caSjbe2y32WAjneE3w+HM8OOIyeXyvf50e7s88NPtgzjduld5elB35wd5d1oe9N3d3fnWjcKAOMHvs8c9SHiqsx+HPxdmuwsytXiMOgV9MHURIgP289w7WLB7G6Vh5gubsRZAA2qBqSNCyoyQ3kt2Ck48CDCuvGF2SpKwnAT083szpi+YSUFJC4mmNiJsLscxzssLYGLg7qLmg8mXNYS3UUSWAEIXE7/SCPNeLG75i5e6GabNDAnlXXRIlGoZksNOTnmN3Tn6I3wCkt2kdlEjsR8Xv6yRKxiOnipcYv5nWGY2T91fXm1/ZzauWWH7UpXtL7HYtrl+YOcQkhAOtAuE2dop1M9GHIvYae4C6LdazrNbRdx+m9JK6lxs1VVYWZwvergP4/J8ml7Kjg+xD2QK424RS4jjJoRhgmUTwlSkotmpH4UvRn7JoS/qLgfKr9ZdDpSRLpc73ZjTFPlT5DE0hYo8FnN0UUMcQxUbfZf3S0x3oJQ1qykdONPeYZT8uPMltR6Nh+SdiUlE7avZTcTcuididkP5iS7cWp/D6wBAeLUtaMzDKSBp21w4K6Bw4B2GH2PW7bczFNMst6nGhvKWjLmkHp1v110q7xBoi3l5MoJZyK7HoH2yLjwdzWsYFxSitCGxWU4V1H6hbNyBMNOggzsNp+1xWnNXIcRShKA5CkHKPUda1Hktau/lhfUIsLOed64zvBs9xzbE2TAIhue/sDVMOZp74TkIJRKuk1zWLeF1Lzb/dONo2Fm5sPW39qlyLBH2y72rrwvv6fiCT8qw0Xx4Loofg8+J6WVqIPBhumYqjfBT4m+pS0bLOrdps2eGWZsKVNfYUO7/QmZW2t6g8vmaJpMnetTwZ3RjkxArCbA1we6oZG2z+FCEboOQ0aaAPmPDLyLXbbEiaWKzvXMiV3kIQokopSEfq3JlanWMQsst1S82hHbzfjzm4dDAOY7PxfEFWShkMkxfHjofD937IT6SoeWZhAtVgPMT6vlUrliRu/dCIvIJGlx5CaXO6SDWZRTJVxm4tl65TApxX3aZswcI5akLnwVbAM5dcRZf+wnRFBApvcWxmF8SN/e9WpAqzORJunhwQazQZgztdLkbEPUG5L9T9Wu+uff2j/qfHoPwB1G2eyKVtjk5iElDUMUDHBXRsvtoij1KBqoycNn3ReYZ3NZisyJxz7ttllOtz0Us7ayzH0WNM26A9/upeYXGEvdD0fr9+i2QI736UxONg7rJPLqgvhpdhay7NSd2B8hz7cbyPqPJy5tkwX3shSksXlN4yV5s26PY2l5m9Nv3S7Eyqkt070Gub/oS/YI58qu+MMc7l28///Dwl68f/vZ1+y3/yruDRN/9/as/f/9ZiKf7+3/oSrPu/v7fSov2T61u2eNnzvpWaNZKBj+F6KtqaHmvbf34ixJNyzp49K3ubpQwrRK6ewIVXVKZm+6zkFPLuJVttRmxnVciI6aqD0f6oxFoaCe3ABC2/JkFgMtctAp6hRtmGzc2dL8INbTKSCHmWXU3QvVBDm+js9DdwFCrtOz+9YNkoOT/0da+MA+YGfrur5KPENMnePbueSO5gQEwzyvtEQA1cUbFnR3J3JtystG91S7iUqjkZN39R3LbCutfJv/ynWQ1rPyG675VA+A5A6Pd0zcSQvOdUE07PN6ooWph5dwFUMD6WjPBVDr+NPGp4nOMzz4+h/hs/AQ3kNRBuwmgP/xRcVj4I2dzy+zYOqFwLg2tCLPaVa0OVp4Gly6IHFjvdSub/vE3Cd+Qv0nYyaDOux+Z7VvzyAbwY3CTWfgL9kfI8QBZGOr26WelG8g5JKiCBNUQJT63VfeNAl76p+RNC2dwByBDQIyCNAFxClIEJAjI8BVk2JFPpiKggk8zARV8sgRU8GnIoP7Qp4aAqE+mJiDqkzEERH2q5QqqxZFPNScg6lPNCIj6VFcEVPBpyqDx0KeBgAo+9QRU8KkhIOKTmVycdkLYRIpKVTOWhLwklCWhLgnrkrCnQqFmKpRjYSLOBiL8Vcm8A6Uqxx5AkoAYBQkC4hTECUhQECMgSUEVASkCEjMBaQqyBGQoaCKgmvpEp2soiE7XUxCdbqCgkYBGChoIaKKgnoAsBTUENFNQTUulUFCGomhFCbo+ti+pMxerLQ5dUbGCAaQIiFGQJKDCdIKABAVxApIUxAhIEVAu8xWkqaWZgAwFWQKqKWgioIaCRgLqKWggoIGCegIaKaghoImCagKyFESDSSoYGkDKqE46UamZeAHKLaNSoQr6qqdHxxmmUkUpPRIGC/0tb6cWGjr9CO0qa62BpEoBzbBk0Ly5pltx3nL4fv6Z+UPNPd0E4Olk4u85PG0V5DbgeJWeAc+ZjM86yLmNzznIfc/XDbqq/UcBWHv0bshxcE5x5xRsPGGG4BWDtvpXyfysT4P1u0ZgtcklSbdayagK/0qqDV2QZCyYUnbYeTDJrQd9yYOZeDBpp6aDG3P4Y1dfptf50ux9mV7li9r7Mr/ZF1cv8GGAjNqq+1EC8dWPFpjNgmUr4C98/1ggVguFZqHwnN7Tbt4wW+XKQYUyYLEcNI9PEZ+xjHT0phrjc4pPG5+hDOVYxSeLTx6fIqxC+uMDR9Ty5I+A8h1Uivy+Dm39qsjXu8jb/q2R/z0Y5Y+fXChhJd0nJ4FhGJP++I1jEKXuk/Mc/PF6Oow5OFjvfoJd53WQPYh898lFBZbudFSF5qpm0NHGyX1/ssotyJn0covlU/cTMICXD1g+gnxydkIVrXMrZ6f2vqrkq/JLi4vl3t+4Drcd3NLiYv08/kyNemGNVZDzJOfYXoiZSvYGbE94vSrreXvAcM5vf+I6v7f2Km9PhjFHXsie833mddaL9px/3AR78BNyFgaVl/Moh90VnQjysE5YnuriYoNcRjmfu5hokLvtChQO27VB9N64UjQbjlev5vgbCUuRE+teJHt4Nl9E+sqaF0j/YLMNlPTfTrn6Ovq3b6R/H1+hVFd0Sl11DvivoXc/B+wz5wBwPh+A93t4jvCEdz7BE95B7+gcQBWj/jfngAo3kl/M736rvze/J/5wIQr8DpLE7zaPRX6Xid9l4jiAI35HHAs6VeM4sfHcjudB3K4ElmduVxzLM7crhuWI27GviNslS36yxJ125fYpcbFK3GlXbp+z3obbbeJoi+2FeI3Jnsb2ArePWQ9xe+ARLx+wvcDtQ7JnsD3P7f7rIuptuF0hbg+Dgav1htvtKjeY2/1ig7zG3O6T7Ll9djf07dgC2YvE7X3g9kjrmtB6oO+x6b60h4+833eH/B75PACt7jCxi6uI3TdpbyH2SKa6TKb8Kob3nda7N/jsKmLn4xuJ/bnTxvpebCwwvAGGBzZ3H8hQvRZ6JQtSy6HbB52X2P2I1d/O5rMvQH5Ey0yleErRb0KhNrWCKJmndte1o56S3T2Mp+SZR8pyIrcj/f7E9Ac6mHYTxXlbuKUesRzRrsZyRLsKy1faDcXg/RkjfXmnPb0mqnaFFujLORfoNR0TTg/Ta/qkcC/InqfX9HngNhGy5+k1fVY4PUyv0iS5wfYCvc7JnsD2PL2mNt3pbei1wfTqBwNd9phevRNBPmB69Yv1NKphJ+xvQAbcHUtxRKOme++rkMiesivdiTTX3InoaTy8E1HP3InE/SBL1KCrq7jTVB9wOaKrq7jTVPr9m2LtB8pNsZ6mVk9Vq6Eu9MThyeAp4AnvoPdHuhxpXnU5oqvqmubZVP0bm+dnSvP3YN19hQPUU7aT7G5J/JZ3XbRbQuiiTRXpycFLtyReJ9ySNPGWxHCN5sqUbrjC8pXSDZdYvlK64QzLV0oP5bTOvXbSoXa9rzpQaVjs5pbE7QtPpWGxfp5KZD1E9WFfejnH9ja3JLri2J7welXWQ1SvpyH5PWJ7u1uSBttzvutZZ70N1Y+I6sNgoPQJUX1wIsgtovqw2CCfUScdEh2PgJrckozklkSaDzgHvvyWZJ6vaaZNZd+nmS4eCGqerjoQGPuAZnoerzoQmPqIA6E+PhCg19GgoKEw9ATHMXz6aigeDZ+sTu8PdEsyD1cRPWve/5YkGPUcUUd+Z83+lsSNhVuSeUj8zhJnuv8XLPM74tgat+uG92gezO14fsztNZYjbjdYjrgd4TG3M5X8VIk7a3JLMo+JO+vE7YxnPcztjCU5w/a2tySwfZG9wO1z1kPcHnjEc77F9ra3JPOM7XGvN2Q9zO11hbg9DHqurhnmdrbehtQccztbb8BrgbndJ9lzu+GC3JJM+JZETu/3HzifvxNR+E5k7q+icTZ9wGX33FzF3rz6CPaur2FvPfcfwd7z4Q2ItsDUUwNsXcOzh78W/rqWfv4/3oDo+fkbkP4VNyAK34BEg46m5kC3ek43IHpObd68uQFB1DZvKVUgW5hS/Zb+LySzBb0=###4416:XlxV32DM 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fb4eNq1m8uO5SYTx19mdtmYOxyr998zfIuRsMFSb5JFlq28e7hUYeCAx25NMlLsNuby/5WhirLPa3mR1/Javn5w4l/c8fV/nNE1/HW8CFN2/SEofZFDr39xEu57rf9shFEezlhdT8Z6cv2TU/k68n8eWuFkx1bM+klcrPeDU/1iQq3xgojNhuYJNs9i87xuXuWWsUnGFTbp1k+66FgzHG0+UpNbtDa3KFw8aXS6OzrpYXudx+/TyWSU6KvW/bL+nwfx+otp8mLyeDFNX0yFMSge/mbhKF6x3j/dAHK3S2SQtVMiMgtJ4cjgyOEIo1l2ODo4ejge6T6+L3AkcKRwZOVhUJ21PAE+37XW1lnL63vWcp21vP2dTyXVvc4tt0yWbwn9O4w4wqdfH6nxcH39SaXOJS6XRGMH1utHuhRGE0q53M7CYMj1IyILIHJNKEwVgq7QJnWhRNhoURE7Y+wVBrV+pJkGZ8GKeKbT2U+6+FCNSV91tph43eSOTBm8gsGTWMLZ3nSkS0e6dKRLRzo2GDXzND6UvBx4B01tWl8XemwoF24HjiR2E67BbS4V+lLI6sI9ieOVOCKiBOBvC0WbsIMlaOIPhXFdidjBEDzX1FXNzH9hsYRRVg0zASNe5BJeUPK6t2xtg72Zujdok1Y1U2/E+VyyVLpzb07nElLqkLq3JfWmsTdd90ZTTXJUNaG3OA5q8oMc/hQrlopU4KAgrG04yFyQzRLgiBVZ5YIDCuix4kMcCuIMXFRYFvxrfxHz9Sdn4VyrOMPVmibkxvPso1Q2M5rvtprRgUKajoFTuSGICBf8km/wsHQuZwtuX+MFLMCJbeDoYc2Fv6krFb1ZQ0GCuoaVbe9Wtn275W+XpVvZdvdbVzbTrWy7h5WNfHcJd69vBRYJ+X8XWFA7CSwI/a5Q/63Igi3yv4wsVBzmPogs1BdTMkQQIYpQKhzDuQrNyHAe6vwqqphFE78litgmUQRh3zNNYJwWzlk8EI5Al5kZXb22j88+iwD4NyMAtuiyou5NBACjD64pGCZHAPFSjgDSUgj1wsWxlw+doUe35WwrZ3vr5fnZW+3lWVrz8gC3iZdPHenSkS4d6dLR6eU3VskCL78XR07rQo8NQeHptiw48nRb9vLF28XRnIV7FiELLQkeL1HN3tyjx/Pg8SKD7M3ZwquajTdfaDWcxpsvxc+Hs6q37M0d9ubq3qBNUtWsvTk9jkpf482XojycVb1lb75jb3vdG81t+qpm7c3t0njzVJp8syWNN0+DzAW09uaZVXLalKRwNCx1DF22zt5aWPTWfP2LsTQj/uAkHTcuj3buMr7gxBLrJ9we5qbIc5OSvb8flg9meJnnZUmTpeon9IgjJXUTLDchTel7L0MMolMF9vUROw9X1494JZ78jP+LNwD9qCYMeYU7IzGu3VkWL/2MNwRgfOc9MAPA9itgankEjO9iCozdA5ZHOgSmjxGwXCEAi50nYPFKBQwGFW6IW16WbhBvwNTSACPUi56YzcTCrLoitj0iFvqRM2R6v4cMxjpmpkfMoAaL+wkvM7V0rcKGI4tstswNbu7AbQ04JlJB/IfcNnjSzMntky9bw40J32OggMGdG2GJYlRE6VqUuechBTukkCsECLHzqOEjXqkQhCkKniPcEPoL15ctizz6h2MHkfrq4dDy0cPB5DKdTvTes5FHOn40/BjKAVDkkh+MeKWCAoMKlg9q0mOR72yfCi2bp0K5vP6EiYnAHMwmcgmsfypYWQP44BHg5nq94nt7v3LT9So/tb8GnJWNAasR4FwhAI6dJ8DxSgVYOYUQ81MHdybABnx5VHoCDuCPs056lOMNQW+EL9jeT0mf4XNyMSWFWGZTct/uTcnc83hKshGcXCHAiZ0nHfFKBQcGlW+op6Tgqhd5gMjtUqSdirQ3RaaexyLpUGSqkERaEBmuNCIxFRROWpG6E2kWWHeuLblNRZq7IvVUJBmL1ChyQ5G6FbmhyK0TaXqRBESqS5H7VKS+K9JMRS5jkQZF7ijStCIxVA4nrUjbi6Qg8vpxdVOR6q5IO41Ij7FIiyIdirStSNx9hJNW5NaLZFkksZcip7HALu+KnIfdfixyQ5EeRW6tSNzQdbGA4P3qmvcGoRl6KfKYihR3RU5XV+PGIsvqeqDIbnU9UOTRieyjOiNA5HIlUs5dCL8rchrVmX0sEqI6IdGF8CaqExjAxJNWpO9FyhXCjkuRZCqS3RXppyK3sUiPIgmK9K1IgiJJJ/LoRUKim10+rilHNxZJ74qchqLGjkUeKJKiyKMVSVEkbUXKfvNmMD8gLsNN9Sg+F9LOwkdl74WPeaRDKEoOoUiBUPIi/BGvNFAshoIqx+f5zi4+V018LqTsgWF+gF8C0w+BbVNg5i4wOQUmxsAkAtsQmGyBbQhFI7DtHZjugKkeGKQHxGV6QJuHwKYZKKXvApuGp4qPgWF4KncE1oanmP+LagDYewZKmw6Y6YFhXoBeArMPgbkpMHUX2DQKVONNi8QoUDoE1kaBskCxCMy9A7MdMN8DgxwDPy6BPUtACcWmwPxdYFPvpcYLu0TvpRgCa72XYggFUk/5zg7Y1gHrkzIGcgzcXwLbHwLjU2DuLrCpJ1RmDAw9oeIIrPWEiiOUHYHxd2B7CwyyuxUwzAu4yxQneQhsmmRRNzOceaRjYMPUXq6QgEGSRailBVaSwgSBDZLCpANGe2CYY7jOotOHwKYpYbXdBUanwNQYGEVgEoHRFljJBlMENkgG0w5Y7yUt5Cu4uQTGHgKbeklN7wKbe8nxhlGhl1ToJVXrJRV6yaAGgL17SVjWTmC6Bwa5D36ZWH5fk34BbOolNbkLbJoQUuPNp8KEkEIvqdqEkCpQOAJ795KwrJ3A+rDCQh6Fq0tg4iEwPwW23AU2DyvGG1mFYYXyCKwNK5RHKAKB+XdgogPWvzq1kJPB3dsEmHwI7JiuYcddYNMcjhpvihXmcNSBwNocjsIsuZII7HgH1r66ELr3khbzO5dbI/VwL6nnryLkTWB66iX1OBGt0Utq9JK69ZK6eEncS+qBl+z2kpr0wDBXdP3m9OFeUs9fnIq7wMgU2DipnSokYOglNWmBFS+Je0k98JLdXlL3YYWFvJNcLoE93Eu+ZzcKMH4X2DSs0OMEucawQisE1oYVGl92KdxLQmqiAdbtJXX/NYOFHJa4Dlwf7iXfsxsFGLsLbPp2UI2T7ZojMI3AeAtMIxTcS0JqogHW7SX1m5eEfBi53Bqph1sjPfeSd/Nheuol9TgfptFLavSSuvWSunhJ3BrpgZfstkaQdqiAQT6MXD9h7iGwqZfUd/Nhevo6R4/zYRpf52j0krp9nVPeJSuHwAZe0nXA3sIKyIeR662RfwbMTL+I0HfzYXoaVuhxPkxjWGEWBNaGFfiZSFSTgZn3LyIgNDuBuR4Y5MPIdgnseAiMTIHdzYfp6RsYPc6HaXwDYwgCa9/AlK8Y1IHAyDuw9hM2wlj+qQx/CSSGH90MEmL9G4xPkX6gEAiaZ7vx0K+ZIdxOhO7yC63cKhu9PtnOl9N+/vokDH8vbc13XuOoZXPlRxv2FRpafwYY6TPPjDSVGPgMLN6TXrak0vrDQ7lXzZyvW/5m+LOiiDZ/KJabS/a0/Czs7Cl6e0K+TvhH9mRP7TkNHDdx255qak/52J7zV0DjsH2zxRCqs6co9pTFnqrYU8zsqVp7YubCsGJP+W7PNnVB2dKbE7KJ9Jk5n8UclE8XuO1mkEY5nRrz1lvq05gZwtiWwwBZ4Q+74iAqUwLNeB3W0HhDsmMsqj8X8/RsobEivtYyEPfkpjoj7p0R39ZYyHBS98iI7qERp3HQdjMfRcUyNSJ9asTpAiuPayOGQTRG1GhECLUoftZG27VVeXO20BgRX+Yah0Y83o3oOiOazogbZF3p/siIz2IzKqYz0R53jTifictTI043EtL/wojdTDRgRIEzUZSZaFoj2rOFxogGDQXxYW6qM6LvjGh7I0ImmG6PjPjwJw9i+jrQurtG/BcNyf00###4204:XlxV32DM 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1290eNqtW8uy5CYM/Zl8gHnj7ppfSZXBuCqbzCLLqfx7ECAhuHb7dk8WyfWIlwTo6EXbhxbm+YcWx0OodX3+YaR8iGN9/iX25bE8/tDSP5TRTyCITlCFIDMB/qr2V/cOvnQwneCez59awBTPf/8RIh35S/76IYRZMw/i+aeUa245jp015Bmg4cgNScuhQUNDyg1mw6nksj7ksuWGJdVFxDBkgSFbbTFsjN5gjFhrS6KWra2/GGiBf/cWYLmtKNtANQxUMFCBRCIODcD4osuQCC2q8OfLkB9JqzpW7FUEs9TBtUFDA+yGXhYSzWdmsmgi6bJNug8o+yp2ENnt68AFbPgiilxp5E9Ci6yL9y0XbbJY9y8q1lJ2Cf5XWuzQUjiu0u6BiwIc76E2aN5QWI51rmPYH4n7I6HLXrusw3Jl51Q9Dz0cfrlhZb3FhKEFBJZlwUWPlw/OUMI6MtSGvMkLMpHF/TekdX+IR3qoR/r1t1aZBbmvoE/pIcxe1UlK//yZN64pCWmRPiRpUSWk44nq1Hosz0Gv9CFGvdJH1sSf+Yjb5KE3hNIzdsJaCHsnbIWQOmEvhKMTIhASXLW8SNnQZ0gbSACnvPwqgurDPf/W0j5U3sUKJVqOUMKQw44yI5SoGWwYlphXWJL5Af405+dAfgJCW8ajxo+foG2ZoE2niUF9lNWWttoK+2X6aiZrUVttw9WONEgvZ9nUIMoorCVhGV6mrWkiLM+0Oq0N+2ATGApkVT76AIYbXT9rAyHNEU3VNZipqlrp0FVN8rW4mkpjeQMpdoob0gf0AJ0hOsOOurVEJ+Q4wsbppOLHFji9cCqLKAenF0ZFUeLElbiIV5V4y/r8EHCJxEJqvKEap1M1XgYVfFevxazXCzt2sbv296VaT9q8kzZPSryeKrGflcbgNXb3SiNnf0DMSpMGpdncqDQMMuy90nxBCDMrjT5RmryquQSG9R1gmNiRo2j6Eg/8vWjueeE/qXMYUHiz9QADG1rQLPIAA0L2ASMMrLyBwcCKMGAaDJQODAY20dcaYWDlDR0GNoIHN8BAuRSFjh7M7irTpg8YPIgYeUMHgo5d6CaUDoQImWnd12KQkJneeUNhYilYcTSsyBDRpgOMknHhGFL2pmJIkCcYEhBDjncxpEEG97CvXAJ5Ah3ZKS0js7/b/hKEGAEzZI+nE0QhEJaY5SiE1AmpEI46t3UVQ4K4xBDxPoYww8v1KyyX0LG80K87n8KeIkbQo0RGqLaYOF5IdAOGE2IENSGGwG0T6R3EeAcM/4H7WS96UDzeqtwUuq5amI+3aIb0fQALt3pUVRvIR+7QEXTTwqAG91oG19fiHrl0kjdQnJYwtINbwKEjYFQUxAgdUvUB58FHaTiBjiCQ6WWEjiD6WgN02J03dOiIgkNHma5CRxWyxLNtbwp0xFSgY3tkBNoIOmKDDrvcQYeY3Q81uR8NIV5gSEOb2f3wbbG1+Q6m/juFiimLb39TxQXRMEfsJxg0AEmYoaaD0bJPYNTQKc34NYBR/tuYsWtzcNIlOKn3owIjZ50WoxewX6KUvNdpexsCnbkD+eKss4y+rnoQNGqHi+78xNAq1JPV24YzbhMALrLOmI4PZzzMPGNsM6bPZkwFRc5Ber89WX3MJ7u8dl2DvUTr+IHr+q14L+/afA7Ctl3bP9q1f+LW4BymBujPOA/4D+BD9JoIs75ALDpheQMGe4HeXHCTvdj6gNFeKN5wZi8cQq+d7MXa1xrtheYNZC8iuppw66qQYqcUocn0VDOEP+Ci1w/oWT82njyMaOWgA0sQRuH5VB6n8jiVx6k8TAVbGdfmtpaewFVGUKCjTQJ6WSIjLNA9SpHW1n8vS8fU6bX/Xo5qI7d4Hx1s8m3T5GDvfcBoJTVvOHOwEzrY++Rgh77WaCUdb2BWUg0O9k5WUg9W0qKV9CYf9cPCf2Qjd7SR4t1M26Fmk2ivI/JuIzMX/iL5pSMhpDffTn598eb8tTfXIaW7dbArZXt9SQPT2cf96HSWY4mY+K50Onp3SE6nk486cjodeNQrp+N5gwVZahxkeByU8KDk3UHd+y72LiUKB/X7zsvkT3h9lfXUOxkyb68O3j3vTL6/zXryg88Wwl7Y/j1+aqndhe3fw6cz+gvbv2+fzrhe2MV9/dQuasT5dbSLS6czuxg3spf+3MTkg2kGxeGHx4+hPkU6Ch1OTUyZyuNUHqfyOFU3MRtx60YTkzqdm5iV6HYwMfve6czEeN3mBzXgMIO2HegMZjqc6CGVG/fI6Scwo8U5zGgxwkyOGEQOmPSjR0wHgozuIPMuuHwzLztgR2YGdk1xXdT1Vpqe3tQBr6V8dcHlVdhiAmmhtYNzexOljDCzcOc2qqvkigmooXpZvx22fC8vG0vopk6gy0hzocUX2lu1LjsmcARVx/LkXMck+l6Zzi50lRzoqmYW6sDi4tYzkG3STPoBFHCgoC30tjafK/Stz8ddqlpdLRzWekvrQVe/Fmapg8QOpAPGO1xycK1kNMyDqoOKp2TFVmqS2V8SqBxpacrh1KAco11lVnOf64avyoTb1woDGtyf4jiasuge48PNkYvpBPf8YpL/MqKY6mB2O9+XdkutQfXSKgy3dDSsePfwLuY9kna++e0O9ucQ2n/fkCCzMLOfZ05tZiqs6DhgwTdn1sFf1DPE0Ws2asAGOadX1QwW+qLQafYv7kArbIhEu74cV7vuvgUFVrq5etJ8DmF/8xhK5UPxmQOyr+nSjI76aVR+9nzFlSKq/vUDrlFe8vnDlsRU+XDl40/4HwJU61kACnq2D8eRyhaJqKfHnh57krG3S8MgkLEa4+Mo9Njp7OWKxVpwpdP7EyuQLgfnQGPoD1egYGNhoGCjxhRuYQ6wEW5lxUaLyVdoa/PVdXRFOOgK65eJWTUKAIt1UNiBqlJWtmC8dqBilBUWVxzcFY2RL0BHk8A2CaxQvY3hsGyF8VrZqQwUOHVlkTwKLiXhqUA8jQOexrlQy4oqyxs42t9fUOQiF9HnUgUvZSdshaBmRGWYa2bMrSA8hT88NbvPdaJlTs3quU50UGq2J28xlgo2ujGGIkiRB2VJd30VQ5nZufHP74NO1+uOPk7pGSMQfaJ+yxHJoq2zaAFFE/eiqfdFMzeimVm0iKKpd0ULk2iYAZU9zfyGaB9Evm4UbXIHKAYUUb7nPjrVwgu4mayW7Qgx44BDDmtilU445ND7g71iGUxH+FTolPq028HplCu1hK6FTm8fbWTzFzyDTah45kTjCUgsUCXLA7e8GBy4E+3DcsvjhMYZhlSnU4lzQ+lXJ2nXVv5e0OFjg0qnB5B2S5ze7U+wnN7tVfSd3qQ1iN6Y66wn0E0IljErHQLRVGxStJ3e5tK4cyry9elFpBML7odmdjHfPMh1gVv9cGQHJNqB/a5MZ//XMl2PVwtby8OdFZ+spwd55uptr3++nat6UZ7qKszcJYNXdExSusV1Oot46CK5MRnpxMbpPXmJaubGZKdDR6nSKfdM6u2m5KXTUIk9Mrj03GVSeMJpsPRheiX54qXlR6Y/DKY/TRXVlsR8aZzFtXHuwZUr74XdmU1OFFTEdHV57PP3LZl+dXnKmZynJUXYLmKEm9jAmXRh0fTSZRZfLNqdWryw0UwbTGzOKUjGQoXKVbmViVfc6H079OewjY+VoT+DZ4sPtCq9GyMbOb0X6Ba38oZudTbD6WS9nFbIkG6YCpxVTNWuM8tiCrFgJg8GMYB2+Ky/0ruptZrTCeidEZzeTTYWxyq9m2a9cTq+SsuXwBsoVMQHBFmk7BqV/RiU/fSh1oTe9jaXKF8XKuKMF3trSPOT7aOVMr4TKWxzpKDnSMFQpHAaIFzUSfiDMjEHCpqw6CY+gBiDai2ESSFeGDS9UXZmv8Qkd/Vw09/mK+3LmosrmnWaNGIlko/SFa78wMCeZluovBT2KyfbP2/fvb2MFkpR4zQNs2+/K1i6CIygQoFYu9wLdvWA3nxTwvnRHcVDrHL0oYTHhTURiTYvHN+uDPqrJ8GvC4Ju/fJQBcOi3f+WhL22BQpQI4hN4odqH+sQU6gDYTrvDjdOUnN6N04BXcSQmk2BmatNWdHeZBKLT+y2crY8suWRLY9s9dSZlH0ZFrpYfBFR6T10EY7TKXRxGJBVOoUu6iDx4uBxkpUrdMrhdytX6N0DjrTuPljLwOhtm8j0rrjGNphedQwyU5hjyZsO+2BhVzw6+NlGT6qpQ/H+ZHkpOVfpLDk39O+WnSx4kbl792SpC7179xikV3r37jF8BHrbC4F74dF1WceguPhe7cqUfC1sVvtQ7WO1g1tGXlC+sXWZlWJvcuXKbe6ek1g5vcf3cuF09KjAyd3o9bgkZ8Q0Z8QvX5yRKZQU7z9vmZ0RCDZZZXOZHYZXLoX6f5KPZP9VuLT/KwW0+ov9v8sX3j+2+WL/9Zh5unpvKcL6YSii4xx+BRSVUHv13/5drn++/QDxJpGot4s3HCKEj2RuSqggv7I2lcuLDJEQqoneOOBTtRcGVqujh0d7ztLABr/5IhdoCZ3eIpaNIhbPxxCUO3twes9abZrTO5zi28NK71kxnTidZcUQV1QYoJ9gUIUBBslUqDDCpuT0Do8EsyoMJofgVA2vCHvYWPp306UYPy2D1n70/G8Qy1beru+QFTsIuCy+xHCXSbGLIEqdOz+IX2Pm6+wHchg7vfyB3FChOf25K0vkXNRd7hCvl7g50GkOeP/bC3l9/UK+R2j5sMpvQDiu/gfOn3Cm###4676:XlxV32DM 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122ceNq9W8my5KYS/Rl/ALOkq/CvOEJIENEbe9FLh//9MeZAiRqu+3nRfas4AkECJw+ZVFz2P41yX0bZ/Tcj45fUwe2/WaW+ZNz2H/ISX+Ir/5Xtr0p/fzNq/dJ22XOBboBBYC2AxQK7738ZWZr4x0tx5GeX9E/8nV4avqyQtRvqkr0bXj10g7X+tD/4Wt4xN3ZMDx0L6ZOmHVtrx6zTvWPG946p/YcSR+mHUlv++5c5jt6Wz68xtK2ttuWE6G05sPXax1Q7ZsLeBzeMSZUeC+hxNqOlb/GtxzG2t5j0YmrKm0aXuaG4fdRon7PbR4F9lv6266l91jgsAmlrWzqG3tZ1zRaB2bnB2lwrNrV8kOvL1bCQ1fBzMbkx9ffvpaup4v6HUiEB8YwMsBmICZBiEwRJLWVky21ZyaroDFwZcIYBpYYvbZW1iIjIyJEQe+TX6wykR5KB99/LxORPfygRStcPVlflumdtVXckrZw6KGEK4qEnqdk0TwmRDbEEyQP6vZSlVVibXEiTedCtP2Xk6aMDWPV2GwJ2TK3VsSciSN2/tj7CAqi9dzcPRKhcWYWTPaPhmWxboesLsOOmToe8sgnj4QlQ3iyvbJ/oDwaoDFxlzi0DdAayqUNcGGAyUBfDGhiSlokM2WIhAOBVb6t22EuGlMbaHAiG5MbSfwXRBKmDPI86fMU6IHIdXzoQWWNllMWqwlmGlCp1lr1jSDFZnix1VgMko1uYg9SzvMU39yXTt7TLZfz7T6PTFxWWvWx36da6t5Va979SlxsrTf2NiY7vaBMl39EmMTLb0SZmfk9z3tryHbCJgnPBiU/6UnBhwVEKAhZcpSBiwZYLgsCCc8+MJ/EtrhRUwk2LEoGlAAYLdCmw7clQyDLtv/a3kmcj0USmB1bMjiJRBhZcpeBsT8KArJQFCFhgSkHEgmSUPGsrJ2YTm0hQB3jnQ70rEtbPnfIyOOVjpha2CGpBv1YLM0dh9lfeUI89dEMP16lssJ/KhuOaygb1UjZY+aZs2PxENjgh/4Vs0PeyYXNT2WA+lQ2FCO9lA6yGdX1bNuj93bGtzxYB88pr98pp3MQrp+/gXRLCXSG6BEGdPSN+wSQFypNSBVQI0RoFAN1CVEEB7kRIAYhcWBxDiDxBqZPmhni39N0ThHjd9H0D5Jo4/AIUh5+W6MThl2c0PEMc/gbOuCBE3RwnvHrl6qZsuI40dZPKurrZPGmyqZs8r2USIkqYYgUQEo0TEAHnm2qDFRLTEodNNEYCiC4gqqQA4K+JjikAOOUQN/b2W1VSqhAhsTmGgO8nEqcAoEqiv9hbiFo6GQBqSZ0rEwtllppY8FksmPwPpAJRCFUzaJHd+dp260a95Q8rszF236SKoQ6s0bFc8BS3vqab3uQgf9rWTf2oiCdIXhYJ2YARAEAeCPEgQHrH/kf+LxkhJscuv65ElQFssHW5dKAxUofFKDJkM8b3xcYoMs5RKaCWEBG0xI2EiNaPHrt7FwM+7Jwe7dzD+f5bbifaY+J1nNSfep2oBn/ZvY6RV28rigd/+VoDPfMpUQAhREW5X4rgCELIn5wtoqLkTzR/VJT8ozkZAOQP6zcbkizfqDyWEydWZ72UN6IsFStPCoNY7a6wyOoAAGFHddByoPjqKaAc3YNozNIAcC24cyuQPWsS/2mzZYvIfDT5WmCzHX2z+enZBA8WVEj0wwmeVkL8/LSSN0+IciK/tV67NMvRuvvNs4wCZ30ZF3ktyA1dlbCSck+p+9IbllMnpU9ajl7NrLQcvUqf+loODipqR8vBPUWtaXn3gYkAygs4m/o+wecDm44kytj1GZvaT9lUDmza6DWMZ7iRVl2Y0qp+QquTg5l7eeyxt7Tqrimtfizmo57SanhNq8vLCN/Tg1tiJRA2qSMzftUzftUzftWMXy1v6oZfk0Upv5oNyym/utDLQ+PXXLHxq0Psnl8LgPzaN18tv+HXUn7HrwW449cCIL9KoX3RYVTRnX3/XZRgQ908MviJomstkTWnmqJz4buKToNuS5+qogtVCOtAkKrogueKLgO3ii4BVNFJYR+NcHUjBGqEl7LW+qmsFd81ggUjWM9lrY0EuZe1dmYEOxrhOnMgUGU7NDPEKLoVYreCu7MC+txr4+E1c507I2tzeU7W5lo5WZvrmMfZfih5jfE1ExzE1xiLm6A5i5uwcBY3wQKL02ksQUc6jWfoa/n41jR6mTbhoBnSYa/yqMOQ3fJ2UGTZX/kK/ZavSB0bYncmSazWMVizq37/JDDTMMu7/dkG44fmvIyNvRch1fSNkQq55Rbqd3OKJoJwsaf5xMX+U2+dPPK7Ur0eaNAQyMlGqYGE/Eh6VeVXT2CWVLKCIeByEnIxBHyOlJdjCEZ05GkYghGdGg1HBGNQ8nR0TGdG5MW5IFUmXKAhkZGXJh2sY86kwNRfCXMxhERwrGcIRn3qvCOCTkuemiHotWouAJHutrLrF3RMSHxt53YEyfIfrzfkNwU0HxrBLYLR/EMyouYNqvmHHMT2MgfhIQeR2o6x8RpRp0h4qF9vMwlNlnomOplwbbmGa9SpYYwLxEqrbqmUJ4s6uYvgG3ECC5j/kAXMKGGbkFYnxOsjj34/CwTzfIUU6yhqdRutAYK3kkXwBQvUz0L67WrAcLAsdwVIbF8WVXsXITdmg9Gdbx8g3ct8yVvO4GfeJH3LLVRt6w33/Frirn+kpVN54iBVGPWZHm7PdWo0uD6DJCjsyZ5R8AylQ82ekfAMIcZCf/iMgGcIRUKoJi+ueiqOcWQ0w7mOMJph4lyipRyLoEuhCUKi7kZIBkDAVx8nAyAUy0jY0egtI1THotqUNh2Naqtza4Hd5LS6eWpgN5sv8eGRQy0nkGPs5ChfRVrEEGlpgRU1xlH0GJwxY+ilLshbBvZjOvjcX1Hxwam4pZRpOvj6r9LBz0IJcQwlyJzkldFNokzGeKDk+I002r+LLqSOnTNfoSDSuk3vhtmX7PXgNMz+Ib9HP8n2OhE/zPYmfT/L9urwy7K9Ms4viV2/PNsro51le238NEBUjn/mzpcJWKaRK4dn8SD79MaXEZBSFSzXmjgMVH30LH1YZ7AjNX2Yy1r6UELuLH9qQjgZCNpF2NJgD6aTS7MlnVzqkXSyxHtoQnD5D4K9Iug3URFXhBwz0E+lLcjcAR5ACgIuJEZeBZwOcWAFwORwOl0RhLm2iHUmyeEKFDceZ7fB6jManiHHhOjIVBB3S4RJdDQSTc5y0bFcadqKBKGXruTJh07yvujuCwJelfju6GgWl/ju6NhtLKIDoqPBdqKloqPRdtWkVMu8VhO0zKsyY+YVgjOLYXHy5ohcDdIotw2xDWXG7ep6bOP8XoiKHLRT4+Sgnb4vBCkHtdShihiC1F3lVn5ezVVgL/3jg0+D/Qo0VxBlt4F9eVGN6Y4H6uwa5jb1kwXJMvjzh2hTP2n1+NSzS1zZv4fjIVbYb8ngRW+7PpxBBv+icDzoTkKZInuXoFKQAIjhlTcxb105DuWWsLtxAOqwkA3z7GVPT4qf+PqfeVXU1BK/zivleiBAWDSeGy3HK8P9okbg13/hZkfg93ThinHgt4JDv0ET4GpNoZ06J6Xc1xNUWlSFGOWKFeiFUnAeAW9oaLiEomtLhWwD3u2oXNvv+9YngK2kcpICwFaqhbYKebbmCvOEM83ZVz4dONh0qm86d7vpnh0DHq6HivkxADesD5vlSwzvO24Gltj5sMRmynd9KTCfq5BslWrGzXLXshkEaGK03xuq5ZhIhUW32dvrRLUcE7WwJDbLEqlG2DGHEXWfp+V2nh62GjuDZWG3jgTVzx8oom+E3TuBBoPXJgS7YCWVVQShDl1hlk6wO064qhvSzZgcZw5wVacBt5uj6XYhd5dmFwXedxLsNvM6P8Ye82Ps+5eZwdGnEW56sjccJmiDn+2Ndf+c/G/PXGobfngCuS+bieKjM4UsCezbE+YKvnE73j76uv3fnJeIJsmDpPpeLSD/ciYYtbLuDFEAKq9xGVeE3PsDTVQREgeSC0NQ+ON2qQjGgaoCRARVrnIHGQ7NKNa1VBHdjkJlyNWlqsUTmNKbjAygW3NhCP6QAtLeDQGOg/x2A5DkymjTFnbZIa2wn23fz9urOJXap2pwdiPIjTtejDtePvx+Ydjg12yDH+MGP9kG/39FpZIdVzULLTmg9mN9He2fJSNf/7DLPP/9odqWaYxpBQaQ04s0Dx37lrRN3XDTQNLxYSBJbes0kLT9skCSWvU0kKR+eSBJrXIWSDLhI9LPVNY1QW71NtCi2m39+gj9NR0EINTW8wjZEvcBCLX1fER9BgMQdWPUPmiW21QLUqNj4aU6rx2p4SW1rT28VCekN9k4Nfe+cyq8cVt4MEJZhpCL63JjCLoDIXgd/A2cWRhA4kCRAcRRbfQtNA6kNmxsZTlbdEfZkuzHaeDcKoJnEnRuFSE/dYP0R0XAeej1ZACGg7xlAFGPK0WI4lQtGtSiLnXebROPsqZFkrvx4G5cdzfHVFY/+I7BZaj93RzHNv/JW/cdJLkczDPX0QrMeFvS7m/ko59cmzzGTIYfE9bnmLB+lp8OmJ/OSnCbHEKU7xcqjX4juvz012FyEaN2bZdztFiAmg9GzbfZXhqDMev0N3FwSVjIl1mS/wEIFD9O###4776:XlxV32DM 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121ceNqtW0mS3LgOvUwfQBxFVYav4ghOiuhNe+Glw3f/nAACSimn+ouqUgEUSXDAewApoby7/WOk/BL7dvtXpOVr+ap/Rfn7j5buSxl3qwI5FGoq1qbQU6CbwEyBvd1+aVHruv0NQqZYntbys/z5R4v8ZRZx+09L+1V+bkWyfwm1ibv+sNpJx9TLHbPYMd6fUJ4U7Y/r/bHlYfRHB+iPvP0rF99ak3LrdXmPdaXypGld26hLrVCXtVCXO5gi0JQhkDduk97bUC7QXHTlydDmQm/O7GI0p0sP6FDK4wCp49jq49jejVi0xxGLo1mdcMRWaDZdj9hvIbdcnuSfH63WIr/9lGIrGuP32khVlAkqFdx6kfr0Uy65FFnThkXSVzGtFXHtqRSRrf4cWRmFZVQto1qZuGIfqkZXjW6a4EBTOjF61zVtpkFT7Lr1Fsrk9CodqbIMHfRebr1ebLHshrK+bz9FClWzkHqrRlRN7JqFaWTVpKZpozs1qmrqAGW9MYWuir0odsnrMkWRe8dTJpra8fKK75qImtR7JsvObXOImjKSw5ql95lrWm3tnSVmpmnWyK5xTNOsqfOknGGKZk2dDBU0U1Rryq82DZ5oujWxWiNTb6SYYHBFlFf+BifLgHyJrexisf35T6vyjypz3ha62Hxf1VK62y8R/fA66J/0vnD/pHfLN7XeD5ta551vO70L7kH1XvbhrzINo7U0FbGVzCAwS29+nyVCFWTSwVTr2ve+H5dlvlp3f5nRKVibQI6SaipUU+gp8E1gpqC6/LHZy6YPqBC1f1LGKRBNkOarqQmmSaL1S+6zRBmvIMTqOYzofR0w4iQ4IRdfhhF39L326B3V0TuaI9CtDOiWJR698wA6VYZheGclr7zzXfvu7fbDEWgDtA/ooLJ6eYTWK6C9Gxj3kAG4NtuW9EuYMXMZAdcZ1i9xHJdHMPa8P4b057eTw0nVjjUfAV7ag/eoQ0lwQTmuMLfmR5grrprucPbqcSO44tpId54yNHmk8gpcsrr7dZdUXsFKVmcfs6Dy2iVZXX1MrP7aI7l3qBkvtB1D3GkxLzDN9KfoaLuC+FO/Ms302tJrppkYID3vwMQAGRQbRoIoPjMNwfNtZxqC4ohCXbNUzeiBRA2DwaIxTIM4qFwgCgKDKlJrCKIUazZW18TnifZdA/j8N+RYUKZshfKDUGMAasIp1Igjbsgj9iiGGxxZ5CR0IW+W70P0oHIz4J9kvNqH6rgP9e0TAv67jkEbndofOqBi26aCrMI9GirHZbvDeu5yXOh78FSOa3aPO5XDuqyzYu9mxcKsRDIrZwhX0Ykh3AC0dIS8BwhXUTLktgTP3KTc7PPpMcfpUU+n56Hb/p0b66/D5QJzk2WlTgVxPXOeXKCuas6TC9S1zXlygbrCOU8uENf5N6itsLavXCIRsfSJ2ncJ85RgniyjOToFTnN0iuc0RyfHaY5OG9KcMvdC9zdEGmvAz51pbmxR6LzyRaGz5YtCZ8UXhc5zUVS201qhbKc4sI6ZJgBm+vUKy+3nWK5PQ0AhDkG8zh764xHDL7mFue7Py+zrqmOBR+A6R+gYBsK5vBlMNz7YUUP/X8ceXP+ui2s4elHXu4HQT03YFHGEdrVIqbGHL1RNkXgRnmlwQ4hFWqbBLSGk5bXhphDSKKZBRlHeyUxTgVB2iDKW2hSrRqRmU0JFYjZZHpJVNeM7YmWaGTovUjMNAWrL3yHgbiTTEEJgE9MAuNdsRFNVL7Cjt17BC+TprXlUJg/YOcBUHYMwfQzk7qIy19bPjM7mrt99eyMeo7M0Ss7Nvm8Yth2ite6ccvcCBZcvENuqBRl9eJk530GCeQoJPMSQm+aZIL2P3Jlx/q1MUNm5dr/IC6qZh4MJfSugu/Qkj+BuTZg7KaPOaGuOTENIMK7SrpkUROxMgZylMELk2sV+lolZM9EQCtozY70yTfNh5RXePiHumyGakY+qb49IZ11IlS3PVRb2wZm0/s1MFdnGTYOZKpU3pphEWAhuLCaqyv+OaYCi/w2xxFplT/uvgvUZN7iDDb4/3+DPOPFCgGRsZ7prIcnycNfS/X2XbMlmcIvT3ApLoahRkuRWzDG30vM0bpTMg41QJvokxTL4Zj5mZXiK5Zdsc3ILcbnyOtLssDGTe+51Xj84ID4mxngAdHAxZe9cuBgYmwtXE5dD4IOeRtrlGwap97xnjHeHBbJ3Y98/NWw9GhZgptJzw+5ImEN8eJZ50sywljXXJ+cDhXl9aJi7ioVMfmDYs0yRu45QTzJFxbDtYFiJC7th6SPDfkfgd9XC5pZrG90rR8hBVFE/e7DVJ0el5juEYEZwyF0+U0xmp3KkkBGyWF0+U0xmo/KZYhJ1AkyRly1ZLCt9LSu4P5QZHw9be/hZf9UmoKpS4O5wB6vyUJWHqjxUheAWIclfdy+BjmgClSPYRCupHNEpSkPliLcxgLz0pCNgNs2EZZbvM1S7OmbIgW6lFDeaROVIcCPw7y5HshwhA9nlSK+jNVSOdDhaP+Vj1Tjok1HUPsx1RZFBzqhBXPcpH/ZFqAsSdFVEWEE0ntaFBCgGSeVIf6JZqBzZT7SCymcGJm5noL8N0PfiVVZ/nxGz5+Sv8f9z9A+3w5mLvx1oQDqeucQjDdjuaMDFycp6PFmxR/RX76L/co3+D0E/XYG+xcODtL0cauhr13vwuIp73HyB/rv7FEryJfjL54aZ72Q9zy3cr1jA+pmFYb9kAVY9sPD9axSn9rQEyin420/t2a7A3+oX7Hl+nvYQ81vC/xTzzYeYjzhaFvdAzR0AdYEHwXAUUuG1AMFRBJo65xRoIHnV5QSYLJXfA1CXTwBa5ZQPcFjugSYzoJkAmxnArmLKB2jtUNcG1KWIKPgCAPZ+TQCEcLYOIQWmCfqZgf4kCZmRhM1SOSEVCHCJAdymqfwM4BIDuAm6iYMuKT/GIsNYTFBMNO+AtK/uB0r7ViIfcyRwXMHuIqIUEiher2tSPKCKXT6p4uapfFJFoJxdjpRz8ru2xD0scQ9L3MMSB35XMV+eYL4HzJdXmK+uMf/yWsUF1CcO9ZCvy6Pko1sV/irQt7dXod6/H+izAP81zB9158cR/3YZ8W/PMXK9xsjLOJIhor/C/Pgp5vsrzJ+nFW/Y83FcHK6gPnxqWLgM+MM7LO3to8GDYfEK8/2nhsXLgD9+MGPPL9PoJ5F/umIB27dZgAcWEOAB4uuQOAsAZAiRswBE3MBZwELlhAVkKj8LQwMPQ0n5gVYYIhp8x1+wAM9YgE1TPuoKGE5DKBrCKQuI/JpIdFBXGcJzFuA5C2DyyQJcpnLCAnD8NsYCXKRywgI8lZ+xgI2xAEvqGWPh71nAdsoC4hJ58mef8lEXpik2eCckxgLsQusiLMBROWEBksrvWUCXn7EADywgwAPkfULiLKCsmwL88qvwPYMsIAALUIwF3F1TP2ED8joDcJf/nzzh5FxvP2QADml+QOjHl0FILv4AyGke9//qRysTj1OjCad3HS2GwWl9doX//+4VUyM6Z8d/6jJ4vXL44u4WPkD0ivmGnZv4qJ880y6PF9bFAF4j37ziH+V6BAI1qgrp+Q3/5fqGP7nYH1ur5gT9TIjv3Ot/5Tp/lO44OBYG571JJE5fOuZoJISvEhydxHylBOch+/X4H1XSr9FHuENQdaO+tcnVrI9epMDb/rWOdtm/l0BXhZ8M9AISCqCPMw4iQrne+zL950dd891zSQsPjiWq4ZpHFIEe20Ztp5wgYloklSOCpmUYWVsk6NadQZPrPpitS30wlZs6ijSATF2OyNQ3MMonklkmn8inDZVPVAKk7HK8/CnHIXoDqTHU7ZZ9ZT+iRHryy6GTj+Dk9dt37NV37thXJ7/2uEfcnXRipgmP5Kxim3thH+fw3S6Pu10cv+fJR4e70A98olgvk7AZ/YD9nAU/uNJOrkJ0qtpWKPuIIgrYnsK0HVtmfcXVo7q8LrT2IiVEbTliAQUFcP0NYIECEgocFiIWEFDgfkX2AmRF9p3QNsZ4qa3ItZDlsgxjXZQLrskEa/LynoF4Y+k9ST9sx5OG9PTrjruThvDxSYN/76TBH0nOw4sHzz7pSDP78K9pVOAW1nZz/Wz1ix2P6cPrF2AfrP4TWFy3xDF43jtI83jevR7ygV2l6nasdpaOEDsmtKN9+eL1d4+11/YNnjnJS9Q46Jum+osEhcgYOEf38VmEe3gWsbaPBcxJXqIGft807PhxDX7E4udXrC9cgH2Vuz2x1C9HxmjB0vgtS3+bdk2lRHF1RxTp7UddL+NhHw+l+frws/4qLAsSD1VOeOAKZ+x19Bp1qQU6dVE70ZHAdjWCypHrrVZT+WR42lP5/KBGSypHYreqjcrxsiwGr9XsxvOq2eNh5LJb78n3qJC/qAVIfsb6jVbloCoHVTmoClM9a0DrRpqklWwjtcY0dSRNY8VG5ZjWsfCxZ5djGshKTeWYNlK7pXJMt6yQJqm9J+mZNeDIKuhrxr76qSOk18K94S5H0mtFonJMxVgpqRxTN2pn9WCqZ4XUUB1yQp7XgGMhoK8J+7pOHSHPVigqRxZjhadyJC9WCipHzqJ2R+XztoPtVxxT/eRk3mHOg3oE+eQ7oPtbD/bZd0CDkwxv8j/lW2mD###4788:XlxV32DM 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1260eNrFW0uS3KoS3YwXwE+AqsJbcYRAKMKT64GHN7z3xzc/tFTqsn3jDdzdJhGChMyTeUg9zGGfz+9yNw/x+GKUf5hD1oYFG/Tz+UPuW24ogqP9TqL8/qHUWv+v1N5/p/679gtSKpn/cPmf+PeLkSmP557/GGUfRqpnbjkeUnvz/LIo9ZDHWl4hxrv1YupkJDbo2qCwoc1fY4PnC9LLwhekF5cXZGQZ9Pkrz1CWqWqc4SJkm6GKfswwT4zO0HRlLFUJOJYQRQ2GjCWXsVoJY/HV6j7W+Zg/pQrlL/Xv16rLrJ3nt/KjSNajS8p78wjPb1n/TRKZZCmSI0uMcERQJpUFaxYcSpC3VIGMWxlL7GOsoqn6lnwKqiQmJslvyeeiSCSOliVttL2OpjbHZqbLBPYmCWyd9RnZ3uOZRBWJyhLtFybQRaDrMi0T1DmbOjOZmKTMOf/4lTevqDM32Yd9SP/vP0bn/+istbqRTrdNU8pna4jDGkT/LdFcFD+h5hD8hA4LIyZnX5tcQMFWe0Zs2GvDjg1rbUjYEJ7DbHtDfIL9flcCZr6IMg0lFDa42qCxYakNBht0bVj6WKn5BGn677X5ABXjlQ8w6AOODz5gMn07m76ZTX+ZTd+/Nn1VR3Mnpm+UGxNb1aedk5tnqG9niFvPJyZnn+TbxKxYx8RMGBNTRflbd7xrG2vbYCw9+aQ8RBtLg3+zdozlpzXJeU1qXpOoOhXjdbEcxoW+LrTXLfn0ttcZwd2pmlX4SmP6XGMxzBqL/bVLBI258dr9WmPUR5STS/wNupUmABelV8kE4Ij0KpgAHFE+Vkww/BDxaU1A3H2k06IuWm1mSLIu+zOBQ0RRUF5idrey+Ptlq6hXH5GPrItn61L++pYtmXv+NmxdbuSev0mqhqoXl45PpWqijVb1jRLAEYSeJkAYUTsdjMHIDurLh6VOLbuyLHH7CuvSdWZf65Gsc8zOrT6cIuujoU9BI6GbsmHtcWCrME3ZcAiy5rpKm6Se2yEpuNrekI2jDbmTIctqusorAKvUtJBfs8B8OjBlzMxYFAow7QOYtOjAZBCYGBClYwYiNQPRZ2M/Xw3kc4AUOCAtQsyAtF4DEgG118hkZmRyMzItp8i0TlHrhg8UdSkVsKHOQkVsSM8Xga6qyGBPQM6q4fd0Cszv/adxrYpTXGuOjiGL1295xBwju0ugXA8ASvFpoFzm1fp5tfoaKC+g3HL1A+xYtd6r/z62cNfq5/NYrnDIq7e17iatQzbhd9D6dqX15TZ3wkW+SEA0OOFyCoh7dgQeLPXBNDFwzNUTPGoShAd1CDYacddhJ88wFAg4mqPZTIYuKuFphmASSJp0XJkAciaSs7SpAUocSjIBAYmQmKQMJpYGEpZIOgpknfeJq82DeLkA7GzYHbDLcwSw1baxJYiyhKapNTFJ1VRomlJMUvSuYlsD7q+gIUr3dUMykOzANQAO5sa6howhTaLY9mOgQrJMx2MNzGWbBGINGjcIGlu1GAAFmEk25EcJRHZ5ZpJJRgRXknqfG3IAnf8B+MoOvgsB3wllvivZoGKRoUFEGWiKxLtvyCsD3+DvfcMY8tfPdIwdL4Pn5ue38qMo1BsiKTuTD9IOBwkENN7zgkjw7P0K7ij7lh7qkUAFqqvA0sT4ODrgihmrT9H8DsRJenkK2tJMoC3FNWj3HvI50Jvh/MEigeDdNiNeGL4XmJxt/TTiIcDc4cp5fiO1usACdQACJ3c1H//8c8DTMwIvBIF/umMYfZkq88XJEQl1rEJxCRJYQgcmQf8t1cEk6K+IC9GK+zhlmAT8oju61ZftbshyHLVdYTvx3j4G2g7+ft122g4A4Uc21NoB03QUtB2Q029s/DLPHD9nA2x5pM8GCMyU1t0AHTFAbiTDNrhJdBvZ59CXBbQ/lHWDwdVTQi/1YG/AEhbJ+APK3kznTL6mD6S6OufGCGBQ4yVXdBdFI51wFuqsSIKyM4z5fdFGyee+Zf3M3OR0hGsQpPszLctsffAwtyOLfRT0ITC88j4S+uABb2EV9hHQB466SrLnl9n2hrTml9bX9DKfpIwGcLpMO11esvRSzNkk1fmUXeo7mrNkqCfZZZwyQ8pubnMyuc/J5Irs5g+ZGhOJsCRnsFEzLBE42q7hiCWZniaZHJ/EnFQeMz7td/jUMe5gkJbN07PgwurtgmNVO+QKabnCB/t6M0/Q4AO1qmk+ZteVOw1IPiUmjFOoM9T4OuQJtsZwbOijrzTBSpfls3ymOWYXoaalmkQ9lE3HnGiO66IERGNe0N9LNE8DAqvjRb5rBPjJuFxNw71PN7yE/zyfcOG3tYX5hPX+/F0xBPr59ok0/ERuM4zZcSLTH53In3bZmvctpz4/9fxaXlb++FZ+kNytddhGBwi9re7AU9RI4xN90HZw+HbEJ60dwML5QNsBaPTO2gGk7CCbWztEZnYl49f8rk64YmGBiybLTS1JsHWRld7siyxJSO1AUhI7MvxiQiSNd2YfL4uMyjWWtkPw5CzrD8GWs4q2Q3DmVk3bIZjTI14s7TT4W2RfSGrvrRMmiaczG+0gRwfIWa0fM8+qIPmvHWFE8dZdrWtXq7OGDqrHoMCQOKNoBzM6ALli09BLii1GyfhX2tWObyUXCk6vtB2yZJsCbYcc2eGh2Ogdh02JtmMaPjLQ1g70gUptnEoj9UXUQKScIJlD3PwPwpClhyHqNMht3OvS6KYT32OXccNlNI8Zp8hvGdx8GYsEfm732I4GUgJVv52Q8rbH5P6elJ+pt9d3wX9AwY8w6pNR07vMO94J/23C/WOikp5nJSZBXTLv/h3m/XRHbi+RZZBXPLtL7zK+5ppnd3+DZ7fP36Qfgr+k193foNdf5WXl9e6KVXf72zq+ZNXX5W+w6h90bF7mnBH4DHNBrxflM3rdevYI0uvSSyY5o9fbaEivy5VOgNLrcsPRJnrdayJh9MwkIfR6YgJkgYonpVNDel0GJkB6XW58NUivt4M6JI2aLqenT1x6VKo7p9eLPTd6vT5H+FHp+RKQXpfAnDYJoZ5sZBLM6yVS8kExer05tCEZa5C4BihuCpLR6xLrocxEr5MJcnpdusQkSK/Ljc3vhF5vgjN6vUmQXpfARjcJodelL2VXKVv3ATDqOoyun4fRqytt9Xk8vSMf9pvSqn7XTW+yG4WQBlBtl0AlfgeorlI1e4dY6yVixbe96XqFWD688KZ3AOHer+2i6R655SirZVa8oYdaqb/TSOVlAStnJG515SWQxK5WXu5i+Wi0RCYxCbHFlY+G9iuRgAwrt/mAZrqBs1jBWeCNW2BRODXvjZdI+oNJINBn9s1TA+ISaC5RDsha9kyqcoGmwcB9N/DttKryFYmoTkjE/0PIehep7ieR6nFEfv+HdZBY1XdSHXwVqtmXFFzeiiuKyLY85b+O2S4r8lbxtpe5ZJcExNiFxrmL2e5CNf0qVMvGhPgaWPX0sRIBC26MYRJyPwBXt02CZI3nj5CQAS3TMD4oW9nCJBCaUD/Iq/vkaomEhEL94DRJBJcS0KUYIibBF3UpkcdrK3+E1NmlyCTI8hCXwmghffQVFXOiVZDgV4uAxVPDfTcB9XQbFWBQojfbYxLZb0SONArBw3BZdtxzM/9j9o37H7NH8D/sPsHsK73eloZVDRC/Y5LlqbJJmqfKJjnugExa+DWCSXiNUEIRMSWaZu8kurEGrrfDHWwv17A9+SpznlaK+euQtI1pQI1a8J9mjfX7YcTVxKZSDZPimBjUg6f8ZGjoIYPtI7T/myi6zxAWkhghpwtCLgGnoTH+F3LYX55QflmRQv1pacsvhPpTYmVCketj5jiEYrkkCUaEYnkhCW2EYjZLQhuhmJ2T21ChGNcaNBHQJdkpwCprimIUq1DHJiTPuTAkEpI7Q3cwCSkR8IpJhs8thXuFVX0sD/WwEKWs3eTjxyoffkUnpiu6con34YpO6ynsBhCTSQNNaT98aPTJAsgU50+P+v3Gb5YWOSxUy0PT0iJSRVWYZrwCyHFdE5Sl9rKw3GOUhaUVpay+bhSINAFYCGJXHQWw61fwBeQK80o2a+ubtZ8yxS+uYD8Eb/3G9UWJUNnfPIk5vgIiaQcf6i+v4Ja/cAVHj8BPb0bxiIk0OIl7wnai95gMbQe1Y/GLiTQuiSbSdrCqaFbaPuww75K1H3Yp9F1Kl7v0+c05K9uqVSunexK3F3vy+a14VQNVFtw0YRlfFpPAdrYDlraf7IB15ztg3fkOWMd2IEqfte+yU3OwA7HvwHFnJ0jHX5a9Q5WQr8GkOSsSOsD/WHlxKV9u2GcOHm/cY83Izj6qVA78ptze+aiy6KUqrIxNNsoPtCnrIWU+cYTkpT/ZqLYhuvWvl3atA9mxFQekO7ZL2g7YpZImVTptsHo3FnXZyaNYE16O7f1yTFzV6Ijn3ceJ9nmTcHeqbWEfiQwCjaDhaQ3m/fXNOEEDLUOsHObpx4IB6Pmkf6Pw8upTg/cKHUM7C2fsmU7re3ltNPPHAlKNocJ7n/lF46+q9AJc0FhzXxXDldOrY8xkkTWSOfWywcI3fu6eWXjjoqRawKQsO5S1vfeFXxxxSvmDxC9x3IjHEb+UDt2Hm/GMacX6X0tL+7QrGoeyPl51G7qXAJau9co+8ggnBzYH7aFHD3QgOtIOanTAko+KLdBBjg7gUloUZXKHfHDrxUZdQfnjf1wkJhE=###4876:XlxV32DM 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12f4eNqtW0uSIykSvUwfgD+EZLmfU5QZEIRZb6YWtSzLuw/Ox3GQQpHKHGurlvJ5iD/+njtElO4mmL//EizdP/9Ep27sJv5+wBflM853V3DdcX1TnN/LA0JsYNN+2Piu4Te64IziCnCVcS5SpAYJBpkNdncUF4ALKMhwinPAOeBKU5wBzjIuUu3ELyGO3FC5lVZ9fgbj9hvPf9zMjR9//6tk/kPKdP9H8XRz+/0fLUTulLv/5hH6dP83V5Q//1HC3dQh7gCIAcgCyAGYAqgB8AJoBNJRgNABzVgBYqttHz/diyENYCvAMYAIQGIDCPfc8gS15c/jKGUKxkdl/g6AGIApgByALYAagC6AHoAqgGuFp/opPD7Aoc9CjC7y8gsRB8AKsI8y9wKkARwFOAaQcteEqbVqDoXfg1HQE5P/sb9lCtVh7/9VwtwUkzCpR57eqOu08jx+dDqlNvN0Sm3n6ZTazdMptZ6nU+q8An7n7QDNyctLwRc72qMZr+2RBtsTtqk9bK2Nt5Xwql1ybZdZ26Wndm0w1Jq2S9R28S30dinX27XT+fVtfreyqLJHoDMAXVbzFGgW+hSo6ylw6xSYtav2cgrUPAVymQKu+xSo6ymw97cbKN9s4JaWueCmz4X/0Vz80RGmWf79gPnO6P0DKoMvv+B/n3/A/RV/CXhx7nlHAb6ZhufRK84dHqjO3bgwbMW5g1P9/COTpLgCHAjEuoPiEvAdyjkExQXgEZ6X0/Mc8NJWySjOAPfQSX+MTgJx1bYOBjOFjfAB1x9w8IArLVe9ZFV6+yu7ytJyN/DaUwY0Zo2gOPSUqYLvFIeessJiylAcespEwafnoaeMlxGOfVb2RrlJl1nR/XneZ2XHWfHDVik3sdI3TvFCubVvieKFcctgpQkvjLuXWdkoXhgXZsuIneKFcUOpF8dItDGNvtRrB06kgdWc4igNrFEUH8pACYqjMrDKU7wrg88gY8pMb+Ef8vzReF4+5XlCo2z2Ap20xaoE5MrzalUCetIKgXPlZvc0GGsb7smeuSe1uid56Z706p7c6p4scU9/YNzKgJamkpmU4SAGMpWcu9kydB7f1GTB6cy/8ZMFJzRb7GRBsZctc2ld7n3mYd0C6DoPui70+Vaszbca873wax+rL8zdb17EKXz2FRMm4dVE3KTV9kWrUTW3r2rOo5qj4k2uwkutak6v4q1Ist+NJiZp1mRVWJVYXJXYPgmvJs26IgMhZosA4zyeKTAjdV/PKTzQ/8sJuFijUCt8k7RWV2vV7kAOtROHPuVOKKt45WeaTXHckdupYNDv78gHRaOwt1MnS3CjnigrEUxrmJJqaphcC31jTFWcx1Rz2YRTXhNtHIzv1bm5lyotvVRHKZ3V0pNiJ6pMoABVedy/OsgPyl3eT7v/OLY5zty6J4li8TG2iocyHuCsPqDtRMdkQ3ND1YDCRxL3FPPiAcVibDYkxccPiketHD7C4NYMdIJV41QDp9pmeNRaOaqi4YSrAWVU87SjR6L3CBUYZ8Zhy3eqDpI8JgPKiePYJgPqD869JZbKH7tf3bemeilb+GRBhcW5TZMFNVn+2xALUXGFC+ioIukc3E8GwlPeTBbCbVEQSxFhdU7qDPJtJxNF0iXZMo8QKqVsiZMFtRVnjk0WVGMiaZLPqNNX8hkwD5nqQo4nCO/xxnv6SufwReccZtU57P6cIpsieqBIT9IYV3wXn/IdW3MTJHsh1+yFXbMXeqVIhRSZWYurJ8y4ECJHQuw8uGQmEmYmip7zZ3rOYTTn4pcd20O4qe4nFClfuvPjCGvE3zMR3CF5iKldlI/PqMqcUJVca9u6qjXIHWziDjIKyzLsZEJGQSztmNkl799wloSwncMVP01CyMs8kP4SZR+HP8s98A3FkHxYDEtz7P1CHT2rHLzojo6+RtIfZWBIpJl9j52eEfgMRqnUGxcL8dObmH6t8NfosWUcjCEbCfJiCIGUOvlrEj546pZpxOGpV5bREQOJUYbvh/VPHOhwx9WADJdr19SADJcNjhpGhB3NwAm/yWhJzys1M7ZGNJ6mqSdK9IsO8ZOFxEfb/BsaU8neMj8rFheoYSiWqCmOqR1kd8CpYEE6rj8g6mNz1EDUxza1CTWHSKYxWnbZfRXpGstZiNy5gVjOIaeJxmnmitPEZezOvhW7L3HfEu7ta7jn13AvvKC/meXMynLyMkdPWG7Ef53t+Na4ym9nXGUxVvPujKvMZaSjfpZ7yC0M6SwWEwljMf51B/rlhp3wWtiXmIi1ONNwhnEmRrfiZZxZvJl6wpFGYsxqzMSRfOXIFwEXcOREiX6l5EaJ+tAYcW0PAuAsnvpq0OrdOmKxVav5W5E5uC2Uw7nUmq7mG00BlwkqOeDyCAmUaoRXHzmQ6PxEdDX8Gs9IfIZQnkcZ7/0cmmzoocPeW1ctg7dCzdfWGoANS5GeFNlCCmh9DymwxrwbaODABjEXCwkcjJ8syHskTiuGZ5FdMYzIjs9FkcguMmKZIruAUVoZSKI3Rvzmt4n6SKxTLIP6SDRaLIP6WJwtSH1EKRQDkRBhMpDAzkdiIRpCJDszk0dmYsBhN38TN4+8JBsv2R/w0tUZMntNR8dCMpVToLn7mb9nIzZR3/D3V6ek6rWbZyU4kU/cvIiYcjtm3/T0fI3I37FuodtUE46VxhaJN1YamzVe/jsSC1V5uNKgGqq+xuKsFprRnn+DS10es2EkJNjhJwtZtyj/qmUkwRMH3ZQdzm3H1ana6nRv32xYRVJbri9uNjwRSZMWimsu/EmOYNxwGOvYbcfZIX8UGFWlLx/yq/cPcBeVUrID9unyxUxp+voZjjnbV/JVDpMziUkrEadgh0k2WUa0w8Q+WcheGFmpYsG9kPhBDGQrJNGiB5ggst4TDxTHHZL4RnFc7LBuCY5L3TFSzrShZZqaShhShsmCDJkEp3WMY0Jnc5RxS3nTJNw0um2a7d1jwoNfHhOuvv0qjxbWTfNwT6hfIHqVaQvrPaG8z3LXwxk9HF1sK8G/vIz15cHHA0+8zmE5686iAcewgfKav5Z2ufevmNBbPn+cby4YRpBoGucZxdHNh91SHDdKkJriuFGCdBQnYmbvuKM71Fk7cLJBY3L0edzrzguK4yYZG8466k8iOyiO3gT2DmknSc+QcaB3AY6p3r5tP0OEg4m8CdWNM9yFpu1C/3B4O929E+tWektIiXGue7bZnp/nPtl1/nLX7eN2Xo/Sc9/DGbt5vDKW4hm72cuDsGtxZuimi2o7OVqVyb13tBrVcbJ/9cgKb+r7+QZ3vzrzfM3k8eHIs1+L02p7L1iNqnESlEnu8GCoCuNaIlV4gJ7ooW6ElUBvyOwTToQmt9SA7qGupIbXG7pQ53LUWH9EbtBO+Lhx2+/VQBn0GrA6On70SmKrZOuZUbBNajp6akBHFPuFqIoTmcIdNQxPpDaKo+cal5YLPjxLECx7lrz3SMRmm2MJxLGMa6wvrka0o6F9vU3x/Gyo35Hol1ZzW/h6wN5XGz/eSyYFIZZcUj+r18G+n0vSYt1IjOaSglDrjUXdazPXqaRvHqYEIdfhMn240nubE1ZBWR5QJrn2WDtW8HoRsDxQF3Md4mKrp70fgNQUTuiSGGytPFvwNMojefaRaYIySqKpPoEpekxX1QdEfwDz5dpilYIm2NG/lGaCfyldGP5FNBFQj45rqSWbEfMM5P3AIc3OcXO4tjniRcB4nr1gT4IWvtv22am2zlAnQ55CI0W3pLDbQS3f6Vb6V5ia0nZczvtAHbpL2HHuKE72wdM7K73tY/k7txylEp2Mh4ssXB2lvrqQEmLa14401k3qZK2/vBMMJaY13dy8TZLfLfEhgd1Su0l8s8SDrW6sbfHEv1ViI4i8HWBllI0Gs0fYs1F+f0D1B5BFHe8ilbfzy7x4Ae8HcvA8EbVx76+mpH1+XyYOHPxHxsu7Mrsa5VMi3tkonxLx1toDg1XKyYu/4P3dmjwtFeeFInc9nie+rjoK3dpThEhK/cvRvkAV5FWgXY4qSPo9FnbGolwvyvWiXC8Kr1zHvfciJSqPYr+WXEooo5RC8VqV6IsWakNSvJaFUOOWZ+A2rrts1Wdtk8/6/3oafOPElmSifrJReUw/e5PClvT+05c0Rlrpu0WLtejYi44/LVqevc4Qf/ZqyR/T40sYGbI4jG/rDyajrLbyQP0i+hdJ15+1vhclHk+SsCjfi/K9KN+LGidLdhutIkvZWtdxRh2BsXLgxBGYUY6gG9ja0PFJrBgbB04cQX3po3WhvPQBDWtfRP8iyWsgn8FYkMXZAeW4G6/HK9/2UZoibvWKwR9OtPNGUycb7uGVMvfquLrvxIe3wlZd/bBFzbqPgKbbCzaD+uKks7/6spMtbmzWG/9R0jyUb/dJdCySwtj9zIts9ofvY61bHZJ5rWjx097rtffH1Hvxovcj9KDDkE5fSzM/HYaHG2k4wvynw+DmYYCDfDoM/HoY2DwMx5l33vRPh+EhdMMRZj8dhrAMQ45B6TCwd4dhpVbyYpz6KZP0N7ua7/wwJVUKwZzpZ+ewGinLdPYxPXtaD/5NpxKD/plXvL+t1fz5ByC9jn3UQd/wkv0dOrvP3IC4pgkT0zO9ptNYdrcF729NIScV0dr8VcVbmwS2KYy6J77q793Z6ZJ05ZmtllVfLrT9LcPOM9C9hsiOHB1R/QubXkk0/QU0N+lbY/pLcXbSt0ibpifHa4yN9Gj6e+s1JjedTk17Xb38sA2B5aNuSrXaja7WNwhtf5WwC4yyWioiO3J0RPUvkwg25hhdehAhWJ3v1flene/V+V6d79X5Xp3v1XWhAgeVubz8Xw7nM440H1qIX2n+f35tUc4=###4984:XlxV32DM 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124ceNq9W1uu4zYS3UwWwLcoG72VAUiJAvKT/ujPRu99+KoHacm+VxkMguQ6xxRFFll1ThVpbZfn82+5m4d4/GWUf2jrK2AJsM/nTyNlBp5/4r7t+UNpLn7/ZWR6WLE9/zHKPaTanxk5HlKb5fmXVeohj/35txK+PJr/hvZXreXvTxNC71KWLh3rUtrWpVoidLmv0OVahldHk/+q/lfP4zf9CzYPN84jTfOQDuax3ZrHr10t+YP9/WPf4iO3fuYPG3zY4UOqH/5T/pMfCWUC6ndtkDvKuFwL7lzH5fbIsyztVW0vOa4Lrmv7g+Om4Kbgeue4Lbgt+MLaZ5v0Ear2bnwmtr7kftS+HMdzXzKJ2lcivPe1QV9BwPy2Nj+Z2vuH+ckyLlnwFfrKJmzt92qnRfN3y4JvdawDrgq+134OjuuCp9oe7RegfbXrunO8tm92jRyvtqh2VQfHiy32Ni/WT7dFBFssij9T51DnbAzge18jVe3tBeG9r4R2hWcy1PaNa3aSvK+yD1Sb98rxsp9UtV/QHC/7SVX7LZ7jZX1UzLgNB9/iAbZ4gC0eYIuXIYn86uxpyVdPkw/z+x+jZfartXpYeqTuX0r558+80t1n1+5n4G9lTzxjEnb0WHP47rFS3/TY1KdZ+ubbLVjCi8UzXs2uVoaTGzezIM7nnrf3I491yf/B2e999p7Pfgt99gIiljnUE2JdB/TzNOiZdIxR3BwCo3ixLPQdqUGsDbb+xU5fbPWLRMBegQMAK2rfiY1zzZE1O3brK8X20uPoxhf0pHkWQBKwVEARoCugCbAVMAS4CtizPfJTSdP/9j1UqSX/v+vtqh88o1flDQvfS0vbS9oE2EvBDpQjBibh66I7iZ6QkZ7Z1bB1QTLySozDsTka9uGsfThGiavh2OdMicM49TzOd2SvOUkm4WayV+By6h7Ze5kmshdr69IkJHtzQJd+nKo5Zsur5zhnk+Y5i3nOsk5RdB2g5DzF2MWHP8D02Zm56fVsejObfFrfJJYr0ZTj+i07JuGv9IsU96KhD53sindkq5eoVwi+LRniRFypk11pwEk8rRwn8WILrgHXmSqy8ZmKWQ7FHxQFrwojBQivjqsILw8YmKgMmQcWKh4IZ0rFK8knguzvQaW09qR4wkLvbTSQCgt6MRgK1UJzY8RRLXi5chzVwpIY3sa/1fEDu7fx1IWI1T6R46iCvNw4jirIy6E9qaC0wbz8oB7sxhfIwAKRnIQdUh6sBskBteLIi0vHZZURKRLO5G3jS9MNW0RDfbB98IxB8xTYHstOW3poAgzEUR5hM91xIENjzx569tAzcraWjfurIu4TtYWzvc6L9Mga5kGMnTpjr58YW1wz9sDURN2Hm6lbjjG5yoBzDt+RwwdSvybzzt1E5uYIJ2SebeAv+dF95kdzzY8DL55mbUNkvUrfvLaXjGk/M+YyD9A+P1Gnv2byE+r85TX4cB4pj01aEM5jUxhwjEHkwxVHH/ZacRx9nmJExSlGBMNxiikJ2/shBkGGU3AWs5rhEacYJyLHKSZC1thwirlacxxJhUio4kBCf2LMy5X/cVk7SIeOeXTHDKeOKWcvU7Nj6tntTiU0ue6cpcyy90SRTkpU9f9XkZyyxISckBGQKoB+bGUVzor8WIoKkCiXRdW8yFzjRrGFbmx21B3evlRWhi2vZrd5J3/eOkVeQ3+RwsWbtaNYl+FMocbtZo/JXGi1GO9K3nhR3zIpfF6Fl9BkPoYmN6/CMqxCWi+kYwz3lGP0nf/LcjChFGuaZgveuLc1qB+ymfuHldNy3HscLA2YZIgbewXXgAbiUd7rLH7FGKG956l9hCpMHRKl9lGzflg8itpzHOMXadWKY7yLu+Y4xse4bRzHeBoxPkJlq1Va4qrJDkxSYQWmmTSASQOYNIBJUUNFHfgrsPizHJbjWPyJm+c4FpHiNrTHQhXJ7V4A/E8rUsVdwhRWLjPjagknFZk35na8hvggeoiPn0K8nEO8+ii15hBfWOFTiGeVDTmXKVghI8yFjGUuZGgsZAzVkQ/8MYd4HS9DPMYr774cXG7onim4XFXpwno3IF8VIYK/GZCtmmsQPec323bDZv5jmUXPNjOjza7KA2G5a7Or6kBwN0P8doDT+tGZJeEsJaQ4lSxEJQcfFvgw5HrR4yuGLDJuiXBOCcguyQKXOPiwwAc/sguo4LwF2HmIt5Jwlk5Gv8OrhwpA3HbeD6tgWI5j4kxRvuJYKqHQXHEslUQP7JWGAjSySBkPZ0HsR8eBBTfWD2NBYi8dB5baB5yxlOc4smDcAseJBSlLiIxN88bMsV8+yq7LXweM8bLH+I1i/Pu8uqfR74K9vs6rS4xf+l//mlaH76bVNWnuaTVk04U3zMAf7yvhLwSyzASi/1UlXIU5vYhzNrH1lpR3iB3zDkg3CgUtnIqy0noJ+aYFG0oyTIRgo74QvkIqb7S8RzgRpvJ8jqFfLBL3mrAaSsBjgBa8Jhzqgp1xqqLqx3Fc8YN+frsMb8+qxrEezp1R6W5v0kJ0c4+p9yjurtQxr9QBporfX6lerD9dqWGBlpnAJbx1+bxAn0WPfrlDMKyLuRAkOYbeXJcXAdBXejtursshxnXBYxZltv/Fuqi3pyqhVpjPFJYy/sYCLc9P52ru3IOOC2G167sr9SKs+tpv6e5KyWmlpAZT7TdWSg5HkS+Oc3nVBg8a36yL+3zMebYK0VyI0V3dFKOuy46yHEUe/ShWLMcD5bsutcpc67WJ8v6eka4OnjODiK0Jgf5duynKpj7MUmVMWRtOqXI9hsAHDTxIOTNcaCkj7W9cCm4kf1DCg9NNi7U8CPo500H7EEFIB0j4Iyjq/FRHoDoQzaCx4aJLe285T1FVKMIFkdpVs6hAi+Lk+2Wh+ppm0SpQcJgehulhmB6G6WGYHobpYZgehkk6fe06vbTkkt95GKbrw8wEBMMUMMwFhokL72HDBMN1c1wjmEPwE8eoD1geAcszXFSKVvIGChqQgof6TcMxQ4jrRobuM6vKe8WZoVKvG2UNNOM+8treLdS+WyKBJSwumAVLaLAE3KQqEK+LrSs8c/DzgVhvkGnAqyUWfrAQzcEbKGiAJxJYHGw4nmBEqfiDBh7Eo4+4LvBg4ufRUW/wYIIh2aFmZ3beQEEDSlugCNhwSlvqIQY+aOBByo/kwpfdwLJjoqf7UW/Nm/rTtuKh40nARBse2Slk66zhW8fVAbHBtgSqHoOEh2c3ioLq+dM+5E+3Lg6pIUuC7GibDx33/sVpDsSzJEyG7LeKZpDqTCUy/a5E9qWMJs0nKebNSUomTH+VCmhMBfZwRZhfvxd0rl+iuMgAtpvXRkKt/Z8qZ738H+YjL5TzJu7OJ1wJTe0/z+dNKe/iEvF4nhXV1VnRcXc+V2dFSq+f53Mp0MzHi19jFTfqqyOidFOyrXDuEvUgvQwwcIqj4pIcJ8VlDcdJaCnBcTyciI6173IQuXCFs6a8ji/XU0phMftfV1ESPij4oAddZTR/PR3jSCS/wAuO0WnC+7DUoKnw9R5e7+H1Hl5PesmjzJSDvjGCv57kixmGxeqOB8dJtVjFcaprQn20xBXO7VZwnChdKo7j7YfoGN7NIcEcZuHPkK4QuHOGGwrRScJ7XwJ1IKovMagfPcyDxI3e+DuYwnAcJ2HhhzGRsDA7x0FP/InelXroUv5FMtedzNN3Lxu9FkXdx0sO6uQELI/KXVz/MRtGoTV++fqP/nhiYr91hP0rKKjjO8elYVCe4+xWydD+5BTXDae4YRtw1H8hbhynWzGQIhWc6u9/4nqUy2T1X1xf09f3YOtL10J4rZWuh+SOygz0KTHghSc9XiI4oS/+W55fZXB11KVzdnAbIJMqOIulaN2GQ+wtB2ruZRfbNstDnM4yzJdfTqXbUIR+cxumi7pRw+VRLdMdMbx3QcWa611sn5fk+uVLbG/PSn8Vs/XTn2WwP9xdKDi3/yY5jtxHu9gunCtp19uFcyt5iV04WZFXVRyKA1mV5A0hc8ahcqYP6+v6+sqvHtm8XIVk0WkMSj2O2SFsYTICvwcJNc6fBqmA6ivp+3cU/fnwTk5zh1/INe/RJ6JdpyvVfiGaAlKZa7dcf5TOJyctHxiV4W9RalNSKAEpzkkeGpfdcxxDo1RwS7h9QbFRDTjFRjjjbDjGxoDKzMnhRl/ISaR8xGyqDXfV0neVutpV6iPnie9fsGW3PthF22NKbfkl2RqSYCMmcbURHeWIy5d/TKK/f+HLvlXzoWbrpzvysN/akZmG3ERDlD9iSf1YXmjoynNGVt8T8IvjqjEoxXFUjSucthec3bElF9j3wQV2hjOXoR2aBHcNcpkkuGs0eyJOnoEekMTgGVJznDwjsfc2997hV5jkZUkMXrOqWgDSpQBEl6R89xs9+M3oBKycs89Vm+ufe/Eb4mdn2lMtZmD4idjll2sydLsVj5v/trVUlmk9vsTX7m7O4o+ldLz6xY6nHQcFimxUI+djTPQQdBD/9XwXBlt6VnPPCdgAe96+fmBEPftaTNFnR68Svdrtw8HRy++kzHCSRAdFPqr5/BD8nH5edIx1iHfKaPnS7+DWmkXbk/qQ3v/dMvh9vvKFp2z0SzanX07ZLn9tNs7PHG+PQ/1ur6o6+PsvI9y3q27mK1W3X772ZXKYzLs8W+T5o2zK+uG/kceNfw==###4884:XlxV32DM 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12fceNq1W0uy5KgO3UwvgL9xZvRWOgKMHVGTrkENO3rvDwQSgrTTN2/1G9xKlyxjQP+DvBr9sDI+/yr//PvLJ/MQD/XPnz7Zh5Hy+ZdSa6avyma6LnT1kMk8gaFcZIYdHtT4oMoPikx3S3lQbvxBjQ/q8mAqDFvgDAoZVGHYCoPQnEEiA8wtwitkY4iyjRDrUH/JBK9Qss0t1jlk+g4PBv6gwQdNYTiAQeCDAh/UZbHb3ulll/5cjXy0nZK23iskE0J5xme6DUemm0pXIpRnFF5ouPhLiTot1bdSprKVKsAWi76M9laNb1ULvlW3t+4WnvH8rR7f6vGtvrzVw1t3HEHhCAbWenR6eRnsVpHwv7+0THAvswrcPAv0Olae+IHiyvR/42riI291ePiH3P/52+j8Hx3W5x8mP3GY5x9WlZf4548s3zzEH0b5hzn0sxDKrpRf3W84uGE6QQDBdoJ6Pn9K2IRyY+s3VuBMnbABYe+EBIQDCVbA4LvoHKEMvlsYXAnZOcu8lFCdEICgO2EBgukECwTbCRoIvg1e5vX8qeRa/69i+6UVWWnKAyq1G3v7ZfM/8nSVgxGj38p0Xf4T/8Dum2N5/m2UyzqhijyOLJmsuCARmXeLS0Tb5Vwi2vpRItqaUSLa5r35acBkn1khfJmv4dPwdRrZe7RZmAVnkfiOhLZA2JGfWWPriH5T48KskLgwfb+wrmp9uuMKl3mFfl6hGVe4jyu0eX/rCt13V6jnFUZcobhfoZtX6G9XaOcV6mGFyzqvcGsrtN9doZlWKC2uUL5Z4eXCcD3TMuy4jDAtQ7q2DPOtZWSnHJvDzuupDju/ozlsszW3mkngbrNlFnd7yP5M8ZrgQ5mDr3QW/A5O71HTRE7v4RY8CNFZ/C4rt3k+2SJrfMiKWy+yfNtFGCKGCbiEtS1BrhTpaKiAQwUcKuBQPeQtFmc1RejI6SyiK06XhV5W7XfN6fYJkamM79pU80xYeFyN6PxVQmWqTUK0U7rtoNAwp8TpZcezRRe64/SyswIC6B44vUhUWEqpiF4kmpW70Bl/05qVkothfZSo+LQhXbZ1QyBe9dHpbX0Jx1oM7kniiUrNimgs2HNY36I5nZKhniRtEudkhqwL6CAjWZIAl+1EPrL8H7GlAEKamgLIYt41B1iKrYpms9y4r2y6/DowQIz3U/SMDiQaWLDZEzqqnUw8oImHz2fQ3vRDOVNdQXUuPyyE4WdZe5zi3b7jFI7veZlqbjmLLcsr5vRneQkzrgW2ozHYkpFVBjJkJZv2wAgOJOgy3almAYWfaYhDyygXoFUwIGiVcke/x7RBuZ3TSXuUS5xO2qbcxumoPTm1PFrKmRPjdhNSUSWQbpEOKaezWcEeS97zlRLOgNqmWMZJsuM5laCcqhHkE5OrllSlJ2ZZJbla2m9Nspwt6qJ5SGmxX6ce/CNKW70Jic7qeShdhzIh4lALhUQ/hUI5x3gFoU/g4HYOfRYHD21wI+MQb9/lC5ryBRZfnTXzChxuxlWecKHyRaZVOfKYLHjWdQDdNsXMDFUx6wbCvVbHFEqtY5wV/V4bbwFFP/p4LFh2i7I1NDQGirJmo4loHpW7rdpW+8EEu63q5jRr5VRHBTVOOf7LXDaphyc1jq1uil2Lf8otNI/EPddLHTWUS6ygknNBpZgoZQL1znNxc+2A6ZknP+r0oIsvswEVHJTUHLOSilmxJNfapPxVCeMTam0uxW5LmKFS0XPaa+bUedTrXwkzszIfgEyyDIBuke4qIpL3r9AXVXWg0AF1KA8yV5lc5AwaGchn7tJyBoUM5DyTdZxBIgN50eRknxtADOhFFfOi9SFQP2+K+rnyR+q3NfXbTtXvndqpW7Vzcx2fVSFP4krgJlHN6u2XBe5uBf62tPtVNqVmOGaU/H50OsvG0mE5nQS+HIrTSc7JbpzOxLtyes+s0moLvJL34yEXklNqckoDvCJm+XSB7ccsMDcLTMwCk2+Al5/yOFoOI2YE5CPQxM6giZ5BE8BAECxRCJaEAQNp6MmAmmxzhOcwykukb4Q962Raiz4uZzoZPerkrgedFLNOvsMfXqpzc1udDwhL0Ykh7BLCovf0UdjN9pfGtRLwoA0BD8F+ea33SIS9zizOsBYPFelyksdojdm1UeJqgnaeoJ8nuLwgCl+ZV3YUZLCBo+rMgQSeJngqe4FOaYUPgtN78W4spxNosBzDOAQaeIMof5YoK0mXPXV6dWjHQWlLCRdZmVi24oPh4xNSXXWu8bPCwYfI31v4hYD5eE6nUtibgZ9KbS8GOpXmHhGJSqcSvBopzMfVvBAWAjKo0bbd4856UZxOobPmfkQnpyzVvvEb3YtTrF3dEOat43SMwdliS/GSUz3zCOTD9+bD99OC5QQMvvRix5t6peUNZ/XKfnxWryRbhrRn9UoMlCOaIUc8gfDUlcGJIRMEuZ/hhSaulAkud3jhpXXbs3omgVGf1jP7/lk9k9A/lAtWzyTU59T8BjA0vbWoh1loUM8USq1numpZx+uZZFr5UVhr6jk6kqbExKGRg1xQghhADAoZyHdRbVQZJDKQ86EaCCZeaiBYFK+BNKuBUnNpJQlVEUr5/EeGcTTDOFgS+qXA38L5u1rfzLX+PmUAxcryrLaLoGN2OsNY45eDzv0JxP0ZyzJEH4Kh80xZ9AnRdTqLGiEmTu9VL6WpQGdRyXA6aUJQntNJAYIa+DFqZPnaNMs3CoRqxO8LWH4uYCg77H4l4M3+FwJenr91iPar7Fvd0DxTfmgfVKfzswQKw0A/ETDQmYAHfnYyP9D7mYRwnN4F7Iotj1hclChgN5Qnai5PXtwyrzkIm2DYL2K+25z+mualD/UhBGf2+awS9cARBOfiFQT3tVDmIOWxZ/WEIyhOhEHZvh3CHMSX09rgkB9Ccobw2g1Tvgqh7Z1eYTezI+yG6V25qHCdCQTXSQStq84BE8u3GKq9NwwOGCjvcubgDAYZKAFzGF3LxUunhm5TBpDOhDFAmQFrjhigCjBTjjNK/S1JwxVquL4qwNVtAf4C1LnbAlzzAjwhLBPnhoet3Ujtd59bJGrpXvseSruDGexrl/6q/nUrHdUuV87R3TpHc+sc7bvoFxtYdqrj/rP6V0o4Ths8wNEQx0S9BfZ4AT4HEH44SeJo5jafomPfwirI8NMVBq+fL6dRDKLE/LJIi9U4VXiNDgZYdqsa4C4XvDfUcFLEZrWwHa1wiXBnk8MdOpbNz7jhDh3k7nhomjCnqAe/VDTVGRNASZltpXdAE6u1SicvsWM3VqWzoixyOvkEqnRhI7rJJ7vwedLB64G5DCysorzQNpUw6UqYdGUbBN9hWctUaplXqfryCuQj5iqGGqOiRs8xdkaNboC1N6XZdq+7maB5abZq1sw0RNEfFgCJXCCKF2Na8PiSIHd9eVDku2GikhaASs0RrxloVhsyUP/1I1GcbRlaz0PvODQVoWYbgv9XhxZu3gl0BSuFTpcukgGzT06snH0wXyCWqXgmX+A3HPy4TAL0bUOPOS1oVzO/VeFurb8liGwNzUzKyhoAgwdzaSEcxPDejGpBptBbx2IRZ7sw/PyaWisrZ0DOgJzdjMH6GmfpeAXOdmF4I2zCc+nCwNohUytO6yug7BYOy246uBF4spOXy7xFx5SAzrwdDaq4r01O8QEVDkjus2NLwg7uTalOb/ut2n5r5bgHggHbGU94Kb+oL8PelF+tlvqkvm4V2219DVniafnVg+51+eU/r6/th/V1Rx3jWF8zOq+vN8HpJ+UXJrJzfY0Z8FxfA/2kvgZ6L7+SMTOwGC0K+LhEFgdpfXZQcgIxGnsBMVptP4QYjZu7FhrEaDcCXpx7gRiHw+XzAo1Diy84psWXOErL1o/rMX0OKS4XkKLV5lNIET1uHnOAFBE2bGeWwNA8sUFPbGzzbYZ8m9H93gApqj7eOZJo8BQbTzerWi9p5QwKGXqzxIrOzbhzANFYBBCXsT5bBgDR9yaK48UAXDMAqb4Krf9eT1DS4soA1PahAWh5aQDyjQF81BuUtL40AHFvAPft0+eWoNWVJaj4oSUoPLzSarAEjRqtW59lYWiWoFH1srSqJWj86CGpvd/jlqBSH+/cErRslqD1uSXo9gFLZeiW4OmV8twSyjTBErQaLcFzS9AaLcEmCf0cqvdzxAUtQfOGDiou1qFCkHs8rRAsCP+soV9fJfM3mbYF7TlroNfhWyP+0kfDqspki3Rz1gSNy0kiffiIxuKHN4WfA0VbOwspdEgiy4MsiST5wIuKfAoDk4/Fj2uADjPZYz3qMC+5mMdQvXwKhTeX9QYKb6nXPudzx+DU8rTs5VmH+QYU7m6hcHPbkqPHsw46Wxi/X1tjpw9QuOb0s7MOew6FK3sOhSt7DoUDnZ91iCzcPRtgL/dXFLC/bOgbwL53gKG+7dhxZx07ozrdtMo0pXn/xVH0+rJDZlf/l+OTe50ZOmQ8QM3n5zvxzQTvmkXMJ5+f5GoBvynUQ5vAGrCN3kquuR57Vguda3o/lBliBTvEkcN57aE5vX8oEgKnk2WEuPB5Epbote101gzHDoMk7xHpVYoeWhB7VaOHvoteBemh76JbquZtF//GNRQXmoWXvehBNkat3+udjbnnab6Etvb2POoVgu8B9D0UP6B17/C8+B7Pm6P0xXeE8C3LfxZF7g9USxTBVPiHcmv9FlGGSw+xflLhX+JgH50YrGG/SGHsd79JNPMJMuJ5Jn3hBPnlkOSlk1V/AGEMKz0uUiv7zW8T1xguvgW03/0WEOqlc/iHepLW7T9MOe5P38fPH+Nx8d2g/e53g64d15ShISvMlgKuFNsIteCudF03Tmftfwun93ZBrIi8/h/5qEFw###4680:XlxV32DM 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RwkWXyHeQHyF+ArxFeJ3SDUgDiFYaV6Hwzr4QhY3+gzRRSRFQe93A7+lbpsrpNL3QuAOpPTa1xFuQJQUs12IPifteGoXhDM23c9GPijrZvWoxOqdqJ3gSGeCd77aMGfrKoVTDnnhRHbAuaETFb0NbTiu2LUTnbMWp8Uk+Thy1kzSA+w8JO1BzAoKlc6nm4HmcPqssEeFPTTsoWGPDfaosAfFZZT7vr4OclF/jOI5HMdq/R1ih7Qd0gwecyAKxFaI3SGWQj7Kjasom/AYpeTAv3TyXSy/o+tCZJIQ8jPcXtzduPk/7E8088do14/RkB+j5abbsvaEUxu3zgHTKIiF2jt1xgjCgvBChFNmK/7j6P6ckUHuiHi6xqywg9JYTm/Wj9GjM2XArXfrB7r1Tnkznhhc0ngijXlxPGvD4JdlUYBOO2aZfcgH1gIRVBWsHvJkb+aZcJ2IMG3Ewnh3MMJ74UCff6DPP0afT5DDmD1BVAx5zHZYJp0KZEkGhBiTGv2+AF2wAFl2hJCYPJBhvALT9sNAXx0sBa+cLg3DDgf4Qe11mGzwMA6mDdDaTDcGPTBxTz9SHP0k0RfpNRAsO7ghPMFcecgeoamnxBHmUR6t8H5E2MSUQYi6rRz8D7goYYs=###6860:XlxV32DM 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MlSGJwHlgn2NitQVPdq7vkF0D6LDYyf9ilgUZQSUkT0Y6cHIDPI9yG9ONcirM0pbrtZQsEokcdKQIXGJ03+Cfgo0guoMqpqrpJ1t2o/g/SCnOv0GwjgpcDK9PUX7ve7Ns/037D69Lcg5mUE/B5rByQhOlsbsp0uhPD1b8PTtzgyevv8R2B5REuPuIfaqgAmbVdkc6hjqX89PtMO+/AT9HjRuXo2yUD8R6idCff16deKH7vGqxRYE856CZ95brLQYGQ4qwXDdSTI3/1ru0mgjVCxwTwTuKb5qe3zVFl+1iDU+dSiE7SlOPmJ09SAFRdatlcMoWi3dHURArmvZtu9s+xJL8LpHoT2z3O7hFdgGnYTl2/LA205pByxC5fwQIe+A6I5ZBL0VsIhjI6DVqE8vmCQklAzQHYEe7aXmvC2P3zSRtd1KHoI/NawjZSxrI0xSZC9sHoCkbYsy0+bWpqohfs681DKqxDNGtQfV4VRN/1NYjNJaoaAbVJ2TTu/x5k0C5p0qKppQUXMipYehJlIYo/8E2fEPWzY8aaZCRu3DUNTArFrztF/TKNCd/7jHqmi2NQ+X7vHP8rRbGwnnMF83vTvT2RzB5gw2V7A5g80SzH0MR0Zv+eVD5itElINCObtQznY+F5ZRw+lU+Ax1nKpq939ULbzIcepTDxXNLK/INaqF9OX3s/LF2SN8ykbxwILep2Csc/w6A43CLweeDSwC2jtSihmBvqnE3u274mSfIJsCDc5wo9TgpVDyAeMkgu2MD7JdpXRqUo/gZAQnylN27qTvEebsKnQL7mbwlAPpsXKJ6+zNYKoGUw9M7TA1g6kv41rBVNQgaca04C57vG3Ajn/+HLBEYr5q0QNuyQ8YoZ/+W3fwLedGzysQyysQlq3eHsX5f2eaplwkS9dvkcFUpKXI487HovonCrLywf0lP4N8D/IjyOPCxQWYLx/Bxw75O9z7RiXkhxE7yrb9xi96g3HhvB5PNOwnPX+VKrzxNoO3+LoUOPoKMTMYSYFGfHH4vrBuIs2Ufwjd4Zgfm7D3xRvZ/zVUn+HsrWBvBHsT9ji4/AR7TzCVA03Y0w1IlECdvcn3rwI0DzrTT4qjvWGHJwGaLB2XJkvXT7J0XHRFkTXphWOj48iasugpU3D4BmjWpN1ZezzaPW272/jJo4SI9arQn3RYslV/8qhvEgmVciKFp6/3KS9abZbXpA6aoHSk+X2xdb0szZ7mT4olRKwVgfYT5UTQl2J9k8i1lBOp21m/gRTwjkaTBX0kmY4QBRfttNrUIJyMvv1kX0LErsBvB8qJoC+xyqRoWmZ8sh+hlEy/zgUNcO9Kc2bxa3nVP27+DWTnZI70k04JAwpETzQxUyIy9CVmwq7NJkOzi+lafy6mM79jZm49M/e5BlyXtOTn7y//X0U7TyrFu0d/xjisXmK3nIni4eaThF277ox7TxWuXixpXPozbZA9/Iu8v5qql5NWUEzaDzp+mvQ0wqyEmsf12xm50xK4876IUrUx+F27jmprW6vq0I5kz4RtiP8rRYKj0o976N932ScJ4/ZMblhEBO3stb3ICFUAIabu3KHxnGwddeiJH7QL68xBDe6pM2ByYZ05w8E9dQZMLqwzxzu4p64ADnyrnPzDhXXUgXe4rlxYLy6sq7Y9+Jbaa6c98z7sg3vm1y/YUT6FVqlM+1Dev5sya2PK1BTuqJh4U7oDfti1nxOyU+n8tqGTrGEyXTy7vHkvFfoK1Ve8B2CtfrQ0a/Xn8BYx6/Cj1U/Lh4L0mO21zKQCaAB1snpVL8dsPYuZ5sVJ82KmeXHQs1gBONKt4lEfehYzYNK8KCP/D6Imiv0=###7060:XlxV32DM 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1Uerrd7/g7qjwfKg1wkPy4NIncQvWU+UeLLm9+4lMwsR/LlEdtQdaegf581Hvny2EjeN84FxngOvZUBf89KhAHVHw17dJkhb4OrttaumSmLyd7jJ3+EmXgv0LWx0dCjHUcWXr+IL+jSe3s/16UucN/FRll2YjNavUru94D2ANH6wL4Ca6q+4arevpFI4Mf8CAcAerAw8GbVPET3jNvwNUrEPgHKsfYDoH2Bz4aZkiijIQpyDJ5AKtiXyYoVkpbKSPZgcC849HCYNVMV8DWxW/mREQvtpX4W6PLrhtGRYWMPLfAnWCQ5rgEkpceuuTAe/fS89377CgKNp3/z0aV1xJ5+3vvMOAxubd359tj/9Nc8e4dtXGCLpvJE+fXY4+0PY1FBStja15JrccJiHkWL/Zzdvyzi279Tfw7HhD8c8j/t7pWX7c0c8v40zuwlkMBNLgS/GPc+swrjqyxV9ucvrMJ7tD6CvEWwS2aqI/FUE+y5TUqVZwP/P/VFSQcLRHwubQrKj7mhSScuUdH+nDirk9zQsO+qOpikpU0mbj4AVaZLWlDQopyvJuKbnoySoP+EdORT3c0aLRExJ11cRBX2qpFtPj8JaamYeyBNCh1mjqRl/5FvPsVcar9BtI22U9ZmFemgUO3TUDzwGLHw5N3+3aJtB+nnoRXpkyj9qDQYpf8zofNUdWZcxZH8V3MxrT9wH3iaUXk2ORDki5VAzlImWbp8oOWsTOAkyTjcqjflB0kiBtijH7BwfcszkSNYW9J7nt8pjKR4LTHTLdD+4uh9cna7RpBiUIlKKQSmKSzEoRaEUBBbBnAd5yjzhjVSbFvrIMPX/9Wa960aaTzOWatf3NVD7vZC8MtBYBrUCccMgrZXeHJQJJJ/zdPwJ8Og3uFkeCwRis8+VMEgdsA/KBPqw5ga7saoNsmJnIBBKoyUOit9BmUAfNT9I0cpzbh1k7xYCgb4VoeDWlNnX6e5FBWtAT/aoQp4tDehJ3hhhEAXXWE/YLTqVNagneSRklXh9yFL5PMDewcOd7vRwZw0aQub1KsOmLOGnacbCZwXJfqHBIO3L4UvzMGO4/kMSNRN0Z/cozf2huQtHGc38o6lGabnLzOTrBpDl7X1gpaecH0kLMHLGDXGn59sn1/QkCRC9Y+frw06OCst+ZqZ/CWSXGzvZmqeGD0lNwWT+YieZGpDcLHjw+r5xubJ8biboSjKS5Kaib1fK/JI8TN8u5pgzwE9KvdXV9CG58QibUp4fSej5fNKDIH5I/KAyfmr+0YSiD2hK06dPbkv6TkXnlfThZ4qmXzR+k7n0DAB+5UNTNY2krtDEC65TFjWd/ofmYco9A4Am9onNa+gDzf6leZhW969XmJbPACB5fUhuDjKSPKRNG4UkNzP9GeD39XTHlvkjaZpOj5NcH5LpMNX/+3qbVYdMoEZW1ofm1dgnRnYdbIVrIYnVAlZuQCo9EnbpX161MdmfYLcX35nZaO0L4UvysG8DaNpdSRaSjEqyfEhul2QpyWy5/WuhQC19JlNAovs6eL18HbzrN9paAKaP1PnR5+s/eat8+6SgtTrst2lilXwTVmDFCRb+jO8hX1VTdzVdH9pX4/yptAfV1Kn5Qc2Pr+YrSQYl2UiyU/PDNX++JA8JSAklIjWqYDtJ03z/kFTNR3rmppfi6x+UUrjexfVitC08wmcabdP8/aNtmo+Xa75/+2S9+pOoal7/QiPftMl3km8AJf0WAuRbGN+qfJ8PbdV8pK9uEb/4CTvVvNEepC0Fqgg/1fDWELS1CsZHdza/cZCu6cCT2FIKP0EE7UTFmbgRd6aW0o+kPaw69CTXGT9xddubuJmARihRmi0gkbYuN+UPbVGFTdM86sUDoeI+IC3mPy5mXRveqtTKUvWml7JpjaNFO6fVL0n1pUydN0QoRvJh6GAk14ek+tJWkUIRz+kk3ZeaC22sc7EiYZGDpsP8vK64rto0TRTU+e3r/F1R3Xq7P+z426HF8I3etVUGTY+zix+S9s9hdaVgs9vfkYUk5fjrlmj7/0qdxL0=###6932:XlxV32DM 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DBlltGhnU8N6QW/2KQz29t7sM13tsIONtau/dbBXd7UbD2sWU0msa0x9tsuUWA4QMsq90k/1ym91UmLmNr9vXDwd8e4RWqDtLEIb54dYvY/VRcNULjI0dZHeNSZeUomPzelY3dQr3Lb/23kkHtZT3MDlaDdx401syGedpmeyb9JdLM8oP1lpHauBQH24fE/COmf+NZAjcvTyBa1H7HQXQM+jEln4FBl/fcCB08CG/XT5tq4U4LTbgz16+bI2LOA0omJvn+GmBESFvVoJEad+EiVy4q2VE0O5hHtRvmBcxLsqM+JQYDFQ35ImA8Zkzw1EowGAunh36cs5rWJUZDHKfFbzB4RyTl1F5JqWH/P5rCiZ93KdvQ0BFbSP7kbUPHFmrKBkTPQJu5nEVQnalawLEAtUqNkbF+stcP2XS32W4+tLqF3c8vgXQIUyLsHscv/i0pczJKS929Yr0JYo1hfAFMBntUKN8rJpYMOradSXRjf5zVXml9hwaCgxPxcUEh0oKoMzMM405xoAWTL79qTiryBh8guqU1NDx2kAio0NyZjpG4kKh/HNOzSEWTINyvRSprBkuinJS0kGJXkpyUtJBiV5lySekkhrxrD2Voj0UiQLb7XKYku2uhuip4nFScuSfRAeULDxYAdJsyXzR2sKlgyNhLjVrtWPMZeUnWfk2JeTjC0K1f62LV5YF+i1xCtrX+q3+8Wl5zouPWl5tkP9WusXmqonu6GrEs2T6ALRIKDPkekvBu10pRajWQjeV9De6w7SEMrV9fZpK95veXlrN35dWS/Gynk2YDGxW1lCFVSF00tbphe2NGs5ng3dGKmwkHqF5b80kLkQ0pyOx8IcPHqxNg9ry8alPr+4LC/4rkYfC8NC5jvMwwbKBU4wXGd128aG65ceKp9/8SONG2vz9ostYc0f/hVvvau7X2g78g73wRd5N75wKn6L0MgbQYJjhbkzPWbW12fpg3smdKaRdC3tFxwNsbRVwaPLWncloJ4ISRuxQXFBLzvlxekrpId1TrhcIL+1BPTFeIA+DyqQdJ/hqVQbbgQroWq1sDJfMxFjW+VUi4Rs26vNDiAKpobj4wQ/iKEEqnVDttdZwbNYr6QZo7LVscT3GGflzVo5301ZniVnO3CqQ30oS13PLzxerKppsjx73MbpfM6l9YtIcly35BjlxcR3Lp4B0upZj7e05n2A1V9I+FuSAIyn+CdW0Da4bzKL8wMd4erMWxeb+Rbd6wjYwgoAv2/K2JisN4IF5qH/GqBHLPAiGzgRNiCo90L62XCTuLlcsz6MPN+QwmtPrk/DwT+yAtsR4OfXjF6fl/RNFnpOhrL2lhxhfePdPOmGJXvMxHZj8mKsrNV15LssShFusi6a27l+RbycDA/IEX6lsCzsRxpMs0Fz53buldvRTTzRIKn1WvmXS2vXCnQA1lgjZS6tegrqIXG3P8D+91/jr5ElwBNa6Vpxbe6TaX2hnaevdZwGq09r8oO/W7beN87y0TEt3HPg9GSmiKRJ6zdxyB3X5hcuHjidz1+LZ+Lpw9paxVjrwz1vL6G7zwrFxZ7tCa/CgIfL3M2To6DRKAT0Dt2eTZQscIS52yoNuNmMdEd88Y2oQuKKLVvuQOHwADDf0hQ3Nk7n19qmbslOA9snqZe+zEoV/qBk4zwLBTKu8C8/LQD5yh9OXsXVQ5aXrlZ3eWtrsce5MNasDDmf4Xcxy569vY+jsZhZNwvwAzeC/aogV500P8Dx+MljpbFd40vD2s9We5Yt0lzhwKKzK5GVUfkkoUfJCRqVVaZQnFgp37BS5V8KhkOrNDoSb/76Z95jrmPclh/RZybzjflFP5EEcaZdZT+9XRbDVh2XRWvnpaa41QzDNm27uIizi6vRmgkdDrXygk3s4dJCtOyyxJr4/wFPCQC9###4964:XlxV32DM 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be0eNqtW82WpSgMfiUhiWDPc8wDVHm9y97Nqk6/+6gIBkgEvX160VUWhPCRfwLQMCDgjEQeZ3qTB6IJLAz59/WnNzqc1m8TLuvvFgysc8mv/94IYNn4104HVzoGXP5dpGN3OtvPo0KFmlTsttJOBT+gMiVOoMLFduMyMlw+oWMTnRyZk44pv4t0BkYHH9M5T9uo3LgmFQCzjpl3KvCYF9zlbf4QGUhUjIoLdlDxiRf7AZWcl+07Fvq40HqaSPvPij4W88wm0bjgAnjMCzQCvXIsZXTfRIT7iYb5+5w/f36Te02/hl/jz2+0469V7/75Dy39sv/8ixbX3+lnYxe+GHkbyRMcWwBxC+MuHMI8dawgpkDKIVBbxMNauxGpj3JVpP0obJOOZSYAVX7aAuqY4pqKit+58R2iFXdlyGf4nhS2I7bruciYQiFaif94nuuoRTlTJ8+sBM0navbKMETDSkbdd6LH1uVnt6z73PZqRX6DQTlnTvu8bTVi8wKNQO8c67KxeIyleuyqMBbN4ZwgzYqKahOF61nmUE/O11LOaqGu7CXIxsjMjklyYgs9DWNp53o+xx6naQSMqNrtrI4t8WR7DOboazVHFMwRzENmjgz6n3XrJjNH0w6HF+AAdlymECCTZkVBMJvIiozH0S6NCKMdOYH2lMaGv5Nq2rCKbKbOKCvMfe0GyShUfJMKHvGREYxaULEnMUDvyYj8aDsJZlPd0Um1NBJhB4cgr99B8bcgnqIuVXP0u0Fov5nQOtMrtJKLHlUdjhsaSytxiKGVxfD4u2YhqfQ5Nw/fpXDJfCDOPokzKVR6koYxJQ0kYKGhrXkNhYvgsRqiOGqiuBqFq5gJCg/LTM9+5ofVPKhYUeGupCqztPMqtMshtF8+E1rE98/GTBX44WG0T8cgbQIrh4WHE7kWRRRzvT2Tu3n4dcCBYDrEGZItqwVxO4o8B1Ts6r7SK+ZZD3mxLGNEIWDs3hPL9FChYjuCaZeC6edUgmTMF1lnz44oUdFxGTp4GRIvcqYHfwUX6MJF5uWe3AUqr0SFmZFEoaW5gzAvOpkzZKuipCqYhSM/dZmbqoPZU79Fk8Vcm2IXnpjjTjRQSGCBudwuFAVkTLHyUseRPXiKsWovjySkcpit8Wxv06O9+SKB6JMwzJ2iki5pMtxOyA48jmRaCbW6drMIAZrsFfVT7fG88qm2PS88mnVPl9vJeTe3G78hhHmxuJu+8rh7HLe422YhjEuCI7CY0r+6DrAvmZI/LXwx8jx1rAQJVKYu8fzA1F3utzPyPWl8EoL5iormCqeUUWhYQAcvkHipKyGn6bAXkfiknCaxCD5markCjafEMEEmMWZvSORpcILAL6vAYxT470zgv+cfGDulfdvbuJqt5UirpTn875JzHB5LCqZARUr6e6mksoAQHuQ6gw2dmTpPZBKR8PFs3uvZwHE2yys7Gz/8rLv+uuZy/UrkG7yaIkTTuQ1XRaDW4nKbptkj+kAHKekgHhgtA6/uQW6wydSFEtp9AvXXkAr1kubnYwXGxVtU7LhysCzXAoVK+6JgYFSMCD92FFVCKeGlXDekHcUriUYBXkK1LCeLO+k+S73AHO+t2jU8p84NUaJhEdYt3o5o0UQxNqsYT0GMCXJVt/57uzPL4w5Mmh7rP3qwF8ZSEeyRyjZktXrtOlG+Ru9LKzGllc+pYBJHEPw6/hXP0UuF1fEUZYcOZcdU+JbKPL1UNGW/R6VuU2jJnoZtKVuyZyFWg9QQjEWalmkpr7oZvw2Zpnv8NjTo2pSVxYDGaoo5611tEBCBJiIgNBtUXv4SBx09uLBVbc527Q+m0/IIoLgqISdHABpjEwuRNchiCD5cZMxX4gtN8fXdQHomGLYhGFruazv43f+vwklxtDRKRrr/TNQeH42TZ/1B9xwQJQckVWp7DW3R2RNEGs7AH/2SifQXhKSsXs2fhr+Bfq2o0r3kwFJMU6WjniWu+k33NtJ1mwvXYaLlU3f3++UC0siRnjOknZdSLDz4LHF+NXE+Zt7AOe6MLk275uZ7MDEME4qYEMckj0WnVfpIlL4xSnH8/8JajFdjBAtQ5wqjaCng0hq6pi005S3PDSSLLsqA5MiQnPLk1M25dOWrzUeRYRbTeGFsF5IaKvI4OYh4gk4RkgZsHMcmd9tbwkOi5uGjzo1jppKJSS1LeMgYb3xbxM6fJFln10+jE+UOcsiQS/rpOXJ5Q5Nzms2ix8gpOexFAIfNMpBUh4in1Eq1TCrTJUQmjgjm/pJyf1kjcq8AriEyqvdF24yp6wYn9KGb4o5Ibn6jNJYaSMse03Tciys+84ujPeaa+5I01zGfeU/+nGKhgN3/1rhM7G5Ob0ukCu07utuDn6i936zgvtgMvWX8AV+VefBC2mQZGstbRlUuTbqRxMvWVY7VVXvshV4/1LX+qybNe/dJehEJPbRNQ7JNKQaYz/O2L8rO+7VGmHlHVGjsIqUVV1rRi/Vcd5dXsWGvp0zkWZmIdDoPG7Oj5bhucotXGG+c1t/zqzmX39MrjW7XuLNOk3Cm2y2xi92ZeaOb+aat5IBVySH2Wc43K2Zy/53NSs+SsrZXAyGwvlgtQTcIZoTYIQ0XCfuN1cS9sdUae9PcHrHw+jpYNrfOQrs+ePbULKD1Up4wUfdDqCEVOvAxFa2JsUT1k87eXlwg4cLKJcupjhbycol9vbfLk9zK1g8SgOXgg/DAg1gWPrCYDMRnJCVlqXY0qM8eKFUX5VVk7uXL93Ps9eW7/FSl5Ie99KrGVi/J1LGQ8q6esa57LGaPZAZmsOqaFDKDlleloPNpDH87V3JzvuFscx7GYjE2Pu8ZKs7D2PjgZWAR23CH85S9DfKTupS/9Vz/lc/WnteBW3gLD/2a8/nIdocqndJxqcGjEm329BuPySyjUNfpfY7YeknMrVGr5zjyA8K5+k4qPf3lfe4m610OJv7NI67CxLtBvh8PALmsu2oRuqswPc2JSRNofTmi1/I3O4ukSK2OKQb5lV96lTFW796ksfxhWkdr6z46voNc/gfmutdW###2932:XlxV32DM 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngc =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngc b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngc new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngc (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngd (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngr =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngr b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngr new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ngr (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pad =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pad b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pad new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pad (revision 224) @@ -0,0 +1,174 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Mon May 23 12:38:47 2016 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: chn5_mem_spi_joint_map.ncd +OUTPUT FILE: chn5_mem_spi_joint.pad +PART TYPE: xc6slx9 +SPEED GRADE: -3 +PACKAGE: tqg144 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +P1|addr<6>|IOB|IO_L83N_VREF_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P2|addr<7>|IOB|IO_L83P_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P3|||GND|||||||||||| +P4|||VCCO_3|||3|||||3.30|||| +P5|oe_ram_bar|IOB|IO_L52N_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P6|ub_bar|IOB|IO_L52P_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P7|lb_bar|IOB|IO_L51N_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P8|DATA_INOUT<15>|IOB|IO_L51P_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P9|DATA_INOUT<14>|IOB|IO_L50N_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P10|DATA_INOUT<13>|IOB|IO_L50P_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P11|DATA_INOUT<12>|IOB|IO_L49N_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P12|DATA_INOUT<11>|IOB|IO_L49P_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P13|||GND|||||||||||| +P14|DATA_INOUT<10>|IOB|IO_L44N_GCLK20_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P15|DATA_INOUT<9>|IOB|IO_L44P_GCLK21_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P16|DATA_INOUT<8>|IOB|IO_L43N_GCLK22_IRDY2_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P17|addr<18>|IOB|IO_L43P_GCLK23_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P18|||VCCO_3|||3|||||3.30|||| +P19|||VCCINT||||||||1.2|||| +P20|||VCCAUX||||||||2.5|||| +P21|addr<8>|IOB|IO_L42N_GCLK24_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P22|addr<9>|IOB|IO_L42P_GCLK25_TRDY2_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P23|addr<10>|IOB|IO_L41N_GCLK26_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P24|addr<11>|IOB|IO_L41P_GCLK27_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P25|||GND|||||||||||| +P26|addr<17>|IOB|IO_L37N_3|OUTPUT|LVCMOS33|3|12|SLOW||||LOCATED|NO|NONE| +P27||IOBM|IO_L37P_3|UNUSED||3||||||||| +P28|||VCCINT||||||||1.2|||| +P29||IOBS|IO_L36N_3|UNUSED||3||||||||| +P30||IOBM|IO_L36P_3|UNUSED||3||||||||| +P31|||VCCO_3|||3|||||3.30|||| +P32|DATA_INOUT<0>|IOB|IO_L2N_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P33|DATA_INOUT<1>|IOB|IO_L2P_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P34|DATA_INOUT<2>|IOB|IO_L1N_VREF_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P35|DATA_INOUT<3>|IOB|IO_L1P_3|BIDIR|LVCMOS33|3|12|SLOW||NONE||LOCATED|NO|NONE| +P36|||VCCAUX||||||||2.5|||| +P37|||PROGRAM_B_2|||||||||||| +P38|DATA_INOUT<4>|IOB|IO_L65N_CSO_B_2|BIDIR|LVCMOS33|2|12|SLOW||NONE||LOCATED|NO|NONE| +P39|DATA_INOUT<5>|IOB|IO_L65P_INIT_B_2|BIDIR|LVCMOS33|2|12|SLOW||NONE||LOCATED|NO|NONE| +P40|DATA_INOUT<6>|IOB|IO_L64N_D9_2|BIDIR|LVCMOS33|2|12|SLOW||NONE||LOCATED|NO|NONE| +P41|DATA_INOUT<7>|IOB|IO_L64P_D8_2|BIDIR|LVCMOS33|2|12|SLOW||NONE||LOCATED|NO|NONE| +P42|||VCCO_2|||2|||||3.30|||| +P43|we_bar|IOB|IO_L62N_D6_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P44|addr<16>|IOB|IO_L62P_D5_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P45|addr<15>|IOB|IO_L49N_D4_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P46|addr<14>|IOB|IO_L49P_D3_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P47|addr<13>|IOB|IO_L48N_RDWR_B_VREF_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P48|addr<12>|IOB|IO_L48P_D7_2|OUTPUT|LVCMOS33|2|12|SLOW||||LOCATED|NO|NONE| +P49|||GND|||||||||||| +P50||IOBS|IO_L31N_GCLK30_D15_2|UNUSED||2||||||||| +P51|clk_main|IOB|IO_L31P_GCLK31_D14_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P52|||VCCINT||||||||1.2|||| +P53|||VCCAUX||||||||2.5|||| +P54|||GND|||||||||||| +P55||IOBS|IO_L30N_GCLK0_USERCCLK_2|UNUSED||2||||||||| +P56||IOBM|IO_L30P_GCLK1_D13_2|UNUSED||2||||||||| +P57|clk_acq_ch5|IOB|IO_L14N_D12_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P58|chn_bits_acq_ch5<0>|IOB|IO_L14P_D11_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P59|chn_bits_acq_ch5<1>|IOB|IO_L13N_D10_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P60||IOBM|IO_L13P_M1_2|UNUSED||2||||||||| +P61|chn_bits_acq_ch5<2>|IOB|IO_L12N_D2_MISO3_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P62|chn_bits_acq_ch5<3>|IOB|IO_L12P_D1_MISO2_2|INPUT|LVCMOS33|2||||NONE||LOCATED|NO|NONE| +P63|||VCCO_2|||2|||||3.30|||| +P64||IOBS|IO_L3N_MOSI_CSI_B_MISO0_2|UNUSED||2||||||||| +P65||IOBM|IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED||2||||||||| +P66||IOBS|IO_L2N_CMPMOSI_2|UNUSED||2||||||||| +P67||IOBM|IO_L2P_CMPCLK_2|UNUSED||2||||||||| +P68|||GND|||||||||||| +P69||IOBS|IO_L1N_M0_CMPMISO_2|UNUSED||2||||||||| +P70||IOBM|IO_L1P_CCLK_2|UNUSED||2||||||||| +P71|||DONE_2|||||||||||| +P72|||CMPCS_B_2|||||||||||| +P73|||SUSPEND|||||||||||| +P74||IOBS|IO_L74N_DOUT_BUSY_1|UNUSED||1||||||||| +P75||IOBM|IO_L74P_AWAKE_1|UNUSED||1||||||||| +P76|||VCCO_1|||1|||||3.30|||| +P77|||GND|||||||||||| +P78|pps|IOB|IO_L47N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE| +P79||IOBM|IO_L47P_1|UNUSED||1||||||||| +P80|clk_to_acq|IOB|IO_L46N_1|OUTPUT|LVCMOS33|1|12|SLOW||||LOCATED|YES|NONE| +P81||IOBM|IO_L46P_1|UNUSED||1||||||||| +P82|lock|IOB|IO_L45N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE| +P83|sda_rpi|IOB|IO_L45P_1|BIDIR|I2C|1||||NONE||LOCATED|NO|NONE| +P84||IOBS|IO_L43N_GCLK4_1|UNUSED||1||||||||| +P85|scl_rpi|IOB|IO_L43P_GCLK5_1|BIDIR|I2C|1||||NONE||LOCATED|NO|NONE| +P86|||VCCO_1|||1|||||3.30|||| +P87||IOBS|IO_L42N_GCLK6_TRDY1_1|UNUSED||1||||||||| +P88||IOBM|IO_L42P_GCLK7_1|UNUSED||1||||||||| +P89|||VCCINT||||||||1.2|||| +P90|||VCCAUX||||||||2.5|||| +P91|||GND|||||||||||| +P92||IOBS|IO_L41N_GCLK8_1|UNUSED||1||||||||| +P93||IOBM|IO_L41P_GCLK9_IRDY1_1|UNUSED||1||||||||| +P94||IOBS|IO_L40N_GCLK10_1|UNUSED||1||||||||| +P95|SCK|IOB|IO_L40P_GCLK11_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE| +P96|||GND|||||||||||| +P97|CS|IOB|IO_L34N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE| +P98|MISO|IOB|IO_L34P_1|OUTPUT|LVCMOS33|1|12|SLOW||||LOCATED|NO|NONE| +P99|MOSI|IOB|IO_L33N_1|INPUT|LVCMOS33|1||||NONE||LOCATED|NO|NONE| +P100||IOBM|IO_L33P_1|UNUSED||1||||||||| +P101||IOBS|IO_L32N_1|UNUSED||1||||||||| +P102||IOBM|IO_L32P_1|UNUSED||1||||||||| +P103|||VCCO_1|||1|||||3.30|||| +P104||IOBS|IO_L1N_VREF_1|UNUSED||1||||||||| +P105||IOBM|IO_L1P_1|UNUSED||1||||||||| +P106|||TDO|||||||||||| +P107|||TMS|||||||||||| +P108|||GND|||||||||||| +P109|||TCK|||||||||||| +P110|||TDI|||||||||||| +P111|clk_acq_ch1|IOB|IO_L66N_SCP0_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P112|chn_bits_acq_ch1<0>|IOB|IO_L66P_SCP1_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P113|||GND|||||||||||| +P114|chn_bits_acq_ch1<1>|IOB|IO_L65N_SCP2_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P115|chn_bits_acq_ch1<2>|IOB|IO_L65P_SCP3_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P116|chn_bits_acq_ch1<3>|IOB|IO_L64N_SCP4_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P117|clk_acq_ch2|IOB|IO_L64P_SCP5_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P118|chn_bits_acq_ch2<0>|IOB|IO_L63N_SCP6_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P119|chn_bits_acq_ch2<1>|IOB|IO_L63P_SCP7_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P120|chn_bits_acq_ch2<2>|IOB|IO_L62N_VREF_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P121|chn_bits_acq_ch2<3>|IOB|IO_L62P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P122|||VCCO_0|||0|||||3.30|||| +P123|clk_acq_ch3|IOB|IO_L37N_GCLK12_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P124|chn_bits_acq_ch3<0>|IOB|IO_L37P_GCLK13_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P125|||VCCO_0|||0|||||3.30|||| +P126|chn_bits_acq_ch3<1>|IOB|IO_L36N_GCLK14_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P127|chn_bits_acq_ch3<2>|IOB|IO_L36P_GCLK15_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P128|||VCCINT||||||||1.2|||| +P129|||VCCAUX||||||||2.5|||| +P130|||GND|||||||||||| +P131|chn_bits_acq_ch3<3>|IOB|IO_L35N_GCLK16_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P132|clk_acq_ch4|IOB|IO_L35P_GCLK17_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P133|chn_bits_acq_ch4<0>|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P134|chn_bits_acq_ch4<1>|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P135|||VCCO_0|||0|||||3.30|||| +P136|||GND|||||||||||| +P137|chn_bits_acq_ch4<2>|IOB|IO_L4N_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P138|chn_bits_acq_ch4<3>|IOB|IO_L4P_0|INPUT|LVCMOS33|0||||NONE||LOCATED|NO|NONE| +P139|addr<4>|IOB|IO_L3N_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| +P140|addr<3>|IOB|IO_L3P_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| +P141|addr<2>|IOB|IO_L2N_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| +P142|addr<1>|IOB|IO_L2P_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| +P143|addr<0>|IOB|IO_L1N_VREF_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| +P144|addr<5>|IOB|IO_L1P_HSWAPEN_0|OUTPUT|LVCMOS33|0|12|SLOW||||LOCATED|NO|NONE| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.par =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.par b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.par new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.par (revision 224) @@ -0,0 +1,491 @@ +Release 14.7 par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +LENOVO-PC:: Mon May 23 12:38:20 2016 + +par -w -intstyle ise -ol high -mt off chn5_mem_spi_joint_map.ncd +chn5_mem_spi_joint.ncd chn5_mem_spi_joint.pcf + + +Constraints file: chn5_mem_spi_joint.pcf. +Loading device for application Rf_Device from file '6slx9.nph' in environment C:\Xilinx\14.7\ISE_DS\ISE\. + "chn5_mem_spi_joint" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -3 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +Device speed data version: "PRODUCTION 1.23 2013-10-13". + + + +Device Utilization Summary: + +Slice Logic Utilization: + Number of Slice Registers: 564 out of 11,440 4% + Number used as Flip Flops: 564 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 739 out of 5,720 12% + Number used as logic: 731 out of 5,720 12% + Number using O6 output only: 536 + Number using O5 output only: 34 + Number using O5 and O6: 161 + Number used as ROM: 0 + Number used as Memory: 1 out of 1,440 1% + Number used as Dual Port RAM: 0 + Number used as Single Port RAM: 0 + Number used as Shift Register: 1 + Number using O6 output only: 1 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 7 + Number with same-slice register load: 4 + Number with same-slice carry load: 3 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 337 out of 1,430 23% + Number of MUXCYs used: 64 out of 2,860 2% + Number of LUT Flip Flop pairs used: 850 + Number with an unused Flip Flop: 375 out of 850 44% + Number with an unused LUT: 111 out of 850 13% + Number of fully used LUT-FF pairs: 364 out of 850 42% + Number of slice register sites lost + to control set restrictions: 0 out of 11,440 0% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 74 out of 102 72% + Number of LOCed IOBs: 74 out of 74 100% + IOB Flip Flops: 1 + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% + Number used as BUFIO2s: 2 + Number used as BUFIO2_2CLKs: 0 + Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6% + Number used as BUFIO2FBs: 2 + Number used as BUFIO2FB_2CLKs: 0 + Number of BUFG/BUFGMUXs: 4 out of 16 25% + Number used as BUFGs: 4 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 2 out of 4 50% + Number used as DCMs: 2 + Number used as DCM_CLKGENs: 0 + Number of ILOGIC2/ISERDES2s: 0 out of 200 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% + Number of OLOGIC2/OSERDES2s: 1 out of 200 1% + Number used as OLOGIC2s: 1 + Number used as OSERDES2s: 0 + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 16 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + + +Overall effort level (-ol): High +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 5 secs +Finished initial Timing Analysis. REAL time: 5 secs + +Starting Router + + +Phase 1 : 4331 unrouted; REAL time: 5 secs + +Phase 2 : 3891 unrouted; REAL time: 6 secs + +Phase 3 : 939 unrouted; REAL time: 8 secs + +Phase 4 : 943 unrouted; (Setup:1141, Hold:0, Component Switching Limit:0) REAL time: 9 secs + +Updating file: chn5_mem_spi_joint.ncd with current fully routed design. + +Phase 5 : 0 unrouted; (Setup:2120, Hold:0, Component Switching Limit:0) REAL time: 13 secs + +Phase 6 : 0 unrouted; (Setup:1359, Hold:0, Component Switching Limit:0) REAL time: 14 secs + +Updating file: chn5_mem_spi_joint.ncd with current fully routed design. + +Phase 7 : 0 unrouted; (Setup:190, Hold:0, Component Switching Limit:0) REAL time: 25 secs + +Phase 8 : 0 unrouted; (Setup:190, Hold:0, Component Switching Limit:0) REAL time: 25 secs + +Phase 9 : 0 unrouted; (Setup:190, Hold:0, Component Switching Limit:0) REAL time: 25 secs + +Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 25 secs +Total REAL time to Router completion: 25 secs +Total CPU time to Router completion: 26 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| clk_u_proc_BUFG | BUFGMUX_X2Y4| No | 226 | 0.118 | 1.186 | ++---------------------+--------------+------+------+------------+-------------+ +|clk_mang/c_16MHz_BUF | | | | | | +| G | BUFGMUX_X2Y2| No | 2 | 0.004 | 1.547 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) + +Number of Timing Constraints that were not applied: 2 + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- + TS_clk_u_proc = PERIOD TIMEGRP "clk_u_pro | SETUP | 0.363ns| 3.803ns| 0| 0 + c" TS_clk_main / 4 HIGH 50% | HOLD | 0.385ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_clk_main = PERIOD TIMEGRP "clk_main" 1 | MINLOWPULSE | 8.666ns| 8.000ns| 0| 0 + 6.667 ns HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 | MAXDELAY | 2.067ns| 14.600ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "MISO" OFFSET = OUT 10 ns AFTER COMP | MAXDELAY | 2.482ns| 7.518ns| 0| 0 + "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 | MAXDELAY | 2.610ns| 14.057ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 | MAXDELAY | 2.920ns| 13.747ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "scl_rpi" OFFSET = OUT 16.667 ns AFT | MAXDELAY | 2.923ns| 13.744ns| 0| 0 + ER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 | MAXDELAY | 3.137ns| 13.530ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 | MAXDELAY | 3.206ns| 13.461ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 | MAXDELAY | 3.211ns| 13.456ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 | MAXDELAY | 3.283ns| 13.384ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 | MAXDELAY | 3.310ns| 13.357ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 | MAXDELAY | 3.414ns| 13.253ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "sda_rpi" OFFSET = OUT 16.667 ns AFT | MAXDELAY | 3.515ns| 13.152ns| 0| 0 + ER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 | MAXDELAY | 3.847ns| 12.820ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 | MAXDELAY | 3.886ns| 12.781ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 | MAXDELAY | 4.040ns| 12.627ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 | MAXDELAY | 4.053ns| 12.614ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 | MAXDELAY | 4.178ns| 12.489ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_to_acq" OFFSET = OUT 40 ns AFTE | MAXDELAY | 4.349ns| 35.651ns| 0| 0 + R COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 | MAXDELAY | 4.359ns| 12.308ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 | MAXDELAY | 4.573ns| 12.094ns| 0| 0 + ns AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns | SETUP | 4.821ns| 7.179ns| 0| 0 + BEFORE COMP "clk_main" "RISING" | HOLD | 3.457ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "CS" OFFSET = IN 12 ns VALID 12 ns B | SETUP | 5.708ns| 6.292ns| 0| 0 + EFORE COMP "clk_main" "RISING" | HOLD | 2.894ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + COMP "ub_bar" OFFSET = OUT 16.667 ns AFTE | MAXDELAY | 8.046ns| 8.621ns| 0| 0 + R COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "oe_ram_bar" OFFSET = OUT 16.667 ns | MAXDELAY | 8.178ns| 8.489ns| 0| 0 + AFTER COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "we_bar" OFFSET = OUT 16.667 ns AFTE | MAXDELAY | 8.398ns| 8.269ns| 0| 0 + R COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "lb_bar" OFFSET = OUT 16.667 ns AFTE | MAXDELAY | 8.421ns| 8.246ns| 0| 0 + R COMP "clk_main" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<11>" OFFSET = IN 16.667 | SETUP | 8.976ns| 7.691ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 3.780ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<15>" OFFSET = IN 16.667 | SETUP | 9.164ns| 7.503ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 3.702ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<13>" OFFSET = IN 16.667 | SETUP | 9.466ns| 7.201ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 3.481ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<12>" OFFSET = IN 16.667 | SETUP | 9.471ns| 7.196ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 3.503ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<14>" OFFSET = IN 16.667 | SETUP | 9.535ns| 7.132ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 3.461ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "lock" OFFSET = IN 16.667 ns VALID 1 | SETUP | 10.582ns| 6.085ns| 0| 0 + 6.667 ns BEFORE COMP "clk_main" " | HOLD | 1.602ns| | 0| 0 + RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<9>" OFFSET = IN 16.667 n | SETUP | 10.593ns| 6.074ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.753ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<10>" OFFSET = IN 16.667 | SETUP | 10.685ns| 5.982ns| 0| 0 + ns VALID 16.667 ns BEFORE COMP "c | HOLD | 2.754ns| | 0| 0 + lk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<8>" OFFSET = IN 16.667 n | SETUP | 10.751ns| 5.916ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.696ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_acq_ch4" OFFSET = IN 16.667 ns | SETUP | 10.790ns| 5.877ns| 0| 0 + VALID 16.667 ns BEFORE COMP "clk_ | HOLD | 2.755ns| | 0| 0 + main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_acq_ch5" OFFSET = IN 16.667 ns | SETUP | 10.806ns| 5.861ns| 0| 0 + VALID 16.667 ns BEFORE COMP "clk_ | HOLD | 2.688ns| | 0| 0 + main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16 | SETUP | 11.158ns| 5.509ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 2.506ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16 | SETUP | 11.535ns| 5.132ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 2.294ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16 | SETUP | 11.582ns| 5.085ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 2.309ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_acq_ch2" OFFSET = IN 16.667 ns | SETUP | 11.646ns| 5.021ns| 0| 0 + VALID 16.667 ns BEFORE COMP "clk_ | HOLD | 2.226ns| | 0| 0 + main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<6>" OFFSET = IN 16.667 n | SETUP | 11.656ns| 5.011ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.222ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "scl_rpi" OFFSET = IN 16.667 ns VALI | SETUP | 11.713ns| 4.954ns| 0| 0 + D 16.667 ns BEFORE COMP "clk_main" | HOLD | 2.053ns| | 0| 0 + "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16 | SETUP | 11.713ns| 4.954ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 2.133ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<4>" OFFSET = IN 16.667 n | SETUP | 11.833ns| 4.834ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.135ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16 | SETUP | 11.860ns| 4.807ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 2.066ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<7>" OFFSET = IN 16.667 n | SETUP | 11.876ns| 4.791ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.009ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<1>" OFFSET = IN 16.667 n | SETUP | 11.877ns| 4.790ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.068ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<3>" OFFSET = IN 16.667 n | SETUP | 11.894ns| 4.773ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.073ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_acq_ch3" OFFSET = IN 16.667 ns | SETUP | 11.956ns| 4.711ns| 0| 0 + VALID 16.667 ns BEFORE COMP "clk_ | HOLD | 2.027ns| | 0| 0 + main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "pps" OFFSET = IN 16.667 ns VALID 16 | SETUP | 11.982ns| 4.685ns| 0| 0 + .667 ns BEFORE COMP "clk_main" "R | HOLD | 1.955ns| | 0| 0 + ISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<5>" OFFSET = IN 16.667 n | SETUP | 11.984ns| 4.683ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 2.004ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<2>" OFFSET = IN 16.667 n | SETUP | 12.022ns| 4.645ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 1.974ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16 | SETUP | 12.089ns| 4.578ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.907ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16 | SETUP | 12.090ns| 4.577ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.923ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16 | SETUP | 12.131ns| 4.536ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.894ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16 | SETUP | 12.162ns| 4.505ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.822ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16 | SETUP | 12.187ns| 4.480ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.888ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16 | SETUP | 12.202ns| 4.465ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.818ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16 | SETUP | 12.202ns| 4.465ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.843ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "DATA_INOUT<0>" OFFSET = IN 16.667 n | SETUP | 12.227ns| 4.440ns| 0| 0 + s VALID 16.667 ns BEFORE COMP "cl | HOLD | 1.842ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16 | SETUP | 12.281ns| 4.386ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.744ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16 | SETUP | 12.326ns| 4.341ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.731ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16 | SETUP | 12.429ns| 4.238ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.687ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16 | SETUP | 12.579ns| 4.088ns| 0| 0 + .667 ns VALID 16.667 ns BEFORE COMP | HOLD | 1.582ns| | 0| 0 + "clk_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "sda_rpi" OFFSET = IN 16.667 ns VALI | SETUP | 12.691ns| 3.976ns| 0| 0 + D 16.667 ns BEFORE COMP "clk_main" | HOLD | 1.530ns| | 0| 0 + "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "SCK" OFFSET = IN 25 ns VALID 25 ns | SETUP | 19.466ns| 5.534ns| 0| 0 + BEFORE COMP "clk_main" "RISING" | HOLD | 2.480ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk | MINPERIOD | 60.771ns| 1.730ns| 0| 0 + _mang_c_16MHz" TS_clk_main / 0.26 | | | | | + 6666667 HIGH 50% | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch2<2>" OFFSET = IN 80 | SETUP | 795.089ns| 4.911ns| 0| 0 + 0 ns VALID 800 ns BEFORE COMP "cl | HOLD | 2.089ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "clk_acq_ch1" OFFSET = IN 800 ns VAL | SETUP | 795.172ns| 4.828ns| 0| 0 + ID 800 ns BEFORE COMP "clk_main" | HOLD | 2.085ns| | 0| 0 + "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch2<1>" OFFSET = IN 80 | SETUP | 795.421ns| 4.579ns| 0| 0 + 0 ns VALID 800 ns BEFORE COMP "cl | HOLD | 1.962ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch2<0>" OFFSET = IN 80 | SETUP | 795.431ns| 4.569ns| 0| 0 + 0 ns VALID 800 ns BEFORE COMP "cl | HOLD | 1.984ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + COMP "chn_bits_acq_ch2<3>" OFFSET = IN 80 | SETUP | 795.535ns| 4.465ns| 0| 0 + 0 ns VALID 800 ns BEFORE COMP "cl | HOLD | 1.842ns| | 0| 0 + k_main" "RISING" | | | | | +---------------------------------------------------------------------------------------------------------- + + +Derived Constraint Report +Review Timing Report for more details on the following derived constraints. +To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf" +or "Run Timing Analysis" from Timing Analyzer (timingan). +Derived Constraints for TS_clk_main ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_clk_main | 16.667ns| 8.000ns| 15.212ns| 0| 0| 0| 5931| +| TS_clk_u_proc | 4.167ns| 3.803ns| N/A| 0| 0| 5931| 0| +| TS_clk_mang_c_16MHz | 62.501ns| 1.730ns| N/A| 0| 0| 0| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 26 secs +Total CPU time to PAR completion: 26 secs + +Peak Memory Usage: 345 MB + +Placer: Placement generated during map. +Routing: Completed - No errors found. +Timing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 0 +Number of info messages: 0 + +Writing design to file chn5_mem_spi_joint.ncd + + + +PAR done! Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pcf =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pcf b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pcf new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.pcf (revision 224) @@ -0,0 +1,771 @@ +//! ************************************************************************** +// Written by: Map P.20131013 on Mon May 23 12:38:16 2016 +//! ************************************************************************** + +SCHEMATIC START; +COMP "CS" LOCATE = SITE "P97" LEVEL 1; +COMP "SCK" LOCATE = SITE "P95" LEVEL 1; +COMP "pps" LOCATE = SITE "P78" LEVEL 1; +COMP "MISO" LOCATE = SITE "P98" LEVEL 1; +COMP "MOSI" LOCATE = SITE "P99" LEVEL 1; +COMP "lock" LOCATE = SITE "P82" LEVEL 1; +COMP "addr<0>" LOCATE = SITE "P143" LEVEL 1; +COMP "addr<1>" LOCATE = SITE "P142" LEVEL 1; +COMP "addr<2>" LOCATE = SITE "P141" LEVEL 1; +COMP "addr<3>" LOCATE = SITE "P140" LEVEL 1; +COMP "addr<4>" LOCATE = SITE "P139" LEVEL 1; +COMP "addr<5>" LOCATE = SITE "P144" LEVEL 1; +COMP "addr<6>" LOCATE = SITE "P1" LEVEL 1; +COMP "addr<7>" LOCATE = SITE "P2" LEVEL 1; +COMP "addr<8>" LOCATE = SITE "P21" LEVEL 1; +COMP "addr<9>" LOCATE = SITE "P22" LEVEL 1; +COMP "chn_bits_acq_ch1<0>" LOCATE = SITE "P112" LEVEL 1; +COMP "chn_bits_acq_ch1<1>" LOCATE = SITE "P114" LEVEL 1; +COMP "chn_bits_acq_ch1<2>" LOCATE = SITE "P115" LEVEL 1; +COMP "chn_bits_acq_ch1<3>" LOCATE = SITE "P116" LEVEL 1; +COMP "chn_bits_acq_ch2<0>" LOCATE = SITE "P118" LEVEL 1; +COMP "chn_bits_acq_ch2<1>" LOCATE = SITE "P119" LEVEL 1; +COMP "chn_bits_acq_ch2<2>" LOCATE = SITE "P120" LEVEL 1; +COMP "chn_bits_acq_ch2<3>" LOCATE = SITE "P121" LEVEL 1; +COMP "chn_bits_acq_ch3<0>" LOCATE = SITE "P124" LEVEL 1; +COMP "chn_bits_acq_ch3<1>" LOCATE = SITE "P126" LEVEL 1; +COMP "chn_bits_acq_ch3<2>" LOCATE = SITE "P127" LEVEL 1; +COMP "chn_bits_acq_ch3<3>" LOCATE = SITE "P131" LEVEL 1; +COMP "chn_bits_acq_ch4<0>" LOCATE = SITE "P133" LEVEL 1; +COMP "chn_bits_acq_ch4<1>" LOCATE = SITE "P134" LEVEL 1; +COMP "chn_bits_acq_ch4<2>" LOCATE = SITE "P137" LEVEL 1; +COMP "chn_bits_acq_ch4<3>" LOCATE = SITE "P138" LEVEL 1; +COMP "chn_bits_acq_ch5<0>" LOCATE = SITE "P58" LEVEL 1; +COMP "chn_bits_acq_ch5<1>" LOCATE = SITE "P59" LEVEL 1; +COMP "chn_bits_acq_ch5<2>" LOCATE = SITE "P61" LEVEL 1; +COMP "chn_bits_acq_ch5<3>" LOCATE = SITE "P62" LEVEL 1; +COMP "sda_rpi" LOCATE = SITE "P83" LEVEL 1; +COMP "scl_rpi" LOCATE = SITE "P85" LEVEL 1; +COMP "DATA_INOUT<0>" LOCATE = SITE "P32" LEVEL 1; +COMP "DATA_INOUT<1>" LOCATE = SITE "P33" LEVEL 1; +COMP "DATA_INOUT<2>" LOCATE = SITE "P34" LEVEL 1; +COMP "DATA_INOUT<3>" LOCATE = SITE "P35" LEVEL 1; +COMP "DATA_INOUT<4>" LOCATE = SITE "P38" LEVEL 1; +COMP "DATA_INOUT<5>" LOCATE = SITE "P39" LEVEL 1; +COMP "DATA_INOUT<6>" LOCATE = SITE "P40" LEVEL 1; +COMP "DATA_INOUT<7>" LOCATE = SITE "P41" LEVEL 1; +COMP "DATA_INOUT<8>" LOCATE = SITE "P16" LEVEL 1; +COMP "DATA_INOUT<9>" LOCATE = SITE "P15" LEVEL 1; +COMP "addr<10>" LOCATE = SITE "P23" LEVEL 1; +COMP "addr<11>" LOCATE = SITE "P24" LEVEL 1; +COMP "addr<12>" LOCATE = SITE "P48" LEVEL 1; +COMP "addr<13>" LOCATE = SITE "P47" LEVEL 1; +COMP "addr<14>" LOCATE = SITE "P46" LEVEL 1; +COMP "addr<15>" LOCATE = SITE "P45" LEVEL 1; +COMP "addr<16>" LOCATE = SITE "P44" LEVEL 1; +COMP "addr<17>" LOCATE = SITE "P26" LEVEL 1; +COMP "addr<18>" LOCATE = SITE "P17" LEVEL 1; +COMP "clk_to_acq" LOCATE = SITE "P80" LEVEL 1; +COMP "clk_main" LOCATE = SITE "P51" LEVEL 1; +COMP "lb_bar" LOCATE = SITE "P7" LEVEL 1; +COMP "ub_bar" LOCATE = SITE "P6" LEVEL 1; +COMP "we_bar" LOCATE = SITE "P43" LEVEL 1; +COMP "DATA_INOUT<10>" LOCATE = SITE "P14" LEVEL 1; +COMP "DATA_INOUT<11>" LOCATE = SITE "P12" LEVEL 1; +COMP "DATA_INOUT<12>" LOCATE = SITE "P11" LEVEL 1; +COMP "DATA_INOUT<13>" LOCATE = SITE "P10" LEVEL 1; +COMP "DATA_INOUT<14>" LOCATE = SITE "P9" LEVEL 1; +COMP "DATA_INOUT<15>" LOCATE = SITE "P8" LEVEL 1; +COMP "oe_ram_bar" LOCATE = SITE "P5" LEVEL 1; +COMP "clk_acq_ch1" LOCATE = SITE "P111" LEVEL 1; +COMP "clk_acq_ch2" LOCATE = SITE "P117" LEVEL 1; +COMP "clk_acq_ch3" LOCATE = SITE "P123" LEVEL 1; +COMP "clk_acq_ch4" LOCATE = SITE "P132" LEVEL 1; +COMP "clk_acq_ch5" LOCATE = SITE "P57" LEVEL 1; +TIMEGRP clk_u_proc = BEL "pps_rst" BEL "pps_r_0" BEL "pps_r_1" BEL + "reset_gen.cont_200MHz_0" BEL "reset_gen.cont_200MHz_1" BEL + "reset_gen.cont_200MHz_2" BEL "reset_gen.cont_200MHz_3" BEL + "reset_gen.cont_200MHz_4" BEL "reset_gen.cont_200MHz_5" BEL + "reset_gen.cont_200MHz_6" BEL "reset_gen.cont_200MHz_7" BEL + "reset_gen.cont_200MHz_8" BEL "reset_gen.cont_200MHz_9" BEL + "reset_gen.cont_200MHz_10" BEL "reset_gen.cont_200MHz_11" BEL + "reset_gen.cont_200MHz_12" BEL "reset_gen.cont_200MHz_13" BEL + "reset_gen.cont_200MHz_14" BEL "reset_gen.cont_200MHz_15" BEL + "interfaz_spi/cabecera_memoria/ptr_mem_0" BEL + "interfaz_spi/cabecera_memoria/ptr_mem_1" BEL + "interfaz_spi/cabecera_memoria/ptr_mem_2" BEL "i2c_comp/bit_counter_1" + BEL "i2c_comp/bit_counter_0" BEL "i2c_comp/flanco_SCL_1" BEL + "i2c_comp/flanco_SCL_0" BEL "i2c_comp/inc_count" BEL + "nb_mem_cont/nibble_pack_ch1/nibble_counter_2" BEL + "nb_mem_cont/nibble_pack_ch1/nibble_counter_1" BEL + "nb_mem_cont/nibble_pack_ch1/nibble_counter_0" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_23" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_22" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_21" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_20" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_19" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_18" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_17" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_16" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_9" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_8" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_7" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_6" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_5" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_4" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_3" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_2" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_1" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_0" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_23" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_22" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_21" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_20" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_19" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_18" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_17" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_16" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_15" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_14" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_13" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_12" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_11" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_10" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_9" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_8" BEL + "nb_mem_cont/nibble_pack_ch1/resul_mem_internal_7" BEL + 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"nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd20" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd23" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd39" BEL + "interfaz_spi/controlador_spi_esclavo/spi_cur_state_FSM_FFd1" BEL + "interfaz_spi/controlador_spi_esclavo/bit_counter_2" BEL + "interfaz_spi/controlador_spi_esclavo/bit_counter_1" BEL + "interfaz_spi/controlador_spi_esclavo/bit_counter_0" BEL + "interfaz_spi/controlador_spi_esclavo/spi_ready_aux" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_7" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_6" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_5" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_4" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_3" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_2" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_1" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_in_0" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_7" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_6" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_5" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_4" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_3" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_2" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_1" BEL + "interfaz_spi/controlador_spi_esclavo/buffer_out_0" BEL + "interfaz_spi/controlador_spi_esclavo/MOSIr_1" BEL + "interfaz_spi/controlador_spi_esclavo/MOSIr_0" BEL + "interfaz_spi/controlador_spi_principal/spi_contrl_cur_state_FSM_FFd1" + BEL + "interfaz_spi/controlador_spi_principal/spi_contrl_cur_state_FSM_FFd2" + BEL + "interfaz_spi/controlador_spi_principal/spi_contrl_cur_state_FSM_FFd3" + BEL + "interfaz_spi/controlador_spi_principal/spi_contrl_cur_state_FSM_FFd4" + BEL + "interfaz_spi/controlador_spi_principal/spi_contrl_cur_state_FSM_FFd5" + BEL "interfaz_spi/controlador_spi_principal/count_pac_11" BEL + "interfaz_spi/controlador_spi_principal/count_pac_10" BEL + "interfaz_spi/controlador_spi_principal/count_pac_9" BEL + "interfaz_spi/controlador_spi_principal/count_pac_8" BEL + "interfaz_spi/controlador_spi_principal/count_pac_7" BEL + "interfaz_spi/controlador_spi_principal/count_pac_6" BEL + "interfaz_spi/controlador_spi_principal/count_pac_5" BEL + "interfaz_spi/controlador_spi_principal/count_pac_4" BEL + "interfaz_spi/controlador_spi_principal/count_pac_3" BEL + "interfaz_spi/controlador_spi_principal/count_pac_2" BEL + "interfaz_spi/controlador_spi_principal/count_pac_1" BEL + "interfaz_spi/controlador_spi_principal/count_pac_0" BEL + "interfaz_spi/controlador_spi_principal/cmd_cur_state" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_7" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_6" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_5" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_4" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_3" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_2" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_1" BEL + "interfaz_spi/controlador_spi_principal/word_fromspi_int_0" BEL + "interfaz_spi/controlador_spi_principal/word_int_15" BEL + "interfaz_spi/controlador_spi_principal/word_int_14" BEL + "interfaz_spi/controlador_spi_principal/word_int_13" BEL + "interfaz_spi/controlador_spi_principal/word_int_12" BEL + "interfaz_spi/controlador_spi_principal/word_int_11" BEL + "interfaz_spi/controlador_spi_principal/word_int_10" BEL + "interfaz_spi/controlador_spi_principal/word_int_9" BEL + "interfaz_spi/controlador_spi_principal/word_int_8" BEL + "interfaz_spi/controlador_spi_principal/word_int_7" BEL + "interfaz_spi/controlador_spi_principal/word_int_6" BEL + "interfaz_spi/controlador_spi_principal/word_int_5" BEL + "interfaz_spi/controlador_spi_principal/word_int_4" BEL + "interfaz_spi/controlador_spi_principal/word_int_3" BEL + "interfaz_spi/controlador_spi_principal/word_int_2" BEL + "interfaz_spi/controlador_spi_principal/word_int_1" BEL + "interfaz_spi/controlador_spi_principal/word_int_0" BEL + "clk_u_proc_BUFG" BEL "i2c_comp/SCLoe" BEL + "interfaz_spi/controlador_spi_esclavo/spi_cur_state_FSM_FFd2" BEL + "interfaz_spi/controlador_spi_esclavo/SCKr_1" BEL + "interfaz_spi/controlador_spi_esclavo/SCKr_0" BEL "lock_rst_bar" BEL + "interfaz_spi/cabecera_memoria/header_cur_state_FSM_FFd2" BEL + "interfaz_spi/cabecera_memoria/header_cur_state_FSM_FFd1" BEL + "i2c_comp/SDAoe" BEL + "nb_mem_cont/nibble_pack_ch1/data_cur_state_FSM_FFd1" BEL + "nb_mem_cont/nibble_pack_ch1/rdy_mem_aux" BEL + "nb_mem_cont/nibble_pack_ch1/clk_acq_fall" BEL + "nb_mem_cont/nibble_pack_ch1/clk_acq_rise" BEL + "nb_mem_cont/nibble_pack_ch2/data_cur_state_FSM_FFd1" BEL + "nb_mem_cont/nibble_pack_ch2/rdy_mem_aux" BEL + "nb_mem_cont/nibble_pack_ch2/clk_acq_fall" BEL + "nb_mem_cont/nibble_pack_ch2/clk_acq_rise" BEL + "nb_mem_cont/nibble_pack_ch3/data_cur_state_FSM_FFd1" BEL + "nb_mem_cont/nibble_pack_ch3/rdy_mem_aux" BEL + "nb_mem_cont/nibble_pack_ch3/clk_acq_fall" BEL + "nb_mem_cont/nibble_pack_ch3/clk_acq_rise" BEL + "nb_mem_cont/nibble_pack_ch4/data_cur_state_FSM_FFd1" BEL + "nb_mem_cont/nibble_pack_ch4/rdy_mem_aux" BEL + "nb_mem_cont/nibble_pack_ch4/clk_acq_fall" BEL + "nb_mem_cont/nibble_pack_ch4/clk_acq_rise" BEL + "nb_mem_cont/nibble_pack_ch5/data_cur_state_FSM_FFd1" BEL + "nb_mem_cont/nibble_pack_ch5/rdy_mem_aux" BEL + "nb_mem_cont/nibble_pack_ch5/clk_acq_fall" BEL + "nb_mem_cont/nibble_pack_ch5/clk_acq_rise" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32" BEL + "interfaz_spi/controlador_spi_esclavo/SCK_fall" BEL + "interfaz_spi/controlador_spi_esclavo/SCK_rise" BEL + "i2c_comp/bit_counter_2" BEL "nb_mem_cont/nibble_pack_ch1/start_count" + BEL "nb_mem_cont/nibble_pack_ch2/start_count" BEL + "nb_mem_cont/nibble_pack_ch3/start_count" BEL + "nb_mem_cont/nibble_pack_ch4/start_count" BEL + "nb_mem_cont/nibble_pack_ch5/start_count" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_1" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0" BEL + "nb_mem_cont/nibble_pack_ch1/clk_acq_r_2" BEL + "nb_mem_cont/nibble_pack_ch1/clk_acq_r_1" BEL + "nb_mem_cont/nibble_pack_ch1/clk_acq_r_0" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_1" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_1" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_1" BEL + "nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_1" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0" BEL + "nb_mem_cont/nibble_pack_ch2/clk_acq_r_2" BEL + "nb_mem_cont/nibble_pack_ch2/clk_acq_r_1" BEL + "nb_mem_cont/nibble_pack_ch2/clk_acq_r_0" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_1" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_1" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_1" BEL + "nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_1" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0" BEL + "nb_mem_cont/nibble_pack_ch3/clk_acq_r_2" BEL + "nb_mem_cont/nibble_pack_ch3/clk_acq_r_1" BEL + "nb_mem_cont/nibble_pack_ch3/clk_acq_r_0" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_1" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_1" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_1" BEL + "nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_1" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0" BEL + "nb_mem_cont/nibble_pack_ch4/clk_acq_r_2" BEL + "nb_mem_cont/nibble_pack_ch4/clk_acq_r_1" BEL + "nb_mem_cont/nibble_pack_ch4/clk_acq_r_0" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_1" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_1" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_1" BEL + "nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_1" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0" BEL + "nb_mem_cont/nibble_pack_ch5/clk_acq_r_2" BEL + "nb_mem_cont/nibble_pack_ch5/clk_acq_r_1" BEL + "nb_mem_cont/nibble_pack_ch5/clk_acq_r_0" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_1" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_1" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_1" BEL + "nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd6" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd11" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd40" BEL + "nb_mem_cont/ram_control/ch_cont_cur_state_FSM_FFd2" BEL + "nb_mem_cont/nibble_pack_ch1/data_cur_state_FSM_FFd2" BEL + "nb_mem_cont/nibble_pack_ch2/data_cur_state_FSM_FFd2" BEL + "nb_mem_cont/nibble_pack_ch3/data_cur_state_FSM_FFd2" BEL + "nb_mem_cont/nibble_pack_ch4/data_cur_state_FSM_FFd2" BEL + "nb_mem_cont/nibble_pack_ch5/data_cur_state_FSM_FFd2" BEL + "nb_mem_cont/ram_control/ch_cont_cur_state_FSM_FFd3" BEL + "nb_mem_cont/ram_control/ch_cont_cur_state_FSM_FFd1" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_0" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_0" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_0" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_0" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_0" BEL + "nb_mem_cont/ram_control/count_slw_1" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1" BEL + "nb_mem_cont/ram_control/count_slw_2" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd41" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd22" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd28" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd12" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd17" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_1" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_1" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_1" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_1" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_1" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd7" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd33" BEL + "nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd35" BEL + "nb_mem_cont/ram_control/ch_cont_cur_state_FSM_FFd4" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_11" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_10" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_9" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_8" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_7" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_6" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_5" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_4" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_3" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_2" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_1" BEL + "nb_mem_cont/ram_control/addr_rd_aux_int_0" BEL "lock_rst_bar_1" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_5" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_4" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_2" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_5" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_4" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_2" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_5" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_4" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_2" BEL + "nb_mem_cont/ram_control/count_slw_3" BEL + "nb_mem_cont/ram_control/count_slw_0" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_5" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_4" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_2" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_5" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_4" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_2" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_8" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_6" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_8" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_6" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_8" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_6" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_8" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_6" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_8" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_6" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_7" BEL + "nb_mem_cont/ram_control/rel_pos_ch5_int_3" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_7" BEL + "nb_mem_cont/ram_control/rel_pos_ch4_int_3" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_7" BEL + "nb_mem_cont/ram_control/rel_pos_ch3_int_3" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_7" BEL + "nb_mem_cont/ram_control/rel_pos_ch2_int_3" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_7" BEL + "nb_mem_cont/ram_control/rel_pos_ch1_int_3" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_11" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_10" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_9" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_8" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_7" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_6" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_5" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_4" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_3" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_2" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_1" BEL + "nb_mem_cont/ram_control/addr_erase_aux_int_0" BEL + "interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1" BEL + "interfaz_spi/controlador_spi_esclavo/CSr_1"; +PIN clk_mang/ODDR2_inst_pins<1> = BEL "clk_mang/ODDR2_inst" PINNAME CK0; +PIN clk_mang/ODDR2_inst_pins<2> = BEL "clk_mang/ODDR2_inst" PINNAME CK1; +TIMEGRP clk_mang_c_16MHz = BEL "clk_mang/c_16MHz_BUFG" PIN + "clk_mang/ODDR2_inst_pins<1>" PIN "clk_mang/ODDR2_inst_pins<2>" PIN + "clk_mang/ODDR2_inst_pins<1>" PIN "clk_mang/ODDR2_inst_pins<2>"; +PIN SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0> = BEL "SP6_BUFIO_INSERT_ML_BUFIO2_0" + PINNAME DIVCLK; +PIN clk_mang/DCM_SP_inst_pins<3> = BEL "clk_mang/DCM_SP_inst" PINNAME CLKIN; +PIN SP6_BUFIO_INSERT_ML_BUFIO2_1_pins<0> = BEL "SP6_BUFIO_INSERT_ML_BUFIO2_1" + PINNAME DIVCLK; +PIN clk_mang/DCM_SP_inst_int_pins<3> = BEL "clk_mang/DCM_SP_inst_int" PINNAME + CLKIN; +TIMEGRP clk_main = PIN "SP6_BUFIO_INSERT_ML_BUFIO2_0_pins<0>" PIN + "clk_mang/DCM_SP_inst_pins<3>" PIN + "SP6_BUFIO_INSERT_ML_BUFIO2_1_pins<0>" PIN + "clk_mang/DCM_SP_inst_int_pins<3>"; +TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%; +TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%; +TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" TS_clk_main / + 0.266666667 HIGH 50%; +COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" + "RISING"; +COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING"; +COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"; +COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"; +SCHEMATIC END; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.prj =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.prj b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.prj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.prj (revision 224) @@ -0,0 +1,13 @@ +vhdl work "W_R_RAM_CONTROLLER.vhd" +vhdl work "SPI_SLAVE.vhd" +vhdl work "spi_controller.vhd" +vhdl work "SEL_WRbar.vhd" +vhdl work "nibble_pack.vhd" +vhdl work "mux_np.vhd" +vhdl work "header_memory.vhd" +vhdl work "data_header_ram.vhd" +vhdl work "u_np_mux_memcon_seliobar.vhd" +vhdl work "i2c_inst.vhd" +vhdl work "header_spi_interface.vhd" +vhdl work "DCM_fwd_int.vhd" +vhdl work "chn5_mem_spi_joint.vhd" Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ptwx =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ptwx b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ptwx new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ptwx (revision 224) @@ -0,0 +1,332 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING"TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" TS_clk_main / 0.266666667 HIGH 50%COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"0 Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.stx =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.stx b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.stx new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.stx (revision 224) Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.syr =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.syr b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.syr new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.syr (revision 224) @@ -0,0 +1,1013 @@ +Release 14.7 - xst P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Reading design: chn5_mem_spi_joint.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "chn5_mem_spi_joint.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "chn5_mem_spi_joint" +Output Format : NGC +Target Device : xc6slx9-3-tqg144 + +---- Source Options +Top Module Name : chn5_mem_spi_joint +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Parsing * +========================================================================= +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\W_R_RAM_CONTROLLER.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\SPI_SLAVE.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\spi_controller.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\SEL_WRbar.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\nibble_pack.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\mux_np.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\header_memory.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\data_header_ram.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\u_np_mux_memcon_seliobar.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\i2c_inst.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\header_spi_interface.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\DCM_fwd_int.vhd" into library work +Parsing entity . +Parsing architecture of entity . +Parsing VHDL file "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd" into library work +Parsing entity . +Parsing architecture of entity . + +========================================================================= +* HDL Elaboration * +========================================================================= + +Elaborating entity (architecture ) with generics from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) from library . + +Elaborating entity (architecture ) with generics from library . + +Elaborating entity (architecture ) with generics from library . +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\nibble_pack.vhd" Line 248. Case statement is complete. others clause is never selected + +Elaborating entity (architecture ) with generics from library . +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\W_R_RAM_CONTROLLER.vhd" Line 298. Case statement is complete. others clause is never selected +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\W_R_RAM_CONTROLLER.vhd" Line 405. Case statement is complete. others clause is never selected +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\W_R_RAM_CONTROLLER.vhd" Line 1667. Case statement is complete. others clause is never selected + +Elaborating entity (architecture ) with generics from library . + +Elaborating entity (architecture ) with generics from library . + +Elaborating entity (architecture ) with generics from library . + +Elaborating entity (architecture ) with generics from library . +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\SPI_SLAVE.vhd" Line 284. Case statement is complete. others clause is never selected + +Elaborating entity (architecture ) with generics from library . +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\spi_controller.vhd" Line 182. Case statement is complete. others clause is never selected +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\spi_controller.vhd" Line 440. Case statement is complete. others clause is never selected + +Elaborating entity (architecture ) with generics from library . +INFO:HDLCompiler:679 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\header_memory.vhd" Line 145. Case statement is complete. others clause is never selected + +Elaborating entity (architecture ) with generics from library . + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd". + NIBBLE_SZ = 4 + RESUL_NP_SZ = 24 + RESUL_MUX_SZ = 16 + RESUL_RAM_SZ = 16 + CHAN_NUM = 5 + ADDR_LENGTH = 19 + SPI_NIBL_COUNT_WIDTH = 3 + HEADER_CONST_SZ = 4 + HEADER_CH_SZ = 4 + WORD_INT_MUX_SZ = 32 + WORD_OUT_MUX_SZ = 16 + RESUL_IOSEL_SZ = 16 + DATA_MUX_SZ = 16 + COUNT_HEADER_SZ = 3 + HEADER_SZ = 8 + DATA_HEADER_SZ = 16 + WORD_IN_SZ = 16 + WORD_INT_SZ = 16 + WORD_OUT_SZ = 8 + WORD_SPIIN_SZ = 8 + POS_WORD1 = 16 + POS_WORD2 = 8 + SPI_DATA_WIDTH = 8 + SPI_BIT_COUNT_WIDTH = 3 +INFO:Xst:3210 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. +INFO:Xst:3210 - "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.vhd" line 383: Output port of the instance is unconnected or connected to loadless signal. + Found 16-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 16-bit adder for signal created at line 1241. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 20 D-type flip-flop(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\DCM_fwd_int.vhd". + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\i2c_inst.vhd". + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 3-bit adder for signal created at line 1241. + Found 1-bit tristate buffer for signal created at line 52 + Found 1-bit tristate buffer for signal created at line 53 + Summary: + inferred 1 Adder/Subtractor(s). + inferred 8 D-type flip-flop(s). + inferred 2 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\u_np_mux_memcon_seliobar.vhd". + NIBBLE_SZ = 4 + RESUL_NP_SZ = 24 + RESUL_MUX_SZ = 16 + RESUL_RAM_SZ = 16 + CHAN_NUM = 5 + ADDR_LENGTH = 19 + SPI_NIBL_COUNT_WIDTH = 3 + HEADER_CONST_SZ = 4 + HEADER_CH_SZ = 4 + WORD_INT_MUX_SZ = 32 + WORD_OUT_MUX_SZ = 16 + RESUL_IOSEL_SZ = 16 + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\nibble_pack.vhd". + NIBBLE_SZ = 4 + RESUL_NP_SZ = 24 + SPI_NIBL_COUNT_WIDTH = 3 + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit register for signal . + Found 24-bit register for signal . + Found 24-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 6 | + | Inputs | 2 | + | Outputs | 4 | + | Clock | clk_main (rising_edge) | + | Reset | rst_bar_INV_22_o (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 3-bit adder for signal created at line 1241. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 66 D-type flip-flop(s). + inferred 6 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\W_R_RAM_CONTROLLER.vhd". + ADDR_LENGTH = 19 + CHAN_NUM = 5 + Found 12-bit register for signal . + Found 12-bit register for signal . + Found 9-bit register for signal . + Found 9-bit register for signal . + Found 9-bit register for signal . + Found 9-bit register for signal . + Found 9-bit register for signal . + Found 6-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 42 | + | Transitions | 84 | + | Inputs | 9 | + | Outputs | 35 | + | Clock | clk_main (rising_edge) | + | Reset | rst_bar_INV_45_o (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 11 | + | Transitions | 21 | + | Inputs | 6 | + | Outputs | 4 | + | Clock | clk_main (rising_edge) | + | Reset | rst_bar_INV_45_o (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 19-bit adder for signal created at line 316. + Found 19-bit adder for signal created at line 318. + Found 19-bit adder for signal created at line 320. + Found 19-bit adder for signal created at line 322. + Found 12-bit adder for signal created at line 1241. + Found 12-bit adder for signal created at line 1241. + Found 9-bit adder for signal created at line 1241. + Found 9-bit adder for signal created at line 1241. + Found 9-bit adder for signal created at line 1241. + Found 9-bit adder for signal created at line 1241. + Found 9-bit adder for signal created at line 1241. + Found 4-bit adder for signal created at line 1241. + Summary: + inferred 9 Adder/Subtractor(s). + inferred 73 D-type flip-flop(s). + inferred 40 Multiplexer(s). + inferred 2 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\mux_np.vhd". + CHAN_NUM = 5 + HEADER_CONST_SZ = 4 + HEADER_CH_SZ = 4 + RESUL_NP_SZ = 24 + WORD_INT_MUX_SZ = 32 + WORD_OUT_MUX_SZ = 16 + Summary: + inferred 7 Multiplexer(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\SEL_WRbar.vhd". + RESUL_IOSEL_SZ = 16 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Found 1-bit tristate buffer for signal > created at line 48 + Summary: + inferred 16 Tristate(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\header_spi_interface.vhd". + DATA_MUX_SZ = 16 + COUNT_HEADER_SZ = 3 + HEADER_SZ = 8 + DATA_HEADER_SZ = 16 + WORD_IN_SZ = 16 + WORD_INT_SZ = 16 + WORD_OUT_SZ = 8 + WORD_SPIIN_SZ = 8 + POS_WORD1 = 16 + POS_WORD2 = 8 + SPI_DATA_WIDTH = 8 + SPI_BIT_COUNT_WIDTH = 3 + Summary: + no macro. +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\SPI_SLAVE.vhd". + SPI_DATA_WIDTH = 8 + SPI_BIT_COUNT_WIDTH = 3 + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found 3-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 2-bit register for signal . + Found 2-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 3 | + | Transitions | 5 | + | Inputs | 2 | + | Outputs | 1 | + | Clock | clk_main (rising_edge) | + | Reset | rst_bar_INV_82_o (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | free | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 3-bit adder for signal created at line 1241. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 28 D-type flip-flop(s). + inferred 5 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\spi_controller.vhd". + WORD_IN_SZ = 16 + WORD_INT_SZ = 16 + WORD_OUT_SZ = 8 + WORD_SPIIN_SZ = 8 + POS_WORD1 = 16 + POS_WORD2 = 8 + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 12-bit register for signal . + Found 5-bit register for signal . + Found 16-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 17 | + | Transitions | 34 | + | Inputs | 6 | + | Outputs | 14 | + | Clock | clk_main (rising_edge) | + | Reset | rst_bar_INV_106_o (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 12-bit adder for signal created at line 1241. + Summary: + inferred 1 Adder/Subtractor(s). + inferred 37 D-type flip-flop(s). + inferred 3 Multiplexer(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\header_memory.vhd". + COUNT_HEADER_SZ = 3 + HEADER_SZ = 8 + DATA_HEADER_SZ = 16 + Found 2-bit register for signal . + Found 3-bit register for signal . + Found finite state machine for signal . + ----------------------------------------------------------------------- + | States | 4 | + | Transitions | 6 | + | Inputs | 1 | + | Outputs | 2 | + | Clock | clk_main (rising_edge) | + | Reset | rst_ptr (positive) | + | Reset type | synchronous | + | Reset State | idle | + | Power Up State | idle | + | Encoding | auto | + | Implementation | LUT | + ----------------------------------------------------------------------- + Found 3-bit adder for signal created at line 1241. + Found 8x16-bit Read Only RAM for signal + Summary: + inferred 1 RAM(s). + inferred 1 Adder/Subtractor(s). + inferred 3 D-type flip-flop(s). + inferred 1 Finite State Machine(s). +Unit synthesized. + +Synthesizing Unit . + Related source file is "C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\data_header_ram.vhd". + DATA_MUX_SZ = 16 + Summary: + inferred 1 Multiplexer(s). +Unit synthesized. + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# RAMs : 1 + 8x16-bit single-port Read Only RAM : 1 +# Adders/Subtractors : 19 + 12-bit adder : 3 + 16-bit adder : 1 + 19-bit adder : 1 + 3-bit adder : 8 + 4-bit adder : 1 + 9-bit adder : 5 +# Registers : 91 + 1-bit register : 29 + 12-bit register : 3 + 16-bit register : 2 + 2-bit register : 25 + 24-bit register : 10 + 3-bit register : 13 + 4-bit register : 1 + 8-bit register : 3 + 9-bit register : 5 +# Multiplexers : 86 + 1-bit 2-to-1 multiplexer : 3 + 12-bit 2-to-1 multiplexer : 3 + 16-bit 2-to-1 multiplexer : 3 + 19-bit 2-to-1 multiplexer : 23 + 24-bit 2-to-1 multiplexer : 30 + 3-bit 2-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 5 + 4-bit 2-to-1 multiplexer : 4 + 8-bit 2-to-1 multiplexer : 3 + 9-bit 2-to-1 multiplexer : 10 +# Tristates : 18 + 1-bit tristate buffer : 18 +# FSMs : 10 + +========================================================================= +INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing. + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style. + ----------------------------------------------------------------------- + | ram_type | Distributed | | + ----------------------------------------------------------------------- + | Port A | + | aspect ratio | 8-word x 16-bit | | + | weA | connected to signal | high | + | addrA | connected to signal | | + | diA | connected to signal | | + | doA | connected to signal | | + ----------------------------------------------------------------------- +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +Synthesizing (advanced) Unit . +The following registers are absorbed into counter : 1 register on signal . +Unit synthesized (advanced). + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# RAMs : 1 + 8x16-bit single-port distributed Read Only RAM : 1 +# Adders/Subtractors : 10 + 12-bit adder : 2 + 19-bit adder : 1 + 3-bit adder : 1 + 4-bit adder : 1 + 9-bit adder : 5 +# Counters : 9 + 12-bit up counter : 1 + 16-bit up counter : 1 + 3-bit up counter : 7 +# Registers : 450 + Flip-Flops : 450 +# Multiplexers : 84 + 1-bit 2-to-1 multiplexer : 2 + 12-bit 2-to-1 multiplexer : 2 + 16-bit 2-to-1 multiplexer : 3 + 19-bit 2-to-1 multiplexer : 23 + 24-bit 2-to-1 multiplexer : 30 + 3-bit 2-to-1 multiplexer : 2 + 32-bit 2-to-1 multiplexer : 5 + 4-bit 2-to-1 multiplexer : 4 + 8-bit 2-to-1 multiplexer : 3 + 9-bit 2-to-1 multiplexer : 10 +# FSMs : 10 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + idle | 00 + pres | 01 + proc | 11 + aum | 10 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +Optimizing FSM on signal with gray encoding. +----------------------- + State | Encoding +----------------------- + idle | 00 + data_pres | 01 + data_proc | 11 +----------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +--------------------------- + State | Encoding +--------------------------- + idle | 0000 + checking_ch1 | 0001 + attending_ch1 | 0010 + checking_ch2 | 0011 + attending_ch2 | 0100 + checking_ch3 | 0101 + attending_ch3 | 0110 + checking_ch4 | 0111 + attending_ch4 | 1000 + checking_ch5 | 1001 + attending_ch5 | 1010 +--------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with one-hot encoding. +--------------------------------------------------------------- + State | Encoding +--------------------------------------------------------------- + idle | 000000000000000000000000000000000000000001 + set_erase_ram | 000000000000000000000000000000000000000010 + act_erase_ram | 000000000000000000000000000000000000000100 + exe_erase_ram | 000000000000000000000000000000000000001000 + espera_rdy | 000000000000000000000000000000000000010000 + set_wrt_ch1_1 | 000000000000000000000000000000000000100000 + act_wrt_ch1_1 | 000000000000000000000000000000100000000000 + exe_wrt_ch1_1 | 000000000000000000000000000001000000000000 + set_wrt_ch1_2 | 000000000000000000000000000100000000000000 + act_wrt_ch1_2 | 000000000000000000000000001000000000000000 + exe_wrt_ch1_2 | 000000000000000000000000010000000000000000 + set_wrt_ch2_1 | 000000000000000000000000000000000001000000 + act_wrt_ch2_1 | 000000000000000000000001000000000000000000 + exe_wrt_ch2_1 | 000000000000000000000010000000000000000000 + set_wrt_ch2_2 | 000000000000000000000100000000000000000000 + act_wrt_ch2_2 | 000000000000000000001000000000000000000000 + exe_wrt_ch2_2 | 000000000000000000010000000000000000000000 + set_wrt_ch3_1 | 000000000000000000000000000000000010000000 + act_wrt_ch3_1 | 000000000000000000100000000000000000000000 + exe_wrt_ch3_1 | 000000000000000001000000000000000000000000 + set_wrt_ch3_2 | 000000000000000010000000000000000000000000 + act_wrt_ch3_2 | 000000000000000100000000000000000000000000 + exe_wrt_ch3_2 | 000000000000001000000000000000000000000000 + set_wrt_ch4_1 | 000000000000000000000000000000000100000000 + act_wrt_ch4_1 | 000000000000010000000000000000000000000000 + exe_wrt_ch4_1 | 000000000000100000000000000000000000000000 + set_wrt_ch4_2 | 000000000001000000000000000000000000000000 + act_wrt_ch4_2 | 000000000010000000000000000000000000000000 + exe_wrt_ch4_2 | 000000000100000000000000000000000000000000 + set_wrt_ch5_1 | 000000000000000000000000000000001000000000 + act_wrt_ch5_1 | 000000001000000000000000000000000000000000 + exe_wrt_ch5_1 | 000000010000000000000000000000000000000000 + set_wrt_ch5_2 | 000000100000000000000000000000000000000000 + act_wrt_ch5_2 | 000001000000000000000000000000000000000000 + exe_wrt_ch5_2 | 000010000000000000000000000000000000000000 + end_wrt_cycle_1 | 000000000000000000000000000010000000000000 + end_wrt_cycle_2 | 000000000000000000000000100000000000000000 + espera_req | 000100000000000000000000000000000000000000 + set_rd | 000000000000000000000000000000010000000000 + act_rd | 001000000000000000000000000000000000000000 + exe_rd | 010000000000000000000000000000000000000000 + end_rd | 100000000000000000000000000000000000000000 +--------------------------------------------------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with gray encoding. +------------------- + State | Encoding +------------------- + idle | 00 + free | 01 + busy | 11 +------------------- +Analyzing FSM for best encoding. +Optimizing FSM on signal with user encoding. +------------------------------ + State | Encoding +------------------------------ + idle | 00000 + pide_dato_header | 00001 + pide_dato_ram | 00010 + w1_pres_header | 00011 + w1_proc_header | 00100 + w1_espera_header | 00101 + w2_pres_header | 00110 + w2_proc_header | 00111 + w2_espera_header | 01000 + w1_pres_ram | 01001 + w1_proc_ram | 01010 + w1_espera_ram | 01011 + w2_pres_ram | 01100 + w2_proc_ram | 01101 + w2_espera_ram | 01110 + w2_aum_header | 01111 + w2_aum_ram | 10000 +------------------------------ + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block chn5_mem_spi_joint, actual ratio is 17. +FlipFlop lock_rst_bar has been replicated 1 time(s) + +Final Macro Processing ... + +Processing Unit : + Found 2-bit shift register for signal . +Unit processed. + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 563 + Flip-Flops : 563 +# Shift Registers : 1 + 2-bit shift register : 1 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Design Summary * +========================================================================= + +Top Level Output File Name : chn5_mem_spi_joint.ngc + +Primitive and Black Box Usage: +------------------------------ +# BELS : 1012 +# GND : 1 +# INV : 13 +# LUT1 : 37 +# LUT2 : 57 +# LUT3 : 161 +# LUT4 : 108 +# LUT5 : 235 +# LUT6 : 269 +# MUXCY : 59 +# MUXF7 : 8 +# VCC : 1 +# XORCY : 63 +# FlipFlops/Latches : 565 +# FD : 216 +# FDE : 259 +# FDR : 26 +# FDRE : 63 +# ODDR2 : 1 +# Shift Registers : 1 +# SRLC16E : 1 +# Clock Buffers : 4 +# BUFG : 4 +# IO Buffers : 74 +# IBUF : 30 +# IBUFG : 1 +# IOBUF : 18 +# OBUF : 25 +# DCMs : 2 +# DCM_SP : 2 + +Device utilization summary: +--------------------------- + +Selected Device : 6slx9tqg144-3 + + +Slice Logic Utilization: + Number of Slice Registers: 565 out of 11440 4% + Number of Slice LUTs: 881 out of 5720 15% + Number used as Logic: 880 out of 5720 15% + Number used as Memory: 1 out of 1440 0% + Number used as SRL: 1 + +Slice Logic Distribution: + Number of LUT Flip Flop pairs used: 944 + Number with an unused Flip Flop: 379 out of 944 40% + Number with an unused LUT: 63 out of 944 6% + Number of fully used LUT-FF pairs: 502 out of 944 53% + Number of unique control sets: 28 + +IO Utilization: + Number of IOs: 74 + Number of bonded IOBs: 74 out of 102 72% + +Specific Feature Utilization: + Number of BUFG/BUFGCTRLs: 4 out of 16 25% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +Timing Report + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +clk_main | DCM_SP:CLKFX | 565 | +clk_main | DCM_SP:CLKFX | 2 | +-----------------------------------+------------------------+-------+ + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -3 + + Minimum period: 19.089ns (Maximum Frequency: 52.386MHz) + Minimum input arrival time before clock: 3.125ns + Maximum output required time after clock: 10.593ns + Maximum combinational path delay: No path found + +Timing Details: +--------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'clk_main' + Clock period: 19.089ns (frequency: 52.386MHz) + Total number of paths / destination ports: 5932 / 970 +------------------------------------------------------------------------- +Delay: 4.772ns (Levels of Logic = 4) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 (FF) + Destination: nb_mem_cont/ram_control/addr_erase_aux_int_11 (FF) + Source Clock: clk_main rising 4.0X + Destination Clock: clk_main rising 4.0X + + Data Path: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 to nb_mem_cont/ram_control/addr_erase_aux_int_11 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FD:C->Q 6 0.447 1.109 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 (nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32) + LUT6:I0->O 1 0.203 0.808 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>13 (nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>13) + LUT5:I2->O 12 0.205 0.909 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>14 (nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>1) + LUT4:I3->O 1 0.205 0.580 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<1>1 (nb_mem_cont/ram_control/_n0327<1>) + LUT6:I5->O 1 0.205 0.000 nb_mem_cont/ram_control/addr_erase_aux_int_11_rstpot (nb_mem_cont/ram_control/addr_erase_aux_int_11_rstpot) + FD:D 0.102 nb_mem_cont/ram_control/addr_erase_aux_int_11 + ---------------------------------------- + Total 4.772ns (1.367ns logic, 3.405ns route) + (28.6% logic, 71.4% route) + +========================================================================= +Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_main' + Total number of paths / destination ports: 52 / 52 +------------------------------------------------------------------------- +Offset: 3.125ns (Levels of Logic = 2) + Source: lock (PAD) + Destination: pps_rst (FF) + Destination Clock: clk_main rising 4.0X + + Data Path: lock to pps_rst + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 2 1.222 0.616 lock_IBUF (lock_IBUF) + INV:I->O 3 0.206 0.650 lock_inv1_INV_0 (lock_inv) + FDR:R 0.430 pps_rst + ---------------------------------------- + Total 3.125ns (1.858ns logic, 1.266ns route) + (59.5% logic, 40.5% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_main' + Total number of paths / destination ports: 6526 / 35 +------------------------------------------------------------------------- +Offset: 10.593ns (Levels of Logic = 7) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd18 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_main rising 4.0X + + Data Path: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd18 to DATA_INOUT<9> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDR:C->Q 16 0.447 1.349 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd18 (nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd18) + LUT6:I1->O 14 0.203 1.186 nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 (nb_mem_cont/oe_ch_vect<2>) + LUT5:I2->O 18 0.205 1.154 nb_mem_cont/mux_data/_n0022<4>1 (nb_mem_cont/mux_data/Mmux_DATA_OUT110) + LUT4:I2->O 1 0.203 0.580 nb_mem_cont/mux_data/Mmux_DATA_OUT405_SW0 (N199) + LUT6:I5->O 1 0.205 0.580 nb_mem_cont/mux_data/Mmux_DATA_OUT405 (nb_mem_cont/mux_data/Mmux_DATA_OUT404) + LUT6:I5->O 1 0.205 0.924 nb_mem_cont/mux_data/Mmux_DATA_OUT407_SW0 (N201) + LUT6:I1->O 1 0.203 0.579 nb_mem_cont/mux_data/Mmux_DATA_OUT407 (nb_mem_cont/data_mux<9>) + IOBUF:I->IO 2.571 DATA_INOUT_9_IOBUF (DATA_INOUT<9>) + ---------------------------------------- + Total 10.593ns (4.242ns logic, 6.351ns route) + (40.0% logic, 60.0% route) + +========================================================================= + +Cross Clock Domains Report: +-------------------------- + +Clock to Setup on destination clock clk_main +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +clk_main | 4.772| | | | +---------------+---------+---------+---------+---------+ + +========================================================================= + + +Total REAL time to Xst completion: 12.00 secs +Total CPU time to Xst completion: 12.16 secs + +--> + +Total memory usage is 253932 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 4 ( 0 filtered) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twr =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twr b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twr new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twr (revision 224) @@ -0,0 +1,15546 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 +-n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o +chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf + +Design file: chn5_mem_spi_joint.ncd +Physical constraint file: chn5_mem_spi_joint.pcf +Device,package,speed: xc6slx9,tqg144,C,-3 (PRODUCTION 1.23 2013-10-13) +Report level: verbose report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. + +================================================================================ +Timing constraint: TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 8.000ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 1.497ns (period - min period limit) + Period: 4.167ns + Min period limit: 2.670ns (374.532MHz) (Tdcmper_CLKFX) + Physical resource: clk_mang/DCM_SP_inst_int/CLKFX + Logical resource: clk_mang/DCM_SP_inst_int/CLKFX + Location pin: DCM_X0Y0.CLKFX + Clock network: clk_u_proc +-------------------------------------------------------------------------------- +Slack: 8.667ns (period - (min low pulse limit / (low pulse / period))) + Period: 16.667ns + Low pulse: 8.333ns + Low pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100) + Physical resource: clk_mang/DCM_SP_inst_int/CLKIN + Logical resource: clk_mang/DCM_SP_inst_int/CLKIN + Location pin: DCM_X0Y0.CLKIN + Clock network: clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK +-------------------------------------------------------------------------------- +Slack: 8.667ns (period - (min high pulse limit / (high pulse / period))) + Period: 16.667ns + High pulse: 8.333ns + High pulse limit: 4.000ns (Tdcmpw_CLKIN_50_100) + Physical resource: clk_mang/DCM_SP_inst_int/CLKIN + Logical resource: clk_mang/DCM_SP_inst_int/CLKIN + Location pin: DCM_X0Y0.CLKIN + Clock network: clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 +HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 5931 paths analyzed, 2240 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors) + Minimum period is 3.803ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 (SLICE_X6Y41.SR), 6 paths +-------------------------------------------------------------------------------- +Slack (setup path): 0.363ns (requirement - (data path - clock path skew + uncertainty)) + Source: lock_rst_bar (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 (FF) + Requirement: 4.166ns + Data Path Delay: 3.639ns (Levels of Logic = 1) + Clock Path Skew: 0.013ns (0.632 - 0.619) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: lock_rst_bar to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y22.AQ Tcko 0.408 lock_rst_bar + lock_rst_bar + SLICE_X7Y20.C1 net (fanout=26) 1.081 lock_rst_bar + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y41.SR net (fanout=11) 1.484 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y41.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + ------------------------------------------------- --------------------------- + Total 3.639ns (1.074ns logic, 2.565ns route) + (29.5% logic, 70.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.365ns (requirement - (data path - clock path skew + uncertainty)) + Source: pps_rst (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 (FF) + Requirement: 4.166ns + Data Path Delay: 3.635ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.632 - 0.621) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: pps_rst to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y26.DQ Tcko 0.447 pps_rst + pps_rst + SLICE_X7Y20.C6 net (fanout=119) 1.038 pps_rst + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y41.SR net (fanout=11) 1.484 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y41.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + ------------------------------------------------- --------------------------- + Total 3.635ns (1.113ns logic, 2.522ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.419ns (requirement - (data path - clock path skew + uncertainty)) + Source: nb_mem_cont/ram_control/count_slw_3 (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 (FF) + Requirement: 4.166ns + Data Path Delay: 3.474ns (Levels of Logic = 1) + Clock Path Skew: -0.096ns (0.632 - 0.728) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/count_slw_3 to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y15.CMUX Tshcko 0.461 nb_mem_cont/ram_control/count_slw<1> + nb_mem_cont/ram_control/count_slw_3 + SLICE_X7Y20.C2 net (fanout=17) 0.863 nb_mem_cont/ram_control/count_slw<3> + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y41.SR net (fanout=11) 1.484 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y41.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 + ------------------------------------------------- --------------------------- + Total 3.474ns (1.127ns logic, 2.347ns route) + (32.4% logic, 67.6% route) + +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/ram_control/rel_pos_ch4_int_1 (SLICE_X7Y46.C2), 31 paths +-------------------------------------------------------------------------------- +Slack (setup path): 0.366ns (requirement - (data path - clock path skew + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: nb_mem_cont/ram_control/rel_pos_ch4_int_1 (FF) + Requirement: 4.166ns + Data Path Delay: 3.610ns (Levels of Logic = 3) + Clock Path Skew: -0.013ns (0.642 - 0.655) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to nb_mem_cont/ram_control/rel_pos_ch4_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X7Y46.D5 net (fanout=51) 1.605 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X7Y46.D Tilo 0.259 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW0 + SLICE_X7Y46.A3 net (fanout=1) 0.291 N159 + SLICE_X7Y46.A Tilo 0.259 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.C2 net (fanout=1) 0.427 nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.CLK Tas 0.322 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1 + nb_mem_cont/ram_control/rel_pos_ch4_int_1 + ------------------------------------------------- --------------------------- + Total 3.610ns (1.287ns logic, 2.323ns route) + (35.7% logic, 64.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.444ns (requirement - (data path - clock path skew + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: nb_mem_cont/ram_control/rel_pos_ch4_int_1 (FF) + Requirement: 4.166ns + Data Path Delay: 3.532ns (Levels of Logic = 3) + Clock Path Skew: -0.013ns (0.642 - 0.655) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to nb_mem_cont/ram_control/rel_pos_ch4_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X8Y42.D6 net (fanout=51) 1.108 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X8Y42.CMUX Topdc 0.368 N161 + nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2_F + nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2 + SLICE_X7Y46.A6 net (fanout=1) 0.601 N161 + SLICE_X7Y46.A Tilo 0.259 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.C2 net (fanout=1) 0.427 nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.CLK Tas 0.322 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1 + nb_mem_cont/ram_control/rel_pos_ch4_int_1 + ------------------------------------------------- --------------------------- + Total 3.532ns (1.396ns logic, 2.136ns route) + (39.5% logic, 60.5% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.451ns (requirement - (data path - clock path skew + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: nb_mem_cont/ram_control/rel_pos_ch4_int_1 (FF) + Requirement: 4.166ns + Data Path Delay: 3.525ns (Levels of Logic = 3) + Clock Path Skew: -0.013ns (0.642 - 0.655) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to nb_mem_cont/ram_control/rel_pos_ch4_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X8Y42.C6 net (fanout=51) 1.108 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X8Y42.CMUX Tilo 0.361 N161 + nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2_G + nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2 + SLICE_X7Y46.A6 net (fanout=1) 0.601 N161 + SLICE_X7Y46.A Tilo 0.259 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.C2 net (fanout=1) 0.427 nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot + SLICE_X7Y46.CLK Tas 0.322 nb_mem_cont/ram_control/rel_pos_ch4_int<1> + nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1 + nb_mem_cont/ram_control/rel_pos_ch4_int_1 + ------------------------------------------------- --------------------------- + Total 3.525ns (1.389ns logic, 2.136ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 (SLICE_X6Y38.SR), 6 paths +-------------------------------------------------------------------------------- +Slack (setup path): 0.386ns (requirement - (data path - clock path skew + uncertainty)) + Source: lock_rst_bar (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 (FF) + Requirement: 4.166ns + Data Path Delay: 3.616ns (Levels of Logic = 1) + Clock Path Skew: 0.013ns (0.632 - 0.619) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: lock_rst_bar to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y22.AQ Tcko 0.408 lock_rst_bar + lock_rst_bar + SLICE_X7Y20.C1 net (fanout=26) 1.081 lock_rst_bar + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y38.SR net (fanout=11) 1.461 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y38.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + ------------------------------------------------- --------------------------- + Total 3.616ns (1.074ns logic, 2.542ns route) + (29.7% logic, 70.3% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.388ns (requirement - (data path - clock path skew + uncertainty)) + Source: pps_rst (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 (FF) + Requirement: 4.166ns + Data Path Delay: 3.612ns (Levels of Logic = 1) + Clock Path Skew: 0.011ns (0.632 - 0.621) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: pps_rst to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X12Y26.DQ Tcko 0.447 pps_rst + pps_rst + SLICE_X7Y20.C6 net (fanout=119) 1.038 pps_rst + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y38.SR net (fanout=11) 1.461 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y38.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + ------------------------------------------------- --------------------------- + Total 3.612ns (1.113ns logic, 2.499ns route) + (30.8% logic, 69.2% route) + +-------------------------------------------------------------------------------- +Slack (setup path): 0.442ns (requirement - (data path - clock path skew + uncertainty)) + Source: nb_mem_cont/ram_control/count_slw_3 (FF) + Destination: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 (FF) + Requirement: 4.166ns + Data Path Delay: 3.451ns (Levels of Logic = 1) + Clock Path Skew: -0.096ns (0.632 - 0.728) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 4.166ns + Clock Uncertainty: 0.177ns + + Clock Uncertainty: 0.177ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.070ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.000ns + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/count_slw_3 to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X7Y15.CMUX Tshcko 0.461 nb_mem_cont/ram_control/count_slw<1> + nb_mem_cont/ram_control/count_slw_3 + SLICE_X7Y20.C2 net (fanout=17) 0.863 nb_mem_cont/ram_control/count_slw<3> + SLICE_X7Y20.C Tilo 0.259 nb_mem_cont/ram_control/addr_erase_aux_int<4> + nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01 + SLICE_X6Y38.SR net (fanout=11) 1.461 nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0 + SLICE_X6Y38.CLK Tsrck 0.407 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 + ------------------------------------------------- --------------------------- + Total 3.451ns (1.127ns logic, 2.324ns route) + (32.7% logic, 67.3% route) + +-------------------------------------------------------------------------------- + +Hold Paths: TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/buffer_in_3 (SLICE_X14Y5.DX), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.385ns (requirement - (clock path skew + uncertainty - data path)) + Source: interfaz_spi/controlador_spi_esclavo/buffer_in_2 (FF) + Destination: interfaz_spi/controlador_spi_esclavo/buffer_in_3 (FF) + Requirement: 0.000ns + Data Path Delay: 0.385ns (Levels of Logic = 0) + Clock Path Skew: 0.000ns + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: interfaz_spi/controlador_spi_esclavo/buffer_in_2 to interfaz_spi/controlador_spi_esclavo/buffer_in_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y5.CQ Tcko 0.200 interfaz_spi/controlador_spi_esclavo/buffer_in<3> + interfaz_spi/controlador_spi_esclavo/buffer_in_2 + SLICE_X14Y5.DX net (fanout=2) 0.137 interfaz_spi/controlador_spi_esclavo/buffer_in<2> + SLICE_X14Y5.CLK Tckdi (-Th) -0.048 interfaz_spi/controlador_spi_esclavo/buffer_in<3> + interfaz_spi/controlador_spi_esclavo/buffer_in_3 + ------------------------------------------------- --------------------------- + Total 0.385ns (0.248ns logic, 0.137ns route) + (64.4% logic, 35.6% route) + +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_8 (SLICE_X14Y38.AX), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.388ns (requirement - (clock path skew + uncertainty - data path)) + Source: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8 (FF) + Destination: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_8 (FF) + Requirement: 0.000ns + Data Path Delay: 0.390ns (Levels of Logic = 0) + Clock Path Skew: 0.002ns (0.034 - 0.032) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8 to nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X15Y38.AQ Tcko 0.198 nb_mem_cont/nibble_pack_ch3/resul_mem_internal<11> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8 + SLICE_X14Y38.AX net (fanout=2) 0.144 nb_mem_cont/nibble_pack_ch3/resul_mem_internal<8> + SLICE_X14Y38.CLK Tckdi (-Th) -0.048 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_8 + ------------------------------------------------- --------------------------- + Total 0.390ns (0.246ns logic, 0.144ns route) + (63.1% logic, 36.9% route) + +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/cabecera_memoria/ptr_mem_2 (SLICE_X6Y4.B5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 0.400ns (requirement - (clock path skew + uncertainty - data path)) + Source: interfaz_spi/cabecera_memoria/ptr_mem_1 (FF) + Destination: interfaz_spi/cabecera_memoria/ptr_mem_2 (FF) + Requirement: 0.000ns + Data Path Delay: 0.400ns (Levels of Logic = 1) + Clock Path Skew: 0.000ns + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Clock Uncertainty: 0.000ns + + Minimum Data Path at Fast Process Corner: interfaz_spi/cabecera_memoria/ptr_mem_1 to interfaz_spi/cabecera_memoria/ptr_mem_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y4.BQ Tcko 0.200 interfaz_spi/cabecera_memoria/ptr_mem<1> + interfaz_spi/cabecera_memoria/ptr_mem_1 + SLICE_X6Y4.B5 net (fanout=14) 0.079 interfaz_spi/cabecera_memoria/ptr_mem<1> + SLICE_X6Y4.CLK Tah (-Th) -0.121 interfaz_spi/cabecera_memoria/ptr_mem<1> + Result<2>11 + interfaz_spi/cabecera_memoria/ptr_mem_2 + ------------------------------------------------- --------------------------- + Total 0.400ns (0.321ns logic, 0.079ns route) + (80.3% logic, 19.8% route) + +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 2.436ns (period - min period limit) + Period: 4.166ns + Min period limit: 1.730ns (578.035MHz) (Tbcper_I) + Physical resource: clk_u_proc_BUFG/I0 + Logical resource: clk_u_proc_BUFG/I0 + Location pin: BUFGMUX_X2Y4.I0 + Clock network: clk_u_proc +-------------------------------------------------------------------------------- +Slack: 3.166ns (period - min period limit) + Period: 4.166ns + Min period limit: 1.000ns (1000.000MHz) (Tcp) + Physical resource: interfaz_spi/controlador_spi_esclavo/CSr<1>/CLK + Logical resource: interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1/CLK + Location pin: SLICE_X20Y7.CLK + Clock network: clk_u_proc_BUFG +-------------------------------------------------------------------------------- +Slack: 3.736ns (period - min period limit) + Period: 4.166ns + Min period limit: 0.430ns (2325.581MHz) (Tcp) + Physical resource: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27/CLK + Logical resource: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2/CK + Location pin: SLICE_X2Y14.CLK + Clock network: clk_u_proc_BUFG +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" +TS_clk_main / 0.266666667 HIGH 50%; +For more information, see Period Analysis in the Timing Closure User Guide (UG612). + + 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 component switching limit errors) + Minimum period is 1.730ns. +-------------------------------------------------------------------------------- + +Component Switching Limit Checks: TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" TS_clk_main / + 0.266666667 HIGH 50%; +-------------------------------------------------------------------------------- +Slack: 60.771ns (period - min period limit) + Period: 62.501ns + Min period limit: 1.730ns (578.035MHz) (Tbcper_I) + Physical resource: clk_mang/c_16MHz_BUFG/I0 + Logical resource: clk_mang/c_16MHz_BUFG/I0 + Location pin: BUFGMUX_X2Y2.I0 + Clock network: clk_mang/c_16MHz +-------------------------------------------------------------------------------- +Slack: 60.862ns (period - min period limit) + Period: 62.501ns + Min period limit: 1.639ns (610.128MHz) (Tockper) + Physical resource: clk_to_acq_OBUF/CLK0 + Logical resource: clk_mang/ODDR2_inst/CK0 + Location pin: OLOGIC_X12Y22.CLK0 + Clock network: clk_mang/c_16MHz_BUFG +-------------------------------------------------------------------------------- +Slack: 61.098ns (period - min period limit) + Period: 62.501ns + Min period limit: 1.403ns (712.758MHz) (Tockper) + Physical resource: clk_to_acq_OBUF/CLK1 + Logical resource: clk_mang/ODDR2_inst/CK1 + Location pin: OLOGIC_X12Y22.CLK1 + Clock network: clk_mang/c_16MHz_BUFG +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.503ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_15 (SLICE_X8Y9.C2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 9.164ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<15> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_15 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 6.775ns (Levels of Logic = 2) + Clock Path Delay: -0.411ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<15> to interfaz_spi/controlador_spi_principal/word_int_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P8.I Tiopi 1.310 DATA_INOUT<15> + DATA_INOUT<15> + DATA_INOUT_15_IOBUF/IBUF + ProtoComp55.IMUX.17 + SLICE_X8Y9.C2 net (fanout=1) 5.176 N42 + SLICE_X8Y9.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<15> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi71 + interfaz_spi/controlador_spi_principal/word_int_15 + ------------------------------------------------- --------------------------- + Total 6.775ns (1.599ns logic, 5.176ns route) + (23.6% logic, 76.4% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y9.CLK net (fanout=226) 0.702 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.411ns (-2.456ns logic, 2.045ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_15 (SLICE_X8Y9.C2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.702ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<15> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_15 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 4.177ns (Levels of Logic = 2) + Clock Path Delay: 0.158ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<15> to interfaz_spi/controlador_spi_principal/word_int_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P8.I Tiopi 0.763 DATA_INOUT<15> + DATA_INOUT<15> + DATA_INOUT_15_IOBUF/IBUF + ProtoComp55.IMUX.17 + SLICE_X8Y9.C2 net (fanout=1) 3.217 N42 + SLICE_X8Y9.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<15> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi71 + interfaz_spi/controlador_spi_principal/word_int_15 + ------------------------------------------------- --------------------------- + Total 4.177ns (0.960ns logic, 3.217ns route) + (23.0% logic, 77.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y9.CLK net (fanout=226) 0.842 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.158ns (-1.582ns logic, 1.740ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 184 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.489ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<15> (P8.PAD), 184 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.178ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.491ns (Levels of Logic = 4) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X16Y39.B2 net (fanout=9) 3.753 nb_mem_cont/oe_ch_vect<0> + SLICE_X16Y39.BMUX Tilo 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT93 + SLICE_X17Y39.A1 net (fanout=3) 0.641 nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X17Y39.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT157 + P8.O net (fanout=1) 3.345 nb_mem_cont/data_mux<15> + P8.PAD Tioop 2.381 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 12.491ns (3.615ns logic, 8.876ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.220ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.460ns (Levels of Logic = 4) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X16Y39.B2 net (fanout=9) 3.753 nb_mem_cont/oe_ch_vect<0> + SLICE_X16Y39.BMUX Tilo 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT93 + SLICE_X17Y39.A1 net (fanout=3) 0.641 nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X17Y39.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT157 + P8.O net (fanout=1) 3.345 nb_mem_cont/data_mux<15> + P8.PAD Tioop 2.381 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 12.460ns (3.551ns logic, 8.909ns route) + (28.5% logic, 71.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.345ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.324ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X17Y28.D5 net (fanout=9) 2.321 nb_mem_cont/oe_ch_vect<0> + SLICE_X17Y28.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/_n0028<4>11 + SLICE_X17Y39.C3 net (fanout=6) 1.158 nb_mem_cont/mux_data/_n0028<4>1 + SLICE_X17Y39.C Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT155 + SLICE_X17Y39.A2 net (fanout=1) 0.437 nb_mem_cont/mux_data/Mmux_DATA_OUT154 + SLICE_X17Y39.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT157 + P8.O net (fanout=1) 3.345 nb_mem_cont/data_mux<15> + P8.PAD Tioop 2.381 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 12.324ns (3.926ns logic, 8.398ns route) + (31.9% logic, 68.1% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<15> (P8.PAD), 184 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.886ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.644ns (Levels of Logic = 3) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y39.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y39.DQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15 + SLICE_X17Y39.D1 net (fanout=1) 0.385 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + SLICE_X17Y39.D Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X17Y39.A3 net (fanout=1) 0.148 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + SLICE_X17Y39.A Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT157 + P8.O net (fanout=1) 2.169 nb_mem_cont/data_mux<15> + P8.PAD Tioop 1.396 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 4.644ns (1.942ns logic, 2.702ns route) + (41.8% logic, 58.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.850ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.491ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P8.T net (fanout=16) 2.197 nb_mem_cont/io_sel/OEbar_inv + P8.PAD Tiotp 1.396 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 4.491ns (1.790ns logic, 2.701ns route) + (39.9% logic, 60.1% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.744ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15 (FF) + Destination: DATA_INOUT<15> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.503ns (Levels of Logic = 3) + Clock Path Delay: -0.442ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y40.CLK net (fanout=226) 0.448 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.442ns (-1.698ns logic, 1.256ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15 to DATA_INOUT<15> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y40.DQ Tcko 0.200 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15 + SLICE_X17Y39.C6 net (fanout=1) 0.171 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15> + SLICE_X17Y39.C Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT155 + SLICE_X17Y39.A2 net (fanout=1) 0.255 nb_mem_cont/mux_data/Mmux_DATA_OUT154 + SLICE_X17Y39.A Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT151 + nb_mem_cont/mux_data/Mmux_DATA_OUT157 + P8.O net (fanout=1) 2.169 nb_mem_cont/data_mux<15> + P8.PAD Tioop 1.396 DATA_INOUT<15> + DATA_INOUT_15_IOBUF/OBUFT + DATA_INOUT<15> + ------------------------------------------------- --------------------------- + Total 4.503ns (1.908ns logic, 2.595ns route) + (42.4% logic, 57.6% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.132ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_14 (SLICE_X8Y8.D6), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 9.535ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<14> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_14 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 6.402ns (Levels of Logic = 2) + Clock Path Delay: -0.413ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<14> to interfaz_spi/controlador_spi_principal/word_int_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P9.I Tiopi 1.310 DATA_INOUT<14> + DATA_INOUT<14> + DATA_INOUT_14_IOBUF/IBUF + ProtoComp55.IMUX.16 + SLICE_X8Y8.D6 net (fanout=1) 4.803 N43 + SLICE_X8Y8.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi61 + interfaz_spi/controlador_spi_principal/word_int_14 + ------------------------------------------------- --------------------------- + Total 6.402ns (1.599ns logic, 4.803ns route) + (25.0% logic, 75.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.700 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.413ns (-2.456ns logic, 2.043ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_14 (SLICE_X8Y8.D6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.461ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<14> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_14 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.934ns (Levels of Logic = 2) + Clock Path Delay: 0.156ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<14> to interfaz_spi/controlador_spi_principal/word_int_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P9.I Tiopi 0.763 DATA_INOUT<14> + DATA_INOUT<14> + DATA_INOUT_14_IOBUF/IBUF + ProtoComp55.IMUX.16 + SLICE_X8Y8.D6 net (fanout=1) 2.974 N43 + SLICE_X8Y8.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi61 + interfaz_spi/controlador_spi_principal/word_int_14 + ------------------------------------------------- --------------------------- + Total 3.934ns (0.960ns logic, 2.974ns route) + (24.4% logic, 75.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.840 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.156ns (-1.582ns logic, 1.738ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 349 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.253ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<14> (P9.PAD), 349 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.414ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.255ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.A2 net (fanout=24) 2.317 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT131 + SLICE_X15Y39.A2 net (fanout=2) 0.665 nb_mem_cont/mux_data/Mmux_DATA_OUT11 + SLICE_X15Y39.A Tilo 0.259 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 3.122 nb_mem_cont/data_mux<14> + P9.PAD Tioop 2.381 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 13.255ns (3.864ns logic, 9.391ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.456ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.224ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.A2 net (fanout=24) 2.317 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT131 + SLICE_X15Y39.A2 net (fanout=2) 0.665 nb_mem_cont/mux_data/Mmux_DATA_OUT11 + SLICE_X15Y39.A Tilo 0.259 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 3.122 nb_mem_cont/data_mux<14> + P9.PAD Tioop 2.381 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 13.224ns (3.800ns logic, 9.424ns route) + (28.7% logic, 71.3% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.462ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.200ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.A2 net (fanout=24) 2.317 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT131 + SLICE_X15Y39.A2 net (fanout=2) 0.665 nb_mem_cont/mux_data/Mmux_DATA_OUT11 + SLICE_X15Y39.A Tilo 0.259 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 3.122 nb_mem_cont/data_mux<14> + P9.PAD Tioop 2.381 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 13.200ns (3.817ns logic, 9.383ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<14> (P9.PAD), 349 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.695ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.454ns (Levels of Logic = 3) + Clock Path Delay: -0.442ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y40.CLK net (fanout=226) 0.448 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.442ns (-1.698ns logic, 1.256ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y40.CQ Tcko 0.200 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14 + SLICE_X16Y40.A2 net (fanout=1) 0.347 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<14> + SLICE_X16Y40.A Tilo 0.156 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT132 + SLICE_X15Y39.A6 net (fanout=1) 0.164 nb_mem_cont/mux_data/Mmux_DATA_OUT131 + SLICE_X15Y39.A Tilo 0.156 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 2.035 nb_mem_cont/data_mux<14> + P9.PAD Tioop 1.396 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 4.454ns (1.908ns logic, 2.546ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.489ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.247ns (Levels of Logic = 3) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y40.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y40.CQ Tcko 0.234 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14 + SLICE_X16Y40.A4 net (fanout=1) 0.106 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<14> + SLICE_X16Y40.A Tilo 0.156 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT132 + SLICE_X15Y39.A6 net (fanout=1) 0.164 nb_mem_cont/mux_data/Mmux_DATA_OUT131 + SLICE_X15Y39.A Tilo 0.156 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 2.035 nb_mem_cont/data_mux<14> + P9.PAD Tioop 1.396 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 4.247ns (1.942ns logic, 2.305ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.324ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14 (FF) + Destination: DATA_INOUT<14> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.082ns (Levels of Logic = 2) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y39.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14 to DATA_INOUT<14> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y39.CQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14 + SLICE_X15Y39.A3 net (fanout=1) 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<14> + SLICE_X15Y39.A Tilo 0.156 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/mux_data/Mmux_DATA_OUT135 + P9.O net (fanout=1) 2.035 nb_mem_cont/data_mux<14> + P9.PAD Tioop 1.396 DATA_INOUT<14> + DATA_INOUT_14_IOBUF/OBUFT + DATA_INOUT<14> + ------------------------------------------------- --------------------------- + Total 4.082ns (1.786ns logic, 2.296ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.201ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_13 (SLICE_X8Y8.C6), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 9.466ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<13> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_13 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 6.471ns (Levels of Logic = 2) + Clock Path Delay: -0.413ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<13> to interfaz_spi/controlador_spi_principal/word_int_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P10.I Tiopi 1.310 DATA_INOUT<13> + DATA_INOUT<13> + DATA_INOUT_13_IOBUF/IBUF + ProtoComp55.IMUX.15 + SLICE_X8Y8.C6 net (fanout=1) 4.872 N44 + SLICE_X8Y8.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi51 + interfaz_spi/controlador_spi_principal/word_int_13 + ------------------------------------------------- --------------------------- + Total 6.471ns (1.599ns logic, 4.872ns route) + (24.7% logic, 75.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.700 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.413ns (-2.456ns logic, 2.043ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_13 (SLICE_X8Y8.C6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.481ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<13> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_13 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.954ns (Levels of Logic = 2) + Clock Path Delay: 0.156ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<13> to interfaz_spi/controlador_spi_principal/word_int_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P10.I Tiopi 0.763 DATA_INOUT<13> + DATA_INOUT<13> + DATA_INOUT_13_IOBUF/IBUF + ProtoComp55.IMUX.15 + SLICE_X8Y8.C6 net (fanout=1) 2.994 N44 + SLICE_X8Y8.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi51 + interfaz_spi/controlador_spi_principal/word_int_13 + ------------------------------------------------- --------------------------- + Total 3.954ns (0.960ns logic, 2.994ns route) + (24.3% logic, 75.7% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.840 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.156ns (-1.582ns logic, 1.738ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 349 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.781ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<13> (P10.PAD), 349 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.886ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.783ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.D5 net (fanout=24) 2.089 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT112 + SLICE_X15Y40.B2 net (fanout=1) 0.438 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + SLICE_X15Y40.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 3.105 nb_mem_cont/data_mux<13> + P10.PAD Tioop 2.381 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 12.783ns (3.864ns logic, 8.919ns route) + (30.2% logic, 69.8% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.928ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.752ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.D5 net (fanout=24) 2.089 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT112 + SLICE_X15Y40.B2 net (fanout=1) 0.438 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + SLICE_X15Y40.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 3.105 nb_mem_cont/data_mux<13> + P10.PAD Tioop 2.381 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 12.752ns (3.800ns logic, 8.952ns route) + (29.8% logic, 70.2% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.934ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.728ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X15Y40.D5 net (fanout=24) 2.089 nb_mem_cont/mux_data/_n0040 + SLICE_X15Y40.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT112 + SLICE_X15Y40.B2 net (fanout=1) 0.438 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + SLICE_X15Y40.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 3.105 nb_mem_cont/data_mux<13> + P10.PAD Tioop 2.381 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 12.728ns (3.817ns logic, 8.911ns route) + (30.0% logic, 70.0% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<13> (P10.PAD), 349 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.738ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.496ns (Levels of Logic = 3) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y40.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y40.BQ Tcko 0.234 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13 + SLICE_X15Y40.D3 net (fanout=1) 0.278 nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<13> + SLICE_X15Y40.D Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT112 + SLICE_X15Y40.B2 net (fanout=1) 0.253 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + SLICE_X15Y40.B Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 2.023 nb_mem_cont/data_mux<13> + P10.PAD Tioop 1.396 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 4.496ns (1.942ns logic, 2.554ns route) + (43.2% logic, 56.8% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.677ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.436ns (Levels of Logic = 3) + Clock Path Delay: -0.442ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y40.CLK net (fanout=226) 0.448 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.442ns (-1.698ns logic, 1.256ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y40.BQ Tcko 0.200 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13 + SLICE_X15Y40.D2 net (fanout=1) 0.252 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<13> + SLICE_X15Y40.D Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT112 + SLICE_X15Y40.B2 net (fanout=1) 0.253 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + SLICE_X15Y40.B Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 2.023 nb_mem_cont/data_mux<13> + P10.PAD Tioop 1.396 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 4.436ns (1.908ns logic, 2.528ns route) + (43.0% logic, 57.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.633ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13 (FF) + Destination: DATA_INOUT<13> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.391ns (Levels of Logic = 2) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y39.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13 to DATA_INOUT<13> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y39.BQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13 + SLICE_X15Y40.B1 net (fanout=1) 0.582 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<13> + SLICE_X15Y40.B Tilo 0.156 nb_mem_cont/mux_data/Mmux_DATA_OUT111 + nb_mem_cont/mux_data/Mmux_DATA_OUT115 + P10.O net (fanout=1) 2.023 nb_mem_cont/data_mux<13> + P10.PAD Tioop 1.396 DATA_INOUT<13> + DATA_INOUT_13_IOBUF/OBUFT + DATA_INOUT<13> + ------------------------------------------------- --------------------------- + Total 4.391ns (1.786ns logic, 2.605ns route) + (40.7% logic, 59.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.196ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_12 (SLICE_X8Y8.B5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 9.471ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<12> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_12 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 6.466ns (Levels of Logic = 2) + Clock Path Delay: -0.413ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<12> to interfaz_spi/controlador_spi_principal/word_int_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P11.I Tiopi 1.310 DATA_INOUT<12> + DATA_INOUT<12> + DATA_INOUT_12_IOBUF/IBUF + ProtoComp55.IMUX.14 + SLICE_X8Y8.B5 net (fanout=1) 4.867 N45 + SLICE_X8Y8.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi41 + interfaz_spi/controlador_spi_principal/word_int_12 + ------------------------------------------------- --------------------------- + Total 6.466ns (1.599ns logic, 4.867ns route) + (24.7% logic, 75.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.700 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.413ns (-2.456ns logic, 2.043ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_12 (SLICE_X8Y8.B5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.503ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<12> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_12 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.976ns (Levels of Logic = 2) + Clock Path Delay: 0.156ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<12> to interfaz_spi/controlador_spi_principal/word_int_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P11.I Tiopi 0.763 DATA_INOUT<12> + DATA_INOUT<12> + DATA_INOUT_12_IOBUF/IBUF + ProtoComp55.IMUX.14 + SLICE_X8Y8.B5 net (fanout=1) 3.016 N45 + SLICE_X8Y8.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi41 + interfaz_spi/controlador_spi_principal/word_int_12 + ------------------------------------------------- --------------------------- + Total 3.976ns (0.960ns logic, 3.016ns route) + (24.1% logic, 75.9% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.840 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.156ns (-1.582ns logic, 1.738ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 184 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.094ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<12> (P11.PAD), 184 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.573ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.096ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X17Y28.D5 net (fanout=9) 2.321 nb_mem_cont/oe_ch_vect<0> + SLICE_X17Y28.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/_n0028<4>11 + SLICE_X17Y28.C4 net (fanout=6) 0.308 nb_mem_cont/mux_data/_n0028<4>1 + SLICE_X17Y28.C Tilo 0.259 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/Mmux_DATA_OUT95 + SLICE_X16Y39.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT94 + SLICE_X16Y39.C Tilo 0.204 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT97 + P11.O net (fanout=1) 3.019 nb_mem_cont/data_mux<12> + P11.PAD Tioop 2.381 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 12.096ns (3.871ns logic, 8.225ns route) + (32.0% logic, 68.0% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.615ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.065ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X17Y28.D5 net (fanout=9) 2.321 nb_mem_cont/oe_ch_vect<0> + SLICE_X17Y28.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/_n0028<4>11 + SLICE_X17Y28.C4 net (fanout=6) 0.308 nb_mem_cont/mux_data/_n0028<4>1 + SLICE_X17Y28.C Tilo 0.259 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/Mmux_DATA_OUT95 + SLICE_X16Y39.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT94 + SLICE_X16Y39.C Tilo 0.204 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT97 + P11.O net (fanout=1) 3.019 nb_mem_cont/data_mux<12> + P11.PAD Tioop 2.381 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 12.065ns (3.807ns logic, 8.258ns route) + (31.6% logic, 68.4% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.754ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 11.925ns (Levels of Logic = 5) + Clock Path Delay: -0.329ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X10Y17.CLK net (fanout=226) 1.108 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.329ns (-3.088ns logic, 2.759ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X10Y17.BQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + SLICE_X5Y14.D3 net (fanout=16) 1.013 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X17Y28.D5 net (fanout=9) 2.321 nb_mem_cont/oe_ch_vect<0> + SLICE_X17Y28.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/_n0028<4>11 + SLICE_X17Y28.C4 net (fanout=6) 0.308 nb_mem_cont/mux_data/_n0028<4>1 + SLICE_X17Y28.C Tilo 0.259 nb_mem_cont/nibble_pack_ch5/_n0127_inv + nb_mem_cont/mux_data/Mmux_DATA_OUT95 + SLICE_X16Y39.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT94 + SLICE_X16Y39.C Tilo 0.204 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT97 + P11.O net (fanout=1) 3.019 nb_mem_cont/data_mux<12> + P11.PAD Tioop 2.381 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 11.925ns (3.824ns logic, 8.101ns route) + (32.1% logic, 67.9% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<12> (P11.PAD), 184 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.838ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.550ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P11.T net (fanout=16) 2.087 nb_mem_cont/io_sel/OEbar_inv + P11.PAD Tiotp 1.396 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 4.550ns (1.786ns logic, 2.764ns route) + (39.3% logic, 60.7% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.740ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.381ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P11.T net (fanout=16) 2.087 nb_mem_cont/io_sel/OEbar_inv + P11.PAD Tiotp 1.396 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 4.381ns (1.790ns logic, 2.591ns route) + (40.9% logic, 59.1% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.410ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12 (FF) + Destination: DATA_INOUT<12> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.168ns (Levels of Logic = 3) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y39.CLK net (fanout=226) 0.449 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-1.698ns logic, 1.257ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12 to DATA_INOUT<12> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y39.AQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12 + SLICE_X16Y39.A6 net (fanout=1) 0.017 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<12> + SLICE_X16Y39.A Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT92 + SLICE_X16Y39.C1 net (fanout=1) 0.241 nb_mem_cont/mux_data/Mmux_DATA_OUT91 + SLICE_X16Y39.C Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT97 + P11.O net (fanout=1) 1.968 nb_mem_cont/data_mux<12> + P11.PAD Tioop 1.396 DATA_INOUT<12> + DATA_INOUT_12_IOBUF/OBUFT + DATA_INOUT<12> + ------------------------------------------------- --------------------------- + Total 4.168ns (1.942ns logic, 2.226ns route) + (46.6% logic, 53.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.691ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_11 (SLICE_X8Y8.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 8.976ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<11> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_11 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 6.961ns (Levels of Logic = 2) + Clock Path Delay: -0.413ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<11> to interfaz_spi/controlador_spi_principal/word_int_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P12.I Tiopi 1.310 DATA_INOUT<11> + DATA_INOUT<11> + DATA_INOUT_11_IOBUF/IBUF + ProtoComp55.IMUX.13 + SLICE_X8Y8.A5 net (fanout=1) 5.362 N46 + SLICE_X8Y8.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/data_mux<11>1 + interfaz_spi/controlador_spi_principal/word_int_11 + ------------------------------------------------- --------------------------- + Total 6.961ns (1.599ns logic, 5.362ns route) + (23.0% logic, 77.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.700 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.413ns (-2.456ns logic, 2.043ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_11 (SLICE_X8Y8.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.780ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<11> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_11 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 4.253ns (Levels of Logic = 2) + Clock Path Delay: 0.156ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<11> to interfaz_spi/controlador_spi_principal/word_int_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P12.I Tiopi 0.763 DATA_INOUT<11> + DATA_INOUT<11> + DATA_INOUT_11_IOBUF/IBUF + ProtoComp55.IMUX.13 + SLICE_X8Y8.A5 net (fanout=1) 3.293 N46 + SLICE_X8Y8.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<14> + interfaz_spi/data_mux<11>1 + interfaz_spi/controlador_spi_principal/word_int_11 + ------------------------------------------------- --------------------------- + Total 4.253ns (0.960ns logic, 3.293ns route) + (22.6% logic, 77.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y8.CLK net (fanout=226) 0.840 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.156ns (-1.582ns logic, 1.738ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 184 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.308ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<11> (P12.PAD), 184 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.359ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.310ns (Levels of Logic = 4) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X16Y39.B2 net (fanout=9) 3.753 nb_mem_cont/oe_ch_vect<0> + SLICE_X16Y39.BMUX Tilo 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT93 + SLICE_X16Y38.A2 net (fanout=3) 0.629 nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X16Y38.A Tilo 0.203 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT77 + P12.O net (fanout=1) 3.232 nb_mem_cont/data_mux<11> + P12.PAD Tioop 2.381 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 12.310ns (3.559ns logic, 8.751ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.401ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.279ns (Levels of Logic = 4) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X16Y39.B2 net (fanout=9) 3.753 nb_mem_cont/oe_ch_vect<0> + SLICE_X16Y39.BMUX Tilo 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT93 + SLICE_X16Y38.A2 net (fanout=3) 0.629 nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X16Y38.A Tilo 0.203 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT77 + P12.O net (fanout=1) 3.232 nb_mem_cont/data_mux<11> + P12.PAD Tioop 2.381 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 12.279ns (3.495ns logic, 8.784ns route) + (28.5% logic, 71.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.540ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.139ns (Levels of Logic = 4) + Clock Path Delay: -0.329ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X10Y17.CLK net (fanout=226) 1.108 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.329ns (-3.088ns logic, 2.759ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X10Y17.BQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + SLICE_X5Y14.D3 net (fanout=16) 1.013 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X16Y39.B2 net (fanout=9) 3.753 nb_mem_cont/oe_ch_vect<0> + SLICE_X16Y39.BMUX Tilo 0.261 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15> + nb_mem_cont/mux_data/Mmux_DATA_OUT93 + SLICE_X16Y38.A2 net (fanout=3) 0.629 nb_mem_cont/mux_data/Mmux_DATA_OUT152 + SLICE_X16Y38.A Tilo 0.203 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT77 + P12.O net (fanout=1) 3.232 nb_mem_cont/data_mux<11> + P12.PAD Tioop 2.381 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 12.139ns (3.512ns logic, 8.627ns route) + (28.9% logic, 71.1% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<11> (P12.PAD), 184 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.773ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.529ns (Levels of Logic = 3) + Clock Path Delay: -0.439ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y38.CLK net (fanout=226) 0.451 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.439ns (-1.698ns logic, 1.259ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X14Y38.DQ Tcko 0.200 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11 + SLICE_X16Y38.C3 net (fanout=1) 0.274 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + SLICE_X16Y38.C Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT75 + SLICE_X16Y38.A1 net (fanout=1) 0.258 nb_mem_cont/mux_data/Mmux_DATA_OUT74 + SLICE_X16Y38.A Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT77 + P12.O net (fanout=1) 2.089 nb_mem_cont/data_mux<11> + P12.PAD Tioop 1.396 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 4.529ns (1.908ns logic, 2.621ns route) + (42.1% logic, 57.9% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.740ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.381ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P12.T net (fanout=16) 2.087 nb_mem_cont/io_sel/OEbar_inv + P12.PAD Tiotp 1.396 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 4.381ns (1.790ns logic, 2.591ns route) + (40.9% logic, 59.1% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.434ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11 (FF) + Destination: DATA_INOUT<11> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.190ns (Levels of Logic = 3) + Clock Path Delay: -0.439ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y38.CLK net (fanout=226) 0.451 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.439ns (-1.698ns logic, 1.259ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11 to DATA_INOUT<11> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y38.DQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11 + SLICE_X16Y38.D6 net (fanout=1) 0.017 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + SLICE_X16Y38.D Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT72 + SLICE_X16Y38.A3 net (fanout=1) 0.142 nb_mem_cont/mux_data/Mmux_DATA_OUT71 + SLICE_X16Y38.A Tilo 0.156 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT77 + P12.O net (fanout=1) 2.089 nb_mem_cont/data_mux<11> + P12.PAD Tioop 1.396 DATA_INOUT<11> + DATA_INOUT_11_IOBUF/OBUFT + DATA_INOUT<11> + ------------------------------------------------- --------------------------- + Total 4.190ns (1.942ns logic, 2.248ns route) + (46.3% logic, 53.7% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.982ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_10 (SLICE_X6Y8.D5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.685ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<10> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_10 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.260ns (Levels of Logic = 2) + Clock Path Delay: -0.405ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<10> to interfaz_spi/controlador_spi_principal/word_int_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P14.I Tiopi 1.310 DATA_INOUT<10> + DATA_INOUT<10> + DATA_INOUT_10_IOBUF/IBUF + ProtoComp55.IMUX.12 + SLICE_X6Y8.D5 net (fanout=1) 3.609 N47 + SLICE_X6Y8.CLK Tas 0.341 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi21 + interfaz_spi/controlador_spi_principal/word_int_10 + ------------------------------------------------- --------------------------- + Total 5.260ns (1.651ns logic, 3.609ns route) + (31.4% logic, 68.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.708 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.405ns (-2.456ns logic, 2.051ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_10 (SLICE_X6Y8.D5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.754ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<10> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_10 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.235ns (Levels of Logic = 2) + Clock Path Delay: 0.164ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<10> to interfaz_spi/controlador_spi_principal/word_int_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P14.I Tiopi 0.763 DATA_INOUT<10> + DATA_INOUT<10> + DATA_INOUT_10_IOBUF/IBUF + ProtoComp55.IMUX.12 + SLICE_X6Y8.D5 net (fanout=1) 2.282 N47 + SLICE_X6Y8.CLK Tah (-Th) -0.190 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi21 + interfaz_spi/controlador_spi_principal/word_int_10 + ------------------------------------------------- --------------------------- + Total 3.235ns (0.953ns logic, 2.282ns route) + (29.5% logic, 70.5% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.848 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.164ns (-1.582ns logic, 1.746ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 304 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.614ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<10> (P14.PAD), 304 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.053ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.616ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.D Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0034<4>1 + SLICE_X14Y38.B1 net (fanout=18) 1.909 nb_mem_cont/mux_data/_n0034 + SLICE_X14Y38.BMUX Tilo 0.251 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT51 + SLICE_X14Y38.D4 net (fanout=1) 0.857 nb_mem_cont/mux_data/Mmux_DATA_OUT5 + SLICE_X14Y38.CMUX Topdc 0.338 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT57_F + nb_mem_cont/mux_data/Mmux_DATA_OUT57 + P14.O net (fanout=1) 2.674 nb_mem_cont/data_mux<10> + P14.PAD Tioop 2.381 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 12.616ns (3.889ns logic, 8.727ns route) + (30.8% logic, 69.2% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.095ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.585ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.D Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0034<4>1 + SLICE_X14Y38.B1 net (fanout=18) 1.909 nb_mem_cont/mux_data/_n0034 + SLICE_X14Y38.BMUX Tilo 0.251 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT51 + SLICE_X14Y38.D4 net (fanout=1) 0.857 nb_mem_cont/mux_data/Mmux_DATA_OUT5 + SLICE_X14Y38.CMUX Topdc 0.338 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT57_F + nb_mem_cont/mux_data/Mmux_DATA_OUT57 + P14.O net (fanout=1) 2.674 nb_mem_cont/data_mux<10> + P14.PAD Tioop 2.381 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 12.585ns (3.825ns logic, 8.760ns route) + (30.4% logic, 69.6% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.101ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.561ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.D Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0034<4>1 + SLICE_X14Y38.B1 net (fanout=18) 1.909 nb_mem_cont/mux_data/_n0034 + SLICE_X14Y38.BMUX Tilo 0.251 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT51 + SLICE_X14Y38.D4 net (fanout=1) 0.857 nb_mem_cont/mux_data/Mmux_DATA_OUT5 + SLICE_X14Y38.CMUX Topdc 0.338 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT57_F + nb_mem_cont/mux_data/Mmux_DATA_OUT57 + P14.O net (fanout=1) 2.674 nb_mem_cont/data_mux<10> + P14.PAD Tioop 2.381 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 12.561ns (3.842ns logic, 8.719ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<10> (P14.PAD), 304 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.192ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.904ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P14.T net (fanout=16) 1.441 nb_mem_cont/io_sel/OEbar_inv + P14.PAD Tiotp 1.396 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 3.904ns (1.786ns logic, 2.118ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.109ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.865ns (Levels of Logic = 2) + Clock Path Delay: -0.439ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y38.CLK net (fanout=226) 0.451 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.439ns (-1.698ns logic, 1.259ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X16Y38.CQ Tcko 0.234 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11> + nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10 + SLICE_X14Y38.C4 net (fanout=1) 0.218 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<10> + SLICE_X14Y38.CMUX Tilo 0.234 nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT57_G + nb_mem_cont/mux_data/Mmux_DATA_OUT57 + P14.O net (fanout=1) 1.783 nb_mem_cont/data_mux<10> + P14.PAD Tioop 1.396 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 3.865ns (1.864ns logic, 2.001ns route) + (48.2% logic, 51.8% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.094ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<10> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.735ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<10> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P14.T net (fanout=16) 1.441 nb_mem_cont/io_sel/OEbar_inv + P14.PAD Tiotp 1.396 DATA_INOUT<10> + DATA_INOUT_10_IOBUF/OBUFT + DATA_INOUT<10> + ------------------------------------------------- --------------------------- + Total 3.735ns (1.790ns logic, 1.945ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 6.074ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_9 (SLICE_X6Y8.C6), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.593ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<9> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_9 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.352ns (Levels of Logic = 2) + Clock Path Delay: -0.405ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<9> to interfaz_spi/controlador_spi_principal/word_int_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P15.I Tiopi 1.310 DATA_INOUT<9> + DATA_INOUT<9> + DATA_INOUT_9_IOBUF/IBUF + ProtoComp55.IMUX.11 + SLICE_X6Y8.C6 net (fanout=1) 3.701 N48 + SLICE_X6Y8.CLK Tas 0.341 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi161 + interfaz_spi/controlador_spi_principal/word_int_9 + ------------------------------------------------- --------------------------- + Total 5.352ns (1.651ns logic, 3.701ns route) + (30.8% logic, 69.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.708 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.405ns (-2.456ns logic, 2.051ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_9 (SLICE_X6Y8.C6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.753ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<9> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_9 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.234ns (Levels of Logic = 2) + Clock Path Delay: 0.164ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<9> to interfaz_spi/controlador_spi_principal/word_int_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P15.I Tiopi 0.763 DATA_INOUT<9> + DATA_INOUT<9> + DATA_INOUT_9_IOBUF/IBUF + ProtoComp55.IMUX.11 + SLICE_X6Y8.C6 net (fanout=1) 2.281 N48 + SLICE_X6Y8.CLK Tah (-Th) -0.190 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi161 + interfaz_spi/controlador_spi_principal/word_int_9 + ------------------------------------------------- --------------------------- + Total 3.234ns (0.953ns logic, 2.281ns route) + (29.5% logic, 70.5% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.848 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.164ns (-1.582ns logic, 1.746ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 304 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.627ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<9> (P15.PAD), 304 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.040ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.629ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X17Y33.D2 net (fanout=24) 1.393 nb_mem_cont/mux_data/_n0040 + SLICE_X17Y33.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + nb_mem_cont/mux_data/Mmux_DATA_OUT401 + SLICE_X11Y25.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + SLICE_X11Y25.C Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/mux_data/Mmux_DATA_OUT407 + P15.O net (fanout=1) 2.645 nb_mem_cont/data_mux<9> + P15.PAD Tioop 2.381 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 12.629ns (3.864ns logic, 8.765ns route) + (30.6% logic, 69.4% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.082ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.598ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X17Y33.D2 net (fanout=24) 1.393 nb_mem_cont/mux_data/_n0040 + SLICE_X17Y33.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + nb_mem_cont/mux_data/Mmux_DATA_OUT401 + SLICE_X11Y25.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + SLICE_X11Y25.C Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/mux_data/Mmux_DATA_OUT407 + P15.O net (fanout=1) 2.645 nb_mem_cont/data_mux<9> + P15.PAD Tioop 2.381 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 12.598ns (3.800ns logic, 8.798ns route) + (30.2% logic, 69.8% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.088ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.574ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X17Y33.D2 net (fanout=24) 1.393 nb_mem_cont/mux_data/_n0040 + SLICE_X17Y33.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + nb_mem_cont/mux_data/Mmux_DATA_OUT401 + SLICE_X11Y25.C3 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT40 + SLICE_X11Y25.C Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/mux_data/Mmux_DATA_OUT407 + P15.O net (fanout=1) 2.645 nb_mem_cont/data_mux<9> + P15.PAD Tioop 2.381 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 12.574ns (3.817ns logic, 8.757ns route) + (30.4% logic, 69.6% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<9> (P15.PAD), 304 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.199ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.908ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P15.T net (fanout=16) 1.441 nb_mem_cont/io_sel/OEbar_inv + P15.PAD Tiotp 1.396 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 3.908ns (1.752ns logic, 2.156ns route) + (44.8% logic, 55.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.192ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.904ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P15.T net (fanout=16) 1.441 nb_mem_cont/io_sel/OEbar_inv + P15.PAD Tiotp 1.396 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 3.904ns (1.786ns logic, 2.118ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.094ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<9> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.735ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<9> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P15.T net (fanout=16) 1.441 nb_mem_cont/io_sel/OEbar_inv + P15.PAD Tiotp 1.396 DATA_INOUT<9> + DATA_INOUT_9_IOBUF/OBUFT + DATA_INOUT<9> + ------------------------------------------------- --------------------------- + Total 3.735ns (1.790ns logic, 1.945ns route) + (47.9% logic, 52.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.916ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_8 (SLICE_X6Y8.B6), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.751ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<8> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_8 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.194ns (Levels of Logic = 2) + Clock Path Delay: -0.405ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<8> to interfaz_spi/controlador_spi_principal/word_int_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P16.I Tiopi 1.310 DATA_INOUT<8> + DATA_INOUT<8> + DATA_INOUT_8_IOBUF/IBUF + ProtoComp55.IMUX.10 + SLICE_X6Y8.B6 net (fanout=1) 3.543 N49 + SLICE_X6Y8.CLK Tas 0.341 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi151 + interfaz_spi/controlador_spi_principal/word_int_8 + ------------------------------------------------- --------------------------- + Total 5.194ns (1.651ns logic, 3.543ns route) + (31.8% logic, 68.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.708 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.405ns (-2.456ns logic, 2.051ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_8 (SLICE_X6Y8.B6), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.696ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<8> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_8 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.177ns (Levels of Logic = 2) + Clock Path Delay: 0.164ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<8> to interfaz_spi/controlador_spi_principal/word_int_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P16.I Tiopi 0.763 DATA_INOUT<8> + DATA_INOUT<8> + DATA_INOUT_8_IOBUF/IBUF + ProtoComp55.IMUX.10 + SLICE_X6Y8.B6 net (fanout=1) 2.224 N49 + SLICE_X6Y8.CLK Tah (-Th) -0.190 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi151 + interfaz_spi/controlador_spi_principal/word_int_8 + ------------------------------------------------- --------------------------- + Total 3.177ns (0.953ns logic, 2.224ns route) + (30.0% logic, 70.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_8 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.848 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.164ns (-1.582ns logic, 1.746ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 349 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 12.820ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<8> (P16.PAD), 349 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.847ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.822ns (Levels of Logic = 6) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X14Y36.D5 net (fanout=24) 1.411 nb_mem_cont/mux_data/_n0040 + SLICE_X14Y36.D Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C6 net (fanout=1) 0.118 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0 + SLICE_X14Y25.B4 net (fanout=1) 1.099 N197 + SLICE_X14Y25.B Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/Mmux_DATA_OUT387 + P16.O net (fanout=1) 2.946 nb_mem_cont/data_mux<8> + P16.PAD Tioop 2.381 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 12.822ns (3.961ns logic, 8.861ns route) + (30.9% logic, 69.1% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.889ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.791ns (Levels of Logic = 6) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X14Y36.D5 net (fanout=24) 1.411 nb_mem_cont/mux_data/_n0040 + SLICE_X14Y36.D Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C6 net (fanout=1) 0.118 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0 + SLICE_X14Y25.B4 net (fanout=1) 1.099 N197 + SLICE_X14Y25.B Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/Mmux_DATA_OUT387 + P16.O net (fanout=1) 2.946 nb_mem_cont/data_mux<8> + P16.PAD Tioop 2.381 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 12.791ns (3.897ns logic, 8.894ns route) + (30.5% logic, 69.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.895ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 12.767ns (Levels of Logic = 6) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X14Y36.D5 net (fanout=24) 1.411 nb_mem_cont/mux_data/_n0040 + SLICE_X14Y36.D Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C6 net (fanout=1) 0.118 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + SLICE_X14Y36.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT385 + nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0 + SLICE_X14Y25.B4 net (fanout=1) 1.099 N197 + SLICE_X14Y25.B Tilo 0.205 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/Mmux_DATA_OUT387 + P16.O net (fanout=1) 2.946 nb_mem_cont/data_mux<8> + P16.PAD Tioop 2.381 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 12.767ns (3.914ns logic, 8.853ns route) + (30.7% logic, 69.3% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<8> (P16.PAD), 349 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.096ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.805ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P16.T net (fanout=16) 1.338 nb_mem_cont/io_sel/OEbar_inv + P16.PAD Tiotp 1.396 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 3.805ns (1.752ns logic, 2.053ns route) + (46.0% logic, 54.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.089ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.801ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P16.T net (fanout=16) 1.338 nb_mem_cont/io_sel/OEbar_inv + P16.PAD Tiotp 1.396 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 3.801ns (1.786ns logic, 2.015ns route) + (47.0% logic, 53.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 2.991ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<8> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.632ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<8> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P16.T net (fanout=16) 1.338 nb_mem_cont/io_sel/OEbar_inv + P16.PAD Tiotp 1.396 DATA_INOUT<8> + DATA_INOUT_8_IOBUF/OBUFT + DATA_INOUT<8> + ------------------------------------------------- --------------------------- + Total 3.632ns (1.790ns logic, 1.842ns route) + (49.3% logic, 50.7% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.791ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_7 (SLICE_X6Y8.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.876ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<7> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_7 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.069ns (Levels of Logic = 2) + Clock Path Delay: -0.405ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<7> to interfaz_spi/controlador_spi_principal/word_int_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P41.I Tiopi 1.310 DATA_INOUT<7> + DATA_INOUT<7> + DATA_INOUT_7_IOBUF/IBUF + ProtoComp55.IMUX.9 + SLICE_X6Y8.A5 net (fanout=1) 2.418 N50 + SLICE_X6Y8.CLK Tas 0.341 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi141 + interfaz_spi/controlador_spi_principal/word_int_7 + ------------------------------------------------- --------------------------- + Total 4.069ns (1.651ns logic, 2.418ns route) + (40.6% logic, 59.4% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.708 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.405ns (-2.456ns logic, 2.051ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_7 (SLICE_X6Y8.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.009ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<7> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_7 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.490ns (Levels of Logic = 2) + Clock Path Delay: 0.164ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<7> to interfaz_spi/controlador_spi_principal/word_int_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P41.I Tiopi 0.763 DATA_INOUT<7> + DATA_INOUT<7> + DATA_INOUT_7_IOBUF/IBUF + ProtoComp55.IMUX.9 + SLICE_X6Y8.A5 net (fanout=1) 1.537 N50 + SLICE_X6Y8.CLK Tah (-Th) -0.190 interfaz_spi/controlador_spi_principal/word_int<10> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi141 + interfaz_spi/controlador_spi_principal/word_int_7 + ------------------------------------------------- --------------------------- + Total 2.490ns (0.953ns logic, 1.537ns route) + (38.3% logic, 61.7% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y8.CLK net (fanout=226) 0.848 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.164ns (-1.582ns logic, 1.746ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.357ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<7> (P41.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.310ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.359ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X20Y33.D5 net (fanout=24) 1.425 nb_mem_cont/mux_data/_n0046 + SLICE_X20Y33.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + nb_mem_cont/mux_data/Mmux_DATA_OUT361 + SLICE_X16Y23.A2 net (fanout=1) 1.613 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X16Y23.A Tilo 0.203 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT368 + P41.O net (fanout=1) 3.533 nb_mem_cont/data_mux<7> + P41.PAD Tioop 2.381 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 13.359ns (3.706ns logic, 9.653ns route) + (27.7% logic, 72.3% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.352ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.328ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X20Y33.D5 net (fanout=24) 1.425 nb_mem_cont/mux_data/_n0046 + SLICE_X20Y33.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + nb_mem_cont/mux_data/Mmux_DATA_OUT361 + SLICE_X16Y23.A2 net (fanout=1) 1.613 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X16Y23.A Tilo 0.203 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT368 + P41.O net (fanout=1) 3.533 nb_mem_cont/data_mux<7> + P41.PAD Tioop 2.381 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 13.328ns (3.642ns logic, 9.686ns route) + (27.3% logic, 72.7% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.445ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.217ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y24.C3 net (fanout=11) 0.712 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X20Y33.D5 net (fanout=24) 1.425 nb_mem_cont/mux_data/_n0046 + SLICE_X20Y33.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + nb_mem_cont/mux_data/Mmux_DATA_OUT361 + SLICE_X16Y23.A2 net (fanout=1) 1.613 nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X16Y23.A Tilo 0.203 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11> + nb_mem_cont/mux_data/Mmux_DATA_OUT368 + P41.O net (fanout=1) 3.533 nb_mem_cont/data_mux<7> + P41.PAD Tioop 2.381 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 13.217ns (3.659ns logic, 9.558ns route) + (27.7% logic, 72.3% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<7> (P41.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.650ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.359ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P41.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P41.PAD Tiotp 1.396 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 4.359ns (1.752ns logic, 2.607ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.643ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.355ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P41.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P41.PAD Tiotp 1.396 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 4.355ns (1.786ns logic, 2.569ns route) + (41.0% logic, 59.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.545ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<7> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.186ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<7> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P41.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P41.PAD Tiotp 1.396 DATA_INOUT<7> + DATA_INOUT_7_IOBUF/OBUFT + DATA_INOUT<7> + ------------------------------------------------- --------------------------- + Total 4.186ns (1.790ns logic, 2.396ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.011ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_6 (SLICE_X9Y5.D1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.656ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<6> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_6 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.286ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<6> to interfaz_spi/controlador_spi_principal/word_int_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P40.I Tiopi 1.310 DATA_INOUT<6> + DATA_INOUT<6> + DATA_INOUT_6_IOBUF/IBUF + ProtoComp55.IMUX.8 + SLICE_X9Y5.D1 net (fanout=1) 2.654 N51 + SLICE_X9Y5.CLK Tas 0.322 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi131 + interfaz_spi/controlador_spi_principal/word_int_6 + ------------------------------------------------- --------------------------- + Total 4.286ns (1.632ns logic, 2.654ns route) + (38.1% logic, 61.9% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_6 (SLICE_X9Y5.D1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.222ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<6> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_6 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.700ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<6> to interfaz_spi/controlador_spi_principal/word_int_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P40.I Tiopi 0.763 DATA_INOUT<6> + DATA_INOUT<6> + DATA_INOUT_6_IOBUF/IBUF + ProtoComp55.IMUX.8 + SLICE_X9Y5.D1 net (fanout=1) 1.722 N51 + SLICE_X9Y5.CLK Tah (-Th) -0.215 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi131 + interfaz_spi/controlador_spi_principal/word_int_6 + ------------------------------------------------- --------------------------- + Total 2.700ns (0.978ns logic, 1.722ns route) + (36.2% logic, 63.8% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_6 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 14.600ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<6> (P40.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.067ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.602ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X19Y37.D1 net (fanout=24) 2.002 nb_mem_cont/mux_data/_n0040 + SLICE_X19Y37.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + nb_mem_cont/mux_data/Mmux_DATA_OUT336 + SLICE_X17Y21.A2 net (fanout=1) 1.933 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + SLICE_X17Y21.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT334 + nb_mem_cont/mux_data/Mmux_DATA_OUT338 + P40.O net (fanout=1) 3.516 nb_mem_cont/data_mux<6> + P40.PAD Tioop 2.381 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 14.602ns (3.864ns logic, 10.738ns route) + (26.5% logic, 73.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.109ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.571ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X19Y37.D1 net (fanout=24) 2.002 nb_mem_cont/mux_data/_n0040 + SLICE_X19Y37.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + nb_mem_cont/mux_data/Mmux_DATA_OUT336 + SLICE_X17Y21.A2 net (fanout=1) 1.933 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + SLICE_X17Y21.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT334 + nb_mem_cont/mux_data/Mmux_DATA_OUT338 + P40.O net (fanout=1) 3.516 nb_mem_cont/data_mux<6> + P40.PAD Tioop 2.381 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 14.571ns (3.800ns logic, 10.771ns route) + (26.1% logic, 73.9% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.115ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.547ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X19Y37.D1 net (fanout=24) 2.002 nb_mem_cont/mux_data/_n0040 + SLICE_X19Y37.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + nb_mem_cont/mux_data/Mmux_DATA_OUT336 + SLICE_X17Y21.A2 net (fanout=1) 1.933 nb_mem_cont/mux_data/Mmux_DATA_OUT335 + SLICE_X17Y21.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT334 + nb_mem_cont/mux_data/Mmux_DATA_OUT338 + P40.O net (fanout=1) 3.516 nb_mem_cont/data_mux<6> + P40.PAD Tioop 2.381 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 14.547ns (3.817ns logic, 10.730ns route) + (26.2% logic, 73.8% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<6> (P40.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.650ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.359ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P40.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P40.PAD Tiotp 1.396 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 4.359ns (1.752ns logic, 2.607ns route) + (40.2% logic, 59.8% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.643ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.355ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P40.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P40.PAD Tiotp 1.396 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 4.355ns (1.786ns logic, 2.569ns route) + (41.0% logic, 59.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.545ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<6> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.186ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<6> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P40.T net (fanout=16) 1.892 nb_mem_cont/io_sel/OEbar_inv + P40.PAD Tiotp 1.396 DATA_INOUT<6> + DATA_INOUT_6_IOBUF/OBUFT + DATA_INOUT<6> + ------------------------------------------------- --------------------------- + Total 4.186ns (1.790ns logic, 2.396ns route) + (42.8% logic, 57.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.683ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_5 (SLICE_X9Y5.C2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.984ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<5> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_5 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.958ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<5> to interfaz_spi/controlador_spi_principal/word_int_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P39.I Tiopi 1.310 DATA_INOUT<5> + DATA_INOUT<5> + DATA_INOUT_5_IOBUF/IBUF + ProtoComp55.IMUX.7 + SLICE_X9Y5.C2 net (fanout=1) 2.326 N52 + SLICE_X9Y5.CLK Tas 0.322 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi121 + interfaz_spi/controlador_spi_principal/word_int_5 + ------------------------------------------------- --------------------------- + Total 3.958ns (1.632ns logic, 2.326ns route) + (41.2% logic, 58.8% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_5 (SLICE_X9Y5.C2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.004ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<5> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_5 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.482ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<5> to interfaz_spi/controlador_spi_principal/word_int_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P39.I Tiopi 0.763 DATA_INOUT<5> + DATA_INOUT<5> + DATA_INOUT_5_IOBUF/IBUF + ProtoComp55.IMUX.7 + SLICE_X9Y5.C2 net (fanout=1) 1.504 N52 + SLICE_X9Y5.CLK Tah (-Th) -0.215 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi121 + interfaz_spi/controlador_spi_principal/word_int_5 + ------------------------------------------------- --------------------------- + Total 2.482ns (0.978ns logic, 1.504ns route) + (39.4% logic, 60.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_5 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 14.057ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<5> (P39.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.610ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.059ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X21Y34.D4 net (fanout=24) 1.717 nb_mem_cont/mux_data/_n0040 + SLICE_X21Y34.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + nb_mem_cont/mux_data/Mmux_DATA_OUT306 + SLICE_X20Y20.C1 net (fanout=1) 1.481 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + SLICE_X20Y20.C Tilo 0.204 nb_mem_cont/nibble_pack_ch5/rdy_mem_aux + nb_mem_cont/mux_data/Mmux_DATA_OUT308 + P39.O net (fanout=1) 3.765 nb_mem_cont/data_mux<5> + P39.PAD Tioop 2.381 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 14.059ns (3.809ns logic, 10.250ns route) + (27.1% logic, 72.9% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.652ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.028ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X21Y34.D4 net (fanout=24) 1.717 nb_mem_cont/mux_data/_n0040 + SLICE_X21Y34.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + nb_mem_cont/mux_data/Mmux_DATA_OUT306 + SLICE_X20Y20.C1 net (fanout=1) 1.481 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + SLICE_X20Y20.C Tilo 0.204 nb_mem_cont/nibble_pack_ch5/rdy_mem_aux + nb_mem_cont/mux_data/Mmux_DATA_OUT308 + P39.O net (fanout=1) 3.765 nb_mem_cont/data_mux<5> + P39.PAD Tioop 2.381 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 14.028ns (3.745ns logic, 10.283ns route) + (26.7% logic, 73.3% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.658ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 14.004ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X21Y34.D4 net (fanout=24) 1.717 nb_mem_cont/mux_data/_n0040 + SLICE_X21Y34.D Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + nb_mem_cont/mux_data/Mmux_DATA_OUT306 + SLICE_X20Y20.C1 net (fanout=1) 1.481 nb_mem_cont/mux_data/Mmux_DATA_OUT305 + SLICE_X20Y20.C Tilo 0.204 nb_mem_cont/nibble_pack_ch5/rdy_mem_aux + nb_mem_cont/mux_data/Mmux_DATA_OUT308 + P39.O net (fanout=1) 3.765 nb_mem_cont/data_mux<5> + P39.PAD Tioop 2.381 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 14.004ns (3.762ns logic, 10.242ns route) + (26.9% logic, 73.1% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<5> (P39.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.586ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.295ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P39.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P39.PAD Tiotp 1.396 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 4.295ns (1.752ns logic, 2.543ns route) + (40.8% logic, 59.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.579ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.291ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P39.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P39.PAD Tiotp 1.396 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 4.291ns (1.786ns logic, 2.505ns route) + (41.6% logic, 58.4% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.481ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<5> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.122ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<5> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P39.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P39.PAD Tiotp 1.396 DATA_INOUT<5> + DATA_INOUT_5_IOBUF/OBUFT + DATA_INOUT<5> + ------------------------------------------------- --------------------------- + Total 4.122ns (1.790ns logic, 2.332ns route) + (43.4% logic, 56.6% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.834ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_4 (SLICE_X9Y5.B1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.833ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<4> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_4 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.109ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<4> to interfaz_spi/controlador_spi_principal/word_int_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P38.I Tiopi 1.310 DATA_INOUT<4> + DATA_INOUT<4> + DATA_INOUT_4_IOBUF/IBUF + ProtoComp55.IMUX.6 + SLICE_X9Y5.B1 net (fanout=1) 2.477 N53 + SLICE_X9Y5.CLK Tas 0.322 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/data_mux<4>1 + interfaz_spi/controlador_spi_principal/word_int_4 + ------------------------------------------------- --------------------------- + Total 4.109ns (1.632ns logic, 2.477ns route) + (39.7% logic, 60.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_4 (SLICE_X9Y5.B1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.135ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<4> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_4 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.613ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<4> to interfaz_spi/controlador_spi_principal/word_int_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P38.I Tiopi 0.763 DATA_INOUT<4> + DATA_INOUT<4> + DATA_INOUT_4_IOBUF/IBUF + ProtoComp55.IMUX.6 + SLICE_X9Y5.B1 net (fanout=1) 1.635 N53 + SLICE_X9Y5.CLK Tah (-Th) -0.215 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/data_mux<4>1 + interfaz_spi/controlador_spi_principal/word_int_4 + ------------------------------------------------- --------------------------- + Total 2.613ns (0.978ns logic, 1.635ns route) + (37.4% logic, 62.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.747ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<4> (P38.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.920ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.749ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X23Y33.A2 net (fanout=24) 1.723 nb_mem_cont/mux_data/_n0046 + SLICE_X23Y33.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7> + nb_mem_cont/mux_data/Mmux_DATA_OUT271 + SLICE_X10Y16.C2 net (fanout=1) 2.279 nb_mem_cont/mux_data/Mmux_DATA_OUT27 + SLICE_X10Y16.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT274 + nb_mem_cont/mux_data/Mmux_DATA_OUT278 + P38.O net (fanout=1) 2.901 nb_mem_cont/data_mux<4> + P38.PAD Tioop 2.381 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 13.749ns (3.764ns logic, 9.985ns route) + (27.4% logic, 72.6% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.962ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.718ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X23Y33.A2 net (fanout=24) 1.723 nb_mem_cont/mux_data/_n0046 + SLICE_X23Y33.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7> + nb_mem_cont/mux_data/Mmux_DATA_OUT271 + SLICE_X10Y16.C2 net (fanout=1) 2.279 nb_mem_cont/mux_data/Mmux_DATA_OUT27 + SLICE_X10Y16.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT274 + nb_mem_cont/mux_data/Mmux_DATA_OUT278 + P38.O net (fanout=1) 2.901 nb_mem_cont/data_mux<4> + P38.PAD Tioop 2.381 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 13.718ns (3.700ns logic, 10.018ns route) + (27.0% logic, 73.0% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.055ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.607ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y24.C3 net (fanout=11) 0.712 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X23Y33.A2 net (fanout=24) 1.723 nb_mem_cont/mux_data/_n0046 + SLICE_X23Y33.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7> + nb_mem_cont/mux_data/Mmux_DATA_OUT271 + SLICE_X10Y16.C2 net (fanout=1) 2.279 nb_mem_cont/mux_data/Mmux_DATA_OUT27 + SLICE_X10Y16.C Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT274 + nb_mem_cont/mux_data/Mmux_DATA_OUT278 + P38.O net (fanout=1) 2.901 nb_mem_cont/data_mux<4> + P38.PAD Tioop 2.381 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 13.607ns (3.717ns logic, 9.890ns route) + (27.3% logic, 72.7% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<4> (P38.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.586ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.295ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P38.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P38.PAD Tiotp 1.396 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 4.295ns (1.752ns logic, 2.543ns route) + (40.8% logic, 59.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.579ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.291ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P38.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P38.PAD Tiotp 1.396 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 4.291ns (1.786ns logic, 2.505ns route) + (41.6% logic, 58.4% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.481ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<4> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.122ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<4> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P38.T net (fanout=16) 1.828 nb_mem_cont/io_sel/OEbar_inv + P38.PAD Tiotp 1.396 DATA_INOUT<4> + DATA_INOUT_4_IOBUF/OBUFT + DATA_INOUT<4> + ------------------------------------------------- --------------------------- + Total 4.122ns (1.790ns logic, 2.332ns route) + (43.4% logic, 56.6% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.773ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_3 (SLICE_X9Y5.A3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.894ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<3> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_3 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.048ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<3> to interfaz_spi/controlador_spi_principal/word_int_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P35.I Tiopi 1.310 DATA_INOUT<3> + DATA_INOUT<3> + DATA_INOUT_3_IOBUF/IBUF + ProtoComp55.IMUX.5 + SLICE_X9Y5.A3 net (fanout=1) 2.416 N54 + SLICE_X9Y5.CLK Tas 0.322 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/data_mux<3>1 + interfaz_spi/controlador_spi_principal/word_int_3 + ------------------------------------------------- --------------------------- + Total 4.048ns (1.632ns logic, 2.416ns route) + (40.3% logic, 59.7% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_3 (SLICE_X9Y5.A3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.073ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<3> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_3 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.551ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<3> to interfaz_spi/controlador_spi_principal/word_int_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P35.I Tiopi 0.763 DATA_INOUT<3> + DATA_INOUT<3> + DATA_INOUT_3_IOBUF/IBUF + ProtoComp55.IMUX.5 + SLICE_X9Y5.A3 net (fanout=1) 1.573 N54 + SLICE_X9Y5.CLK Tah (-Th) -0.215 interfaz_spi/controlador_spi_principal/word_int<6> + interfaz_spi/data_mux<3>1 + interfaz_spi/controlador_spi_principal/word_int_3 + ------------------------------------------------- --------------------------- + Total 2.551ns (0.978ns logic, 1.573ns route) + (38.3% logic, 61.7% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.461ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<3> (P35.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.206ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.463ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X22Y34.D5 net (fanout=24) 1.701 nb_mem_cont/mux_data/_n0046 + SLICE_X22Y34.D Tilo 0.205 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3> + nb_mem_cont/mux_data/Mmux_DATA_OUT241 + SLICE_X19Y23.A4 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT24 + SLICE_X19Y23.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT244 + nb_mem_cont/mux_data/Mmux_DATA_OUT248 + P35.O net (fanout=1) 3.476 nb_mem_cont/data_mux<3> + P35.PAD Tioop 2.381 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 13.463ns (3.764ns logic, 9.699ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.248ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.432ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y24.C2 net (fanout=9) 1.945 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X22Y34.D5 net (fanout=24) 1.701 nb_mem_cont/mux_data/_n0046 + SLICE_X22Y34.D Tilo 0.205 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3> + nb_mem_cont/mux_data/Mmux_DATA_OUT241 + SLICE_X19Y23.A4 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT24 + SLICE_X19Y23.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT244 + nb_mem_cont/mux_data/Mmux_DATA_OUT248 + P35.O net (fanout=1) 3.476 nb_mem_cont/data_mux<3> + P35.PAD Tioop 2.381 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 13.432ns (3.700ns logic, 9.732ns route) + (27.5% logic, 72.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.341ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.321ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y24.C3 net (fanout=11) 0.712 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y24.C Tilo 0.205 nb_mem_cont/oe_ch_vect<1> + nb_mem_cont/mux_data/_n0046<4>1 + SLICE_X22Y34.D5 net (fanout=24) 1.701 nb_mem_cont/mux_data/_n0046 + SLICE_X22Y34.D Tilo 0.205 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3> + nb_mem_cont/mux_data/Mmux_DATA_OUT241 + SLICE_X19Y23.A4 net (fanout=1) 1.440 nb_mem_cont/mux_data/Mmux_DATA_OUT24 + SLICE_X19Y23.A Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT244 + nb_mem_cont/mux_data/Mmux_DATA_OUT248 + P35.O net (fanout=1) 3.476 nb_mem_cont/data_mux<3> + P35.PAD Tioop 2.381 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 13.321ns (3.717ns logic, 9.604ns route) + (27.9% logic, 72.1% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<3> (P35.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.315ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.024ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P35.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P35.PAD Tiotp 1.396 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 4.024ns (1.752ns logic, 2.272ns route) + (43.5% logic, 56.5% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.308ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.020ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P35.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P35.PAD Tiotp 1.396 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 4.020ns (1.786ns logic, 2.234ns route) + (44.4% logic, 55.6% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.210ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<3> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<3> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P35.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P35.PAD Tiotp 1.396 DATA_INOUT<3> + DATA_INOUT_3_IOBUF/OBUFT + DATA_INOUT<3> + ------------------------------------------------- --------------------------- + Total 3.851ns (1.790ns logic, 2.061ns route) + (46.5% logic, 53.5% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.645ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_2 (SLICE_X8Y5.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.022ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<2> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_2 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.920ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<2> to interfaz_spi/controlador_spi_principal/word_int_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P34.I Tiopi 1.310 DATA_INOUT<2> + DATA_INOUT<2> + DATA_INOUT_2_IOBUF/IBUF + ProtoComp55.IMUX.4 + SLICE_X8Y5.D4 net (fanout=1) 2.321 N55 + SLICE_X8Y5.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/data_mux<2>1 + interfaz_spi/controlador_spi_principal/word_int_2 + ------------------------------------------------- --------------------------- + Total 3.920ns (1.599ns logic, 2.321ns route) + (40.8% logic, 59.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_2 (SLICE_X8Y5.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.974ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<2> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_2 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.452ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<2> to interfaz_spi/controlador_spi_principal/word_int_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P34.I Tiopi 0.763 DATA_INOUT<2> + DATA_INOUT<2> + DATA_INOUT_2_IOBUF/IBUF + ProtoComp55.IMUX.4 + SLICE_X8Y5.D4 net (fanout=1) 1.492 N55 + SLICE_X8Y5.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/data_mux<2>1 + interfaz_spi/controlador_spi_principal/word_int_2 + ------------------------------------------------- --------------------------- + Total 2.452ns (0.960ns logic, 1.492ns route) + (39.2% logic, 60.8% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.384ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<2> (P34.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.283ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.386ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X20Y31.D4 net (fanout=24) 1.382 nb_mem_cont/mux_data/_n0040 + SLICE_X20Y31.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + nb_mem_cont/mux_data/Mmux_DATA_OUT216 + SLICE_X18Y25.A1 net (fanout=1) 1.340 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + SLICE_X18Y25.A Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT211 + nb_mem_cont/mux_data/Mmux_DATA_OUT218 + P34.O net (fanout=1) 3.623 nb_mem_cont/data_mux<2> + P34.PAD Tioop 2.381 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 13.386ns (3.754ns logic, 9.632ns route) + (28.0% logic, 72.0% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.325ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.355ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X20Y31.D4 net (fanout=24) 1.382 nb_mem_cont/mux_data/_n0040 + SLICE_X20Y31.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + nb_mem_cont/mux_data/Mmux_DATA_OUT216 + SLICE_X18Y25.A1 net (fanout=1) 1.340 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + SLICE_X18Y25.A Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT211 + nb_mem_cont/mux_data/Mmux_DATA_OUT218 + P34.O net (fanout=1) 3.623 nb_mem_cont/data_mux<2> + P34.PAD Tioop 2.381 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 13.355ns (3.690ns logic, 9.665ns route) + (27.6% logic, 72.4% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.331ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.331ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X20Y31.D4 net (fanout=24) 1.382 nb_mem_cont/mux_data/_n0040 + SLICE_X20Y31.D Tilo 0.203 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + nb_mem_cont/mux_data/Mmux_DATA_OUT216 + SLICE_X18Y25.A1 net (fanout=1) 1.340 nb_mem_cont/mux_data/Mmux_DATA_OUT215 + SLICE_X18Y25.A Tilo 0.205 nb_mem_cont/mux_data/Mmux_DATA_OUT211 + nb_mem_cont/mux_data/Mmux_DATA_OUT218 + P34.O net (fanout=1) 3.623 nb_mem_cont/data_mux<2> + P34.PAD Tioop 2.381 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 13.331ns (3.707ns logic, 9.624ns route) + (27.8% logic, 72.2% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<2> (P34.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.315ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.024ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P34.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P34.PAD Tiotp 1.396 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 4.024ns (1.752ns logic, 2.272ns route) + (43.5% logic, 56.5% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.308ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.020ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P34.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P34.PAD Tiotp 1.396 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 4.020ns (1.786ns logic, 2.234ns route) + (44.4% logic, 55.6% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.210ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<2> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.851ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<2> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P34.T net (fanout=16) 1.557 nb_mem_cont/io_sel/OEbar_inv + P34.PAD Tiotp 1.396 DATA_INOUT<2> + DATA_INOUT_2_IOBUF/OBUFT + DATA_INOUT<2> + ------------------------------------------------- --------------------------- + Total 3.851ns (1.790ns logic, 2.061ns route) + (46.5% logic, 53.5% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.790ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_1 (SLICE_X8Y5.C4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.877ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<1> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.065ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<1> to interfaz_spi/controlador_spi_principal/word_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P33.I Tiopi 1.310 DATA_INOUT<1> + DATA_INOUT<1> + DATA_INOUT_1_IOBUF/IBUF + ProtoComp55.IMUX.3 + SLICE_X8Y5.C4 net (fanout=1) 2.466 N56 + SLICE_X8Y5.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/data_mux<1>1 + interfaz_spi/controlador_spi_principal/word_int_1 + ------------------------------------------------- --------------------------- + Total 4.065ns (1.599ns logic, 2.466ns route) + (39.3% logic, 60.7% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_1 (SLICE_X8Y5.C4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.068ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<1> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.546ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<1> to interfaz_spi/controlador_spi_principal/word_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P33.I Tiopi 0.763 DATA_INOUT<1> + DATA_INOUT<1> + DATA_INOUT_1_IOBUF/IBUF + ProtoComp55.IMUX.3 + SLICE_X8Y5.C4 net (fanout=1) 1.586 N56 + SLICE_X8Y5.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/data_mux<1>1 + interfaz_spi/controlador_spi_principal/word_int_1 + ------------------------------------------------- --------------------------- + Total 2.546ns (0.960ns logic, 1.586ns route) + (37.7% logic, 62.3% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.456ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<1> (P33.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.211ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.450ns (Levels of Logic = 5) + Clock Path Delay: -0.311ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X3Y16.CLK net (fanout=226) 1.126 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.311ns (-3.088ns logic, 2.777ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X3Y16.CMUX Tshcko 0.461 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd6 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9 + SLICE_X5Y18.B6 net (fanout=5) 0.902 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9 + SLICE_X5Y18.B Tilo 0.259 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11 + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>2 + SLICE_X11Y25.D3 net (fanout=2) 1.207 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11 + SLICE_X11Y25.D Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3 + SLICE_X15Y42.D1 net (fanout=56) 2.343 nb_mem_cont/hb_lbbar + SLICE_X15Y42.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110 + nb_mem_cont/mux_data/Mmux_DATA_OUT187 + SLICE_X19Y21.A3 net (fanout=1) 1.822 nb_mem_cont/mux_data/Mmux_DATA_OUT186 + SLICE_X19Y21.A Tilo 0.259 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19> + nb_mem_cont/mux_data/Mmux_DATA_OUT188 + P33.O net (fanout=1) 3.244 nb_mem_cont/data_mux<1> + P33.PAD Tioop 2.381 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 13.450ns (3.932ns logic, 9.518ns route) + (29.2% logic, 70.8% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.244ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.418ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19 + SLICE_X5Y18.B3 net (fanout=5) 0.876 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19 + SLICE_X5Y18.B Tilo 0.259 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11 + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>2 + SLICE_X11Y25.D3 net (fanout=2) 1.207 nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11 + SLICE_X11Y25.D Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3 + SLICE_X15Y42.D1 net (fanout=56) 2.343 nb_mem_cont/hb_lbbar + SLICE_X15Y42.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110 + nb_mem_cont/mux_data/Mmux_DATA_OUT187 + SLICE_X19Y21.A3 net (fanout=1) 1.822 nb_mem_cont/mux_data/Mmux_DATA_OUT186 + SLICE_X19Y21.A Tilo 0.259 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19> + nb_mem_cont/mux_data/Mmux_DATA_OUT188 + P33.O net (fanout=1) 3.244 nb_mem_cont/data_mux<1> + P33.PAD Tioop 2.381 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 13.418ns (3.926ns logic, 9.492ns route) + (29.3% logic, 70.7% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.250ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.419ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y16.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y16.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37 + SLICE_X8Y24.B2 net (fanout=5) 1.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37 + SLICE_X8Y24.B Tilo 0.203 nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>1 + SLICE_X11Y25.D2 net (fanout=1) 0.636 nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8> + SLICE_X11Y25.D Tilo 0.259 nb_mem_cont/hb_lbbar + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3 + SLICE_X15Y42.D1 net (fanout=56) 2.343 nb_mem_cont/hb_lbbar + SLICE_X15Y42.DMUX Tilo 0.313 nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110 + nb_mem_cont/mux_data/Mmux_DATA_OUT187 + SLICE_X19Y21.A3 net (fanout=1) 1.822 nb_mem_cont/mux_data/Mmux_DATA_OUT186 + SLICE_X19Y21.A Tilo 0.259 nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19> + nb_mem_cont/mux_data/Mmux_DATA_OUT188 + P33.O net (fanout=1) 3.244 nb_mem_cont/data_mux<1> + P33.PAD Tioop 2.381 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 13.419ns (3.870ns logic, 9.549ns route) + (28.8% logic, 71.2% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<1> (P33.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.293ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.002ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P33.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P33.PAD Tiotp 1.396 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 4.002ns (1.752ns logic, 2.250ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.286ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.998ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P33.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P33.PAD Tiotp 1.396 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 3.998ns (1.786ns logic, 2.212ns route) + (44.7% logic, 55.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.188ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<1> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.829ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<1> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P33.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P33.PAD Tiotp 1.396 DATA_INOUT<1> + DATA_INOUT_1_IOBUF/OBUFT + DATA_INOUT<1> + ------------------------------------------------- --------------------------- + Total 3.829ns (1.790ns logic, 2.039ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.440ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_0 (SLICE_X8Y5.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.227ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: DATA_INOUT<0> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.715ns (Levels of Logic = 2) + Clock Path Delay: -0.408ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: DATA_INOUT<0> to interfaz_spi/controlador_spi_principal/word_int_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P32.I Tiopi 1.310 DATA_INOUT<0> + DATA_INOUT<0> + DATA_INOUT_0_IOBUF/IBUF + ProtoComp55.IMUX.2 + SLICE_X8Y5.A5 net (fanout=1) 2.116 N57 + SLICE_X8Y5.CLK Tas 0.289 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi11 + interfaz_spi/controlador_spi_principal/word_int_0 + ------------------------------------------------- --------------------------- + Total 3.715ns (1.599ns logic, 2.116ns route) + (43.0% logic, 57.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.705 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.408ns (-2.456ns logic, 2.048ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_principal/word_int_0 (SLICE_X8Y5.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.842ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: DATA_INOUT<0> (PAD) + Destination: interfaz_spi/controlador_spi_principal/word_int_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.320ns (Levels of Logic = 2) + Clock Path Delay: 0.161ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: DATA_INOUT<0> to interfaz_spi/controlador_spi_principal/word_int_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P32.I Tiopi 0.763 DATA_INOUT<0> + DATA_INOUT<0> + DATA_INOUT_0_IOBUF/IBUF + ProtoComp55.IMUX.2 + SLICE_X8Y5.A5 net (fanout=1) 1.360 N57 + SLICE_X8Y5.CLK Tah (-Th) -0.197 interfaz_spi/controlador_spi_principal/word_int<2> + interfaz_spi/multiplexor_ram_header/Mmux_data_tospi11 + interfaz_spi/controlador_spi_principal/word_int_0 + ------------------------------------------------- --------------------------- + Total 2.320ns (0.960ns logic, 1.360ns route) + (41.4% logic, 58.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_principal/word_int_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y5.CLK net (fanout=226) 0.845 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.161ns (-1.582ns logic, 1.743ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 339 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.530ns. +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<0> (P32.PAD), 339 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.137ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.532ns (Levels of Logic = 5) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D2 net (fanout=5) 1.137 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X23Y35.A5 net (fanout=24) 1.663 nb_mem_cont/mux_data/_n0040 + SLICE_X23Y35.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23> + nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X15Y24.B6 net (fanout=1) 1.300 nb_mem_cont/mux_data/Mmux_DATA_OUT37 + SLICE_X15Y24.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT35 + nb_mem_cont/mux_data/Mmux_DATA_OUT39 + P32.O net (fanout=1) 3.418 nb_mem_cont/data_mux<0> + P32.PAD Tioop 2.381 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 13.532ns (3.864ns logic, 9.668ns route) + (28.6% logic, 71.4% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.179ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.501ns (Levels of Logic = 5) + Clock Path Delay: -0.330ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X11Y18.CLK net (fanout=226) 1.107 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.330ns (-3.088ns logic, 2.758ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X11Y18.CQ Tcko 0.391 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D4 net (fanout=14) 1.170 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30 + SLICE_X5Y14.D Tilo 0.259 nb_mem_cont/oe_ch_vect<0> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1 + SLICE_X14Y25.D1 net (fanout=9) 2.150 nb_mem_cont/oe_ch_vect<0> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X23Y35.A5 net (fanout=24) 1.663 nb_mem_cont/mux_data/_n0040 + SLICE_X23Y35.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23> + nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X15Y24.B6 net (fanout=1) 1.300 nb_mem_cont/mux_data/Mmux_DATA_OUT37 + SLICE_X15Y24.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT35 + nb_mem_cont/mux_data/Mmux_DATA_OUT39 + P32.O net (fanout=1) 3.418 nb_mem_cont/data_mux<0> + P32.PAD Tioop 2.381 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 13.501ns (3.800ns logic, 9.701ns route) + (28.1% logic, 71.9% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.185ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.477ns (Levels of Logic = 5) + Clock Path Delay: -0.312ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y17.CLK net (fanout=226) 1.125 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.312ns (-3.088ns logic, 2.776ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y17.CQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B1 net (fanout=4) 2.275 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16 + SLICE_X13Y23.B Tilo 0.259 nb_mem_cont/oe_ch_vect<2> + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1 + SLICE_X14Y25.D2 net (fanout=11) 1.004 nb_mem_cont/oe_ch_vect<2> + SLICE_X14Y25.DMUX Tilo 0.251 nb_mem_cont/mux_data/_n0034 + nb_mem_cont/mux_data/_n0040<4>2 + SLICE_X23Y35.A5 net (fanout=24) 1.663 nb_mem_cont/mux_data/_n0040 + SLICE_X23Y35.A Tilo 0.259 nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23> + nb_mem_cont/mux_data/Mmux_DATA_OUT36 + SLICE_X15Y24.B6 net (fanout=1) 1.300 nb_mem_cont/mux_data/Mmux_DATA_OUT37 + SLICE_X15Y24.B Tilo 0.259 nb_mem_cont/mux_data/Mmux_DATA_OUT35 + nb_mem_cont/mux_data/Mmux_DATA_OUT39 + P32.O net (fanout=1) 3.418 nb_mem_cont/data_mux<0> + P32.PAD Tioop 2.381 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 13.477ns (3.817ns logic, 9.660ns route) + (28.3% logic, 71.7% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point DATA_INOUT<0> (P32.PAD), 339 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.293ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.002ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A5 net (fanout=7) 0.715 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P32.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P32.PAD Tiotp 1.396 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 4.002ns (1.752ns logic, 2.250ns route) + (43.8% logic, 56.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.286ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.998ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A2 net (fanout=19) 0.677 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P32.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P32.PAD Tiotp 1.396 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 3.998ns (1.786ns logic, 2.212ns route) + (44.7% logic, 55.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.188ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: DATA_INOUT<0> (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.829ns (Levels of Logic = 2) + Clock Path Delay: -0.324ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 0.566 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.324ns (-1.698ns logic, 1.374ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to DATA_INOUT<0> + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A3 net (fanout=8) 0.504 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X3Y20.A Tilo 0.156 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21 + nb_mem_cont/io_sel/OEbar_inv1 + P32.T net (fanout=16) 1.535 nb_mem_cont/io_sel/OEbar_inv + P32.PAD Tiotp 1.396 DATA_INOUT<0> + DATA_INOUT_0_IOBUF/OBUFT + DATA_INOUT<0> + ------------------------------------------------- --------------------------- + Total 3.829ns (1.790ns logic, 2.039ns route) + (46.7% logic, 53.3% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE +COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 3.976ns. +-------------------------------------------------------------------------------- + +Paths for end point i2c_comp/SDAoe (SLICE_X23Y26.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.691ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: sda_rpi (PAD) + Destination: i2c_comp/SDAoe (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.165ns (Levels of Logic = 2) + Clock Path Delay: -0.494ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: sda_rpi to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P83.I Tiopi 1.300 sda_rpi + sda_rpi + sda_rpi_IOBUF/IBUF + ProtoComp55.IMUX + SLICE_X23Y26.D4 net (fanout=1) 1.543 N59 + SLICE_X23Y26.CLK Tas 0.322 i2c_comp/SDAoe + i2c_comp/SDAoe_rstpot + i2c_comp/SDAoe + ------------------------------------------------- --------------------------- + Total 3.165ns (1.622ns logic, 1.543ns route) + (51.2% logic, 48.8% route) + + Minimum Clock Path at Slow Process Corner: clk_main to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y26.CLK net (fanout=226) 0.619 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.494ns (-2.456ns logic, 1.962ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point i2c_comp/SDAoe (SLICE_X23Y26.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.530ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: sda_rpi (PAD) + Destination: i2c_comp/SDAoe (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 1.922ns (Levels of Logic = 2) + Clock Path Delay: 0.075ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: sda_rpi to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P83.I Tiopi 0.754 sda_rpi + sda_rpi + sda_rpi_IOBUF/IBUF + ProtoComp55.IMUX + SLICE_X23Y26.D4 net (fanout=1) 0.953 N59 + SLICE_X23Y26.CLK Tah (-Th) -0.215 i2c_comp/SDAoe + i2c_comp/SDAoe_rstpot + i2c_comp/SDAoe + ------------------------------------------------- --------------------------- + Total 1.922ns (0.969ns logic, 0.953ns route) + (50.4% logic, 49.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y26.CLK net (fanout=226) 0.759 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.075ns (-1.582ns logic, 1.657ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.152ns. +-------------------------------------------------------------------------------- + +Paths for end point sda_rpi (P83.PAD), 1 path +-------------------------------------------------------------------------------- +Slack (slowest paths): 3.515ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: i2c_comp/SDAoe (FF) + Destination: sda_rpi (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.194ns (Levels of Logic = 1) + Clock Path Delay: -0.359ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y26.CLK net (fanout=226) 1.078 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.359ns (-3.088ns logic, 2.729ns route) + + Maximum Data Path at Slow Process Corner: i2c_comp/SDAoe to sda_rpi + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X23Y26.DQ Tcko 0.391 i2c_comp/SDAoe + i2c_comp/SDAoe + P83.T net (fanout=2) 1.252 i2c_comp/SDAoe + P83.PAD Tiotp 11.551 sda_rpi + sda_rpi_IOBUF/OBUFT + sda_rpi + ------------------------------------------------- --------------------------- + Total 13.194ns (11.942ns logic, 1.252ns route) + (90.5% logic, 9.5% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point sda_rpi (P83.PAD), 1 path +-------------------------------------------------------------------------------- +Delay (fastest paths): 10.248ns (clock arrival + clock path + data path - uncertainty) + Source: i2c_comp/SDAoe (FF) + Destination: sda_rpi (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 10.997ns (Levels of Logic = 1) + Clock Path Delay: -0.432ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to i2c_comp/SDAoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y26.CLK net (fanout=226) 0.458 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.432ns (-1.698ns logic, 1.266ns route) + + Minimum Data Path at Fast Process Corner: i2c_comp/SDAoe to sda_rpi + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X23Y26.DQ Tcko 0.198 i2c_comp/SDAoe + i2c_comp/SDAoe + P83.T net (fanout=2) 0.768 i2c_comp/SDAoe + P83.PAD Tiotp 10.031 sda_rpi + sda_rpi_IOBUF/OBUFT + sda_rpi + ------------------------------------------------- --------------------------- + Total 10.997ns (10.229ns logic, 0.768ns route) + (93.0% logic, 7.0% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE +COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.954ns. +-------------------------------------------------------------------------------- + +Paths for end point i2c_comp/flanco_SCL_0 (SLICE_X22Y8.AX), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.713ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: scl_rpi (PAD) + Destination: i2c_comp/flanco_SCL_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.201ns (Levels of Logic = 1) + Clock Path Delay: -0.436ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: scl_rpi to i2c_comp/flanco_SCL_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P85.I Tiopi 1.300 scl_rpi + scl_rpi + scl_rpi_IOBUF/IBUF + ProtoComp55.IMUX.1 + SLICE_X22Y8.AX net (fanout=1) 2.765 N58 + SLICE_X22Y8.CLK Tdick 0.136 i2c_comp/flanco_SCL<1> + i2c_comp/flanco_SCL_0 + ------------------------------------------------- --------------------------- + Total 4.201ns (1.436ns logic, 2.765ns route) + (34.2% logic, 65.8% route) + + Minimum Clock Path at Slow Process Corner: clk_main to i2c_comp/flanco_SCL_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y8.CLK net (fanout=226) 0.677 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.436ns (-2.456ns logic, 2.020ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point i2c_comp/flanco_SCL_0 (SLICE_X22Y8.AX), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.053ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: scl_rpi (PAD) + Destination: i2c_comp/flanco_SCL_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.503ns (Levels of Logic = 1) + Clock Path Delay: 0.133ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: scl_rpi to i2c_comp/flanco_SCL_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P85.I Tiopi 0.754 scl_rpi + scl_rpi + scl_rpi_IOBUF/IBUF + ProtoComp55.IMUX.1 + SLICE_X22Y8.AX net (fanout=1) 1.701 N58 + SLICE_X22Y8.CLK Tckdi (-Th) -0.048 i2c_comp/flanco_SCL<1> + i2c_comp/flanco_SCL_0 + ------------------------------------------------- --------------------------- + Total 2.503ns (0.802ns logic, 1.701ns route) + (32.0% logic, 68.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to i2c_comp/flanco_SCL_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y8.CLK net (fanout=226) 0.817 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.133ns (-1.582ns logic, 1.715ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 13.744ns. +-------------------------------------------------------------------------------- + +Paths for end point scl_rpi (P85.PAD), 1 path +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.923ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: i2c_comp/SCLoe (FF) + Destination: scl_rpi (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 13.788ns (Levels of Logic = 1) + Clock Path Delay: -0.361ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to i2c_comp/SCLoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y22.CLK net (fanout=226) 1.076 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.361ns (-3.088ns logic, 2.727ns route) + + Maximum Data Path at Slow Process Corner: i2c_comp/SCLoe to scl_rpi + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X23Y22.AQ Tcko 0.391 i2c_comp/SCLoe + i2c_comp/SCLoe + P85.T net (fanout=2) 1.846 i2c_comp/SCLoe + P85.PAD Tiotp 11.551 scl_rpi + scl_rpi_IOBUF/OBUFT + scl_rpi + ------------------------------------------------- --------------------------- + Total 13.788ns (11.942ns logic, 1.846ns route) + (86.6% logic, 13.4% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point scl_rpi (P85.PAD), 1 path +-------------------------------------------------------------------------------- +Delay (fastest paths): 10.608ns (clock arrival + clock path + data path - uncertainty) + Source: i2c_comp/SCLoe (FF) + Destination: scl_rpi (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 11.359ns (Levels of Logic = 1) + Clock Path Delay: -0.434ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to i2c_comp/SCLoe + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y22.CLK net (fanout=226) 0.456 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.434ns (-1.698ns logic, 1.264ns route) + + Minimum Data Path at Fast Process Corner: i2c_comp/SCLoe to scl_rpi + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X23Y22.AQ Tcko 0.198 i2c_comp/SCLoe + i2c_comp/SCLoe + P85.T net (fanout=2) 1.130 i2c_comp/SCLoe + P85.PAD Tiotp 10.031 scl_rpi + scl_rpi_IOBUF/OBUFT + scl_rpi + ------------------------------------------------- --------------------------- + Total 11.359ns (10.229ns logic, 1.130ns route) + (90.1% logic, 9.9% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.505ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (SLICE_X22Y52.B3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.162ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch1<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.759ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch1<3> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P116.I Tiopi 1.310 chn_bits_acq_ch1<3> + chn_bits_acq_ch1<3> + chn_bits_acq_ch1_3_IBUF + ProtoComp52.IMUX.7 + SLICE_X22Y52.B3 net (fanout=1) 2.236 chn_bits_acq_ch1_3_IBUF + SLICE_X22Y52.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 3.759ns (1.523ns logic, 2.236ns route) + (40.5% logic, 59.5% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (SLICE_X22Y52.B3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.822ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch1<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.279ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch1<3> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P116.I Tiopi 0.763 chn_bits_acq_ch1<3> + chn_bits_acq_ch1<3> + chn_bits_acq_ch1_3_IBUF + ProtoComp52.IMUX.7 + SLICE_X22Y52.B3 net (fanout=1) 1.395 chn_bits_acq_ch1_3_IBUF + SLICE_X22Y52.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 2.279ns (0.884ns logic, 1.395ns route) + (38.8% logic, 61.2% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.386ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (SLICE_X22Y52.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.281ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch1<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.640ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch1<2> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P115.I Tiopi 1.310 chn_bits_acq_ch1<2> + chn_bits_acq_ch1<2> + chn_bits_acq_ch1_2_IBUF + ProtoComp52.IMUX.6 + SLICE_X22Y52.A5 net (fanout=1) 2.117 chn_bits_acq_ch1_2_IBUF + SLICE_X22Y52.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 3.640ns (1.523ns logic, 2.117ns route) + (41.8% logic, 58.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (SLICE_X22Y52.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.744ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch1<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.201ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch1<2> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P115.I Tiopi 0.763 chn_bits_acq_ch1<2> + chn_bits_acq_ch1<2> + chn_bits_acq_ch1_2_IBUF + ProtoComp52.IMUX.6 + SLICE_X22Y52.A5 net (fanout=1) 1.317 chn_bits_acq_ch1_2_IBUF + SLICE_X22Y52.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 2.201ns (0.884ns logic, 1.317ns route) + (40.2% logic, 59.8% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.578ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (SLICE_X22Y52.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.089ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch1<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.832ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch1<1> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P114.I Tiopi 1.310 chn_bits_acq_ch1<1> + chn_bits_acq_ch1<1> + chn_bits_acq_ch1_1_IBUF + ProtoComp52.IMUX.5 + SLICE_X22Y52.D4 net (fanout=1) 2.309 chn_bits_acq_ch1_1_IBUF + SLICE_X22Y52.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 3.832ns (1.523ns logic, 2.309ns route) + (39.7% logic, 60.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (SLICE_X22Y52.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.907ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch1<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.364ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch1<1> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P114.I Tiopi 0.763 chn_bits_acq_ch1<1> + chn_bits_acq_ch1<1> + chn_bits_acq_ch1_1_IBUF + ProtoComp52.IMUX.5 + SLICE_X22Y52.D4 net (fanout=1) 1.480 chn_bits_acq_ch1_1_IBUF + SLICE_X22Y52.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 2.364ns (0.884ns logic, 1.480ns route) + (37.4% logic, 62.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y52.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.341ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (SLICE_X23Y52.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.326ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch1<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.595ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch1<0> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P112.I Tiopi 1.310 chn_bits_acq_ch1<0> + chn_bits_acq_ch1<0> + chn_bits_acq_ch1_0_IBUF + ProtoComp52.IMUX.4 + SLICE_X23Y52.A5 net (fanout=1) 2.058 chn_bits_acq_ch1_0_IBUF + SLICE_X23Y52.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 3.595ns (1.537ns logic, 2.058ns route) + (42.8% logic, 57.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y52.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (SLICE_X23Y52.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.731ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch1<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.188ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch1<0> to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P112.I Tiopi 0.763 chn_bits_acq_ch1<0> + chn_bits_acq_ch1<0> + chn_bits_acq_ch1_0_IBUF + ProtoComp52.IMUX.4 + SLICE_X23Y52.A5 net (fanout=1) 1.270 chn_bits_acq_ch1_0_IBUF + SLICE_X23Y52.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 2.188ns (0.918ns logic, 1.270ns route) + (42.0% logic, 58.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X23Y52.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.465ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (SLICE_X17Y55.D3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 795.535ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch2<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 800.000ns + Data Path Delay: 3.707ns (Levels of Logic = 2) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch2<3> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P121.I Tiopi 1.310 chn_bits_acq_ch2<3> + chn_bits_acq_ch2<3> + chn_bits_acq_ch2_3_IBUF + ProtoComp52.IMUX.11 + SLICE_X17Y55.D3 net (fanout=1) 2.170 chn_bits_acq_ch2_3_IBUF + SLICE_X17Y55.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 3.707ns (1.537ns logic, 2.170ns route) + (41.5% logic, 58.5% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X17Y55.CLK net (fanout=226) 0.672 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-2.456ns logic, 2.015ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (SLICE_X17Y55.D3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.842ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch2<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.287ns (Levels of Logic = 2) + Clock Path Delay: 0.128ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch2<3> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P121.I Tiopi 0.763 chn_bits_acq_ch2<3> + chn_bits_acq_ch2<3> + chn_bits_acq_ch2_3_IBUF + ProtoComp52.IMUX.11 + SLICE_X17Y55.D3 net (fanout=1) 1.369 chn_bits_acq_ch2_3_IBUF + SLICE_X17Y55.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 2.287ns (0.918ns logic, 1.369ns route) + (40.1% logic, 59.9% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X17Y55.CLK net (fanout=226) 0.812 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.128ns (-1.582ns logic, 1.710ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.911ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (SLICE_X18Y44.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 795.089ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch2<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 800.000ns + Data Path Delay: 4.101ns (Levels of Logic = 2) + Clock Path Delay: -0.493ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch2<2> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P120.I Tiopi 1.310 chn_bits_acq_ch2<2> + chn_bits_acq_ch2<2> + chn_bits_acq_ch2_2_IBUF + ProtoComp52.IMUX.10 + SLICE_X18Y44.D4 net (fanout=1) 2.578 chn_bits_acq_ch2_2_IBUF + SLICE_X18Y44.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 4.101ns (1.523ns logic, 2.578ns route) + (37.1% logic, 62.9% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y44.CLK net (fanout=226) 0.620 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.493ns (-2.456ns logic, 1.963ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (SLICE_X18Y44.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.089ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch2<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.482ns (Levels of Logic = 2) + Clock Path Delay: 0.076ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch2<2> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P120.I Tiopi 0.763 chn_bits_acq_ch2<2> + chn_bits_acq_ch2<2> + chn_bits_acq_ch2_2_IBUF + ProtoComp52.IMUX.10 + SLICE_X18Y44.D4 net (fanout=1) 1.598 chn_bits_acq_ch2_2_IBUF + SLICE_X18Y44.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 2.482ns (0.884ns logic, 1.598ns route) + (35.6% logic, 64.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y44.CLK net (fanout=226) 0.760 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.076ns (-1.582ns logic, 1.658ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.579ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (SLICE_X18Y55.A2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 795.421ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch2<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 800.000ns + Data Path Delay: 3.821ns (Levels of Logic = 2) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch2<1> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P119.I Tiopi 1.310 chn_bits_acq_ch2<1> + chn_bits_acq_ch2<1> + chn_bits_acq_ch2_1_IBUF + ProtoComp52.IMUX.9 + SLICE_X18Y55.A2 net (fanout=1) 2.298 chn_bits_acq_ch2_1_IBUF + SLICE_X18Y55.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 3.821ns (1.523ns logic, 2.298ns route) + (39.9% logic, 60.1% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y55.CLK net (fanout=226) 0.672 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-2.456ns logic, 2.015ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (SLICE_X18Y55.A2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.962ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch2<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.407ns (Levels of Logic = 2) + Clock Path Delay: 0.128ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch2<1> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P119.I Tiopi 0.763 chn_bits_acq_ch2<1> + chn_bits_acq_ch2<1> + chn_bits_acq_ch2_1_IBUF + ProtoComp52.IMUX.9 + SLICE_X18Y55.A2 net (fanout=1) 1.523 chn_bits_acq_ch2_1_IBUF + SLICE_X18Y55.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 2.407ns (0.884ns logic, 1.523ns route) + (36.7% logic, 63.3% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y55.CLK net (fanout=226) 0.812 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.128ns (-1.582ns logic, 1.710ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.569ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (SLICE_X18Y57.A2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 795.431ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch2<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 800.000ns + Data Path Delay: 3.813ns (Levels of Logic = 2) + Clock Path Delay: -0.439ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch2<0> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P118.I Tiopi 1.310 chn_bits_acq_ch2<0> + chn_bits_acq_ch2<0> + chn_bits_acq_ch2_0_IBUF + ProtoComp52.IMUX.8 + SLICE_X18Y57.A2 net (fanout=1) 2.290 chn_bits_acq_ch2_0_IBUF + SLICE_X18Y57.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 3.813ns (1.523ns logic, 2.290ns route) + (39.9% logic, 60.1% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y57.CLK net (fanout=226) 0.674 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.439ns (-2.456ns logic, 2.017ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (SLICE_X18Y57.A2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.984ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch2<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.431ns (Levels of Logic = 2) + Clock Path Delay: 0.130ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch2<0> to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P118.I Tiopi 0.763 chn_bits_acq_ch2<0> + chn_bits_acq_ch2<0> + chn_bits_acq_ch2_0_IBUF + ProtoComp52.IMUX.8 + SLICE_X18Y57.A2 net (fanout=1) 1.547 chn_bits_acq_ch2_0_IBUF + SLICE_X18Y57.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 2.431ns (0.884ns logic, 1.547ns route) + (36.4% logic, 63.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y57.CLK net (fanout=226) 0.814 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.130ns (-1.582ns logic, 1.712ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.085ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (SLICE_X13Y46.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.582ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch3<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.275ns (Levels of Logic = 2) + Clock Path Delay: -0.493ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch3<3> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P131.I Tiopi 1.310 chn_bits_acq_ch3<3> + chn_bits_acq_ch3<3> + chn_bits_acq_ch3_3_IBUF + ProtoComp52.IMUX.15 + SLICE_X13Y46.D4 net (fanout=1) 2.738 chn_bits_acq_ch3_3_IBUF + SLICE_X13Y46.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 4.275ns (1.537ns logic, 2.738ns route) + (36.0% logic, 64.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X13Y46.CLK net (fanout=226) 0.620 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.493ns (-2.456ns logic, 1.963ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (SLICE_X13Y46.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.309ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch3<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.702ns (Levels of Logic = 2) + Clock Path Delay: 0.076ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch3<3> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P131.I Tiopi 0.763 chn_bits_acq_ch3<3> + chn_bits_acq_ch3<3> + chn_bits_acq_ch3_3_IBUF + ProtoComp52.IMUX.15 + SLICE_X13Y46.D4 net (fanout=1) 1.784 chn_bits_acq_ch3_3_IBUF + SLICE_X13Y46.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 2.702ns (0.918ns logic, 1.784ns route) + (34.0% logic, 66.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X13Y46.CLK net (fanout=226) 0.760 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.076ns (-1.582ns logic, 1.658ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.509ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (SLICE_X15Y39.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.158ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch3<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.688ns (Levels of Logic = 2) + Clock Path Delay: -0.504ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch3<2> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P127.I Tiopi 1.310 chn_bits_acq_ch3<2> + chn_bits_acq_ch3<2> + chn_bits_acq_ch3_2_IBUF + ProtoComp52.IMUX.14 + SLICE_X15Y39.D4 net (fanout=1) 3.151 chn_bits_acq_ch3_2_IBUF + SLICE_X15Y39.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 4.688ns (1.537ns logic, 3.151ns route) + (32.8% logic, 67.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y39.CLK net (fanout=226) 0.609 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.504ns (-2.456ns logic, 1.952ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (SLICE_X15Y39.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.506ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch3<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.888ns (Levels of Logic = 2) + Clock Path Delay: 0.065ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch3<2> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P127.I Tiopi 0.763 chn_bits_acq_ch3<2> + chn_bits_acq_ch3<2> + chn_bits_acq_ch3_2_IBUF + ProtoComp52.IMUX.14 + SLICE_X15Y39.D4 net (fanout=1) 1.970 chn_bits_acq_ch3_2_IBUF + SLICE_X15Y39.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 2.888ns (0.918ns logic, 1.970ns route) + (31.8% logic, 68.2% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y39.CLK net (fanout=226) 0.749 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.065ns (-1.582ns logic, 1.647ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.807ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (SLICE_X15Y48.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.860ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch3<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.061ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch3<1> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P126.I Tiopi 1.310 chn_bits_acq_ch3<1> + chn_bits_acq_ch3<1> + chn_bits_acq_ch3_1_IBUF + ProtoComp52.IMUX.13 + SLICE_X15Y48.A5 net (fanout=1) 2.524 chn_bits_acq_ch3_1_IBUF + SLICE_X15Y48.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 4.061ns (1.537ns logic, 2.524ns route) + (37.8% logic, 62.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y48.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (SLICE_X15Y48.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.066ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch3<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.523ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch3<1> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P126.I Tiopi 0.763 chn_bits_acq_ch3<1> + chn_bits_acq_ch3<1> + chn_bits_acq_ch3_1_IBUF + ProtoComp52.IMUX.13 + SLICE_X15Y48.A5 net (fanout=1) 1.605 chn_bits_acq_ch3_1_IBUF + SLICE_X15Y48.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 2.523ns (0.918ns logic, 1.605ns route) + (36.4% logic, 63.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y48.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.465ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (SLICE_X15Y50.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.202ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch3<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.717ns (Levels of Logic = 2) + Clock Path Delay: -0.431ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch3<0> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P124.I Tiopi 1.310 chn_bits_acq_ch3<0> + chn_bits_acq_ch3<0> + chn_bits_acq_ch3_0_IBUF + ProtoComp52.IMUX.12 + SLICE_X15Y50.D4 net (fanout=1) 2.180 chn_bits_acq_ch3_0_IBUF + SLICE_X15Y50.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 3.717ns (1.537ns logic, 2.180ns route) + (41.4% logic, 58.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y50.CLK net (fanout=226) 0.682 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.431ns (-2.456ns logic, 2.025ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (SLICE_X15Y50.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.818ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch3<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.273ns (Levels of Logic = 2) + Clock Path Delay: 0.138ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch3<0> to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P124.I Tiopi 0.763 chn_bits_acq_ch3<0> + chn_bits_acq_ch3<0> + chn_bits_acq_ch3_0_IBUF + ProtoComp52.IMUX.12 + SLICE_X15Y50.D4 net (fanout=1) 1.355 chn_bits_acq_ch3_0_IBUF + SLICE_X15Y50.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 2.273ns (0.918ns logic, 1.355ns route) + (40.4% logic, 59.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y50.CLK net (fanout=226) 0.822 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.138ns (-1.582ns logic, 1.720ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.954ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (SLICE_X7Y51.A3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.713ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch4<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.241ns (Levels of Logic = 2) + Clock Path Delay: -0.396ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch4<3> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P138.I Tiopi 1.310 chn_bits_acq_ch4<3> + chn_bits_acq_ch4<3> + chn_bits_acq_ch4_3_IBUF + ProtoComp52.IMUX.19 + SLICE_X7Y51.A3 net (fanout=1) 2.704 chn_bits_acq_ch4_3_IBUF + SLICE_X7Y51.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 4.241ns (1.537ns logic, 2.704ns route) + (36.2% logic, 63.8% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X7Y51.CLK net (fanout=226) 0.717 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.396ns (-2.456ns logic, 2.060ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (SLICE_X7Y51.A3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.133ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch4<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.623ns (Levels of Logic = 2) + Clock Path Delay: 0.173ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch4<3> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P138.I Tiopi 0.763 chn_bits_acq_ch4<3> + chn_bits_acq_ch4<3> + chn_bits_acq_ch4_3_IBUF + ProtoComp52.IMUX.19 + SLICE_X7Y51.A3 net (fanout=1) 1.705 chn_bits_acq_ch4_3_IBUF + SLICE_X7Y51.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 2.623ns (0.918ns logic, 1.705ns route) + (35.0% logic, 65.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X7Y51.CLK net (fanout=226) 0.857 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.173ns (-1.582ns logic, 1.755ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.577ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (SLICE_X5Y51.A5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.090ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch4<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.864ns (Levels of Logic = 2) + Clock Path Delay: -0.396ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch4<2> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P137.I Tiopi 1.310 chn_bits_acq_ch4<2> + chn_bits_acq_ch4<2> + chn_bits_acq_ch4_2_IBUF + ProtoComp52.IMUX.18 + SLICE_X5Y51.A5 net (fanout=1) 2.327 chn_bits_acq_ch4_2_IBUF + SLICE_X5Y51.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 3.864ns (1.537ns logic, 2.327ns route) + (39.8% logic, 60.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X5Y51.CLK net (fanout=226) 0.717 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.396ns (-2.456ns logic, 2.060ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (SLICE_X5Y51.A5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.923ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch4<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.413ns (Levels of Logic = 2) + Clock Path Delay: 0.173ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch4<2> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P137.I Tiopi 0.763 chn_bits_acq_ch4<2> + chn_bits_acq_ch4<2> + chn_bits_acq_ch4_2_IBUF + ProtoComp52.IMUX.18 + SLICE_X5Y51.A5 net (fanout=1) 1.495 chn_bits_acq_ch4_2_IBUF + SLICE_X5Y51.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 2.413ns (0.918ns logic, 1.495ns route) + (38.0% logic, 62.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X5Y51.CLK net (fanout=226) 0.857 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.173ns (-1.582ns logic, 1.755ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.480ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (SLICE_X8Y56.D3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.187ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch4<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.750ns (Levels of Logic = 2) + Clock Path Delay: -0.413ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch4<1> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P134.I Tiopi 1.310 chn_bits_acq_ch4<1> + chn_bits_acq_ch4<1> + chn_bits_acq_ch4_1_IBUF + ProtoComp52.IMUX.17 + SLICE_X8Y56.D3 net (fanout=1) 2.286 chn_bits_acq_ch4_1_IBUF + SLICE_X8Y56.CLK Tas 0.154 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 3.750ns (1.464ns logic, 2.286ns route) + (39.0% logic, 61.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y56.CLK net (fanout=226) 0.700 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.413ns (-2.456ns logic, 2.043ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (SLICE_X8Y56.D3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.888ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch4<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.361ns (Levels of Logic = 2) + Clock Path Delay: 0.156ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch4<1> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P134.I Tiopi 0.763 chn_bits_acq_ch4<1> + chn_bits_acq_ch4<1> + chn_bits_acq_ch4_1_IBUF + ProtoComp52.IMUX.17 + SLICE_X8Y56.D3 net (fanout=1) 1.467 chn_bits_acq_ch4_1_IBUF + SLICE_X8Y56.CLK Tah (-Th) -0.131 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 2.361ns (0.894ns logic, 1.467ns route) + (37.9% logic, 62.1% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y56.CLK net (fanout=226) 0.840 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.156ns (-1.582ns logic, 1.738ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.465ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (SLICE_X9Y54.A4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.202ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch4<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.737ns (Levels of Logic = 2) + Clock Path Delay: -0.411ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch4<0> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P133.I Tiopi 1.310 chn_bits_acq_ch4<0> + chn_bits_acq_ch4<0> + chn_bits_acq_ch4_0_IBUF + ProtoComp52.IMUX.16 + SLICE_X9Y54.A4 net (fanout=1) 2.200 chn_bits_acq_ch4_0_IBUF + SLICE_X9Y54.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 3.737ns (1.537ns logic, 2.200ns route) + (41.1% logic, 58.9% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y54.CLK net (fanout=226) 0.702 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.411ns (-2.456ns logic, 2.045ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (SLICE_X9Y54.A4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.843ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch4<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.318ns (Levels of Logic = 2) + Clock Path Delay: 0.158ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch4<0> to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P133.I Tiopi 0.763 chn_bits_acq_ch4<0> + chn_bits_acq_ch4<0> + chn_bits_acq_ch4_0_IBUF + ProtoComp52.IMUX.16 + SLICE_X9Y54.A4 net (fanout=1) 1.400 chn_bits_acq_ch4_0_IBUF + SLICE_X9Y54.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 2.318ns (0.918ns logic, 1.400ns route) + (39.6% logic, 60.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y54.CLK net (fanout=226) 0.842 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.158ns (-1.582ns logic, 1.740ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.088ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (SLICE_X22Y4.D3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.579ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch5<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.342ns (Levels of Logic = 2) + Clock Path Delay: -0.429ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch5<3> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P62.I Tiopi 1.310 chn_bits_acq_ch5<3> + chn_bits_acq_ch5<3> + chn_bits_acq_ch5_3_IBUF + ProtoComp52.IMUX.23 + SLICE_X22Y4.D3 net (fanout=1) 1.819 chn_bits_acq_ch5_3_IBUF + SLICE_X22Y4.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 3.342ns (1.523ns logic, 1.819ns route) + (45.6% logic, 54.4% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y4.CLK net (fanout=226) 0.684 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.429ns (-2.456ns logic, 2.027ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (SLICE_X22Y4.D3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.582ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch5<3> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.039ns (Levels of Logic = 2) + Clock Path Delay: 0.140ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch5<3> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P62.I Tiopi 0.763 chn_bits_acq_ch5<3> + chn_bits_acq_ch5<3> + chn_bits_acq_ch5_3_IBUF + ProtoComp52.IMUX.23 + SLICE_X22Y4.D3 net (fanout=1) 1.155 chn_bits_acq_ch5_3_IBUF + SLICE_X22Y4.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + ------------------------------------------------- --------------------------- + Total 2.039ns (0.884ns logic, 1.155ns route) + (43.4% logic, 56.6% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y4.CLK net (fanout=226) 0.824 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.140ns (-1.582ns logic, 1.722ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.132ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (SLICE_X19Y17.A1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.535ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch5<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.325ns (Levels of Logic = 2) + Clock Path Delay: -0.490ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch5<2> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P61.I Tiopi 1.310 chn_bits_acq_ch5<2> + chn_bits_acq_ch5<2> + chn_bits_acq_ch5_2_IBUF + ProtoComp52.IMUX.22 + SLICE_X19Y17.A1 net (fanout=1) 2.788 chn_bits_acq_ch5_2_IBUF + SLICE_X19Y17.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 4.325ns (1.537ns logic, 2.788ns route) + (35.5% logic, 64.5% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X19Y17.CLK net (fanout=226) 0.623 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.490ns (-2.456ns logic, 1.966ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (SLICE_X19Y17.A1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.294ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch5<2> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.690ns (Levels of Logic = 2) + Clock Path Delay: 0.079ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch5<2> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P61.I Tiopi 0.763 chn_bits_acq_ch5<2> + chn_bits_acq_ch5<2> + chn_bits_acq_ch5_2_IBUF + ProtoComp52.IMUX.22 + SLICE_X19Y17.A1 net (fanout=1) 1.772 chn_bits_acq_ch5_2_IBUF + SLICE_X19Y17.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + ------------------------------------------------- --------------------------- + Total 2.690ns (0.918ns logic, 1.772ns route) + (34.1% logic, 65.9% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X19Y17.CLK net (fanout=226) 0.763 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.079ns (-1.582ns logic, 1.661ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.238ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (SLICE_X18Y7.D3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.429ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch5<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.480ns (Levels of Logic = 2) + Clock Path Delay: -0.441ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch5<1> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P59.I Tiopi 1.310 chn_bits_acq_ch5<1> + chn_bits_acq_ch5<1> + chn_bits_acq_ch5_1_IBUF + ProtoComp52.IMUX.21 + SLICE_X18Y7.D3 net (fanout=1) 1.957 chn_bits_acq_ch5_1_IBUF + SLICE_X18Y7.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 3.480ns (1.523ns logic, 1.957ns route) + (43.8% logic, 56.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y7.CLK net (fanout=226) 0.672 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.441ns (-2.456ns logic, 2.015ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (SLICE_X18Y7.D3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.687ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch5<1> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.132ns (Levels of Logic = 2) + Clock Path Delay: 0.128ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch5<1> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P59.I Tiopi 0.763 chn_bits_acq_ch5<1> + chn_bits_acq_ch5<1> + chn_bits_acq_ch5_1_IBUF + ProtoComp52.IMUX.21 + SLICE_X18Y7.D3 net (fanout=1) 1.248 chn_bits_acq_ch5_1_IBUF + SLICE_X18Y7.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + ------------------------------------------------- --------------------------- + Total 2.132ns (0.884ns logic, 1.248ns route) + (41.5% logic, 58.5% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X18Y7.CLK net (fanout=226) 0.812 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.128ns (-1.582ns logic, 1.710ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID +16.667 ns BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.536ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (SLICE_X22Y7.D2), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 12.131ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: chn_bits_acq_ch5<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.783ns (Levels of Logic = 2) + Clock Path Delay: -0.436ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: chn_bits_acq_ch5<0> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P58.I Tiopi 1.310 chn_bits_acq_ch5<0> + chn_bits_acq_ch5<0> + chn_bits_acq_ch5_0_IBUF + ProtoComp52.IMUX.20 + SLICE_X22Y7.D2 net (fanout=1) 2.260 chn_bits_acq_ch5_0_IBUF + SLICE_X22Y7.CLK Tas 0.213 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 3.783ns (1.523ns logic, 2.260ns route) + (40.3% logic, 59.7% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y7.CLK net (fanout=226) 0.677 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.436ns (-2.456ns logic, 2.020ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (SLICE_X22Y7.D2), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.894ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: chn_bits_acq_ch5<0> (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.344ns (Levels of Logic = 2) + Clock Path Delay: 0.133ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: chn_bits_acq_ch5<0> to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P58.I Tiopi 0.763 chn_bits_acq_ch5<0> + chn_bits_acq_ch5<0> + chn_bits_acq_ch5_0_IBUF + ProtoComp52.IMUX.20 + SLICE_X22Y7.D2 net (fanout=1) 1.460 chn_bits_acq_ch5_0_IBUF + SLICE_X22Y7.CLK Tah (-Th) -0.121 nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1> + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0_rstpot + nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + ------------------------------------------------- --------------------------- + Total 2.344ns (0.884ns logic, 1.460ns route) + (37.7% logic, 62.3% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X22Y7.CLK net (fanout=226) 0.817 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.133ns (-1.582ns logic, 1.715ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE +COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 5 paths analyzed, 5 endpoints analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 6.085ns. +-------------------------------------------------------------------------------- + +Paths for end point lock_rst_bar (SLICE_X14Y22.AX), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.582ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: lock (PAD) + Destination: lock_rst_bar (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.266ns (Levels of Logic = 3) + Clock Path Delay: -0.502ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: lock to lock_rst_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 1.337 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X14Y27.D6 net (fanout=3) 2.216 lock_inv + SLICE_X14Y27.D Tilo 0.205 lock_rst_bar_1 + PWR_5_o_reset_gen.cont_200MHz[15]_equal_1_o_inv3_SW0 + SLICE_X14Y27.C4 net (fanout=1) 0.447 N88 + SLICE_X14Y27.C Tilo 0.205 lock_rst_bar_1 + lock_rst_bar_rstpot + SLICE_X14Y22.AX net (fanout=1) 0.720 lock_rst_bar_rstpot + SLICE_X14Y22.CLK Tdick 0.136 lock_rst_bar + lock_rst_bar + ------------------------------------------------- --------------------------- + Total 5.266ns (1.883ns logic, 3.383ns route) + (35.8% logic, 64.2% route) + + Minimum Clock Path at Slow Process Corner: clk_main to lock_rst_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y22.CLK net (fanout=226) 0.611 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.502ns (-2.456ns logic, 1.954ns route) + +-------------------------------------------------------------------------------- + +Paths for end point lock_rst_bar_1 (SLICE_X14Y27.C4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.307ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: lock (PAD) + Destination: lock_rst_bar_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.546ns (Levels of Logic = 3) + Clock Path Delay: -0.497ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: lock to lock_rst_bar_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 1.337 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X14Y27.D6 net (fanout=3) 2.216 lock_inv + SLICE_X14Y27.D Tilo 0.205 lock_rst_bar_1 + PWR_5_o_reset_gen.cont_200MHz[15]_equal_1_o_inv3_SW0 + SLICE_X14Y27.C4 net (fanout=1) 0.447 N88 + SLICE_X14Y27.CLK Tas 0.341 lock_rst_bar_1 + lock_rst_bar_rstpot + lock_rst_bar_1 + ------------------------------------------------- --------------------------- + Total 4.546ns (1.883ns logic, 2.663ns route) + (41.4% logic, 58.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to lock_rst_bar_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y27.CLK net (fanout=226) 0.616 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.497ns (-2.456ns logic, 1.959ns route) + +-------------------------------------------------------------------------------- + +Paths for end point pps_rst (SLICE_X12Y26.SR), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.817ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: lock (PAD) + Destination: pps_rst (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.033ns (Levels of Logic = 1) + Clock Path Delay: -0.500ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: lock to pps_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 1.337 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X12Y26.SR net (fanout=3) 2.257 lock_inv + SLICE_X12Y26.CLK Tsrck 0.439 pps_rst + pps_rst + ------------------------------------------------- --------------------------- + Total 4.033ns (1.776ns logic, 2.257ns route) + (44.0% logic, 56.0% route) + + Minimum Clock Path at Slow Process Corner: clk_main to pps_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X12Y26.CLK net (fanout=226) 0.613 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.500ns (-2.456ns logic, 1.956ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point pps_r_0 (SLICE_X14Y26.SR), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.602ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: lock (PAD) + Destination: pps_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 1.989ns (Levels of Logic = 1) + Clock Path Delay: 0.070ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: lock to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 0.773 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X14Y26.SR net (fanout=3) 1.191 lock_inv + SLICE_X14Y26.CLK Tcksr (-Th) -0.025 pps_r<1> + pps_r_0 + ------------------------------------------------- --------------------------- + Total 1.989ns (0.798ns logic, 1.191ns route) + (40.1% logic, 59.9% route) + + Maximum Clock Path at Fast Process Corner: clk_main to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y26.CLK net (fanout=226) 0.754 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.070ns (-1.582ns logic, 1.652ns route) + +-------------------------------------------------------------------------------- + +Paths for end point pps_r_1 (SLICE_X14Y26.SR), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.623ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: lock (PAD) + Destination: pps_r_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.010ns (Levels of Logic = 1) + Clock Path Delay: 0.070ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: lock to pps_r_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 0.773 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X14Y26.SR net (fanout=3) 1.191 lock_inv + SLICE_X14Y26.CLK Tcksr (-Th) -0.046 pps_r<1> + pps_r_1 + ------------------------------------------------- --------------------------- + Total 2.010ns (0.819ns logic, 1.191ns route) + (40.7% logic, 59.3% route) + + Maximum Clock Path at Fast Process Corner: clk_main to pps_r_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y26.CLK net (fanout=226) 0.754 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.070ns (-1.582ns logic, 1.652ns route) + +-------------------------------------------------------------------------------- + +Paths for end point pps_rst (SLICE_X12Y26.SR), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.859ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: lock (PAD) + Destination: pps_rst (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.245ns (Levels of Logic = 1) + Clock Path Delay: 0.069ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: lock to pps_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P82.I Tiopi 0.773 lock + lock + lock_IBUF + ProtoComp54.IINV + ProtoComp54.IMUX + SLICE_X12Y26.SR net (fanout=3) 1.445 lock_inv + SLICE_X12Y26.CLK Tcksr (-Th) -0.027 pps_rst + pps_rst + ------------------------------------------------- --------------------------- + Total 2.245ns (0.800ns logic, 1.445ns route) + (35.6% logic, 64.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to pps_rst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X12Y26.CLK net (fanout=226) 0.753 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.069ns (-1.582ns logic, 1.651ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP +"clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.685ns. +-------------------------------------------------------------------------------- + +Paths for end point pps_r_0 (SLICE_X14Y26.AX), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.982ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: pps (PAD) + Destination: pps_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.869ns (Levels of Logic = 1) + Clock Path Delay: -0.499ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: pps to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P78.I Tiopi 1.310 pps + pps + pps_IBUF + ProtoComp52.IMUX.2 + SLICE_X14Y26.AX net (fanout=1) 2.423 pps_IBUF + SLICE_X14Y26.CLK Tdick 0.136 pps_r<1> + pps_r_0 + ------------------------------------------------- --------------------------- + Total 3.869ns (1.446ns logic, 2.423ns route) + (37.4% logic, 62.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y26.CLK net (fanout=226) 0.614 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.499ns (-2.456ns logic, 1.957ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point pps_r_0 (SLICE_X14Y26.AX), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 1.955ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: pps (PAD) + Destination: pps_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.342ns (Levels of Logic = 1) + Clock Path Delay: 0.070ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: pps to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P78.I Tiopi 0.763 pps + pps + pps_IBUF + ProtoComp52.IMUX.2 + SLICE_X14Y26.AX net (fanout=1) 1.531 pps_IBUF + SLICE_X14Y26.CLK Tckdi (-Th) -0.048 pps_r<1> + pps_r_0 + ------------------------------------------------- --------------------------- + Total 2.342ns (0.811ns logic, 1.531ns route) + (34.6% logic, 65.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to pps_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X14Y26.CLK net (fanout=226) 0.754 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.070ns (-1.582ns logic, 1.652ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE +COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.828ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (SLICE_X16Y47.B5), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 795.172ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: clk_acq_ch1 (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 800.000ns + Data Path Delay: 4.021ns (Levels of Logic = 2) + Clock Path Delay: -0.490ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: clk_acq_ch1 to nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P111.I Tiopi 1.310 clk_acq_ch1 + clk_acq_ch1 + clk_acq_ch1_IBUF + ProtoComp52.IMUX.25 + SLICE_X16Y47.B5 net (fanout=1) 2.557 clk_acq_ch1_IBUF + SLICE_X16Y47.CLK Tas 0.154 nb_mem_cont/nibble_pack_ch1/clk_acq_r<2> + nb_mem_cont/nibble_pack_ch1/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 4.021ns (1.464ns logic, 2.557ns route) + (36.4% logic, 63.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y47.CLK net (fanout=226) 0.623 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.490ns (-2.456ns logic, 1.966ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" + "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (SLICE_X16Y47.B5), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.085ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: clk_acq_ch1 (PAD) + Destination: nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.481ns (Levels of Logic = 2) + Clock Path Delay: 0.079ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: clk_acq_ch1 to nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P111.I Tiopi 0.763 clk_acq_ch1 + clk_acq_ch1 + clk_acq_ch1_IBUF + ProtoComp52.IMUX.25 + SLICE_X16Y47.B5 net (fanout=1) 1.587 clk_acq_ch1_IBUF + SLICE_X16Y47.CLK Tah (-Th) -0.131 nb_mem_cont/nibble_pack_ch1/clk_acq_r<2> + nb_mem_cont/nibble_pack_ch1/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 2.481ns (0.894ns logic, 1.587ns route) + (36.0% logic, 64.0% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y47.CLK net (fanout=226) 0.763 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.079ns (-1.582ns logic, 1.661ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.021ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (SLICE_X16Y46.A3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.646ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: clk_acq_ch2 (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 4.214ns (Levels of Logic = 2) + Clock Path Delay: -0.490ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: clk_acq_ch2 to nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P117.I Tiopi 1.310 clk_acq_ch2 + clk_acq_ch2 + clk_acq_ch2_IBUF + ProtoComp52.IMUX.26 + SLICE_X16Y46.A3 net (fanout=1) 2.750 clk_acq_ch2_IBUF + SLICE_X16Y46.CLK Tas 0.154 nb_mem_cont/nibble_pack_ch3/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch2/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 4.214ns (1.464ns logic, 2.750ns route) + (34.7% logic, 65.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y46.CLK net (fanout=226) 0.623 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.490ns (-2.456ns logic, 1.966ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (SLICE_X16Y46.A3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.226ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: clk_acq_ch2 (PAD) + Destination: nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.622ns (Levels of Logic = 2) + Clock Path Delay: 0.079ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: clk_acq_ch2 to nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P117.I Tiopi 0.763 clk_acq_ch2 + clk_acq_ch2 + clk_acq_ch2_IBUF + ProtoComp52.IMUX.26 + SLICE_X16Y46.A3 net (fanout=1) 1.728 clk_acq_ch2_IBUF + SLICE_X16Y46.CLK Tah (-Th) -0.131 nb_mem_cont/nibble_pack_ch3/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch2/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 2.622ns (0.894ns logic, 1.728ns route) + (34.1% logic, 65.9% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y46.CLK net (fanout=226) 0.763 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.079ns (-1.582ns logic, 1.661ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 4.711ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (SLICE_X16Y46.C3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 11.956ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: clk_acq_ch3 (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 3.904ns (Levels of Logic = 2) + Clock Path Delay: -0.490ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: clk_acq_ch3 to nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P123.I Tiopi 1.310 clk_acq_ch3 + clk_acq_ch3 + clk_acq_ch3_IBUF + ProtoComp52.IMUX.27 + SLICE_X16Y46.C3 net (fanout=1) 2.440 clk_acq_ch3_IBUF + SLICE_X16Y46.CLK Tas 0.154 nb_mem_cont/nibble_pack_ch3/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch3/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 3.904ns (1.464ns logic, 2.440ns route) + (37.5% logic, 62.5% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y46.CLK net (fanout=226) 0.623 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.490ns (-2.456ns logic, 1.966ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (SLICE_X16Y46.C3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.027ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: clk_acq_ch3 (PAD) + Destination: nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.423ns (Levels of Logic = 2) + Clock Path Delay: 0.079ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: clk_acq_ch3 to nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P123.I Tiopi 0.763 clk_acq_ch3 + clk_acq_ch3 + clk_acq_ch3_IBUF + ProtoComp52.IMUX.27 + SLICE_X16Y46.C3 net (fanout=1) 1.529 clk_acq_ch3_IBUF + SLICE_X16Y46.CLK Tah (-Th) -0.131 nb_mem_cont/nibble_pack_ch3/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch3/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 2.423ns (0.894ns logic, 1.529ns route) + (36.9% logic, 63.1% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y46.CLK net (fanout=226) 0.763 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.079ns (-1.582ns logic, 1.661ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.877ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (SLICE_X15Y35.A1), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.790ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: clk_acq_ch4 (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.066ns (Levels of Logic = 2) + Clock Path Delay: -0.494ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: clk_acq_ch4 to nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P132.I Tiopi 1.310 clk_acq_ch4 + clk_acq_ch4 + clk_acq_ch4_IBUF + ProtoComp52.IMUX.28 + SLICE_X15Y35.A1 net (fanout=1) 3.529 clk_acq_ch4_IBUF + SLICE_X15Y35.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch5/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch4/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 5.066ns (1.537ns logic, 3.529ns route) + (30.3% logic, 69.7% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y35.CLK net (fanout=226) 0.619 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.494ns (-2.456ns logic, 1.962ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (SLICE_X15Y35.A1), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.755ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: clk_acq_ch4 (PAD) + Destination: nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.147ns (Levels of Logic = 2) + Clock Path Delay: 0.075ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: clk_acq_ch4 to nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P132.I Tiopi 0.763 clk_acq_ch4 + clk_acq_ch4 + clk_acq_ch4_IBUF + ProtoComp52.IMUX.28 + SLICE_X15Y35.A1 net (fanout=1) 2.229 clk_acq_ch4_IBUF + SLICE_X15Y35.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch5/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch4/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 3.147ns (0.918ns logic, 2.229ns route) + (29.2% logic, 70.8% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y35.CLK net (fanout=226) 0.759 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.075ns (-1.582ns logic, 1.657ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns +BEFORE COMP "clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.861ns. +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (SLICE_X15Y35.C3), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 10.806ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: clk_acq_ch5 (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 5.050ns (Levels of Logic = 2) + Clock Path Delay: -0.494ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: clk_acq_ch5 to nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P57.I Tiopi 1.310 clk_acq_ch5 + clk_acq_ch5 + clk_acq_ch5_IBUF + ProtoComp52.IMUX.29 + SLICE_X15Y35.C3 net (fanout=1) 3.513 clk_acq_ch5_IBUF + SLICE_X15Y35.CLK Tas 0.227 nb_mem_cont/nibble_pack_ch5/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch5/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 5.050ns (1.537ns logic, 3.513ns route) + (30.4% logic, 69.6% route) + + Minimum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y35.CLK net (fanout=226) 0.619 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.494ns (-2.456ns logic, 1.962ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (SLICE_X15Y35.C3), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.688ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: clk_acq_ch5 (PAD) + Destination: nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.080ns (Levels of Logic = 2) + Clock Path Delay: 0.075ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: clk_acq_ch5 to nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P57.I Tiopi 0.763 clk_acq_ch5 + clk_acq_ch5 + clk_acq_ch5_IBUF + ProtoComp52.IMUX.29 + SLICE_X15Y35.C3 net (fanout=1) 2.162 clk_acq_ch5_IBUF + SLICE_X15Y35.CLK Tah (-Th) -0.155 nb_mem_cont/nibble_pack_ch5/clk_acq_r<1> + nb_mem_cont/nibble_pack_ch5/clk_acq_r_0_rstpot + nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + ------------------------------------------------- --------------------------- + Total 3.080ns (0.918ns logic, 2.162ns route) + (29.8% logic, 70.2% route) + + Maximum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X15Y35.CLK net (fanout=226) 0.759 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.075ns (-1.582ns logic, 1.657ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 7.179ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/MOSIr_0 (SLICE_X16Y11.AX), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 4.821ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: MOSI (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/MOSIr_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 6.428ns (Levels of Logic = 1) + Clock Path Delay: -0.434ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: MOSI to interfaz_spi/controlador_spi_esclavo/MOSIr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P99.I Tiopi 1.310 MOSI + MOSI + MOSI_IBUF + ProtoComp52.IMUX.3 + SLICE_X16Y11.AX net (fanout=1) 5.032 MOSI_IBUF + SLICE_X16Y11.CLK Tdick 0.086 interfaz_spi/controlador_spi_esclavo/MOSIr<1> + interfaz_spi/controlador_spi_esclavo/MOSIr_0 + ------------------------------------------------- --------------------------- + Total 6.428ns (1.396ns logic, 5.032ns route) + (21.7% logic, 78.3% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/MOSIr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y11.CLK net (fanout=226) 0.679 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.434ns (-2.456ns logic, 2.022ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/MOSIr_0 (SLICE_X16Y11.AX), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 3.457ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: MOSI (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/MOSIr_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.909ns (Levels of Logic = 1) + Clock Path Delay: 0.135ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: MOSI to interfaz_spi/controlador_spi_esclavo/MOSIr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P99.I Tiopi 0.763 MOSI + MOSI + MOSI_IBUF + ProtoComp52.IMUX.3 + SLICE_X16Y11.AX net (fanout=1) 3.105 MOSI_IBUF + SLICE_X16Y11.CLK Tckdi (-Th) -0.041 interfaz_spi/controlador_spi_esclavo/MOSIr<1> + interfaz_spi/controlador_spi_esclavo/MOSIr_0 + ------------------------------------------------- --------------------------- + Total 3.909ns (0.804ns logic, 3.105ns route) + (20.6% logic, 79.4% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/MOSIr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X16Y11.CLK net (fanout=226) 0.819 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.135ns (-1.582ns logic, 1.717ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP +"clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 5.534ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/SCKr_0 (SLICE_X20Y8.D4), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 19.466ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: SCK (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/SCKr_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 25.000ns + Data Path Delay: 4.781ns (Levels of Logic = 2) + Clock Path Delay: -0.436ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: SCK to interfaz_spi/controlador_spi_esclavo/SCKr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P95.I Tiopi 1.310 SCK + SCK + SCK_IBUF + ProtoComp52.IMUX.1 + SLICE_X20Y8.D4 net (fanout=1) 3.317 SCK_IBUF + SLICE_X20Y8.CLK Tas 0.154 interfaz_spi/controlador_spi_esclavo/SCKr<1> + interfaz_spi/controlador_spi_esclavo/SCKr_0_glue_set + interfaz_spi/controlador_spi_esclavo/SCKr_0 + ------------------------------------------------- --------------------------- + Total 4.781ns (1.464ns logic, 3.317ns route) + (30.6% logic, 69.4% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/SCKr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X20Y8.CLK net (fanout=226) 0.677 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.436ns (-2.456ns logic, 2.020ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/SCKr_0 (SLICE_X20Y8.D4), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.480ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: SCK (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/SCKr_0 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 2.930ns (Levels of Logic = 2) + Clock Path Delay: 0.133ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: SCK to interfaz_spi/controlador_spi_esclavo/SCKr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P95.I Tiopi 0.763 SCK + SCK + SCK_IBUF + ProtoComp52.IMUX.1 + SLICE_X20Y8.D4 net (fanout=1) 2.036 SCK_IBUF + SLICE_X20Y8.CLK Tah (-Th) -0.131 interfaz_spi/controlador_spi_esclavo/SCKr<1> + interfaz_spi/controlador_spi_esclavo/SCKr_0_glue_set + interfaz_spi/controlador_spi_esclavo/SCKr_0 + ------------------------------------------------- --------------------------- + Total 2.930ns (0.894ns logic, 2.036ns route) + (30.5% logic, 69.5% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/SCKr_0 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X20Y8.CLK net (fanout=226) 0.817 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.133ns (-1.582ns logic, 1.715ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP +"clk_main" "RISING"; +For more information, see Offset In Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. (0 setup errors, 0 hold errors) + Minimum allowable offset is 6.292ns. +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (SLICE_X20Y7.AI), 1 path +-------------------------------------------------------------------------------- +Slack (setup path): 5.708ns (requirement - (data path - clock path - clock arrival + uncertainty)) + Source: CS (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 12.000ns + Data Path Delay: 5.539ns (Levels of Logic = 1) + Clock Path Delay: -0.436ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Data Path at Slow Process Corner: CS to interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P97.I Tiopi 1.310 CS + CS + CS_IBUF + ProtoComp52.IMUX + SLICE_X20Y7.AI net (fanout=1) 4.191 CS_IBUF + SLICE_X20Y7.CLK Tds 0.038 interfaz_spi/controlador_spi_esclavo/CSr<1> + interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + ------------------------------------------------- --------------------------- + Total 5.539ns (1.348ns logic, 4.191ns route) + (24.3% logic, 75.7% route) + + Minimum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.126 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.278 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.105 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.562 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -3.884 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.503 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.197 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X20Y7.CLK net (fanout=226) 0.677 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.436ns (-2.456ns logic, 2.020ns route) + +-------------------------------------------------------------------------------- + +Hold Paths: COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +-------------------------------------------------------------------------------- + +Paths for end point interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (SLICE_X20Y7.AI), 1 path +-------------------------------------------------------------------------------- +Slack (hold path): 2.894ns (requirement - (clock path + clock arrival + uncertainty - data path)) + Source: CS (PAD) + Destination: interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (FF) + Destination Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 0.000ns + Data Path Delay: 3.344ns (Levels of Logic = 1) + Clock Path Delay: 0.133ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Data Path at Fast Process Corner: CS to interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P97.I Tiopi 0.763 CS + CS + CS_IBUF + ProtoComp52.IMUX + SLICE_X20Y7.AI net (fanout=1) 2.551 CS_IBUF + SLICE_X20Y7.CLK Tdh (-Th) -0.030 interfaz_spi/controlador_spi_esclavo/CSr<1> + interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + ------------------------------------------------- --------------------------- + Total 3.344ns (0.793ns logic, 2.551ns route) + (23.7% logic, 76.3% route) + + Maximum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.887 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.245 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.130 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.391 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.662 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.262 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.063 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X20Y7.CLK net (fanout=226) 0.817 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total 0.133ns (-1.582ns logic, 1.715ns route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 9 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 8.269ns. +-------------------------------------------------------------------------------- + +Paths for end point we_bar (P43.PAD), 9 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.398ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.283ns (Levels of Logic = 3) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.CQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.D1 net (fanout=5) 1.741 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.DMUX Tilo 0.251 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0 + SLICE_X2Y23.C4 net (fanout=1) 0.374 N22 + SLICE_X2Y23.C Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 2.884 we_bar_OBUF + P43.PAD Tioop 2.381 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 8.283ns (3.284ns logic, 4.999ns route) + (39.6% logic, 60.4% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.776ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 7.905ns (Levels of Logic = 3) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.D3 net (fanout=51) 1.363 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.DMUX Tilo 0.251 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0 + SLICE_X2Y23.C4 net (fanout=1) 0.374 N22 + SLICE_X2Y23.C Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 2.884 we_bar_OBUF + P43.PAD Tioop 2.381 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 7.905ns (3.284ns logic, 4.621ns route) + (41.5% logic, 58.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.868ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 7.740ns (Levels of Logic = 3) + Clock Path Delay: -0.258ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y15.CLK net (fanout=226) 1.179 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.258ns (-3.088ns logic, 2.830ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y15.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D4 net (fanout=5) 1.190 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.DMUX Tilo 0.251 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0 + SLICE_X2Y23.C4 net (fanout=1) 0.374 N22 + SLICE_X2Y23.C Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 2.884 we_bar_OBUF + P43.PAD Tioop 2.381 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 7.740ns (3.292ns logic, 4.448ns route) + (42.5% logic, 57.5% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point we_bar (P43.PAD), 9 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.484ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.196ns (Levels of Logic = 3) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X1Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y25.CQ Tcko 0.198 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.D5 net (fanout=4) 0.352 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.DMUX Tilo 0.183 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0 + SLICE_X2Y23.C4 net (fanout=1) 0.115 N22 + SLICE_X2Y23.C Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 1.810 we_bar_OBUF + P43.PAD Tioop 1.396 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 4.196ns (1.919ns logic, 2.277ns route) + (45.7% logic, 54.3% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.438ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.151ns (Levels of Logic = 2) + Clock Path Delay: -0.396ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X5Y20.CLK net (fanout=226) 0.494 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.396ns (-1.698ns logic, 1.302ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y20.AQ Tcko 0.198 nb_mem_cont/ram_control/addr_erase_aux_int<5> + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.C5 net (fanout=7) 0.605 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.C Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 1.810 we_bar_OBUF + P43.PAD Tioop 1.396 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 4.151ns (1.736ns logic, 2.415ns route) + (41.8% logic, 58.2% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.177ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: we_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 3.889ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to we_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X2Y23.C6 net (fanout=19) 0.307 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X2Y23.C Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<2> + P43.O net (fanout=1) 1.810 we_bar_OBUF + P43.PAD Tioop 1.396 we_bar + we_bar_OBUF + we_bar + ------------------------------------------------- --------------------------- + Total 3.889ns (1.772ns logic, 2.117ns route) + (45.6% logic, 54.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 5 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 8.621ns. +-------------------------------------------------------------------------------- + +Paths for end point ub_bar (P6.PAD), 5 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.046ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.635ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.CQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.D1 net (fanout=5) 1.741 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 3.861 lb_bar_OBUF + P6.PAD Tioop 2.381 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 8.635ns (3.033ns logic, 5.602ns route) + (35.1% logic, 64.9% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.424ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.257ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.D3 net (fanout=51) 1.363 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 3.861 lb_bar_OBUF + P6.PAD Tioop 2.381 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 8.257ns (3.033ns logic, 5.224ns route) + (36.7% logic, 63.3% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.516ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.092ns (Levels of Logic = 2) + Clock Path Delay: -0.258ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y15.CLK net (fanout=226) 1.179 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.258ns (-3.088ns logic, 2.830ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y15.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D4 net (fanout=5) 1.190 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 3.861 lb_bar_OBUF + P6.PAD Tioop 2.381 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 8.092ns (3.041ns logic, 5.051ns route) + (37.6% logic, 62.4% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point ub_bar (P6.PAD), 5 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 4.234ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.882ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y15.CLK net (fanout=226) 0.559 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-1.698ns logic, 1.367ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y15.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D4 net (fanout=5) 0.701 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 2.405 lb_bar_OBUF + P6.PAD Tioop 1.396 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 4.882ns (1.776ns logic, 3.106ns route) + (36.4% logic, 63.6% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 4.224ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.937ns (Levels of Logic = 2) + Clock Path Delay: -0.396ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X5Y20.CLK net (fanout=226) 0.494 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.396ns (-1.698ns logic, 1.302ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y20.AQ Tcko 0.198 nb_mem_cont/ram_control/addr_erase_aux_int<5> + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.D2 net (fanout=7) 0.796 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 2.405 lb_bar_OBUF + P6.PAD Tioop 1.396 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 4.937ns (1.736ns logic, 3.201ns route) + (35.2% logic, 64.8% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.781ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 (FF) + Destination: ub_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.493ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X1Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 to ub_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y25.CQ Tcko 0.198 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.D5 net (fanout=4) 0.352 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P6.O net (fanout=2) 2.405 lb_bar_OBUF + P6.PAD Tioop 1.396 ub_bar + ub_bar_OBUF + ub_bar + ------------------------------------------------- --------------------------- + Total 4.493ns (1.736ns logic, 2.757ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 5 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 8.246ns. +-------------------------------------------------------------------------------- + +Paths for end point lb_bar (P7.PAD), 5 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.421ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.260ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.CQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.D1 net (fanout=5) 1.741 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 3.486 lb_bar_OBUF + P7.PAD Tioop 2.381 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 8.260ns (3.033ns logic, 5.227ns route) + (36.7% logic, 63.3% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.799ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 7.882ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X8Y28.CLK net (fanout=226) 1.106 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-3.088ns logic, 2.757ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X8Y28.DQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.D3 net (fanout=51) 1.363 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 3.486 lb_bar_OBUF + P7.PAD Tioop 2.381 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 7.882ns (3.033ns logic, 4.849ns route) + (38.5% logic, 61.5% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.891ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 7.717ns (Levels of Logic = 2) + Clock Path Delay: -0.258ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y15.CLK net (fanout=226) 1.179 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.258ns (-3.088ns logic, 2.830ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y15.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D4 net (fanout=5) 1.190 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D Tilo 0.205 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 3.486 lb_bar_OBUF + P7.PAD Tioop 2.381 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 7.717ns (3.041ns logic, 4.676ns route) + (39.4% logic, 60.6% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point lb_bar (P7.PAD), 5 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.987ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.635ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y15.CLK net (fanout=226) 0.559 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-1.698ns logic, 1.367ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y15.CMUX Tshcko 0.238 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D4 net (fanout=5) 0.701 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 2.158 lb_bar_OBUF + P7.PAD Tioop 1.396 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 4.635ns (1.776ns logic, 2.859ns route) + (38.3% logic, 61.7% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.977ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.690ns (Levels of Logic = 2) + Clock Path Delay: -0.396ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X5Y20.CLK net (fanout=226) 0.494 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.396ns (-1.698ns logic, 1.302ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X5Y20.AQ Tcko 0.198 nb_mem_cont/ram_control/addr_erase_aux_int<5> + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.D2 net (fanout=7) 0.796 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 2.158 lb_bar_OBUF + P7.PAD Tioop 1.396 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 4.690ns (1.736ns logic, 2.954ns route) + (37.0% logic, 63.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.534ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 (FF) + Destination: lb_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.246ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X1Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 to lb_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X1Y25.CQ Tcko 0.198 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.D5 net (fanout=4) 0.352 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4 + SLICE_X2Y23.D Tilo 0.142 lb_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1 + P7.O net (fanout=2) 2.158 lb_bar_OBUF + P7.PAD Tioop 1.396 lb_bar + lb_bar_OBUF + lb_bar + ------------------------------------------------- --------------------------- + Total 4.246ns (1.736ns logic, 2.510ns route) + (40.9% logic, 59.1% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP +"clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 4 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 8.489ns. +-------------------------------------------------------------------------------- + +Paths for end point oe_ram_bar (P5.PAD), 4 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.178ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.423ns (Levels of Logic = 2) + Clock Path Delay: -0.251ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X2Y14.CLK net (fanout=226) 1.186 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.251ns (-3.088ns logic, 2.837ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X2Y14.CMUX Tshcko 0.455 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X0Y29.D2 net (fanout=8) 2.148 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2 + SLICE_X0Y29.D Tilo 0.203 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 3.236 oe_ram_bar_OBUF + P5.PAD Tioop 2.381 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 8.423ns (3.039ns logic, 5.384ns route) + (36.1% logic, 63.9% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.403ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 8.205ns (Levels of Logic = 2) + Clock Path Delay: -0.258ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X4Y14.CLK net (fanout=226) 1.179 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.258ns (-3.088ns logic, 2.830ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y14.AQ Tcko 0.447 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + SLICE_X0Y29.D4 net (fanout=5) 1.938 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + SLICE_X0Y29.D Tilo 0.203 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 3.236 oe_ram_bar_OBUF + P5.PAD Tioop 2.381 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 8.205ns (3.031ns logic, 5.174ns route) + (36.9% logic, 63.1% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 8.917ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 16.667ns + Data Path Delay: 7.752ns (Levels of Logic = 2) + Clock Path Delay: -0.319ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 1.118 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.319ns (-3.088ns logic, 2.769ns route) + + Maximum Data Path at Slow Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.408 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X0Y29.D5 net (fanout=7) 1.524 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X0Y29.D Tilo 0.203 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 3.236 oe_ram_bar_OBUF + P5.PAD Tioop 2.381 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 7.752ns (2.992ns logic, 4.760ns route) + (38.6% logic, 61.4% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point oe_ram_bar (P5.PAD), 4 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 4.313ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.961ns (Levels of Logic = 2) + Clock Path Delay: -0.331ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X4Y14.CLK net (fanout=226) 0.559 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.331ns (-1.698ns logic, 1.367ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X4Y14.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + SLICE_X0Y29.D4 net (fanout=5) 1.165 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32 + SLICE_X0Y29.D Tilo 0.156 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 2.010 oe_ram_bar_OBUF + P5.PAD Tioop 1.396 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 4.961ns (1.786ns logic, 3.175ns route) + (36.0% logic, 64.0% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.961ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.670ns (Levels of Logic = 2) + Clock Path Delay: -0.392ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X6Y17.CLK net (fanout=226) 0.498 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.392ns (-1.698ns logic, 1.306ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X6Y17.DQ Tcko 0.200 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X0Y29.D5 net (fanout=7) 0.908 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3 + SLICE_X0Y29.D Tilo 0.156 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 2.010 oe_ram_bar_OBUF + P5.PAD Tioop 1.396 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 4.670ns (1.752ns logic, 2.918ns route) + (37.5% logic, 62.5% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.521ns (clock arrival + clock path + data path - uncertainty) + Source: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 (FF) + Destination: oe_ram_bar (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.233ns (Levels of Logic = 2) + Clock Path Delay: -0.395ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X0Y25.CLK net (fanout=226) 0.495 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.395ns (-1.698ns logic, 1.303ns route) + + Minimum Data Path at Fast Process Corner: nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 to oe_ram_bar + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X0Y25.AQ Tcko 0.234 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X0Y29.D3 net (fanout=19) 0.437 nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1 + SLICE_X0Y29.D Tilo 0.156 oe_ram_bar_OBUF + nb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1 + P5.O net (fanout=1) 2.010 oe_ram_bar_OBUF + P5.PAD Tioop 1.396 oe_ram_bar + oe_ram_bar_OBUF + oe_ram_bar + ------------------------------------------------- --------------------------- + Total 4.233ns (1.786ns logic, 2.447ns route) + (42.2% logic, 57.8% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 7.518ns. +-------------------------------------------------------------------------------- + +Paths for end point MISO (P98.PAD), 1 path +-------------------------------------------------------------------------------- +Slack (slowest paths): 2.482ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: interfaz_spi/controlador_spi_esclavo/buffer_out_7 (FF) + Destination: MISO (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Requirement: 10.000ns + Data Path Delay: 7.479ns (Levels of Logic = 1) + Clock Path Delay: -0.278ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/buffer_out_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -4.718 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.577 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.209 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y8.CLK net (fanout=226) 1.159 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.278ns (-3.088ns logic, 2.810ns route) + + Maximum Data Path at Slow Process Corner: interfaz_spi/controlador_spi_esclavo/buffer_out_7 to MISO + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y8.CQ Tcko 0.391 interfaz_spi/controlador_spi_esclavo/buffer_out<7> + interfaz_spi/controlador_spi_esclavo/buffer_out_7 + P98.O net (fanout=1) 4.707 interfaz_spi/controlador_spi_esclavo/buffer_out<7> + P98.PAD Tioop 2.381 MISO + MISO_OBUF + MISO + ------------------------------------------------- --------------------------- + Total 7.479ns (2.772ns logic, 4.707ns route) + (37.1% logic, 62.9% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point MISO (P98.PAD), 1 path +-------------------------------------------------------------------------------- +Delay (fastest paths): 3.912ns (clock arrival + clock path + data path - uncertainty) + Source: interfaz_spi/controlador_spi_esclavo/buffer_out_7 (FF) + Destination: MISO (PAD) + Source Clock: clk_u_proc_BUFG rising at 0.000ns + Data Path Delay: 4.580ns (Levels of Logic = 1) + Clock Path Delay: -0.351ns (Levels of Logic = 4) + Clock Uncertainty: 0.317ns + + Clock Uncertainty: 0.317ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 0.283ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to interfaz_spi/controlador_spi_esclavo/buffer_out_7 + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X3Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X3Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_1 + SP6_BUFIO_INSERT_ML_BUFIO2_1 + DCM_X0Y0.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLK + DCM_X0Y0.CLKFX Tdmcko_CLKFX -2.642 clk_mang/DCM_SP_inst_int + clk_mang/DCM_SP_inst_int + BUFGMUX_X2Y4.I0 net (fanout=1) 0.231 clk_u_proc + BUFGMUX_X2Y4.O Tgi0o 0.059 clk_u_proc_BUFG + clk_u_proc_BUFG + SLICE_X9Y8.CLK net (fanout=226) 0.539 clk_u_proc_BUFG + ------------------------------------------------- --------------------------- + Total -0.351ns (-1.698ns logic, 1.347ns route) + + Minimum Data Path at Fast Process Corner: interfaz_spi/controlador_spi_esclavo/buffer_out_7 to MISO + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + SLICE_X9Y8.CQ Tcko 0.198 interfaz_spi/controlador_spi_esclavo/buffer_out<7> + interfaz_spi/controlador_spi_esclavo/buffer_out_7 + P98.O net (fanout=1) 2.986 interfaz_spi/controlador_spi_esclavo/buffer_out<7> + P98.PAD Tioop 1.396 MISO + MISO_OBUF + MISO + ------------------------------------------------- --------------------------- + Total 4.580ns (1.594ns logic, 2.986ns route) + (34.8% logic, 65.2% route) + +-------------------------------------------------------------------------------- + +================================================================================ +Timing constraint: COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"; +For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612). + + 2 paths analyzed, 1 endpoint analyzed, 0 failing endpoints + 0 timing errors detected. + Minimum allowable offset is 35.651ns. +-------------------------------------------------------------------------------- + +Paths for end point clk_to_acq (P80.PAD), 2 paths +-------------------------------------------------------------------------------- +Slack (slowest paths): 4.349ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: clk_mang/ODDR2_inst (FF) + Destination: clk_to_acq (PAD) + Source Clock: clk_mang/c_16MHz_BUFG falling at 31.250ns + Requirement: 40.000ns + Data Path Delay: 3.336ns (Levels of Logic = 1) + Clock Path Delay: 0.165ns (Levels of Logic = 4) + Clock Uncertainty: 0.900ns + + Clock Uncertainty: 0.900ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 1.450ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to clk_mang/ODDR2_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X1Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X1Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_0 + SP6_BUFIO_INSERT_ML_BUFIO2_0 + DCM_X0Y1.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_ML_NEW_DIVCLK + DCM_X0Y1.CLKFX Tdmcko_CLKFX -4.659 clk_mang/DCM_SP_inst + clk_mang/DCM_SP_inst + BUFGMUX_X2Y2.I0 net (fanout=1) 0.577 clk_mang/c_16MHz + BUFGMUX_X2Y2.O Tgi0o 0.209 clk_mang/c_16MHz_BUFG + clk_mang/c_16MHz_BUFG + OLOGIC_X12Y22.CLK1 net (fanout=2) 1.543 clk_mang/c_16MHz_BUFG + ------------------------------------------------- --------------------------- + Total 0.165ns (-3.029ns logic, 3.194ns route) + + Maximum Data Path at Slow Process Corner: clk_mang/ODDR2_inst to clk_to_acq + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X12Y22.OQ Tockq 0.722 clk_to_acq_OBUF + clk_mang/ODDR2_inst + P80.O net (fanout=1) 0.233 clk_to_acq_OBUF + P80.PAD Tioop 2.381 clk_to_acq + clk_to_acq_OBUF + clk_to_acq + ------------------------------------------------- --------------------------- + Total 3.336ns (3.103ns logic, 0.233ns route) + (93.0% logic, 7.0% route) + +-------------------------------------------------------------------------------- +Slack (slowest paths): 35.575ns (requirement - (clock arrival + clock path + data path + uncertainty)) + Source: clk_mang/ODDR2_inst (FF) + Destination: clk_to_acq (PAD) + Source Clock: clk_mang/c_16MHz_BUFG rising at 0.000ns + Requirement: 40.000ns + Data Path Delay: 3.356ns (Levels of Logic = 1) + Clock Path Delay: 0.169ns (Levels of Logic = 4) + Clock Uncertainty: 0.900ns + + Clock Uncertainty: 0.900ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 1.450ns + Phase Error (PE): 0.150ns + + Maximum Clock Path at Slow Process Corner: clk_main to clk_mang/ODDR2_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 1.310 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X1Y0.I net (fanout=2) 0.428 clk_main_io + BUFIO2_X1Y0.DIVCLK Tbufcko_DIVCLK 0.111 SP6_BUFIO_INSERT_ML_BUFIO2_0 + SP6_BUFIO_INSERT_ML_BUFIO2_0 + DCM_X0Y1.CLKIN net (fanout=1) 0.646 clk_mang/DCM_SP_inst_ML_NEW_DIVCLK + DCM_X0Y1.CLKFX Tdmcko_CLKFX -4.659 clk_mang/DCM_SP_inst + clk_mang/DCM_SP_inst + BUFGMUX_X2Y2.I0 net (fanout=1) 0.577 clk_mang/c_16MHz + BUFGMUX_X2Y2.O Tgi0o 0.209 clk_mang/c_16MHz_BUFG + clk_mang/c_16MHz_BUFG + OLOGIC_X12Y22.CLK0 net (fanout=2) 1.547 clk_mang/c_16MHz_BUFG + ------------------------------------------------- --------------------------- + Total 0.169ns (-3.029ns logic, 3.198ns route) + + Maximum Data Path at Slow Process Corner: clk_mang/ODDR2_inst to clk_to_acq + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X12Y22.OQ Tockq 0.742 clk_to_acq_OBUF + clk_mang/ODDR2_inst + P80.O net (fanout=1) 0.233 clk_to_acq_OBUF + P80.PAD Tioop 2.381 clk_to_acq + clk_to_acq_OBUF + clk_to_acq + ------------------------------------------------- --------------------------- + Total 3.356ns (3.123ns logic, 0.233ns route) + (93.1% logic, 6.9% route) + +-------------------------------------------------------------------------------- + +Fastest Paths: COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"; +-------------------------------------------------------------------------------- + +Paths for end point clk_to_acq (P80.PAD), 2 paths +-------------------------------------------------------------------------------- +Delay (fastest paths): 32.071ns (clock arrival + clock path + data path - uncertainty) + Source: clk_mang/ODDR2_inst (FF) + Destination: clk_to_acq (PAD) + Source Clock: clk_mang/c_16MHz_BUFG falling at 31.250ns + Data Path Delay: 2.011ns (Levels of Logic = 1) + Clock Path Delay: -0.290ns (Levels of Logic = 4) + Clock Uncertainty: 0.900ns + + Clock Uncertainty: 0.900ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 1.450ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to clk_mang/ODDR2_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X1Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X1Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 + SP6_BUFIO_INSERT_ML_BUFIO2_0 + DCM_X0Y1.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_ML_NEW_DIVCLK + DCM_X0Y1.CLKFX Tdmcko_CLKFX -2.650 clk_mang/DCM_SP_inst + clk_mang/DCM_SP_inst + BUFGMUX_X2Y2.I0 net (fanout=1) 0.231 clk_mang/c_16MHz + BUFGMUX_X2Y2.O Tgi0o 0.059 clk_mang/c_16MHz_BUFG + clk_mang/c_16MHz_BUFG + OLOGIC_X12Y22.CLK1 net (fanout=2) 0.608 clk_mang/c_16MHz_BUFG + ------------------------------------------------- --------------------------- + Total -0.290ns (-1.706ns logic, 1.416ns route) + + Minimum Data Path at Fast Process Corner: clk_mang/ODDR2_inst to clk_to_acq + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X12Y22.OQ Tockq 0.425 clk_to_acq_OBUF + clk_mang/ODDR2_inst + P80.O net (fanout=1) 0.190 clk_to_acq_OBUF + P80.PAD Tioop 1.396 clk_to_acq + clk_to_acq_OBUF + clk_to_acq + ------------------------------------------------- --------------------------- + Total 2.011ns (1.821ns logic, 0.190ns route) + (90.6% logic, 9.4% route) + +-------------------------------------------------------------------------------- +Delay (fastest paths): 0.886ns (clock arrival + clock path + data path - uncertainty) + Source: clk_mang/ODDR2_inst (FF) + Destination: clk_to_acq (PAD) + Source Clock: clk_mang/c_16MHz_BUFG rising at 0.000ns + Data Path Delay: 2.005ns (Levels of Logic = 1) + Clock Path Delay: -0.219ns (Levels of Logic = 4) + Clock Uncertainty: 0.900ns + + Clock Uncertainty: 0.900ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE + Total System Jitter (TSJ): 0.050ns + Total Input Jitter (TIJ): 0.000ns + Discrete Jitter (DJ): 1.450ns + Phase Error (PE): 0.150ns + + Minimum Clock Path at Fast Process Corner: clk_main to clk_mang/ODDR2_inst + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + P51.I Tiopi 0.763 clk_main + clk_main + IBUFG_inst + ProtoComp52.IMUX.24 + BUFIO2_X1Y0.I net (fanout=2) 0.235 clk_main_io + BUFIO2_X1Y0.DIVCLK Tbufcko_DIVCLK 0.122 SP6_BUFIO_INSERT_ML_BUFIO2_0 + SP6_BUFIO_INSERT_ML_BUFIO2_0 + DCM_X0Y1.CLKIN net (fanout=1) 0.342 clk_mang/DCM_SP_inst_ML_NEW_DIVCLK + DCM_X0Y1.CLKFX Tdmcko_CLKFX -2.650 clk_mang/DCM_SP_inst + clk_mang/DCM_SP_inst + BUFGMUX_X2Y2.I0 net (fanout=1) 0.231 clk_mang/c_16MHz + BUFGMUX_X2Y2.O Tgi0o 0.059 clk_mang/c_16MHz_BUFG + clk_mang/c_16MHz_BUFG + OLOGIC_X12Y22.CLK0 net (fanout=2) 0.679 clk_mang/c_16MHz_BUFG + ------------------------------------------------- --------------------------- + Total -0.219ns (-1.706ns logic, 1.487ns route) + + Minimum Data Path at Fast Process Corner: clk_mang/ODDR2_inst to clk_to_acq + Location Delay type Delay(ns) Physical Resource + Logical Resource(s) + ------------------------------------------------- ------------------- + OLOGIC_X12Y22.OQ Tockq 0.419 clk_to_acq_OBUF + clk_mang/ODDR2_inst + P80.O net (fanout=1) 0.190 clk_to_acq_OBUF + P80.PAD Tioop 1.396 clk_to_acq + clk_to_acq_OBUF + clk_to_acq + ------------------------------------------------- --------------------------- + Total 2.005ns (1.815ns logic, 0.190ns route) + (90.5% logic, 9.5% route) + +-------------------------------------------------------------------------------- + + +Derived Constraint Report +Derived Constraints for TS_clk_main ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +| | Period | Actual Period | Timing Errors | Paths Analyzed | +| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| +| | | Direct | Derivative | Direct | Derivative | Direct | Derivative | ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ +|TS_clk_main | 16.667ns| 8.000ns| 15.212ns| 0| 0| 0| 5931| +| TS_clk_u_proc | 4.167ns| 3.803ns| N/A| 0| 0| 5931| 0| +| TS_clk_mang_c_16MHz | 62.501ns| 1.730ns| N/A| 0| 0| 0| 0| ++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ + +All constraints were met. + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Setup/Hold to clock clk_main +-------------------+------------+------------+------------+------------+------------------+--------+ + |Max Setup to| Process |Max Hold to | Process | | Clock | +Source | clk (edge) | Corner | clk (edge) | Corner |Internal Clock(s) | Phase | +-------------------+------------+------------+------------+------------+------------------+--------+ +CS | 6.292(R)| SLOW | -2.894(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<0> | 4.440(R)| SLOW | -1.842(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<1> | 4.790(R)| SLOW | -2.068(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<2> | 4.645(R)| SLOW | -1.974(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<3> | 4.773(R)| SLOW | -2.073(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<4> | 4.834(R)| SLOW | -2.135(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<5> | 4.683(R)| SLOW | -2.004(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<6> | 5.011(R)| SLOW | -2.222(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<7> | 4.791(R)| SLOW | -2.009(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<8> | 5.916(R)| SLOW | -2.696(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<9> | 6.074(R)| SLOW | -2.753(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<10> | 5.982(R)| SLOW | -2.754(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<11> | 7.691(R)| SLOW | -3.780(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<12> | 7.196(R)| SLOW | -3.503(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<13> | 7.201(R)| SLOW | -3.481(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<14> | 7.132(R)| SLOW | -3.461(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<15> | 7.503(R)| SLOW | -3.702(R)| FAST |clk_u_proc_BUFG | 0.000| +MOSI | 7.179(R)| SLOW | -3.457(R)| FAST |clk_u_proc_BUFG | 0.000| +SCK | 5.534(R)| SLOW | -2.480(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch1<0>| 4.341(R)| SLOW | -1.731(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch1<1>| 4.578(R)| SLOW | -1.907(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch1<2>| 4.386(R)| SLOW | -1.744(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch1<3>| 4.505(R)| SLOW | -1.822(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch2<0>| 4.569(R)| SLOW | -1.984(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch2<1>| 4.579(R)| SLOW | -1.962(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch2<2>| 4.911(R)| SLOW | -2.089(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch2<3>| 4.465(R)| SLOW | -1.842(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch3<0>| 4.465(R)| SLOW | -1.818(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch3<1>| 4.807(R)| SLOW | -2.066(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch3<2>| 5.509(R)| SLOW | -2.506(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch3<3>| 5.085(R)| SLOW | -2.309(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch4<0>| 4.465(R)| SLOW | -1.843(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch4<1>| 4.480(R)| SLOW | -1.888(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch4<2>| 4.577(R)| SLOW | -1.923(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch4<3>| 4.954(R)| SLOW | -2.133(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch5<0>| 4.536(R)| SLOW | -1.894(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch5<1>| 4.238(R)| SLOW | -1.687(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch5<2>| 5.132(R)| SLOW | -2.294(R)| FAST |clk_u_proc_BUFG | 0.000| +chn_bits_acq_ch5<3>| 4.088(R)| SLOW | -1.582(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_acq_ch1 | 4.828(R)| SLOW | -2.085(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_acq_ch2 | 5.021(R)| SLOW | -2.226(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_acq_ch3 | 4.711(R)| SLOW | -2.027(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_acq_ch4 | 5.877(R)| SLOW | -2.755(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_acq_ch5 | 5.861(R)| SLOW | -2.688(R)| FAST |clk_u_proc_BUFG | 0.000| +lock | 6.085(R)| SLOW | -1.602(R)| FAST |clk_u_proc_BUFG | 0.000| +pps | 4.685(R)| SLOW | -1.955(R)| FAST |clk_u_proc_BUFG | 0.000| +scl_rpi | 4.954(R)| SLOW | -2.053(R)| FAST |clk_u_proc_BUFG | 0.000| +sda_rpi | 3.976(R)| SLOW | -1.530(R)| FAST |clk_u_proc_BUFG | 0.000| +-------------------+------------+------------+------------+------------+------------------+--------+ + +Clock clk_main to Pad +--------------+-----------------+------------+-----------------+------------+---------------------+--------+ + |Max (slowest) clk| Process |Min (fastest) clk| Process | | Clock | +Destination | (edge) to PAD | Corner | (edge) to PAD | Corner |Internal Clock(s) | Phase | +--------------+-----------------+------------+-----------------+------------+---------------------+--------+ +DATA_INOUT<0> | 13.530(R)| SLOW | 3.188(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<1> | 13.456(R)| SLOW | 3.188(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<2> | 13.384(R)| SLOW | 3.210(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<3> | 13.461(R)| SLOW | 3.210(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<4> | 13.747(R)| SLOW | 3.481(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<5> | 14.057(R)| SLOW | 3.481(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<6> | 14.600(R)| SLOW | 3.545(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<7> | 13.357(R)| SLOW | 3.545(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<8> | 12.820(R)| SLOW | 2.991(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<9> | 12.627(R)| SLOW | 3.094(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<10>| 12.614(R)| SLOW | 3.094(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<11>| 12.308(R)| SLOW | 3.434(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<12>| 12.094(R)| SLOW | 3.410(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<13>| 12.781(R)| SLOW | 3.633(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<14>| 13.253(R)| SLOW | 3.324(R)| FAST |clk_u_proc_BUFG | 0.000| +DATA_INOUT<15>| 12.489(R)| SLOW | 3.744(R)| FAST |clk_u_proc_BUFG | 0.000| +MISO | 7.518(R)| SLOW | 3.912(R)| FAST |clk_u_proc_BUFG | 0.000| +clk_to_acq | 4.425(R)| SLOW | 0.886(R)| FAST |clk_mang/c_16MHz_BUFG| 0.000| + | 35.651(F)| SLOW | 32.071(F)| FAST |clk_mang/c_16MHz_BUFG| 31.250| +lb_bar | 8.246(R)| SLOW | 3.534(R)| FAST |clk_u_proc_BUFG | 0.000| +oe_ram_bar | 8.489(R)| SLOW | 3.521(R)| FAST |clk_u_proc_BUFG | 0.000| +scl_rpi | 13.744(R)| SLOW | 10.608(R)| FAST |clk_u_proc_BUFG | 0.000| +sda_rpi | 13.152(R)| SLOW | 10.248(R)| FAST |clk_u_proc_BUFG | 0.000| +ub_bar | 8.621(R)| SLOW | 3.781(R)| FAST |clk_u_proc_BUFG | 0.000| +we_bar | 8.269(R)| SLOW | 3.177(R)| FAST |clk_u_proc_BUFG | 0.000| +--------------+-----------------+------------+-----------------+------------+---------------------+--------+ + +Clock to Setup on destination clock clk_main +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +clk_main | 3.803| | | | +---------------+---------+---------+---------+---------+ + +COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.801; Ideal Clock Offset To Actual Clock -2.731; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<15> | 7.503(R)| SLOW | -3.702(R)| FAST | 9.164| 3.702| 2.731| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.503| - | -3.702| - | 9.164| 3.702| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.671; Ideal Clock Offset To Actual Clock -3.037; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<14> | 7.132(R)| SLOW | -3.461(R)| FAST | 9.535| 3.461| 3.037| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.132| - | -3.461| - | 9.535| 3.461| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.720; Ideal Clock Offset To Actual Clock -2.992; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<13> | 7.201(R)| SLOW | -3.481(R)| FAST | 9.466| 3.481| 2.992| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.201| - | -3.481| - | 9.466| 3.481| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.693; Ideal Clock Offset To Actual Clock -2.984; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<12> | 7.196(R)| SLOW | -3.503(R)| FAST | 9.471| 3.503| 2.984| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.196| - | -3.503| - | 9.471| 3.503| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.911; Ideal Clock Offset To Actual Clock -2.598; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<11> | 7.691(R)| SLOW | -3.780(R)| FAST | 8.976| 3.780| 2.598| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.691| - | -3.780| - | 8.976| 3.780| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.228; Ideal Clock Offset To Actual Clock -3.966; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<10> | 5.982(R)| SLOW | -2.754(R)| FAST | 10.685| 2.754| 3.966| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.982| - | -2.754| - | 10.685| 2.754| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.321; Ideal Clock Offset To Actual Clock -3.920; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<9> | 6.074(R)| SLOW | -2.753(R)| FAST | 10.593| 2.753| 3.920| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 6.074| - | -2.753| - | 10.593| 2.753| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.220; Ideal Clock Offset To Actual Clock -4.028; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<8> | 5.916(R)| SLOW | -2.696(R)| FAST | 10.751| 2.696| 4.028| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.916| - | -2.696| - | 10.751| 2.696| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.782; Ideal Clock Offset To Actual Clock -4.933; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<7> | 4.791(R)| SLOW | -2.009(R)| FAST | 11.876| 2.009| 4.933| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.791| - | -2.009| - | 11.876| 2.009| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.789; Ideal Clock Offset To Actual Clock -4.717; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<6> | 5.011(R)| SLOW | -2.222(R)| FAST | 11.656| 2.222| 4.717| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.011| - | -2.222| - | 11.656| 2.222| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.679; Ideal Clock Offset To Actual Clock -4.990; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<5> | 4.683(R)| SLOW | -2.004(R)| FAST | 11.984| 2.004| 4.990| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.683| - | -2.004| - | 11.984| 2.004| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.699; Ideal Clock Offset To Actual Clock -4.849; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<4> | 4.834(R)| SLOW | -2.135(R)| FAST | 11.833| 2.135| 4.849| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.834| - | -2.135| - | 11.833| 2.135| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.700; Ideal Clock Offset To Actual Clock -4.911; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<3> | 4.773(R)| SLOW | -2.073(R)| FAST | 11.894| 2.073| 4.911| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.773| - | -2.073| - | 11.894| 2.073| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.671; Ideal Clock Offset To Actual Clock -5.024; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<2> | 4.645(R)| SLOW | -1.974(R)| FAST | 12.022| 1.974| 5.024| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.645| - | -1.974| - | 12.022| 1.974| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.722; Ideal Clock Offset To Actual Clock -4.905; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<1> | 4.790(R)| SLOW | -2.068(R)| FAST | 11.877| 2.068| 4.905| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.790| - | -2.068| - | 11.877| 2.068| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.598; Ideal Clock Offset To Actual Clock -5.193; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +DATA_INOUT<0> | 4.440(R)| SLOW | -1.842(R)| FAST | 12.227| 1.842| 5.193| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.440| - | -1.842| - | 12.227| 1.842| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.446; Ideal Clock Offset To Actual Clock -5.581; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +sda_rpi | 3.976(R)| SLOW | -1.530(R)| FAST | 12.691| 1.530| 5.581| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 3.976| - | -1.530| - | 12.691| 1.530| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.901; Ideal Clock Offset To Actual Clock -4.830; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +scl_rpi | 4.954(R)| SLOW | -2.053(R)| FAST | 11.713| 2.053| 4.830| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.954| - | -2.053| - | 11.713| 2.053| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.683; Ideal Clock Offset To Actual Clock -5.170; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch1<3>| 4.505(R)| SLOW | -1.822(R)| FAST | 12.162| 1.822| 5.170| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.505| - | -1.822| - | 12.162| 1.822| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.642; Ideal Clock Offset To Actual Clock -5.269; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch1<2>| 4.386(R)| SLOW | -1.744(R)| FAST | 12.281| 1.744| 5.269| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.386| - | -1.744| - | 12.281| 1.744| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.671; Ideal Clock Offset To Actual Clock -5.091; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch1<1>| 4.578(R)| SLOW | -1.907(R)| FAST | 12.089| 1.907| 5.091| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.578| - | -1.907| - | 12.089| 1.907| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.610; Ideal Clock Offset To Actual Clock -5.298; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch1<0>| 4.341(R)| SLOW | -1.731(R)| FAST | 12.326| 1.731| 5.298| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.341| - | -1.731| - | 12.326| 1.731| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.623; Ideal Clock Offset To Actual Clock -396.847; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch2<3>| 4.465(R)| SLOW | -1.842(R)| FAST | 795.535| 1.842| 396.847| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.465| - | -1.842| - | 795.535| 1.842| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.822; Ideal Clock Offset To Actual Clock -396.500; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch2<2>| 4.911(R)| SLOW | -2.089(R)| FAST | 795.089| 2.089| 396.500| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.911| - | -2.089| - | 795.089| 2.089| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.617; Ideal Clock Offset To Actual Clock -396.730; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch2<1>| 4.579(R)| SLOW | -1.962(R)| FAST | 795.421| 1.962| 396.730| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.579| - | -1.962| - | 795.421| 1.962| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.585; Ideal Clock Offset To Actual Clock -396.724; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch2<0>| 4.569(R)| SLOW | -1.984(R)| FAST | 795.431| 1.984| 396.724| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.569| - | -1.984| - | 795.431| 1.984| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.776; Ideal Clock Offset To Actual Clock -4.637; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch3<3>| 5.085(R)| SLOW | -2.309(R)| FAST | 11.582| 2.309| 4.637| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 5.085| - | -2.309| - | 11.582| 2.309| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.003; Ideal Clock Offset To Actual Clock -4.326; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch3<2>| 5.509(R)| SLOW | -2.506(R)| FAST | 11.158| 2.506| 4.326| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 5.509| - | -2.506| - | 11.158| 2.506| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.741; Ideal Clock Offset To Actual Clock -4.897; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch3<1>| 4.807(R)| SLOW | -2.066(R)| FAST | 11.860| 2.066| 4.897| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.807| - | -2.066| - | 11.860| 2.066| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.647; Ideal Clock Offset To Actual Clock -5.192; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch3<0>| 4.465(R)| SLOW | -1.818(R)| FAST | 12.202| 1.818| 5.192| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.465| - | -1.818| - | 12.202| 1.818| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.821; Ideal Clock Offset To Actual Clock -4.790; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch4<3>| 4.954(R)| SLOW | -2.133(R)| FAST | 11.713| 2.133| 4.790| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.954| - | -2.133| - | 11.713| 2.133| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.654; Ideal Clock Offset To Actual Clock -5.084; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch4<2>| 4.577(R)| SLOW | -1.923(R)| FAST | 12.090| 1.923| 5.084| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.577| - | -1.923| - | 12.090| 1.923| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.592; Ideal Clock Offset To Actual Clock -5.150; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch4<1>| 4.480(R)| SLOW | -1.888(R)| FAST | 12.187| 1.888| 5.150| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.480| - | -1.888| - | 12.187| 1.888| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.622; Ideal Clock Offset To Actual Clock -5.180; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch4<0>| 4.465(R)| SLOW | -1.843(R)| FAST | 12.202| 1.843| 5.180| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.465| - | -1.843| - | 12.202| 1.843| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.506; Ideal Clock Offset To Actual Clock -5.499; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch5<3>| 4.088(R)| SLOW | -1.582(R)| FAST | 12.579| 1.582| 5.499| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.088| - | -1.582| - | 12.579| 1.582| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.838; Ideal Clock Offset To Actual Clock -4.621; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch5<2>| 5.132(R)| SLOW | -2.294(R)| FAST | 11.535| 2.294| 4.621| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 5.132| - | -2.294| - | 11.535| 2.294| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.551; Ideal Clock Offset To Actual Clock -5.371; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch5<1>| 4.238(R)| SLOW | -1.687(R)| FAST | 12.429| 1.687| 5.371| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.238| - | -1.687| - | 12.429| 1.687| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.642; Ideal Clock Offset To Actual Clock -5.119; +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +chn_bits_acq_ch5<0>| 4.536(R)| SLOW | -1.894(R)| FAST | 12.131| 1.894| 5.119| +-------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary | 4.536| - | -1.894| - | 12.131| 1.894| | +-------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 4.483; Ideal Clock Offset To Actual Clock -4.490; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +lock | 6.085(R)| SLOW | -1.602(R)| FAST | 10.582| 1.602| 4.490| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 6.085| - | -1.602| - | 10.582| 1.602| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.730; Ideal Clock Offset To Actual Clock -5.013; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +pps | 4.685(R)| SLOW | -1.955(R)| FAST | 11.982| 1.955| 5.013| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.685| - | -1.955| - | 11.982| 1.955| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.743; Ideal Clock Offset To Actual Clock -396.544; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +clk_acq_ch1 | 4.828(R)| SLOW | -2.085(R)| FAST | 795.172| 2.085| 396.544| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.828| - | -2.085| - | 795.172| 2.085| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.795; Ideal Clock Offset To Actual Clock -4.710; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +clk_acq_ch2 | 5.021(R)| SLOW | -2.226(R)| FAST | 11.646| 2.226| 4.710| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.021| - | -2.226| - | 11.646| 2.226| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 2.684; Ideal Clock Offset To Actual Clock -4.964; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +clk_acq_ch3 | 4.711(R)| SLOW | -2.027(R)| FAST | 11.956| 2.027| 4.964| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 4.711| - | -2.027| - | 11.956| 2.027| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.122; Ideal Clock Offset To Actual Clock -4.018; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +clk_acq_ch4 | 5.877(R)| SLOW | -2.755(R)| FAST | 10.790| 2.755| 4.018| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.877| - | -2.755| - | 10.790| 2.755| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.173; Ideal Clock Offset To Actual Clock -4.059; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +clk_acq_ch5 | 5.861(R)| SLOW | -2.688(R)| FAST | 10.806| 2.688| 4.059| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.861| - | -2.688| - | 10.806| 2.688| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.722; Ideal Clock Offset To Actual Clock -0.682; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +MOSI | 7.179(R)| SLOW | -3.457(R)| FAST | 4.821| 3.457| 0.682| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 7.179| - | -3.457| - | 4.821| 3.457| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.054; Ideal Clock Offset To Actual Clock -8.493; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +SCK | 5.534(R)| SLOW | -2.480(R)| FAST | 19.466| 2.480| 8.493| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 5.534| - | -2.480| - | 19.466| 2.480| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +Worst Case Data Window 3.398; Ideal Clock Offset To Actual Clock -1.407; +------------------+------------+------------+------------+------------+---------+---------+-------------+ + | | Process | | Process | Setup | Hold |Source Offset| +Source | Setup | Corner | Hold | Corner | Slack | Slack | To Center | +------------------+------------+------------+------------+------------+---------+---------+-------------+ +CS | 6.292(R)| SLOW | -2.894(R)| FAST | 5.708| 2.894| 1.407| +------------------+------------+------------+------------+------------+---------+---------+-------------+ +Worst Case Summary| 6.292| - | -2.894| - | 5.708| 2.894| | +------------------+------------+------------+------------+------------+---------+---------+-------------+ + +COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<15> | 12.489| SLOW | 3.744| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<14> | 13.253| SLOW | 3.324| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<13> | 12.781| SLOW | 3.633| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<12> | 12.094| SLOW | 3.410| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<11> | 12.308| SLOW | 3.434| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<10> | 12.614| SLOW | 3.094| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<9> | 12.627| SLOW | 3.094| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<8> | 12.820| SLOW | 2.991| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<7> | 13.357| SLOW | 3.545| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<6> | 14.600| SLOW | 3.545| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<5> | 14.057| SLOW | 3.481| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<4> | 13.747| SLOW | 3.481| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<3> | 13.461| SLOW | 3.210| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<2> | 13.384| SLOW | 3.210| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<1> | 13.456| SLOW | 3.188| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +DATA_INOUT<0> | 13.530| SLOW | 3.188| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +sda_rpi | 13.152| SLOW | 10.248| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +scl_rpi | 13.744| SLOW | 10.608| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +we_bar | 8.269| SLOW | 3.177| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +ub_bar | 8.621| SLOW | 3.781| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +lb_bar | 8.246| SLOW | 3.534| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +oe_ram_bar | 8.489| SLOW | 3.521| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +MISO | 7.518| SLOW | 3.912| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + +COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"; +Bus Skew: 0.000 ns; +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + |Max (slowest)| Process |Min (fastest)| Process | | +PAD | Delay (ns) | Corner | Delay (ns) | Corner |Edge Skew (ns)| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ +clk_to_acq | 35.651| SLOW | 32.071| FAST | 0.000| +-----------------------------------------------+-------------+------------+-------------+------------+--------------+ + + +Timing summary: +--------------- + +Timing errors: 0 Score: 0 (Setup/Max: 0, Hold: 0) + +Constraints cover 10930 paths, 0 nets, and 3847 connections + +Design statistics: + Minimum period: 8.000ns{1} (Maximum frequency: 125.000MHz) + Minimum input required time before clock: 7.691ns + Minimum output required time after clock: 35.651ns + + +------------------------------------Footnotes----------------------------------- +1) The minimum period statistic assumes all single cycle delays. + +Analysis completed Mon May 23 12:38:55 2016 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 242 MB + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twx =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twx b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twx new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.twx (revision 224) @@ -0,0 +1,612 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.7 Trace (nt64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 +-n 3 -fastpaths -xml chn5_mem_spi_joint.twx chn5_mem_spi_joint.ncd -o +chn5_mem_spi_joint.twr chn5_mem_spi_joint.pcf -ucf chn5_mem_spi_joint.ucf + +chn5_mem_spi_joint.ncdchn5_mem_spi_joint.ncdchn5_mem_spi_joint.pcfchn5_mem_spi_joint.pcfxc6slx9C-3PRODUCTION 1.23 2013-10-1313INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%;00000008.000Component Switching Limit Checks: TS_clk_main = PERIOD TIMEGRP "clk_main" 16.667 ns HIGH 50%;TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%;59310000224003.803Paths for end point nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13 (SLICE_X6Y41.SR), 6 paths +0.363lock_rst_barnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd133.639-0.0134.1660.177lock_rst_barnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131SLICE_X14Y22.CLKclk_u_proc_BUFGSLICE_X14Y22.AQTcko0.408lock_rst_barlock_rst_barSLICE_X7Y20.C1net261.081lock_rst_barSLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y41.SRnet111.484nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y41.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131.0742.5653.639clk_u_proc_BUFG29.570.50.365pps_rstnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd133.635-0.0114.1660.177pps_rstnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131SLICE_X12Y26.CLKclk_u_proc_BUFGSLICE_X12Y26.DQTcko0.447pps_rstpps_rstSLICE_X7Y20.C6net1191.038pps_rstSLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y41.SRnet111.484nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y41.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131.1132.5223.635clk_u_proc_BUFG30.669.40.419nb_mem_cont/ram_control/count_slw_3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd133.4740.0964.1660.177nb_mem_cont/ram_control/count_slw_3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131SLICE_X7Y15.CLKclk_u_proc_BUFGSLICE_X7Y15.CMUXTshcko0.461nb_mem_cont/ram_control/count_slw<1>nb_mem_cont/ram_control/count_slw_3SLICE_X7Y20.C2net170.863nb_mem_cont/ram_control/count_slw<3>SLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y41.SRnet111.484nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y41.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd131.1272.3473.474clk_u_proc_BUFG32.467.6Paths for end point nb_mem_cont/ram_control/rel_pos_ch4_int_1 (SLICE_X7Y46.C2), 31 paths +0.366nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13.6100.0134.1660.177nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X7Y46.D5net511.605nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X7Y46.DTilo0.259nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW0SLICE_X7Y46.A3net10.291N159SLICE_X7Y46.ATilo0.259nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.C2net10.427nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.CLKTas0.322nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1nb_mem_cont/ram_control/rel_pos_ch4_int_11.2872.3233.610clk_u_proc_BUFG35.764.30.444nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13.5320.0134.1660.177nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X8Y42.D6net511.108nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X8Y42.CMUXTopdc0.368N161nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2_Fnb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2SLICE_X7Y46.A6net10.601N161SLICE_X7Y46.ATilo0.259nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.C2net10.427nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.CLKTas0.322nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1nb_mem_cont/ram_control/rel_pos_ch4_int_11.3962.1363.532clk_u_proc_BUFG39.560.50.451nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13.5250.0134.1660.177nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/rel_pos_ch4_int_13SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X8Y42.C6net511.108nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X8Y42.CMUXTilo0.361N161nb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2_Gnb_mem_cont/ram_control/ram_contr_cur_state__n0381_inv2_SW2SLICE_X7Y46.A6net10.601N161SLICE_X7Y46.ATilo0.259nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.C2net10.427nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpotSLICE_X7Y46.CLKTas0.322nb_mem_cont/ram_control/rel_pos_ch4_int<1>nb_mem_cont/ram_control/rel_pos_ch4_int_1_rstpot1nb_mem_cont/ram_control/rel_pos_ch4_int_11.3892.1363.525clk_u_proc_BUFG39.460.6Paths for end point nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10 (SLICE_X6Y38.SR), 6 paths +0.386lock_rst_barnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd103.616-0.0134.1660.177lock_rst_barnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101SLICE_X14Y22.CLKclk_u_proc_BUFGSLICE_X14Y22.AQTcko0.408lock_rst_barlock_rst_barSLICE_X7Y20.C1net261.081lock_rst_barSLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y38.SRnet111.461nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y38.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101.0742.5423.616clk_u_proc_BUFG29.770.30.388pps_rstnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd103.612-0.0114.1660.177pps_rstnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101SLICE_X12Y26.CLKclk_u_proc_BUFGSLICE_X12Y26.DQTcko0.447pps_rstpps_rstSLICE_X7Y20.C6net1191.038pps_rstSLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y38.SRnet111.461nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y38.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101.1132.4993.612clk_u_proc_BUFG30.869.20.442nb_mem_cont/ram_control/count_slw_3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd103.4510.0964.1660.177nb_mem_cont/ram_control/count_slw_3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101SLICE_X7Y15.CLKclk_u_proc_BUFGSLICE_X7Y15.CMUXTshcko0.461nb_mem_cont/ram_control/count_slw<1>nb_mem_cont/ram_control/count_slw_3SLICE_X7Y20.C2net170.863nb_mem_cont/ram_control/count_slw<3>SLICE_X7Y20.CTilo0.259nb_mem_cont/ram_control/addr_erase_aux_int<4>nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_01SLICE_X6Y38.SRnet111.461nb_mem_cont/ram_control/PWR_14_o_count_slw[3]_equal_153_o_0SLICE_X6Y38.CLKTsrck0.407nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd10nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd101.1272.3243.451clk_u_proc_BUFG32.767.3Hold Paths: TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%; +Paths for end point interfaz_spi/controlador_spi_esclavo/buffer_in_3 (SLICE_X14Y5.DX), 1 path +0.385interfaz_spi/controlador_spi_esclavo/buffer_in_2interfaz_spi/controlador_spi_esclavo/buffer_in_30.3850.0000.0000.000interfaz_spi/controlador_spi_esclavo/buffer_in_2interfaz_spi/controlador_spi_esclavo/buffer_in_30SLICE_X14Y5.CLKclk_u_proc_BUFGSLICE_X14Y5.CQTcko0.200interfaz_spi/controlador_spi_esclavo/buffer_in<3>interfaz_spi/controlador_spi_esclavo/buffer_in_2SLICE_X14Y5.DXnet20.137interfaz_spi/controlador_spi_esclavo/buffer_in<2>SLICE_X14Y5.CLKTckdi0.048interfaz_spi/controlador_spi_esclavo/buffer_in<3>interfaz_spi/controlador_spi_esclavo/buffer_in_30.2480.1370.385clk_u_proc_BUFG64.435.6Paths for end point nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_8 (SLICE_X14Y38.AX), 1 path +0.388nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_80.390-0.0020.0000.000nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_80SLICE_X15Y38.CLKclk_u_proc_BUFGSLICE_X15Y38.AQTcko0.198nb_mem_cont/nibble_pack_ch3/resul_mem_internal<11>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_8SLICE_X14Y38.AXnet20.144nb_mem_cont/nibble_pack_ch3/resul_mem_internal<8>SLICE_X14Y38.CLKTckdi0.048nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_80.2460.1440.390clk_u_proc_BUFG63.136.9Paths for end point interfaz_spi/cabecera_memoria/ptr_mem_2 (SLICE_X6Y4.B5), 1 path +0.400interfaz_spi/cabecera_memoria/ptr_mem_1interfaz_spi/cabecera_memoria/ptr_mem_20.4000.0000.0000.000interfaz_spi/cabecera_memoria/ptr_mem_1interfaz_spi/cabecera_memoria/ptr_mem_21SLICE_X6Y4.CLKclk_u_proc_BUFGSLICE_X6Y4.BQTcko0.200interfaz_spi/cabecera_memoria/ptr_mem<1>interfaz_spi/cabecera_memoria/ptr_mem_1SLICE_X6Y4.B5net140.079interfaz_spi/cabecera_memoria/ptr_mem<1>SLICE_X6Y4.CLKTah0.121interfaz_spi/cabecera_memoria/ptr_mem<1>Result<2>11interfaz_spi/cabecera_memoria/ptr_mem_20.3210.0790.400clk_u_proc_BUFG80.319.8Component Switching Limit Checks: TS_clk_u_proc = PERIOD TIMEGRP "clk_u_proc" TS_clk_main / 4 HIGH 50%;TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" TS_clk_main / 0.266666667 HIGH 50%;00000001.730Component Switching Limit Checks: TS_clk_mang_c_16MHz = PERIOD TIMEGRP "clk_mang_c_16MHz" TS_clk_main / + 0.266666667 HIGH 50%;COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000107.503Paths for end point interfaz_spi/controlador_spi_principal/word_int_15 (SLICE_X8Y9.C2), 1 path +9.164DATA_INOUT<15>interfaz_spi/controlador_spi_principal/word_int_15-0.411clk_maininterfaz_spi/controlador_spi_principal/word_int<15>16.667DATA_INOUT<15>clk_main0.317DATA_INOUT<15>interfaz_spi/controlador_spi_principal/word_int_152P8.PADP8.ITiopi1.310DATA_INOUT<15>DATA_INOUT<15>DATA_INOUT_15_IOBUF/IBUFProtoComp55.IMUX.17SLICE_X8Y9.C2net15.176N42SLICE_X8Y9.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<15>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi71interfaz_spi/controlador_spi_principal/word_int_151.5995.1766.775clk_u_proc_BUFG23.676.4clk_maininterfaz_spi/controlador_spi_principal/word_int_154P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y9.CLKnet2260.702clk_u_proc_BUFG-2.4562.045-0.411Hold Paths: COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_15 (SLICE_X8Y9.C2), 1 path +3.702DATA_INOUT<15>interfaz_spi/controlador_spi_principal/word_int_150.158clk_maininterfaz_spi/controlador_spi_principal/word_int<15>0.000DATA_INOUT<15>clk_main0.317DATA_INOUT<15>interfaz_spi/controlador_spi_principal/word_int_152P8.PADP8.ITiopi0.763DATA_INOUT<15>DATA_INOUT<15>DATA_INOUT_15_IOBUF/IBUFProtoComp55.IMUX.17SLICE_X8Y9.C2net13.217N42SLICE_X8Y9.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<15>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi71interfaz_spi/controlador_spi_principal/word_int_150.9603.2174.177clk_u_proc_BUFG23.077.0clk_maininterfaz_spi/controlador_spi_principal/word_int_154P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y9.CLKnet2260.842clk_u_proc_BUFG-1.5821.7400.158COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";18400001012.489Paths for end point DATA_INOUT<15> (P8.PAD), 184 paths +4.178nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<15>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.491nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<15>4SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X16Y39.B2net93.753nb_mem_cont/oe_ch_vect<0>SLICE_X16Y39.BMUXTilo0.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT93SLICE_X17Y39.A1net30.641nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X17Y39.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT157P8.Onet13.345nb_mem_cont/data_mux<15>P8.PADTioop2.381DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>3.6158.87612.49128.971.14.220nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<15>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.460nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<15>4SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X16Y39.B2net93.753nb_mem_cont/oe_ch_vect<0>SLICE_X16Y39.BMUXTilo0.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT93SLICE_X17Y39.A1net30.641nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X17Y39.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT157P8.Onet13.345nb_mem_cont/data_mux<15>P8.PADTioop2.381DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>3.5518.90912.46028.571.54.345nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<15>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<15>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X17Y28.D5net92.321nb_mem_cont/oe_ch_vect<0>SLICE_X17Y28.DMUXTilo0.313nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/_n0028<4>11SLICE_X17Y39.C3net61.158nb_mem_cont/mux_data/_n0028<4>1SLICE_X17Y39.CTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT155SLICE_X17Y39.A2net10.437nb_mem_cont/mux_data/Mmux_DATA_OUT154SLICE_X17Y39.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT157P8.Onet13.345nb_mem_cont/data_mux<15>P8.PADTioop2.381DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>3.9268.39812.32431.968.1Fastest Paths: COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<15> (P8.PAD), 184 paths +3.886nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15DATA_INOUT<15>-0.441clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>4.644nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_154P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y39.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15DATA_INOUT<15>3SLICE_X16Y39.CLKclk_u_proc_BUFGSLICE_X16Y39.DQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_15SLICE_X17Y39.D1net10.385nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>SLICE_X17Y39.DTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X17Y39.A3net10.148nb_mem_cont/mux_data/Mmux_DATA_OUT151SLICE_X17Y39.ATilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT157P8.Onet12.169nb_mem_cont/data_mux<15>P8.PADTioop1.396DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>1.9422.7024.64441.858.23.850nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<15>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.491nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<15>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P8.Tnet162.197nb_mem_cont/io_sel/OEbar_invP8.PADTiotp1.396DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>1.7902.7014.49139.960.13.744nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15DATA_INOUT<15>-0.442clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>4.503nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>DATA_INOUT<15>16.667clk_mainDATA_INOUT<15>0.317clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_154P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y40.CLKnet2260.448clk_u_proc_BUFG-1.6981.256-0.442nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15DATA_INOUT<15>3SLICE_X14Y40.CLKclk_u_proc_BUFGSLICE_X14Y40.DQTcko0.200nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_15SLICE_X17Y39.C6net10.171nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>SLICE_X17Y39.CTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT155SLICE_X17Y39.A2net10.255nb_mem_cont/mux_data/Mmux_DATA_OUT154SLICE_X17Y39.ATilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT151nb_mem_cont/mux_data/Mmux_DATA_OUT157P8.Onet12.169nb_mem_cont/data_mux<15>P8.PADTioop1.396DATA_INOUT<15>DATA_INOUT_15_IOBUF/OBUFTDATA_INOUT<15>1.9082.5954.50342.457.6COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000107.132Paths for end point interfaz_spi/controlador_spi_principal/word_int_14 (SLICE_X8Y8.D6), 1 path +9.535DATA_INOUT<14>interfaz_spi/controlador_spi_principal/word_int_14-0.413clk_maininterfaz_spi/controlador_spi_principal/word_int<14>16.667DATA_INOUT<14>clk_main0.317DATA_INOUT<14>interfaz_spi/controlador_spi_principal/word_int_142P9.PADP9.ITiopi1.310DATA_INOUT<14>DATA_INOUT<14>DATA_INOUT_14_IOBUF/IBUFProtoComp55.IMUX.16SLICE_X8Y8.D6net14.803N43SLICE_X8Y8.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi61interfaz_spi/controlador_spi_principal/word_int_141.5994.8036.402clk_u_proc_BUFG25.075.0clk_maininterfaz_spi/controlador_spi_principal/word_int_144P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.700clk_u_proc_BUFG-2.4562.043-0.413Hold Paths: COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_14 (SLICE_X8Y8.D6), 1 path +3.461DATA_INOUT<14>interfaz_spi/controlador_spi_principal/word_int_140.156clk_maininterfaz_spi/controlador_spi_principal/word_int<14>0.000DATA_INOUT<14>clk_main0.317DATA_INOUT<14>interfaz_spi/controlador_spi_principal/word_int_142P9.PADP9.ITiopi0.763DATA_INOUT<14>DATA_INOUT<14>DATA_INOUT_14_IOBUF/IBUFProtoComp55.IMUX.16SLICE_X8Y8.D6net12.974N43SLICE_X8Y8.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi61interfaz_spi/controlador_spi_principal/word_int_140.9602.9743.934clk_u_proc_BUFG24.475.6clk_maininterfaz_spi/controlador_spi_principal/word_int_144P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.840clk_u_proc_BUFG-1.5821.7380.156COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";34900001013.253Paths for end point DATA_INOUT<14> (P9.PAD), 349 paths +3.414nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<14>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.255nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<14>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.A2net242.317nb_mem_cont/mux_data/_n0040SLICE_X15Y40.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT131SLICE_X15Y39.A2net20.665nb_mem_cont/mux_data/Mmux_DATA_OUT11SLICE_X15Y39.ATilo0.259nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet13.122nb_mem_cont/data_mux<14>P9.PADTioop2.381DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>3.8649.39113.25529.270.83.456nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<14>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.224nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<14>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.A2net242.317nb_mem_cont/mux_data/_n0040SLICE_X15Y40.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT131SLICE_X15Y39.A2net20.665nb_mem_cont/mux_data/Mmux_DATA_OUT11SLICE_X15Y39.ATilo0.259nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet13.122nb_mem_cont/data_mux<14>P9.PADTioop2.381DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>3.8009.42413.22428.771.33.462nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<14>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<14>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.A2net242.317nb_mem_cont/mux_data/_n0040SLICE_X15Y40.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT131SLICE_X15Y39.A2net20.665nb_mem_cont/mux_data/Mmux_DATA_OUT11SLICE_X15Y39.ATilo0.259nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet13.122nb_mem_cont/data_mux<14>P9.PADTioop2.381DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>3.8179.38313.20028.971.1Fastest Paths: COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<14> (P9.PAD), 349 paths +3.695nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14DATA_INOUT<14>-0.442clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>4.454nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_144P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y40.CLKnet2260.448clk_u_proc_BUFG-1.6981.256-0.442nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14DATA_INOUT<14>3SLICE_X14Y40.CLKclk_u_proc_BUFGSLICE_X14Y40.CQTcko0.200nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_14SLICE_X16Y40.A2net10.347nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<14>SLICE_X16Y40.ATilo0.156nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT132SLICE_X15Y39.A6net10.164nb_mem_cont/mux_data/Mmux_DATA_OUT131SLICE_X15Y39.ATilo0.156nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet12.035nb_mem_cont/data_mux<14>P9.PADTioop1.396DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>1.9082.5464.45442.857.23.489nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14DATA_INOUT<14>-0.441clk_mainnb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>4.247nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_144P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y40.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14DATA_INOUT<14>3SLICE_X16Y40.CLKclk_u_proc_BUFGSLICE_X16Y40.CQTcko0.234nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_14SLICE_X16Y40.A4net10.106nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<14>SLICE_X16Y40.ATilo0.156nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT132SLICE_X15Y39.A6net10.164nb_mem_cont/mux_data/Mmux_DATA_OUT131SLICE_X15Y39.ATilo0.156nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet12.035nb_mem_cont/data_mux<14>P9.PADTioop1.396DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>1.9422.3054.24745.754.33.324nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14DATA_INOUT<14>-0.441clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>4.082nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>DATA_INOUT<14>16.667clk_mainDATA_INOUT<14>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_144P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y39.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14DATA_INOUT<14>2SLICE_X16Y39.CLKclk_u_proc_BUFGSLICE_X16Y39.CQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_14SLICE_X15Y39.A3net10.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<14>SLICE_X15Y39.ATilo0.156nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/mux_data/Mmux_DATA_OUT135P9.Onet12.035nb_mem_cont/data_mux<14>P9.PADTioop1.396DATA_INOUT<14>DATA_INOUT_14_IOBUF/OBUFTDATA_INOUT<14>1.7862.2964.08243.856.2COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000107.201Paths for end point interfaz_spi/controlador_spi_principal/word_int_13 (SLICE_X8Y8.C6), 1 path +9.466DATA_INOUT<13>interfaz_spi/controlador_spi_principal/word_int_13-0.413clk_maininterfaz_spi/controlador_spi_principal/word_int<14>16.667DATA_INOUT<13>clk_main0.317DATA_INOUT<13>interfaz_spi/controlador_spi_principal/word_int_132P10.PADP10.ITiopi1.310DATA_INOUT<13>DATA_INOUT<13>DATA_INOUT_13_IOBUF/IBUFProtoComp55.IMUX.15SLICE_X8Y8.C6net14.872N44SLICE_X8Y8.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi51interfaz_spi/controlador_spi_principal/word_int_131.5994.8726.471clk_u_proc_BUFG24.775.3clk_maininterfaz_spi/controlador_spi_principal/word_int_134P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.700clk_u_proc_BUFG-2.4562.043-0.413Hold Paths: COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_13 (SLICE_X8Y8.C6), 1 path +3.481DATA_INOUT<13>interfaz_spi/controlador_spi_principal/word_int_130.156clk_maininterfaz_spi/controlador_spi_principal/word_int<14>0.000DATA_INOUT<13>clk_main0.317DATA_INOUT<13>interfaz_spi/controlador_spi_principal/word_int_132P10.PADP10.ITiopi0.763DATA_INOUT<13>DATA_INOUT<13>DATA_INOUT_13_IOBUF/IBUFProtoComp55.IMUX.15SLICE_X8Y8.C6net12.994N44SLICE_X8Y8.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi51interfaz_spi/controlador_spi_principal/word_int_130.9602.9943.954clk_u_proc_BUFG24.375.7clk_maininterfaz_spi/controlador_spi_principal/word_int_134P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.840clk_u_proc_BUFG-1.5821.7380.156COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";34900001012.781Paths for end point DATA_INOUT<13> (P10.PAD), 349 paths +3.886nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<13>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.783nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<13>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.D5net242.089nb_mem_cont/mux_data/_n0040SLICE_X15Y40.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT112SLICE_X15Y40.B2net10.438nb_mem_cont/mux_data/Mmux_DATA_OUT111SLICE_X15Y40.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet13.105nb_mem_cont/data_mux<13>P10.PADTioop2.381DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>3.8648.91912.78330.269.83.928nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<13>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.752nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<13>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.D5net242.089nb_mem_cont/mux_data/_n0040SLICE_X15Y40.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT112SLICE_X15Y40.B2net10.438nb_mem_cont/mux_data/Mmux_DATA_OUT111SLICE_X15Y40.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet13.105nb_mem_cont/data_mux<13>P10.PADTioop2.381DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>3.8008.95212.75229.870.23.934nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<13>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1612.728nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<13>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X15Y40.D5net242.089nb_mem_cont/mux_data/_n0040SLICE_X15Y40.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT112SLICE_X15Y40.B2net10.438nb_mem_cont/mux_data/Mmux_DATA_OUT111SLICE_X15Y40.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet13.105nb_mem_cont/data_mux<13>P10.PADTioop2.381DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>3.8178.91112.72830.070.0Fastest Paths: COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<13> (P10.PAD), 349 paths +3.738nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13DATA_INOUT<13>-0.441clk_mainnb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>4.496nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_134P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y40.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13DATA_INOUT<13>3SLICE_X16Y40.CLKclk_u_proc_BUFGSLICE_X16Y40.BQTcko0.234nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux_13SLICE_X15Y40.D3net10.278nb_mem_cont/nibble_pack_ch2/resul_mem_internal_aux<13>SLICE_X15Y40.DTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT112SLICE_X15Y40.B2net10.253nb_mem_cont/mux_data/Mmux_DATA_OUT111SLICE_X15Y40.BTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet12.023nb_mem_cont/data_mux<13>P10.PADTioop1.396DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>1.9422.5544.49643.256.83.677nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13DATA_INOUT<13>-0.442clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>4.436nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_134P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y40.CLKnet2260.448clk_u_proc_BUFG-1.6981.256-0.442nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13DATA_INOUT<13>3SLICE_X14Y40.CLKclk_u_proc_BUFGSLICE_X14Y40.BQTcko0.200nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_13SLICE_X15Y40.D2net10.252nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<13>SLICE_X15Y40.DTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT112SLICE_X15Y40.B2net10.253nb_mem_cont/mux_data/Mmux_DATA_OUT111SLICE_X15Y40.BTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet12.023nb_mem_cont/data_mux<13>P10.PADTioop1.396DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>1.9082.5284.43643.057.03.633nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13DATA_INOUT<13>-0.441clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>4.391nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>DATA_INOUT<13>16.667clk_mainDATA_INOUT<13>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_134P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y39.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13DATA_INOUT<13>2SLICE_X16Y39.CLKclk_u_proc_BUFGSLICE_X16Y39.BQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_13SLICE_X15Y40.B1net10.582nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<13>SLICE_X15Y40.BTilo0.156nb_mem_cont/mux_data/Mmux_DATA_OUT111nb_mem_cont/mux_data/Mmux_DATA_OUT115P10.Onet12.023nb_mem_cont/data_mux<13>P10.PADTioop1.396DATA_INOUT<13>DATA_INOUT_13_IOBUF/OBUFTDATA_INOUT<13>1.7862.6054.39140.759.3COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000107.196Paths for end point interfaz_spi/controlador_spi_principal/word_int_12 (SLICE_X8Y8.B5), 1 path +9.471DATA_INOUT<12>interfaz_spi/controlador_spi_principal/word_int_12-0.413clk_maininterfaz_spi/controlador_spi_principal/word_int<14>16.667DATA_INOUT<12>clk_main0.317DATA_INOUT<12>interfaz_spi/controlador_spi_principal/word_int_122P11.PADP11.ITiopi1.310DATA_INOUT<12>DATA_INOUT<12>DATA_INOUT_12_IOBUF/IBUFProtoComp55.IMUX.14SLICE_X8Y8.B5net14.867N45SLICE_X8Y8.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi41interfaz_spi/controlador_spi_principal/word_int_121.5994.8676.466clk_u_proc_BUFG24.775.3clk_maininterfaz_spi/controlador_spi_principal/word_int_124P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.700clk_u_proc_BUFG-2.4562.043-0.413Hold Paths: COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_12 (SLICE_X8Y8.B5), 1 path +3.503DATA_INOUT<12>interfaz_spi/controlador_spi_principal/word_int_120.156clk_maininterfaz_spi/controlador_spi_principal/word_int<14>0.000DATA_INOUT<12>clk_main0.317DATA_INOUT<12>interfaz_spi/controlador_spi_principal/word_int_122P11.PADP11.ITiopi0.763DATA_INOUT<12>DATA_INOUT<12>DATA_INOUT_12_IOBUF/IBUFProtoComp55.IMUX.14SLICE_X8Y8.B5net13.016N45SLICE_X8Y8.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi41interfaz_spi/controlador_spi_principal/word_int_120.9603.0163.976clk_u_proc_BUFG24.175.9clk_maininterfaz_spi/controlador_spi_principal/word_int_124P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.840clk_u_proc_BUFG-1.5821.7380.156COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";18400001012.094Paths for end point DATA_INOUT<12> (P11.PAD), 184 paths +4.573nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<12>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.096nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<12>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X17Y28.D5net92.321nb_mem_cont/oe_ch_vect<0>SLICE_X17Y28.DMUXTilo0.313nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/_n0028<4>11SLICE_X17Y28.C4net60.308nb_mem_cont/mux_data/_n0028<4>1SLICE_X17Y28.CTilo0.259nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/Mmux_DATA_OUT95SLICE_X16Y39.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT94SLICE_X16Y39.CTilo0.204nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT97P11.Onet13.019nb_mem_cont/data_mux<12>P11.PADTioop2.381DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>3.8718.22512.09632.068.04.615nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<12>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.065nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<12>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X17Y28.D5net92.321nb_mem_cont/oe_ch_vect<0>SLICE_X17Y28.DMUXTilo0.313nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/_n0028<4>11SLICE_X17Y28.C4net60.308nb_mem_cont/mux_data/_n0028<4>1SLICE_X17Y28.CTilo0.259nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/Mmux_DATA_OUT95SLICE_X16Y39.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT94SLICE_X16Y39.CTilo0.204nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT97P11.Onet13.019nb_mem_cont/data_mux<12>P11.PADTioop2.381DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>3.8078.25812.06531.668.44.754nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<12>-0.329clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2611.925nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd264P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X10Y17.CLKnet2261.108clk_u_proc_BUFG-3.0882.759-0.329nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<12>5SLICE_X10Y17.CLKclk_u_proc_BUFGSLICE_X10Y17.BQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26SLICE_X5Y14.D3net161.013nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X17Y28.D5net92.321nb_mem_cont/oe_ch_vect<0>SLICE_X17Y28.DMUXTilo0.313nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/_n0028<4>11SLICE_X17Y28.C4net60.308nb_mem_cont/mux_data/_n0028<4>1SLICE_X17Y28.CTilo0.259nb_mem_cont/nibble_pack_ch5/_n0127_invnb_mem_cont/mux_data/Mmux_DATA_OUT95SLICE_X16Y39.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT94SLICE_X16Y39.CTilo0.204nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT97P11.Onet13.019nb_mem_cont/data_mux<12>P11.PADTioop2.381DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>3.8248.10111.92532.167.9Fastest Paths: COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<12> (P11.PAD), 184 paths +3.838nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<12>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.550nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<12>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P11.Tnet162.087nb_mem_cont/io_sel/OEbar_invP11.PADTiotp1.396DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>1.7862.7644.55039.360.73.740nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<12>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.381nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<12>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P11.Tnet162.087nb_mem_cont/io_sel/OEbar_invP11.PADTiotp1.396DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>1.7902.5914.38140.959.13.410nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12DATA_INOUT<12>-0.441clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>4.168nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>DATA_INOUT<12>16.667clk_mainDATA_INOUT<12>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_124P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y39.CLKnet2260.449clk_u_proc_BUFG-1.6981.257-0.441nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12DATA_INOUT<12>3SLICE_X16Y39.CLKclk_u_proc_BUFGSLICE_X16Y39.AQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_12SLICE_X16Y39.A6net10.017nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<12>SLICE_X16Y39.ATilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT92SLICE_X16Y39.C1net10.241nb_mem_cont/mux_data/Mmux_DATA_OUT91SLICE_X16Y39.CTilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT97P11.Onet11.968nb_mem_cont/data_mux<12>P11.PADTioop1.396DATA_INOUT<12>DATA_INOUT_12_IOBUF/OBUFTDATA_INOUT<12>1.9422.2264.16846.653.4COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000107.691Paths for end point interfaz_spi/controlador_spi_principal/word_int_11 (SLICE_X8Y8.A5), 1 path +8.976DATA_INOUT<11>interfaz_spi/controlador_spi_principal/word_int_11-0.413clk_maininterfaz_spi/controlador_spi_principal/word_int<14>16.667DATA_INOUT<11>clk_main0.317DATA_INOUT<11>interfaz_spi/controlador_spi_principal/word_int_112P12.PADP12.ITiopi1.310DATA_INOUT<11>DATA_INOUT<11>DATA_INOUT_11_IOBUF/IBUFProtoComp55.IMUX.13SLICE_X8Y8.A5net15.362N46SLICE_X8Y8.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/data_mux<11>1interfaz_spi/controlador_spi_principal/word_int_111.5995.3626.961clk_u_proc_BUFG23.077.0clk_maininterfaz_spi/controlador_spi_principal/word_int_114P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.700clk_u_proc_BUFG-2.4562.043-0.413Hold Paths: COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_11 (SLICE_X8Y8.A5), 1 path +3.780DATA_INOUT<11>interfaz_spi/controlador_spi_principal/word_int_110.156clk_maininterfaz_spi/controlador_spi_principal/word_int<14>0.000DATA_INOUT<11>clk_main0.317DATA_INOUT<11>interfaz_spi/controlador_spi_principal/word_int_112P12.PADP12.ITiopi0.763DATA_INOUT<11>DATA_INOUT<11>DATA_INOUT_11_IOBUF/IBUFProtoComp55.IMUX.13SLICE_X8Y8.A5net13.293N46SLICE_X8Y8.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<14>interfaz_spi/data_mux<11>1interfaz_spi/controlador_spi_principal/word_int_110.9603.2934.253clk_u_proc_BUFG22.677.4clk_maininterfaz_spi/controlador_spi_principal/word_int_114P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y8.CLKnet2260.840clk_u_proc_BUFG-1.5821.7380.156COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";18400001012.308Paths for end point DATA_INOUT<11> (P12.PAD), 184 paths +4.359nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<11>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.310nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<11>4SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X16Y39.B2net93.753nb_mem_cont/oe_ch_vect<0>SLICE_X16Y39.BMUXTilo0.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT93SLICE_X16Y38.A2net30.629nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X16Y38.ATilo0.203nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT77P12.Onet13.232nb_mem_cont/data_mux<11>P12.PADTioop2.381DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>3.5598.75112.31028.971.14.401nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<11>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.279nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<11>4SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X16Y39.B2net93.753nb_mem_cont/oe_ch_vect<0>SLICE_X16Y39.BMUXTilo0.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT93SLICE_X16Y38.A2net30.629nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X16Y38.ATilo0.203nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT77P12.Onet13.232nb_mem_cont/data_mux<11>P12.PADTioop2.381DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>3.4958.78412.27928.571.54.540nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<11>-0.329clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2612.139nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd264P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X10Y17.CLKnet2261.108clk_u_proc_BUFG-3.0882.759-0.329nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26DATA_INOUT<11>4SLICE_X10Y17.CLKclk_u_proc_BUFGSLICE_X10Y17.BQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26SLICE_X5Y14.D3net161.013nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd26SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X16Y39.B2net93.753nb_mem_cont/oe_ch_vect<0>SLICE_X16Y39.BMUXTilo0.261nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<15>nb_mem_cont/mux_data/Mmux_DATA_OUT93SLICE_X16Y38.A2net30.629nb_mem_cont/mux_data/Mmux_DATA_OUT152SLICE_X16Y38.ATilo0.203nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT77P12.Onet13.232nb_mem_cont/data_mux<11>P12.PADTioop2.381DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>3.5128.62712.13928.971.1Fastest Paths: COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<11> (P12.PAD), 184 paths +3.773nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11DATA_INOUT<11>-0.439clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>4.529nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_114P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y38.CLKnet2260.451clk_u_proc_BUFG-1.6981.259-0.439nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11DATA_INOUT<11>3SLICE_X14Y38.CLKclk_u_proc_BUFGSLICE_X14Y38.DQTcko0.200nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux_11SLICE_X16Y38.C3net10.274nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>SLICE_X16Y38.CTilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT75SLICE_X16Y38.A1net10.258nb_mem_cont/mux_data/Mmux_DATA_OUT74SLICE_X16Y38.ATilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT77P12.Onet12.089nb_mem_cont/data_mux<11>P12.PADTioop1.396DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>1.9082.6214.52942.157.93.740nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<11>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.381nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<11>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P12.Tnet162.087nb_mem_cont/io_sel/OEbar_invP12.PADTiotp1.396DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>1.7902.5914.38140.959.13.434nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11DATA_INOUT<11>-0.439clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>4.190nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>DATA_INOUT<11>16.667clk_mainDATA_INOUT<11>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_114P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y38.CLKnet2260.451clk_u_proc_BUFG-1.6981.259-0.439nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11DATA_INOUT<11>3SLICE_X16Y38.CLKclk_u_proc_BUFGSLICE_X16Y38.DQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_11SLICE_X16Y38.D6net10.017nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>SLICE_X16Y38.DTilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT72SLICE_X16Y38.A3net10.142nb_mem_cont/mux_data/Mmux_DATA_OUT71SLICE_X16Y38.ATilo0.156nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT77P12.Onet12.089nb_mem_cont/data_mux<11>P12.PADTioop1.396DATA_INOUT<11>DATA_INOUT_11_IOBUF/OBUFTDATA_INOUT<11>1.9422.2484.19046.353.7COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.982Paths for end point interfaz_spi/controlador_spi_principal/word_int_10 (SLICE_X6Y8.D5), 1 path +10.685DATA_INOUT<10>interfaz_spi/controlador_spi_principal/word_int_10-0.405clk_maininterfaz_spi/controlador_spi_principal/word_int<10>16.667DATA_INOUT<10>clk_main0.317DATA_INOUT<10>interfaz_spi/controlador_spi_principal/word_int_102P14.PADP14.ITiopi1.310DATA_INOUT<10>DATA_INOUT<10>DATA_INOUT_10_IOBUF/IBUFProtoComp55.IMUX.12SLICE_X6Y8.D5net13.609N47SLICE_X6Y8.CLKTas0.341interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi21interfaz_spi/controlador_spi_principal/word_int_101.6513.6095.260clk_u_proc_BUFG31.468.6clk_maininterfaz_spi/controlador_spi_principal/word_int_104P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.708clk_u_proc_BUFG-2.4562.051-0.405Hold Paths: COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_10 (SLICE_X6Y8.D5), 1 path +2.754DATA_INOUT<10>interfaz_spi/controlador_spi_principal/word_int_100.164clk_maininterfaz_spi/controlador_spi_principal/word_int<10>0.000DATA_INOUT<10>clk_main0.317DATA_INOUT<10>interfaz_spi/controlador_spi_principal/word_int_102P14.PADP14.ITiopi0.763DATA_INOUT<10>DATA_INOUT<10>DATA_INOUT_10_IOBUF/IBUFProtoComp55.IMUX.12SLICE_X6Y8.D5net12.282N47SLICE_X6Y8.CLKTah0.190interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi21interfaz_spi/controlador_spi_principal/word_int_100.9532.2823.235clk_u_proc_BUFG29.570.5clk_maininterfaz_spi/controlador_spi_principal/word_int_104P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.848clk_u_proc_BUFG-1.5821.7460.164COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";30400001012.614Paths for end point DATA_INOUT<10> (P14.PAD), 304 paths +4.053nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<10>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.616nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<10>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0034<4>1SLICE_X14Y38.B1net181.909nb_mem_cont/mux_data/_n0034SLICE_X14Y38.BMUXTilo0.251nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT51SLICE_X14Y38.D4net10.857nb_mem_cont/mux_data/Mmux_DATA_OUT5SLICE_X14Y38.CMUXTopdc0.338nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT57_Fnb_mem_cont/mux_data/Mmux_DATA_OUT57P14.Onet12.674nb_mem_cont/data_mux<10>P14.PADTioop2.381DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>3.8898.72712.61630.869.24.095nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<10>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.585nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<10>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0034<4>1SLICE_X14Y38.B1net181.909nb_mem_cont/mux_data/_n0034SLICE_X14Y38.BMUXTilo0.251nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT51SLICE_X14Y38.D4net10.857nb_mem_cont/mux_data/Mmux_DATA_OUT5SLICE_X14Y38.CMUXTopdc0.338nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT57_Fnb_mem_cont/mux_data/Mmux_DATA_OUT57P14.Onet12.674nb_mem_cont/data_mux<10>P14.PADTioop2.381DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>3.8258.76012.58530.469.64.101nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<10>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1612.561nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<10>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0034<4>1SLICE_X14Y38.B1net181.909nb_mem_cont/mux_data/_n0034SLICE_X14Y38.BMUXTilo0.251nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT51SLICE_X14Y38.D4net10.857nb_mem_cont/mux_data/Mmux_DATA_OUT5SLICE_X14Y38.CMUXTopdc0.338nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT57_Fnb_mem_cont/mux_data/Mmux_DATA_OUT57P14.Onet12.674nb_mem_cont/data_mux<10>P14.PADTioop2.381DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>3.8428.71912.56130.669.4Fastest Paths: COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<10> (P14.PAD), 304 paths +3.192nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<10>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.904nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<10>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P14.Tnet161.441nb_mem_cont/io_sel/OEbar_invP14.PADTiotp1.396DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>1.7862.1183.90445.754.33.109nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10DATA_INOUT<10>-0.439clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>3.865nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_104P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y38.CLKnet2260.451clk_u_proc_BUFG-1.6981.259-0.439nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10DATA_INOUT<10>2SLICE_X16Y38.CLKclk_u_proc_BUFGSLICE_X16Y38.CQTcko0.234nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<11>nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux_10SLICE_X14Y38.C4net10.218nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<10>SLICE_X14Y38.CMUXTilo0.234nb_mem_cont/nibble_pack_ch3/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT57_Gnb_mem_cont/mux_data/Mmux_DATA_OUT57P14.Onet11.783nb_mem_cont/data_mux<10>P14.PADTioop1.396DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>1.8642.0013.86548.251.83.094nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<10>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.735nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<10>16.667clk_mainDATA_INOUT<10>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<10>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P14.Tnet161.441nb_mem_cont/io_sel/OEbar_invP14.PADTiotp1.396DATA_INOUT<10>DATA_INOUT_10_IOBUF/OBUFTDATA_INOUT<10>1.7901.9453.73547.952.1COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000106.074Paths for end point interfaz_spi/controlador_spi_principal/word_int_9 (SLICE_X6Y8.C6), 1 path +10.593DATA_INOUT<9>interfaz_spi/controlador_spi_principal/word_int_9-0.405clk_maininterfaz_spi/controlador_spi_principal/word_int<10>16.667DATA_INOUT<9>clk_main0.317DATA_INOUT<9>interfaz_spi/controlador_spi_principal/word_int_92P15.PADP15.ITiopi1.310DATA_INOUT<9>DATA_INOUT<9>DATA_INOUT_9_IOBUF/IBUFProtoComp55.IMUX.11SLICE_X6Y8.C6net13.701N48SLICE_X6Y8.CLKTas0.341interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi161interfaz_spi/controlador_spi_principal/word_int_91.6513.7015.352clk_u_proc_BUFG30.869.2clk_maininterfaz_spi/controlador_spi_principal/word_int_94P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.708clk_u_proc_BUFG-2.4562.051-0.405Hold Paths: COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_9 (SLICE_X6Y8.C6), 1 path +2.753DATA_INOUT<9>interfaz_spi/controlador_spi_principal/word_int_90.164clk_maininterfaz_spi/controlador_spi_principal/word_int<10>0.000DATA_INOUT<9>clk_main0.317DATA_INOUT<9>interfaz_spi/controlador_spi_principal/word_int_92P15.PADP15.ITiopi0.763DATA_INOUT<9>DATA_INOUT<9>DATA_INOUT_9_IOBUF/IBUFProtoComp55.IMUX.11SLICE_X6Y8.C6net12.281N48SLICE_X6Y8.CLKTah0.190interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi161interfaz_spi/controlador_spi_principal/word_int_90.9532.2813.234clk_u_proc_BUFG29.570.5clk_maininterfaz_spi/controlador_spi_principal/word_int_94P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.848clk_u_proc_BUFG-1.5821.7460.164COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";30400001012.627Paths for end point DATA_INOUT<9> (P15.PAD), 304 paths +4.040nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<9>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.629nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<9>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X17Y33.D2net241.393nb_mem_cont/mux_data/_n0040SLICE_X17Y33.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT40nb_mem_cont/mux_data/Mmux_DATA_OUT401SLICE_X11Y25.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT40SLICE_X11Y25.CTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/mux_data/Mmux_DATA_OUT407P15.Onet12.645nb_mem_cont/data_mux<9>P15.PADTioop2.381DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>3.8648.76512.62930.669.44.082nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<9>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.598nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<9>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X17Y33.D2net241.393nb_mem_cont/mux_data/_n0040SLICE_X17Y33.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT40nb_mem_cont/mux_data/Mmux_DATA_OUT401SLICE_X11Y25.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT40SLICE_X11Y25.CTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/mux_data/Mmux_DATA_OUT407P15.Onet12.645nb_mem_cont/data_mux<9>P15.PADTioop2.381DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>3.8008.79812.59830.269.84.088nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<9>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1612.574nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<9>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X17Y33.D2net241.393nb_mem_cont/mux_data/_n0040SLICE_X17Y33.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT40nb_mem_cont/mux_data/Mmux_DATA_OUT401SLICE_X11Y25.C3net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT40SLICE_X11Y25.CTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/mux_data/Mmux_DATA_OUT407P15.Onet12.645nb_mem_cont/data_mux<9>P15.PADTioop2.381DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>3.8178.75712.57430.469.6Fastest Paths: COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<9> (P15.PAD), 304 paths +3.199nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<9>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd33.908nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<9>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P15.Tnet161.441nb_mem_cont/io_sel/OEbar_invP15.PADTiotp1.396DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>1.7522.1563.90844.855.23.192nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<9>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.904nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<9>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P15.Tnet161.441nb_mem_cont/io_sel/OEbar_invP15.PADTiotp1.396DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>1.7862.1183.90445.754.33.094nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<9>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.735nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<9>16.667clk_mainDATA_INOUT<9>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<9>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P15.Tnet161.441nb_mem_cont/io_sel/OEbar_invP15.PADTiotp1.396DATA_INOUT<9>DATA_INOUT_9_IOBUF/OBUFTDATA_INOUT<9>1.7901.9453.73547.952.1COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.916Paths for end point interfaz_spi/controlador_spi_principal/word_int_8 (SLICE_X6Y8.B6), 1 path +10.751DATA_INOUT<8>interfaz_spi/controlador_spi_principal/word_int_8-0.405clk_maininterfaz_spi/controlador_spi_principal/word_int<10>16.667DATA_INOUT<8>clk_main0.317DATA_INOUT<8>interfaz_spi/controlador_spi_principal/word_int_82P16.PADP16.ITiopi1.310DATA_INOUT<8>DATA_INOUT<8>DATA_INOUT_8_IOBUF/IBUFProtoComp55.IMUX.10SLICE_X6Y8.B6net13.543N49SLICE_X6Y8.CLKTas0.341interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi151interfaz_spi/controlador_spi_principal/word_int_81.6513.5435.194clk_u_proc_BUFG31.868.2clk_maininterfaz_spi/controlador_spi_principal/word_int_84P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.708clk_u_proc_BUFG-2.4562.051-0.405Hold Paths: COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_8 (SLICE_X6Y8.B6), 1 path +2.696DATA_INOUT<8>interfaz_spi/controlador_spi_principal/word_int_80.164clk_maininterfaz_spi/controlador_spi_principal/word_int<10>0.000DATA_INOUT<8>clk_main0.317DATA_INOUT<8>interfaz_spi/controlador_spi_principal/word_int_82P16.PADP16.ITiopi0.763DATA_INOUT<8>DATA_INOUT<8>DATA_INOUT_8_IOBUF/IBUFProtoComp55.IMUX.10SLICE_X6Y8.B6net12.224N49SLICE_X6Y8.CLKTah0.190interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi151interfaz_spi/controlador_spi_principal/word_int_80.9532.2243.177clk_u_proc_BUFG30.070.0clk_maininterfaz_spi/controlador_spi_principal/word_int_84P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.848clk_u_proc_BUFG-1.5821.7460.164COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";34900001012.820Paths for end point DATA_INOUT<8> (P16.PAD), 349 paths +3.847nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<8>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd312.822nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<8>6SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X14Y36.D5net241.411nb_mem_cont/mux_data/_n0040SLICE_X14Y36.DTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.C6net10.118nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0SLICE_X14Y25.B4net11.099N197SLICE_X14Y25.BTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/Mmux_DATA_OUT387P16.Onet12.946nb_mem_cont/data_mux<8>P16.PADTioop2.381DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>3.9618.86112.82230.969.13.889nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<8>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3012.791nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<8>6SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X14Y36.D5net241.411nb_mem_cont/mux_data/_n0040SLICE_X14Y36.DTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.C6net10.118nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0SLICE_X14Y25.B4net11.099N197SLICE_X14Y25.BTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/Mmux_DATA_OUT387P16.Onet12.946nb_mem_cont/data_mux<8>P16.PADTioop2.381DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>3.8978.89412.79130.569.53.895nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<8>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1612.767nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<8>6SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X14Y36.D5net241.411nb_mem_cont/mux_data/_n0040SLICE_X14Y36.DTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.C6net10.118nb_mem_cont/mux_data/Mmux_DATA_OUT385SLICE_X14Y36.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT385nb_mem_cont/mux_data/Mmux_DATA_OUT387_SW0SLICE_X14Y25.B4net11.099N197SLICE_X14Y25.BTilo0.205nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/Mmux_DATA_OUT387P16.Onet12.946nb_mem_cont/data_mux<8>P16.PADTioop2.381DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>3.9148.85312.76730.769.3Fastest Paths: COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<8> (P16.PAD), 349 paths +3.096nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<8>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd33.805nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<8>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P16.Tnet161.338nb_mem_cont/io_sel/OEbar_invP16.PADTiotp1.396DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>1.7522.0533.80546.054.03.089nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<8>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.801nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<8>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P16.Tnet161.338nb_mem_cont/io_sel/OEbar_invP16.PADTiotp1.396DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>1.7862.0153.80147.053.02.991nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<8>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.632nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<8>16.667clk_mainDATA_INOUT<8>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<8>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P16.Tnet161.338nb_mem_cont/io_sel/OEbar_invP16.PADTiotp1.396DATA_INOUT<8>DATA_INOUT_8_IOBUF/OBUFTDATA_INOUT<8>1.7901.8423.63249.350.7COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.791Paths for end point interfaz_spi/controlador_spi_principal/word_int_7 (SLICE_X6Y8.A5), 1 path +11.876DATA_INOUT<7>interfaz_spi/controlador_spi_principal/word_int_7-0.405clk_maininterfaz_spi/controlador_spi_principal/word_int<10>16.667DATA_INOUT<7>clk_main0.317DATA_INOUT<7>interfaz_spi/controlador_spi_principal/word_int_72P41.PADP41.ITiopi1.310DATA_INOUT<7>DATA_INOUT<7>DATA_INOUT_7_IOBUF/IBUFProtoComp55.IMUX.9SLICE_X6Y8.A5net12.418N50SLICE_X6Y8.CLKTas0.341interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi141interfaz_spi/controlador_spi_principal/word_int_71.6512.4184.069clk_u_proc_BUFG40.659.4clk_maininterfaz_spi/controlador_spi_principal/word_int_74P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.708clk_u_proc_BUFG-2.4562.051-0.405Hold Paths: COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_7 (SLICE_X6Y8.A5), 1 path +2.009DATA_INOUT<7>interfaz_spi/controlador_spi_principal/word_int_70.164clk_maininterfaz_spi/controlador_spi_principal/word_int<10>0.000DATA_INOUT<7>clk_main0.317DATA_INOUT<7>interfaz_spi/controlador_spi_principal/word_int_72P41.PADP41.ITiopi0.763DATA_INOUT<7>DATA_INOUT<7>DATA_INOUT_7_IOBUF/IBUFProtoComp55.IMUX.9SLICE_X6Y8.A5net11.537N50SLICE_X6Y8.CLKTah0.190interfaz_spi/controlador_spi_principal/word_int<10>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi141interfaz_spi/controlador_spi_principal/word_int_70.9531.5372.490clk_u_proc_BUFG38.361.7clk_maininterfaz_spi/controlador_spi_principal/word_int_74P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y8.CLKnet2260.848clk_u_proc_BUFG-1.5821.7460.164COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.357Paths for end point DATA_INOUT<7> (P41.PAD), 339 paths +3.310nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<7>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.359nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<7>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X20Y33.D5net241.425nb_mem_cont/mux_data/_n0046SLICE_X20Y33.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT36nb_mem_cont/mux_data/Mmux_DATA_OUT361SLICE_X16Y23.A2net11.613nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X16Y23.ATilo0.203nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT368P41.Onet13.533nb_mem_cont/data_mux<7>P41.PADTioop2.381DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>3.7069.65313.35927.772.33.352nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<7>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.328nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<7>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X20Y33.D5net241.425nb_mem_cont/mux_data/_n0046SLICE_X20Y33.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT36nb_mem_cont/mux_data/Mmux_DATA_OUT361SLICE_X16Y23.A2net11.613nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X16Y23.ATilo0.203nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT368P41.Onet13.533nb_mem_cont/data_mux<7>P41.PADTioop2.381DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>3.6429.68613.32827.372.73.445nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<7>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.217nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<7>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y24.C3net110.712nb_mem_cont/oe_ch_vect<2>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X20Y33.D5net241.425nb_mem_cont/mux_data/_n0046SLICE_X20Y33.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT36nb_mem_cont/mux_data/Mmux_DATA_OUT361SLICE_X16Y23.A2net11.613nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X16Y23.ATilo0.203nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<11>nb_mem_cont/mux_data/Mmux_DATA_OUT368P41.Onet13.533nb_mem_cont/data_mux<7>P41.PADTioop2.381DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>3.6599.55813.21727.772.3Fastest Paths: COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<7> (P41.PAD), 339 paths +3.650nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<7>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.359nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<7>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P41.Tnet161.892nb_mem_cont/io_sel/OEbar_invP41.PADTiotp1.396DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>1.7522.6074.35940.259.83.643nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<7>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.355nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<7>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P41.Tnet161.892nb_mem_cont/io_sel/OEbar_invP41.PADTiotp1.396DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>1.7862.5694.35541.059.03.545nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<7>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.186nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<7>16.667clk_mainDATA_INOUT<7>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<7>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P41.Tnet161.892nb_mem_cont/io_sel/OEbar_invP41.PADTiotp1.396DATA_INOUT<7>DATA_INOUT_7_IOBUF/OBUFTDATA_INOUT<7>1.7902.3964.18642.857.2COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.011Paths for end point interfaz_spi/controlador_spi_principal/word_int_6 (SLICE_X9Y5.D1), 1 path +11.656DATA_INOUT<6>interfaz_spi/controlador_spi_principal/word_int_6-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<6>16.667DATA_INOUT<6>clk_main0.317DATA_INOUT<6>interfaz_spi/controlador_spi_principal/word_int_62P40.PADP40.ITiopi1.310DATA_INOUT<6>DATA_INOUT<6>DATA_INOUT_6_IOBUF/IBUFProtoComp55.IMUX.8SLICE_X9Y5.D1net12.654N51SLICE_X9Y5.CLKTas0.322interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi131interfaz_spi/controlador_spi_principal/word_int_61.6322.6544.286clk_u_proc_BUFG38.161.9clk_maininterfaz_spi/controlador_spi_principal/word_int_64P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_6 (SLICE_X9Y5.D1), 1 path +2.222DATA_INOUT<6>interfaz_spi/controlador_spi_principal/word_int_60.161clk_maininterfaz_spi/controlador_spi_principal/word_int<6>0.000DATA_INOUT<6>clk_main0.317DATA_INOUT<6>interfaz_spi/controlador_spi_principal/word_int_62P40.PADP40.ITiopi0.763DATA_INOUT<6>DATA_INOUT<6>DATA_INOUT_6_IOBUF/IBUFProtoComp55.IMUX.8SLICE_X9Y5.D1net11.722N51SLICE_X9Y5.CLKTah0.215interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi131interfaz_spi/controlador_spi_principal/word_int_60.9781.7222.700clk_u_proc_BUFG36.263.8clk_maininterfaz_spi/controlador_spi_principal/word_int_64P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001014.600Paths for end point DATA_INOUT<6> (P40.PAD), 339 paths +2.067nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<6>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314.602nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<6>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X19Y37.D1net242.002nb_mem_cont/mux_data/_n0040SLICE_X19Y37.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT335nb_mem_cont/mux_data/Mmux_DATA_OUT336SLICE_X17Y21.A2net11.933nb_mem_cont/mux_data/Mmux_DATA_OUT335SLICE_X17Y21.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT334nb_mem_cont/mux_data/Mmux_DATA_OUT338P40.Onet13.516nb_mem_cont/data_mux<6>P40.PADTioop2.381DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>3.86410.73814.60226.573.52.109nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<6>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3014.571nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<6>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X19Y37.D1net242.002nb_mem_cont/mux_data/_n0040SLICE_X19Y37.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT335nb_mem_cont/mux_data/Mmux_DATA_OUT336SLICE_X17Y21.A2net11.933nb_mem_cont/mux_data/Mmux_DATA_OUT335SLICE_X17Y21.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT334nb_mem_cont/mux_data/Mmux_DATA_OUT338P40.Onet13.516nb_mem_cont/data_mux<6>P40.PADTioop2.381DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>3.80010.77114.57126.173.92.115nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<6>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1614.547nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<6>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X19Y37.D1net242.002nb_mem_cont/mux_data/_n0040SLICE_X19Y37.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT335nb_mem_cont/mux_data/Mmux_DATA_OUT336SLICE_X17Y21.A2net11.933nb_mem_cont/mux_data/Mmux_DATA_OUT335SLICE_X17Y21.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT334nb_mem_cont/mux_data/Mmux_DATA_OUT338P40.Onet13.516nb_mem_cont/data_mux<6>P40.PADTioop2.381DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>3.81710.73014.54726.273.8Fastest Paths: COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<6> (P40.PAD), 339 paths +3.650nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<6>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.359nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<6>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P40.Tnet161.892nb_mem_cont/io_sel/OEbar_invP40.PADTiotp1.396DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>1.7522.6074.35940.259.83.643nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<6>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.355nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<6>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P40.Tnet161.892nb_mem_cont/io_sel/OEbar_invP40.PADTiotp1.396DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>1.7862.5694.35541.059.03.545nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<6>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.186nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<6>16.667clk_mainDATA_INOUT<6>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<6>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P40.Tnet161.892nb_mem_cont/io_sel/OEbar_invP40.PADTiotp1.396DATA_INOUT<6>DATA_INOUT_6_IOBUF/OBUFTDATA_INOUT<6>1.7902.3964.18642.857.2COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.683Paths for end point interfaz_spi/controlador_spi_principal/word_int_5 (SLICE_X9Y5.C2), 1 path +11.984DATA_INOUT<5>interfaz_spi/controlador_spi_principal/word_int_5-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<6>16.667DATA_INOUT<5>clk_main0.317DATA_INOUT<5>interfaz_spi/controlador_spi_principal/word_int_52P39.PADP39.ITiopi1.310DATA_INOUT<5>DATA_INOUT<5>DATA_INOUT_5_IOBUF/IBUFProtoComp55.IMUX.7SLICE_X9Y5.C2net12.326N52SLICE_X9Y5.CLKTas0.322interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi121interfaz_spi/controlador_spi_principal/word_int_51.6322.3263.958clk_u_proc_BUFG41.258.8clk_maininterfaz_spi/controlador_spi_principal/word_int_54P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_5 (SLICE_X9Y5.C2), 1 path +2.004DATA_INOUT<5>interfaz_spi/controlador_spi_principal/word_int_50.161clk_maininterfaz_spi/controlador_spi_principal/word_int<6>0.000DATA_INOUT<5>clk_main0.317DATA_INOUT<5>interfaz_spi/controlador_spi_principal/word_int_52P39.PADP39.ITiopi0.763DATA_INOUT<5>DATA_INOUT<5>DATA_INOUT_5_IOBUF/IBUFProtoComp55.IMUX.7SLICE_X9Y5.C2net11.504N52SLICE_X9Y5.CLKTah0.215interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi121interfaz_spi/controlador_spi_principal/word_int_50.9781.5042.482clk_u_proc_BUFG39.460.6clk_maininterfaz_spi/controlador_spi_principal/word_int_54P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001014.057Paths for end point DATA_INOUT<5> (P39.PAD), 339 paths +2.610nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<5>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314.059nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<5>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X21Y34.D4net241.717nb_mem_cont/mux_data/_n0040SLICE_X21Y34.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT305nb_mem_cont/mux_data/Mmux_DATA_OUT306SLICE_X20Y20.C1net11.481nb_mem_cont/mux_data/Mmux_DATA_OUT305SLICE_X20Y20.CTilo0.204nb_mem_cont/nibble_pack_ch5/rdy_mem_auxnb_mem_cont/mux_data/Mmux_DATA_OUT308P39.Onet13.765nb_mem_cont/data_mux<5>P39.PADTioop2.381DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>3.80910.25014.05927.172.92.652nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<5>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3014.028nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<5>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X21Y34.D4net241.717nb_mem_cont/mux_data/_n0040SLICE_X21Y34.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT305nb_mem_cont/mux_data/Mmux_DATA_OUT306SLICE_X20Y20.C1net11.481nb_mem_cont/mux_data/Mmux_DATA_OUT305SLICE_X20Y20.CTilo0.204nb_mem_cont/nibble_pack_ch5/rdy_mem_auxnb_mem_cont/mux_data/Mmux_DATA_OUT308P39.Onet13.765nb_mem_cont/data_mux<5>P39.PADTioop2.381DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>3.74510.28314.02826.773.32.658nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<5>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1614.004nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<5>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X21Y34.D4net241.717nb_mem_cont/mux_data/_n0040SLICE_X21Y34.DTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT305nb_mem_cont/mux_data/Mmux_DATA_OUT306SLICE_X20Y20.C1net11.481nb_mem_cont/mux_data/Mmux_DATA_OUT305SLICE_X20Y20.CTilo0.204nb_mem_cont/nibble_pack_ch5/rdy_mem_auxnb_mem_cont/mux_data/Mmux_DATA_OUT308P39.Onet13.765nb_mem_cont/data_mux<5>P39.PADTioop2.381DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>3.76210.24214.00426.973.1Fastest Paths: COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<5> (P39.PAD), 339 paths +3.586nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<5>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.295nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<5>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P39.Tnet161.828nb_mem_cont/io_sel/OEbar_invP39.PADTiotp1.396DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>1.7522.5434.29540.859.23.579nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<5>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.291nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<5>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P39.Tnet161.828nb_mem_cont/io_sel/OEbar_invP39.PADTiotp1.396DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>1.7862.5054.29141.658.43.481nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<5>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.122nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<5>16.667clk_mainDATA_INOUT<5>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<5>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P39.Tnet161.828nb_mem_cont/io_sel/OEbar_invP39.PADTiotp1.396DATA_INOUT<5>DATA_INOUT_5_IOBUF/OBUFTDATA_INOUT<5>1.7902.3324.12243.456.6COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.834Paths for end point interfaz_spi/controlador_spi_principal/word_int_4 (SLICE_X9Y5.B1), 1 path +11.833DATA_INOUT<4>interfaz_spi/controlador_spi_principal/word_int_4-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<6>16.667DATA_INOUT<4>clk_main0.317DATA_INOUT<4>interfaz_spi/controlador_spi_principal/word_int_42P38.PADP38.ITiopi1.310DATA_INOUT<4>DATA_INOUT<4>DATA_INOUT_4_IOBUF/IBUFProtoComp55.IMUX.6SLICE_X9Y5.B1net12.477N53SLICE_X9Y5.CLKTas0.322interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/data_mux<4>1interfaz_spi/controlador_spi_principal/word_int_41.6322.4774.109clk_u_proc_BUFG39.760.3clk_maininterfaz_spi/controlador_spi_principal/word_int_44P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_4 (SLICE_X9Y5.B1), 1 path +2.135DATA_INOUT<4>interfaz_spi/controlador_spi_principal/word_int_40.161clk_maininterfaz_spi/controlador_spi_principal/word_int<6>0.000DATA_INOUT<4>clk_main0.317DATA_INOUT<4>interfaz_spi/controlador_spi_principal/word_int_42P38.PADP38.ITiopi0.763DATA_INOUT<4>DATA_INOUT<4>DATA_INOUT_4_IOBUF/IBUFProtoComp55.IMUX.6SLICE_X9Y5.B1net11.635N53SLICE_X9Y5.CLKTah0.215interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/data_mux<4>1interfaz_spi/controlador_spi_principal/word_int_40.9781.6352.613clk_u_proc_BUFG37.462.6clk_maininterfaz_spi/controlador_spi_principal/word_int_44P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.747Paths for end point DATA_INOUT<4> (P38.PAD), 339 paths +2.920nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<4>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.749nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<4>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X23Y33.A2net241.723nb_mem_cont/mux_data/_n0046SLICE_X23Y33.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7>nb_mem_cont/mux_data/Mmux_DATA_OUT271SLICE_X10Y16.C2net12.279nb_mem_cont/mux_data/Mmux_DATA_OUT27SLICE_X10Y16.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT274nb_mem_cont/mux_data/Mmux_DATA_OUT278P38.Onet12.901nb_mem_cont/data_mux<4>P38.PADTioop2.381DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>3.7649.98513.74927.472.62.962nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<4>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.718nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<4>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X23Y33.A2net241.723nb_mem_cont/mux_data/_n0046SLICE_X23Y33.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7>nb_mem_cont/mux_data/Mmux_DATA_OUT271SLICE_X10Y16.C2net12.279nb_mem_cont/mux_data/Mmux_DATA_OUT27SLICE_X10Y16.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT274nb_mem_cont/mux_data/Mmux_DATA_OUT278P38.Onet12.901nb_mem_cont/data_mux<4>P38.PADTioop2.381DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>3.70010.01813.71827.073.03.055nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<4>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.607nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<4>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y24.C3net110.712nb_mem_cont/oe_ch_vect<2>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X23Y33.A2net241.723nb_mem_cont/mux_data/_n0046SLICE_X23Y33.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<7>nb_mem_cont/mux_data/Mmux_DATA_OUT271SLICE_X10Y16.C2net12.279nb_mem_cont/mux_data/Mmux_DATA_OUT27SLICE_X10Y16.CTilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT274nb_mem_cont/mux_data/Mmux_DATA_OUT278P38.Onet12.901nb_mem_cont/data_mux<4>P38.PADTioop2.381DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>3.7179.89013.60727.372.7Fastest Paths: COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<4> (P38.PAD), 339 paths +3.586nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<4>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.295nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<4>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P38.Tnet161.828nb_mem_cont/io_sel/OEbar_invP38.PADTiotp1.396DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>1.7522.5434.29540.859.23.579nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<4>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.291nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<4>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P38.Tnet161.828nb_mem_cont/io_sel/OEbar_invP38.PADTiotp1.396DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>1.7862.5054.29141.658.43.481nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<4>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd274.122nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<4>16.667clk_mainDATA_INOUT<4>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<4>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P38.Tnet161.828nb_mem_cont/io_sel/OEbar_invP38.PADTiotp1.396DATA_INOUT<4>DATA_INOUT_4_IOBUF/OBUFTDATA_INOUT<4>1.7902.3324.12243.456.6COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.773Paths for end point interfaz_spi/controlador_spi_principal/word_int_3 (SLICE_X9Y5.A3), 1 path +11.894DATA_INOUT<3>interfaz_spi/controlador_spi_principal/word_int_3-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<6>16.667DATA_INOUT<3>clk_main0.317DATA_INOUT<3>interfaz_spi/controlador_spi_principal/word_int_32P35.PADP35.ITiopi1.310DATA_INOUT<3>DATA_INOUT<3>DATA_INOUT_3_IOBUF/IBUFProtoComp55.IMUX.5SLICE_X9Y5.A3net12.416N54SLICE_X9Y5.CLKTas0.322interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/data_mux<3>1interfaz_spi/controlador_spi_principal/word_int_31.6322.4164.048clk_u_proc_BUFG40.359.7clk_maininterfaz_spi/controlador_spi_principal/word_int_34P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_3 (SLICE_X9Y5.A3), 1 path +2.073DATA_INOUT<3>interfaz_spi/controlador_spi_principal/word_int_30.161clk_maininterfaz_spi/controlador_spi_principal/word_int<6>0.000DATA_INOUT<3>clk_main0.317DATA_INOUT<3>interfaz_spi/controlador_spi_principal/word_int_32P35.PADP35.ITiopi0.763DATA_INOUT<3>DATA_INOUT<3>DATA_INOUT_3_IOBUF/IBUFProtoComp55.IMUX.5SLICE_X9Y5.A3net11.573N54SLICE_X9Y5.CLKTah0.215interfaz_spi/controlador_spi_principal/word_int<6>interfaz_spi/data_mux<3>1interfaz_spi/controlador_spi_principal/word_int_30.9781.5732.551clk_u_proc_BUFG38.361.7clk_maininterfaz_spi/controlador_spi_principal/word_int_34P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.461Paths for end point DATA_INOUT<3> (P35.PAD), 339 paths +3.206nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<3>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.463nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<3>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X22Y34.D5net241.701nb_mem_cont/mux_data/_n0046SLICE_X22Y34.DTilo0.205nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3>nb_mem_cont/mux_data/Mmux_DATA_OUT241SLICE_X19Y23.A4net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT24SLICE_X19Y23.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT244nb_mem_cont/mux_data/Mmux_DATA_OUT248P35.Onet13.476nb_mem_cont/data_mux<3>P35.PADTioop2.381DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>3.7649.69913.46328.072.03.248nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<3>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.432nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<3>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y24.C2net91.945nb_mem_cont/oe_ch_vect<0>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X22Y34.D5net241.701nb_mem_cont/mux_data/_n0046SLICE_X22Y34.DTilo0.205nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3>nb_mem_cont/mux_data/Mmux_DATA_OUT241SLICE_X19Y23.A4net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT24SLICE_X19Y23.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT244nb_mem_cont/mux_data/Mmux_DATA_OUT248P35.Onet13.476nb_mem_cont/data_mux<3>P35.PADTioop2.381DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>3.7009.73213.43227.572.53.341nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<3>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.321nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<3>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y24.C3net110.712nb_mem_cont/oe_ch_vect<2>SLICE_X14Y24.CTilo0.205nb_mem_cont/oe_ch_vect<1>nb_mem_cont/mux_data/_n0046<4>1SLICE_X22Y34.D5net241.701nb_mem_cont/mux_data/_n0046SLICE_X22Y34.DTilo0.205nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<3>nb_mem_cont/mux_data/Mmux_DATA_OUT241SLICE_X19Y23.A4net11.440nb_mem_cont/mux_data/Mmux_DATA_OUT24SLICE_X19Y23.ATilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT244nb_mem_cont/mux_data/Mmux_DATA_OUT248P35.Onet13.476nb_mem_cont/data_mux<3>P35.PADTioop2.381DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>3.7179.60413.32127.972.1Fastest Paths: COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<3> (P35.PAD), 339 paths +3.315nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<3>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.024nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<3>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P35.Tnet161.557nb_mem_cont/io_sel/OEbar_invP35.PADTiotp1.396DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>1.7522.2724.02443.556.53.308nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<3>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.020nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<3>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P35.Tnet161.557nb_mem_cont/io_sel/OEbar_invP35.PADTiotp1.396DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>1.7862.2344.02044.455.63.210nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<3>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.851nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<3>16.667clk_mainDATA_INOUT<3>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<3>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P35.Tnet161.557nb_mem_cont/io_sel/OEbar_invP35.PADTiotp1.396DATA_INOUT<3>DATA_INOUT_3_IOBUF/OBUFTDATA_INOUT<3>1.7902.0613.85146.553.5COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.645Paths for end point interfaz_spi/controlador_spi_principal/word_int_2 (SLICE_X8Y5.D4), 1 path +12.022DATA_INOUT<2>interfaz_spi/controlador_spi_principal/word_int_2-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<2>16.667DATA_INOUT<2>clk_main0.317DATA_INOUT<2>interfaz_spi/controlador_spi_principal/word_int_22P34.PADP34.ITiopi1.310DATA_INOUT<2>DATA_INOUT<2>DATA_INOUT_2_IOBUF/IBUFProtoComp55.IMUX.4SLICE_X8Y5.D4net12.321N55SLICE_X8Y5.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/data_mux<2>1interfaz_spi/controlador_spi_principal/word_int_21.5992.3213.920clk_u_proc_BUFG40.859.2clk_maininterfaz_spi/controlador_spi_principal/word_int_24P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_2 (SLICE_X8Y5.D4), 1 path +1.974DATA_INOUT<2>interfaz_spi/controlador_spi_principal/word_int_20.161clk_maininterfaz_spi/controlador_spi_principal/word_int<2>0.000DATA_INOUT<2>clk_main0.317DATA_INOUT<2>interfaz_spi/controlador_spi_principal/word_int_22P34.PADP34.ITiopi0.763DATA_INOUT<2>DATA_INOUT<2>DATA_INOUT_2_IOBUF/IBUFProtoComp55.IMUX.4SLICE_X8Y5.D4net11.492N55SLICE_X8Y5.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/data_mux<2>1interfaz_spi/controlador_spi_principal/word_int_20.9601.4922.452clk_u_proc_BUFG39.260.8clk_maininterfaz_spi/controlador_spi_principal/word_int_24P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.384Paths for end point DATA_INOUT<2> (P34.PAD), 339 paths +3.283nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<2>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.386nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<2>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X20Y31.D4net241.382nb_mem_cont/mux_data/_n0040SLICE_X20Y31.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT215nb_mem_cont/mux_data/Mmux_DATA_OUT216SLICE_X18Y25.A1net11.340nb_mem_cont/mux_data/Mmux_DATA_OUT215SLICE_X18Y25.ATilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT211nb_mem_cont/mux_data/Mmux_DATA_OUT218P34.Onet13.623nb_mem_cont/data_mux<2>P34.PADTioop2.381DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>3.7549.63213.38628.072.03.325nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<2>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.355nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<2>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X20Y31.D4net241.382nb_mem_cont/mux_data/_n0040SLICE_X20Y31.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT215nb_mem_cont/mux_data/Mmux_DATA_OUT216SLICE_X18Y25.A1net11.340nb_mem_cont/mux_data/Mmux_DATA_OUT215SLICE_X18Y25.ATilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT211nb_mem_cont/mux_data/Mmux_DATA_OUT218P34.Onet13.623nb_mem_cont/data_mux<2>P34.PADTioop2.381DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>3.6909.66513.35527.672.43.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<2>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<2>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X20Y31.D4net241.382nb_mem_cont/mux_data/_n0040SLICE_X20Y31.DTilo0.203nb_mem_cont/mux_data/Mmux_DATA_OUT215nb_mem_cont/mux_data/Mmux_DATA_OUT216SLICE_X18Y25.A1net11.340nb_mem_cont/mux_data/Mmux_DATA_OUT215SLICE_X18Y25.ATilo0.205nb_mem_cont/mux_data/Mmux_DATA_OUT211nb_mem_cont/mux_data/Mmux_DATA_OUT218P34.Onet13.623nb_mem_cont/data_mux<2>P34.PADTioop2.381DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>3.7079.62413.33127.872.2Fastest Paths: COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<2> (P34.PAD), 339 paths +3.315nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<2>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.024nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<2>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P34.Tnet161.557nb_mem_cont/io_sel/OEbar_invP34.PADTiotp1.396DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>1.7522.2724.02443.556.53.308nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<2>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.020nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<2>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P34.Tnet161.557nb_mem_cont/io_sel/OEbar_invP34.PADTiotp1.396DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>1.7862.2344.02044.455.63.210nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<2>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.851nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<2>16.667clk_mainDATA_INOUT<2>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<2>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P34.Tnet161.557nb_mem_cont/io_sel/OEbar_invP34.PADTiotp1.396DATA_INOUT<2>DATA_INOUT_2_IOBUF/OBUFTDATA_INOUT<2>1.7902.0613.85146.553.5COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.790Paths for end point interfaz_spi/controlador_spi_principal/word_int_1 (SLICE_X8Y5.C4), 1 path +11.877DATA_INOUT<1>interfaz_spi/controlador_spi_principal/word_int_1-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<2>16.667DATA_INOUT<1>clk_main0.317DATA_INOUT<1>interfaz_spi/controlador_spi_principal/word_int_12P33.PADP33.ITiopi1.310DATA_INOUT<1>DATA_INOUT<1>DATA_INOUT_1_IOBUF/IBUFProtoComp55.IMUX.3SLICE_X8Y5.C4net12.466N56SLICE_X8Y5.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/data_mux<1>1interfaz_spi/controlador_spi_principal/word_int_11.5992.4664.065clk_u_proc_BUFG39.360.7clk_maininterfaz_spi/controlador_spi_principal/word_int_14P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_1 (SLICE_X8Y5.C4), 1 path +2.068DATA_INOUT<1>interfaz_spi/controlador_spi_principal/word_int_10.161clk_maininterfaz_spi/controlador_spi_principal/word_int<2>0.000DATA_INOUT<1>clk_main0.317DATA_INOUT<1>interfaz_spi/controlador_spi_principal/word_int_12P33.PADP33.ITiopi0.763DATA_INOUT<1>DATA_INOUT<1>DATA_INOUT_1_IOBUF/IBUFProtoComp55.IMUX.3SLICE_X8Y5.C4net11.586N56SLICE_X8Y5.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/data_mux<1>1interfaz_spi/controlador_spi_principal/word_int_10.9601.5862.546clk_u_proc_BUFG37.762.3clk_maininterfaz_spi/controlador_spi_principal/word_int_14P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.456Paths for end point DATA_INOUT<1> (P33.PAD), 339 paths +3.211nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9DATA_INOUT<1>-0.311clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd613.450nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd6DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd94P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X3Y16.CLKnet2261.126clk_u_proc_BUFG-3.0882.777-0.311nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9DATA_INOUT<1>5SLICE_X3Y16.CLKclk_u_proc_BUFGSLICE_X3Y16.CMUXTshcko0.461nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd6nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9SLICE_X5Y18.B6net50.902nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd9SLICE_X5Y18.BTilo0.259nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>2SLICE_X11Y25.D3net21.207nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11SLICE_X11Y25.DTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3SLICE_X15Y42.D1net562.343nb_mem_cont/hb_lbbarSLICE_X15Y42.DMUXTilo0.313nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110nb_mem_cont/mux_data/Mmux_DATA_OUT187SLICE_X19Y21.A3net11.822nb_mem_cont/mux_data/Mmux_DATA_OUT186SLICE_X19Y21.ATilo0.259nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19>nb_mem_cont/mux_data/Mmux_DATA_OUT188P33.Onet13.244nb_mem_cont/data_mux<1>P33.PADTioop2.381DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>3.9329.51813.45029.270.83.244nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19DATA_INOUT<1>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.418nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd194P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19DATA_INOUT<1>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19SLICE_X5Y18.B3net50.876nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd19SLICE_X5Y18.BTilo0.259nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>2SLICE_X11Y25.D3net21.207nb_mem_cont/ram_control/ram_contr_cur_state__n0327<10>11SLICE_X11Y25.DTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3SLICE_X15Y42.D1net562.343nb_mem_cont/hb_lbbarSLICE_X15Y42.DMUXTilo0.313nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110nb_mem_cont/mux_data/Mmux_DATA_OUT187SLICE_X19Y21.A3net11.822nb_mem_cont/mux_data/Mmux_DATA_OUT186SLICE_X19Y21.ATilo0.259nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19>nb_mem_cont/mux_data/Mmux_DATA_OUT188P33.Onet13.244nb_mem_cont/data_mux<1>P33.PADTioop2.381DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>3.9269.49213.41829.370.73.250nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37DATA_INOUT<1>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3413.419nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd374P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y16.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37DATA_INOUT<1>5SLICE_X6Y16.CLKclk_u_proc_BUFGSLICE_X6Y16.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37SLICE_X8Y24.B2net51.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37SLICE_X8Y24.BTilo0.203nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>1SLICE_X11Y25.D2net10.636nb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>SLICE_X11Y25.DTilo0.259nb_mem_cont/hb_lbbarnb_mem_cont/ram_control/ram_contr_cur_state__n0467<8>3SLICE_X15Y42.D1net562.343nb_mem_cont/hb_lbbarSLICE_X15Y42.DMUXTilo0.313nb_mem_cont/nibble_pack_ch4/Mmux_resul_mem110nb_mem_cont/mux_data/Mmux_DATA_OUT187SLICE_X19Y21.A3net11.822nb_mem_cont/mux_data/Mmux_DATA_OUT186SLICE_X19Y21.ATilo0.259nb_mem_cont/nibble_pack_ch5/resul_mem_internal_aux<19>nb_mem_cont/mux_data/Mmux_DATA_OUT188P33.Onet13.244nb_mem_cont/data_mux<1>P33.PADTioop2.381DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>3.8709.54913.41928.871.2Fastest Paths: COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<1> (P33.PAD), 339 paths +3.293nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<1>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.002nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<1>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P33.Tnet161.535nb_mem_cont/io_sel/OEbar_invP33.PADTiotp1.396DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>1.7522.2504.00243.856.23.286nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<1>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.998nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<1>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P33.Tnet161.535nb_mem_cont/io_sel/OEbar_invP33.PADTiotp1.396DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>1.7862.2123.99844.755.33.188nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<1>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.829nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<1>16.667clk_mainDATA_INOUT<1>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<1>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P33.Tnet161.535nb_mem_cont/io_sel/OEbar_invP33.PADTiotp1.396DATA_INOUT<1>DATA_INOUT_1_IOBUF/OBUFTDATA_INOUT<1>1.7902.0393.82946.753.3COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.440Paths for end point interfaz_spi/controlador_spi_principal/word_int_0 (SLICE_X8Y5.A5), 1 path +12.227DATA_INOUT<0>interfaz_spi/controlador_spi_principal/word_int_0-0.408clk_maininterfaz_spi/controlador_spi_principal/word_int<2>16.667DATA_INOUT<0>clk_main0.317DATA_INOUT<0>interfaz_spi/controlador_spi_principal/word_int_02P32.PADP32.ITiopi1.310DATA_INOUT<0>DATA_INOUT<0>DATA_INOUT_0_IOBUF/IBUFProtoComp55.IMUX.2SLICE_X8Y5.A5net12.116N57SLICE_X8Y5.CLKTas0.289interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi11interfaz_spi/controlador_spi_principal/word_int_01.5992.1163.715clk_u_proc_BUFG43.057.0clk_maininterfaz_spi/controlador_spi_principal/word_int_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.705clk_u_proc_BUFG-2.4562.048-0.408Hold Paths: COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_principal/word_int_0 (SLICE_X8Y5.A5), 1 path +1.842DATA_INOUT<0>interfaz_spi/controlador_spi_principal/word_int_00.161clk_maininterfaz_spi/controlador_spi_principal/word_int<2>0.000DATA_INOUT<0>clk_main0.317DATA_INOUT<0>interfaz_spi/controlador_spi_principal/word_int_02P32.PADP32.ITiopi0.763DATA_INOUT<0>DATA_INOUT<0>DATA_INOUT_0_IOBUF/IBUFProtoComp55.IMUX.2SLICE_X8Y5.A5net11.360N57SLICE_X8Y5.CLKTah0.197interfaz_spi/controlador_spi_principal/word_int<2>interfaz_spi/multiplexor_ram_header/Mmux_data_tospi11interfaz_spi/controlador_spi_principal/word_int_00.9601.3602.320clk_u_proc_BUFG41.458.6clk_maininterfaz_spi/controlador_spi_principal/word_int_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y5.CLKnet2260.845clk_u_proc_BUFG-1.5821.7430.161COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";33900001013.530Paths for end point DATA_INOUT<0> (P32.PAD), 339 paths +3.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<0>-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd313.532nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd314P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31DATA_INOUT<0>5SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.D2net51.137nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd31SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X23Y35.A5net241.663nb_mem_cont/mux_data/_n0040SLICE_X23Y35.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23>nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X15Y24.B6net11.300nb_mem_cont/mux_data/Mmux_DATA_OUT37SLICE_X15Y24.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT35nb_mem_cont/mux_data/Mmux_DATA_OUT39P32.Onet13.418nb_mem_cont/data_mux<0>P32.PADTioop2.381DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>3.8649.66813.53228.671.43.179nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<0>-0.330clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3013.501nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd304P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X11Y18.CLKnet2261.107clk_u_proc_BUFG-3.0882.758-0.330nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30DATA_INOUT<0>5SLICE_X11Y18.CLKclk_u_proc_BUFGSLICE_X11Y18.CQTcko0.391nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.D4net141.170nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd30SLICE_X5Y14.DTilo0.259nb_mem_cont/oe_ch_vect<0>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<3>1SLICE_X14Y25.D1net92.150nb_mem_cont/oe_ch_vect<0>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X23Y35.A5net241.663nb_mem_cont/mux_data/_n0040SLICE_X23Y35.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23>nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X15Y24.B6net11.300nb_mem_cont/mux_data/Mmux_DATA_OUT37SLICE_X15Y24.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT35nb_mem_cont/mux_data/Mmux_DATA_OUT39P32.Onet13.418nb_mem_cont/data_mux<0>P32.PADTioop2.381DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>3.8009.70113.50128.171.93.185nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<0>-0.312clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1613.477nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd164P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y17.CLKnet2261.125clk_u_proc_BUFG-3.0882.776-0.312nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16DATA_INOUT<0>5SLICE_X2Y17.CLKclk_u_proc_BUFGSLICE_X2Y17.CQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.B1net42.275nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd16SLICE_X13Y23.BTilo0.259nb_mem_cont/oe_ch_vect<2>nb_mem_cont/ram_control/ram_contr_cur_state__n0467<5>1SLICE_X14Y25.D2net111.004nb_mem_cont/oe_ch_vect<2>SLICE_X14Y25.DMUXTilo0.251nb_mem_cont/mux_data/_n0034nb_mem_cont/mux_data/_n0040<4>2SLICE_X23Y35.A5net241.663nb_mem_cont/mux_data/_n0040SLICE_X23Y35.ATilo0.259nb_mem_cont/nibble_pack_ch1/resul_mem_internal_aux<23>nb_mem_cont/mux_data/Mmux_DATA_OUT36SLICE_X15Y24.B6net11.300nb_mem_cont/mux_data/Mmux_DATA_OUT37SLICE_X15Y24.BTilo0.259nb_mem_cont/mux_data/Mmux_DATA_OUT35nb_mem_cont/mux_data/Mmux_DATA_OUT39P32.Onet13.418nb_mem_cont/data_mux<0>P32.PADTioop2.381DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>3.8179.66013.47728.371.7Fastest Paths: COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point DATA_INOUT<0> (P32.PAD), 339 paths +3.293nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<0>-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.002nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3DATA_INOUT<0>2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.A5net70.715nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P32.Tnet161.535nb_mem_cont/io_sel/OEbar_invP32.PADTiotp1.396DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>1.7522.2504.00243.856.23.286nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<0>-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.998nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1DATA_INOUT<0>2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.A2net190.677nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P32.Tnet161.535nb_mem_cont/io_sel/OEbar_invP32.PADTiotp1.396DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>1.7862.2123.99844.755.33.188nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<0>-0.324clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd273.829nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27DATA_INOUT<0>16.667clk_mainDATA_INOUT<0>0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2260.566clk_u_proc_BUFG-1.6981.374-0.324nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2DATA_INOUT<0>2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.A3net80.504nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X3Y20.ATilo0.156nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd21nb_mem_cont/io_sel/OEbar_inv1P32.Tnet161.535nb_mem_cont/io_sel/OEbar_invP32.PADTiotp1.396DATA_INOUT<0>DATA_INOUT_0_IOBUF/OBUFTDATA_INOUT<0>1.7902.0393.82946.753.3COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000103.976Paths for end point i2c_comp/SDAoe (SLICE_X23Y26.D4), 1 path +12.691sda_rpii2c_comp/SDAoe-0.494clk_maini2c_comp/SDAoe16.667sda_rpiclk_main0.317sda_rpii2c_comp/SDAoe2P83.PADP83.ITiopi1.300sda_rpisda_rpisda_rpi_IOBUF/IBUFProtoComp55.IMUXSLICE_X23Y26.D4net11.543N59SLICE_X23Y26.CLKTas0.322i2c_comp/SDAoei2c_comp/SDAoe_rstpoti2c_comp/SDAoe1.6221.5433.165clk_u_proc_BUFG51.248.8clk_maini2c_comp/SDAoe4P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y26.CLKnet2260.619clk_u_proc_BUFG-2.4561.962-0.494Hold Paths: COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +Paths for end point i2c_comp/SDAoe (SLICE_X23Y26.D4), 1 path +1.530sda_rpii2c_comp/SDAoe0.075clk_maini2c_comp/SDAoe0.000sda_rpiclk_main0.317sda_rpii2c_comp/SDAoe2P83.PADP83.ITiopi0.754sda_rpisda_rpisda_rpi_IOBUF/IBUFProtoComp55.IMUXSLICE_X23Y26.D4net10.953N59SLICE_X23Y26.CLKTah0.215i2c_comp/SDAoei2c_comp/SDAoe_rstpoti2c_comp/SDAoe0.9690.9531.922clk_u_proc_BUFG50.449.6clk_maini2c_comp/SDAoe4P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y26.CLKnet2260.759clk_u_proc_BUFG-1.5821.6570.075COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";100001013.152Paths for end point sda_rpi (P83.PAD), 1 path +3.515i2c_comp/SDAoesda_rpi-0.359clk_maini2c_comp/SDAoe13.194i2c_comp/SDAoesda_rpi16.667clk_mainsda_rpi0.317clk_maini2c_comp/SDAoe4P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y26.CLKnet2261.078clk_u_proc_BUFG-3.0882.729-0.359i2c_comp/SDAoesda_rpi1SLICE_X23Y26.CLKclk_u_proc_BUFGSLICE_X23Y26.DQTcko0.391i2c_comp/SDAoei2c_comp/SDAoeP83.Tnet21.252i2c_comp/SDAoeP83.PADTiotp11.551sda_rpisda_rpi_IOBUF/OBUFTsda_rpi11.9421.25213.19490.59.5Fastest Paths: COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point sda_rpi (P83.PAD), 1 path +10.248i2c_comp/SDAoesda_rpi-0.432clk_maini2c_comp/SDAoe10.997i2c_comp/SDAoesda_rpi16.667clk_mainsda_rpi0.317clk_maini2c_comp/SDAoe4P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y26.CLKnet2260.458clk_u_proc_BUFG-1.6981.266-0.432i2c_comp/SDAoesda_rpi1SLICE_X23Y26.CLKclk_u_proc_BUFGSLICE_X23Y26.DQTcko0.198i2c_comp/SDAoei2c_comp/SDAoeP83.Tnet20.768i2c_comp/SDAoeP83.PADTiotp10.031sda_rpisda_rpi_IOBUF/OBUFTsda_rpi10.2290.76810.99793.07.0COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.954Paths for end point i2c_comp/flanco_SCL_0 (SLICE_X22Y8.AX), 1 path +11.713scl_rpii2c_comp/flanco_SCL_0-0.436clk_maini2c_comp/flanco_SCL<1>16.667scl_rpiclk_main0.317scl_rpii2c_comp/flanco_SCL_01P85.PADP85.ITiopi1.300scl_rpiscl_rpiscl_rpi_IOBUF/IBUFProtoComp55.IMUX.1SLICE_X22Y8.AXnet12.765N58SLICE_X22Y8.CLKTdick0.136i2c_comp/flanco_SCL<1>i2c_comp/flanco_SCL_01.4362.7654.201clk_u_proc_BUFG34.265.8clk_maini2c_comp/flanco_SCL_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y8.CLKnet2260.677clk_u_proc_BUFG-2.4562.020-0.436Hold Paths: COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +Paths for end point i2c_comp/flanco_SCL_0 (SLICE_X22Y8.AX), 1 path +2.053scl_rpii2c_comp/flanco_SCL_00.133clk_maini2c_comp/flanco_SCL<1>0.000scl_rpiclk_main0.317scl_rpii2c_comp/flanco_SCL_01P85.PADP85.ITiopi0.754scl_rpiscl_rpiscl_rpi_IOBUF/IBUFProtoComp55.IMUX.1SLICE_X22Y8.AXnet11.701N58SLICE_X22Y8.CLKTckdi0.048i2c_comp/flanco_SCL<1>i2c_comp/flanco_SCL_00.8021.7012.503clk_u_proc_BUFG32.068.0clk_maini2c_comp/flanco_SCL_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y8.CLKnet2260.817clk_u_proc_BUFG-1.5821.7150.133COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";100001013.744Paths for end point scl_rpi (P85.PAD), 1 path +2.923i2c_comp/SCLoescl_rpi-0.361clk_maini2c_comp/SCLoe13.788i2c_comp/SCLoescl_rpi16.667clk_mainscl_rpi0.317clk_maini2c_comp/SCLoe4P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y22.CLKnet2261.076clk_u_proc_BUFG-3.0882.727-0.361i2c_comp/SCLoescl_rpi1SLICE_X23Y22.CLKclk_u_proc_BUFGSLICE_X23Y22.AQTcko0.391i2c_comp/SCLoei2c_comp/SCLoeP85.Tnet21.846i2c_comp/SCLoeP85.PADTiotp11.551scl_rpiscl_rpi_IOBUF/OBUFTscl_rpi11.9421.84613.78886.613.4Fastest Paths: COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point scl_rpi (P85.PAD), 1 path +10.608i2c_comp/SCLoescl_rpi-0.434clk_maini2c_comp/SCLoe11.359i2c_comp/SCLoescl_rpi16.667clk_mainscl_rpi0.317clk_maini2c_comp/SCLoe4P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y22.CLKnet2260.456clk_u_proc_BUFG-1.6981.264-0.434i2c_comp/SCLoescl_rpi1SLICE_X23Y22.CLKclk_u_proc_BUFGSLICE_X23Y22.AQTcko0.198i2c_comp/SCLoei2c_comp/SCLoeP85.Tnet21.130i2c_comp/SCLoeP85.PADTiotp10.031scl_rpiscl_rpi_IOBUF/OBUFTscl_rpi10.2291.13011.35990.19.9COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.505Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (SLICE_X22Y52.B3), 1 path +12.162chn_bits_acq_ch1<3>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0-0.429clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch1<3>clk_main0.317chn_bits_acq_ch1<3>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_02P116.PADP116.ITiopi1.310chn_bits_acq_ch1<3>chn_bits_acq_ch1<3>chn_bits_acq_ch1_3_IBUFProtoComp52.IMUX.7SLICE_X22Y52.B3net12.236chn_bits_acq_ch1_3_IBUFSLICE_X22Y52.CLKTas0.213nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_01.5232.2363.759clk_u_proc_BUFG40.559.5clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0 (SLICE_X22Y52.B3), 1 path +1.822chn_bits_acq_ch1<3>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_00.140clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch1<3>clk_main0.317chn_bits_acq_ch1<3>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_02P116.PADP116.ITiopi0.763chn_bits_acq_ch1<3>chn_bits_acq_ch1<3>chn_bits_acq_ch1_3_IBUFProtoComp52.IMUX.7SLICE_X22Y52.B3net11.395chn_bits_acq_ch1_3_IBUFSLICE_X22Y52.CLKTah0.121nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_00.8841.3952.279clk_u_proc_BUFG38.861.2clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit3_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.386Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (SLICE_X22Y52.A5), 1 path +12.281chn_bits_acq_ch1<2>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0-0.429clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch1<2>clk_main0.317chn_bits_acq_ch1<2>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_02P115.PADP115.ITiopi1.310chn_bits_acq_ch1<2>chn_bits_acq_ch1<2>chn_bits_acq_ch1_2_IBUFProtoComp52.IMUX.6SLICE_X22Y52.A5net12.117chn_bits_acq_ch1_2_IBUFSLICE_X22Y52.CLKTas0.213nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_01.5232.1173.640clk_u_proc_BUFG41.858.2clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0 (SLICE_X22Y52.A5), 1 path +1.744chn_bits_acq_ch1<2>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_00.140clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch1<2>clk_main0.317chn_bits_acq_ch1<2>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_02P115.PADP115.ITiopi0.763chn_bits_acq_ch1<2>chn_bits_acq_ch1<2>chn_bits_acq_ch1_2_IBUFProtoComp52.IMUX.6SLICE_X22Y52.A5net11.317chn_bits_acq_ch1_2_IBUFSLICE_X22Y52.CLKTah0.121nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_00.8841.3172.201clk_u_proc_BUFG40.259.8clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit2_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.578Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (SLICE_X22Y52.D4), 1 path +12.089chn_bits_acq_ch1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0-0.429clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch1<1>clk_main0.317chn_bits_acq_ch1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_02P114.PADP114.ITiopi1.310chn_bits_acq_ch1<1>chn_bits_acq_ch1<1>chn_bits_acq_ch1_1_IBUFProtoComp52.IMUX.5SLICE_X22Y52.D4net12.309chn_bits_acq_ch1_1_IBUFSLICE_X22Y52.CLKTas0.213nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_01.5232.3093.832clk_u_proc_BUFG39.760.3clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0 (SLICE_X22Y52.D4), 1 path +1.907chn_bits_acq_ch1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_00.140clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch1<1>clk_main0.317chn_bits_acq_ch1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_02P114.PADP114.ITiopi0.763chn_bits_acq_ch1<1>chn_bits_acq_ch1<1>chn_bits_acq_ch1_1_IBUFProtoComp52.IMUX.5SLICE_X22Y52.D4net11.480chn_bits_acq_ch1_1_IBUFSLICE_X22Y52.CLKTah0.121nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_00.8841.4802.364clk_u_proc_BUFG37.462.6clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit1_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y52.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.341Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (SLICE_X23Y52.A5), 1 path +12.326chn_bits_acq_ch1<0>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0-0.429clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1>16.667chn_bits_acq_ch1<0>clk_main0.317chn_bits_acq_ch1<0>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_02P112.PADP112.ITiopi1.310chn_bits_acq_ch1<0>chn_bits_acq_ch1<0>chn_bits_acq_ch1_0_IBUFProtoComp52.IMUX.4SLICE_X23Y52.A5net12.058chn_bits_acq_ch1_0_IBUFSLICE_X23Y52.CLKTas0.227nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_01.5372.0583.595clk_u_proc_BUFG42.857.2clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y52.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0 (SLICE_X23Y52.A5), 1 path +1.731chn_bits_acq_ch1<0>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_00.140clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1>0.000chn_bits_acq_ch1<0>clk_main0.317chn_bits_acq_ch1<0>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_02P112.PADP112.ITiopi0.763chn_bits_acq_ch1<0>chn_bits_acq_ch1<0>chn_bits_acq_ch1_0_IBUFProtoComp52.IMUX.4SLICE_X23Y52.A5net11.270chn_bits_acq_ch1_0_IBUFSLICE_X23Y52.CLKTah0.155nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_00.9181.2702.188clk_u_proc_BUFG42.058.0clk_mainnb_mem_cont/nibble_pack_ch1/chn_bits_acq_bit0_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X23Y52.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";10000104.465Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (SLICE_X17Y55.D3), 1 path +795.535chn_bits_acq_ch2<3>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0-0.441clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1>800.000chn_bits_acq_ch2<3>clk_main0.317chn_bits_acq_ch2<3>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_02P121.PADP121.ITiopi1.310chn_bits_acq_ch2<3>chn_bits_acq_ch2<3>chn_bits_acq_ch2_3_IBUFProtoComp52.IMUX.11SLICE_X17Y55.D3net12.170chn_bits_acq_ch2_3_IBUFSLICE_X17Y55.CLKTas0.227nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_01.5372.1703.707clk_u_proc_BUFG41.558.5clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X17Y55.CLKnet2260.672clk_u_proc_BUFG-2.4562.015-0.441Hold Paths: COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0 (SLICE_X17Y55.D3), 1 path +1.842chn_bits_acq_ch2<3>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_00.128clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1>0.000chn_bits_acq_ch2<3>clk_main0.317chn_bits_acq_ch2<3>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_02P121.PADP121.ITiopi0.763chn_bits_acq_ch2<3>chn_bits_acq_ch2<3>chn_bits_acq_ch2_3_IBUFProtoComp52.IMUX.11SLICE_X17Y55.D3net11.369chn_bits_acq_ch2_3_IBUFSLICE_X17Y55.CLKTah0.155nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_00.9181.3692.287clk_u_proc_BUFG40.159.9clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit3_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X17Y55.CLKnet2260.812clk_u_proc_BUFG-1.5821.7100.128COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";10000104.911Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (SLICE_X18Y44.D4), 1 path +795.089chn_bits_acq_ch2<2>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0-0.493clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1>800.000chn_bits_acq_ch2<2>clk_main0.317chn_bits_acq_ch2<2>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_02P120.PADP120.ITiopi1.310chn_bits_acq_ch2<2>chn_bits_acq_ch2<2>chn_bits_acq_ch2_2_IBUFProtoComp52.IMUX.10SLICE_X18Y44.D4net12.578chn_bits_acq_ch2_2_IBUFSLICE_X18Y44.CLKTas0.213nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_01.5232.5784.101clk_u_proc_BUFG37.162.9clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y44.CLKnet2260.620clk_u_proc_BUFG-2.4561.963-0.493Hold Paths: COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0 (SLICE_X18Y44.D4), 1 path +2.089chn_bits_acq_ch2<2>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_00.076clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1>0.000chn_bits_acq_ch2<2>clk_main0.317chn_bits_acq_ch2<2>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_02P120.PADP120.ITiopi0.763chn_bits_acq_ch2<2>chn_bits_acq_ch2<2>chn_bits_acq_ch2_2_IBUFProtoComp52.IMUX.10SLICE_X18Y44.D4net11.598chn_bits_acq_ch2_2_IBUFSLICE_X18Y44.CLKTah0.121nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_00.8841.5982.482clk_u_proc_BUFG35.664.4clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit2_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y44.CLKnet2260.760clk_u_proc_BUFG-1.5821.6580.076COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";10000104.579Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (SLICE_X18Y55.A2), 1 path +795.421chn_bits_acq_ch2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0-0.441clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1>800.000chn_bits_acq_ch2<1>clk_main0.317chn_bits_acq_ch2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_02P119.PADP119.ITiopi1.310chn_bits_acq_ch2<1>chn_bits_acq_ch2<1>chn_bits_acq_ch2_1_IBUFProtoComp52.IMUX.9SLICE_X18Y55.A2net12.298chn_bits_acq_ch2_1_IBUFSLICE_X18Y55.CLKTas0.213nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_01.5232.2983.821clk_u_proc_BUFG39.960.1clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y55.CLKnet2260.672clk_u_proc_BUFG-2.4562.015-0.441Hold Paths: COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0 (SLICE_X18Y55.A2), 1 path +1.962chn_bits_acq_ch2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_00.128clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch2<1>clk_main0.317chn_bits_acq_ch2<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_02P119.PADP119.ITiopi0.763chn_bits_acq_ch2<1>chn_bits_acq_ch2<1>chn_bits_acq_ch2_1_IBUFProtoComp52.IMUX.9SLICE_X18Y55.A2net11.523chn_bits_acq_ch2_1_IBUFSLICE_X18Y55.CLKTah0.121nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_00.8841.5232.407clk_u_proc_BUFG36.763.3clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit1_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y55.CLKnet2260.812clk_u_proc_BUFG-1.5821.7100.128COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";10000104.569Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (SLICE_X18Y57.A2), 1 path +795.431chn_bits_acq_ch2<0>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0-0.439clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1>800.000chn_bits_acq_ch2<0>clk_main0.317chn_bits_acq_ch2<0>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_02P118.PADP118.ITiopi1.310chn_bits_acq_ch2<0>chn_bits_acq_ch2<0>chn_bits_acq_ch2_0_IBUFProtoComp52.IMUX.8SLICE_X18Y57.A2net12.290chn_bits_acq_ch2_0_IBUFSLICE_X18Y57.CLKTas0.213nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_01.5232.2903.813clk_u_proc_BUFG39.960.1clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y57.CLKnet2260.674clk_u_proc_BUFG-2.4562.017-0.439Hold Paths: COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0 (SLICE_X18Y57.A2), 1 path +1.984chn_bits_acq_ch2<0>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_00.130clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1>0.000chn_bits_acq_ch2<0>clk_main0.317chn_bits_acq_ch2<0>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_02P118.PADP118.ITiopi0.763chn_bits_acq_ch2<0>chn_bits_acq_ch2<0>chn_bits_acq_ch2_0_IBUFProtoComp52.IMUX.8SLICE_X18Y57.A2net11.547chn_bits_acq_ch2_0_IBUFSLICE_X18Y57.CLKTah0.121nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_00.8841.5472.431clk_u_proc_BUFG36.463.6clk_mainnb_mem_cont/nibble_pack_ch2/chn_bits_acq_bit0_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y57.CLKnet2260.814clk_u_proc_BUFG-1.5821.7120.130COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.085Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (SLICE_X13Y46.D4), 1 path +11.582chn_bits_acq_ch3<3>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0-0.493clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1>16.667chn_bits_acq_ch3<3>clk_main0.317chn_bits_acq_ch3<3>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_02P131.PADP131.ITiopi1.310chn_bits_acq_ch3<3>chn_bits_acq_ch3<3>chn_bits_acq_ch3_3_IBUFProtoComp52.IMUX.15SLICE_X13Y46.D4net12.738chn_bits_acq_ch3_3_IBUFSLICE_X13Y46.CLKTas0.227nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_01.5372.7384.275clk_u_proc_BUFG36.064.0clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X13Y46.CLKnet2260.620clk_u_proc_BUFG-2.4561.963-0.493Hold Paths: COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0 (SLICE_X13Y46.D4), 1 path +2.309chn_bits_acq_ch3<3>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_00.076clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1>0.000chn_bits_acq_ch3<3>clk_main0.317chn_bits_acq_ch3<3>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_02P131.PADP131.ITiopi0.763chn_bits_acq_ch3<3>chn_bits_acq_ch3<3>chn_bits_acq_ch3_3_IBUFProtoComp52.IMUX.15SLICE_X13Y46.D4net11.784chn_bits_acq_ch3_3_IBUFSLICE_X13Y46.CLKTah0.155nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_00.9181.7842.702clk_u_proc_BUFG34.066.0clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit3_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X13Y46.CLKnet2260.760clk_u_proc_BUFG-1.5821.6580.076COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.509Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (SLICE_X15Y39.D4), 1 path +11.158chn_bits_acq_ch3<2>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0-0.504clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>16.667chn_bits_acq_ch3<2>clk_main0.317chn_bits_acq_ch3<2>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_02P127.PADP127.ITiopi1.310chn_bits_acq_ch3<2>chn_bits_acq_ch3<2>chn_bits_acq_ch3_2_IBUFProtoComp52.IMUX.14SLICE_X15Y39.D4net13.151chn_bits_acq_ch3_2_IBUFSLICE_X15Y39.CLKTas0.227nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_01.5373.1514.688clk_u_proc_BUFG32.867.2clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y39.CLKnet2260.609clk_u_proc_BUFG-2.4561.952-0.504Hold Paths: COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0 (SLICE_X15Y39.D4), 1 path +2.506chn_bits_acq_ch3<2>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_00.065clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>0.000chn_bits_acq_ch3<2>clk_main0.317chn_bits_acq_ch3<2>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_02P127.PADP127.ITiopi0.763chn_bits_acq_ch3<2>chn_bits_acq_ch3<2>chn_bits_acq_ch3_2_IBUFProtoComp52.IMUX.14SLICE_X15Y39.D4net11.970chn_bits_acq_ch3_2_IBUFSLICE_X15Y39.CLKTah0.155nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_00.9181.9702.888clk_u_proc_BUFG31.868.2clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit2_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y39.CLKnet2260.749clk_u_proc_BUFG-1.5821.6470.065COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.807Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (SLICE_X15Y48.A5), 1 path +11.860chn_bits_acq_ch3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0-0.429clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch3<1>clk_main0.317chn_bits_acq_ch3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_02P126.PADP126.ITiopi1.310chn_bits_acq_ch3<1>chn_bits_acq_ch3<1>chn_bits_acq_ch3_1_IBUFProtoComp52.IMUX.13SLICE_X15Y48.A5net12.524chn_bits_acq_ch3_1_IBUFSLICE_X15Y48.CLKTas0.227nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_01.5372.5244.061clk_u_proc_BUFG37.862.2clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y48.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0 (SLICE_X15Y48.A5), 1 path +2.066chn_bits_acq_ch3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_00.140clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch3<1>clk_main0.317chn_bits_acq_ch3<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_02P126.PADP126.ITiopi0.763chn_bits_acq_ch3<1>chn_bits_acq_ch3<1>chn_bits_acq_ch3_1_IBUFProtoComp52.IMUX.13SLICE_X15Y48.A5net11.605chn_bits_acq_ch3_1_IBUFSLICE_X15Y48.CLKTah0.155nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_00.9181.6052.523clk_u_proc_BUFG36.463.6clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit1_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y48.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.465Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (SLICE_X15Y50.D4), 1 path +12.202chn_bits_acq_ch3<0>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0-0.431clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1>16.667chn_bits_acq_ch3<0>clk_main0.317chn_bits_acq_ch3<0>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_02P124.PADP124.ITiopi1.310chn_bits_acq_ch3<0>chn_bits_acq_ch3<0>chn_bits_acq_ch3_0_IBUFProtoComp52.IMUX.12SLICE_X15Y50.D4net12.180chn_bits_acq_ch3_0_IBUFSLICE_X15Y50.CLKTas0.227nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_01.5372.1803.717clk_u_proc_BUFG41.458.6clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y50.CLKnet2260.682clk_u_proc_BUFG-2.4562.025-0.431Hold Paths: COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0 (SLICE_X15Y50.D4), 1 path +1.818chn_bits_acq_ch3<0>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_00.138clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1>0.000chn_bits_acq_ch3<0>clk_main0.317chn_bits_acq_ch3<0>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_02P124.PADP124.ITiopi0.763chn_bits_acq_ch3<0>chn_bits_acq_ch3<0>chn_bits_acq_ch3_0_IBUFProtoComp52.IMUX.12SLICE_X15Y50.D4net11.355chn_bits_acq_ch3_0_IBUFSLICE_X15Y50.CLKTah0.155nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_00.9181.3552.273clk_u_proc_BUFG40.459.6clk_mainnb_mem_cont/nibble_pack_ch3/chn_bits_acq_bit0_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y50.CLKnet2260.822clk_u_proc_BUFG-1.5821.7200.138COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.954Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (SLICE_X7Y51.A3), 1 path +11.713chn_bits_acq_ch4<3>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0-0.396clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1>16.667chn_bits_acq_ch4<3>clk_main0.317chn_bits_acq_ch4<3>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_02P138.PADP138.ITiopi1.310chn_bits_acq_ch4<3>chn_bits_acq_ch4<3>chn_bits_acq_ch4_3_IBUFProtoComp52.IMUX.19SLICE_X7Y51.A3net12.704chn_bits_acq_ch4_3_IBUFSLICE_X7Y51.CLKTas0.227nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_01.5372.7044.241clk_u_proc_BUFG36.263.8clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X7Y51.CLKnet2260.717clk_u_proc_BUFG-2.4562.060-0.396Hold Paths: COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0 (SLICE_X7Y51.A3), 1 path +2.133chn_bits_acq_ch4<3>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_00.173clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1>0.000chn_bits_acq_ch4<3>clk_main0.317chn_bits_acq_ch4<3>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_02P138.PADP138.ITiopi0.763chn_bits_acq_ch4<3>chn_bits_acq_ch4<3>chn_bits_acq_ch4_3_IBUFProtoComp52.IMUX.19SLICE_X7Y51.A3net11.705chn_bits_acq_ch4_3_IBUFSLICE_X7Y51.CLKTah0.155nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_00.9181.7052.623clk_u_proc_BUFG35.065.0clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit3_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X7Y51.CLKnet2260.857clk_u_proc_BUFG-1.5821.7550.173COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.577Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (SLICE_X5Y51.A5), 1 path +12.090chn_bits_acq_ch4<2>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0-0.396clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1>16.667chn_bits_acq_ch4<2>clk_main0.317chn_bits_acq_ch4<2>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_02P137.PADP137.ITiopi1.310chn_bits_acq_ch4<2>chn_bits_acq_ch4<2>chn_bits_acq_ch4_2_IBUFProtoComp52.IMUX.18SLICE_X5Y51.A5net12.327chn_bits_acq_ch4_2_IBUFSLICE_X5Y51.CLKTas0.227nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_01.5372.3273.864clk_u_proc_BUFG39.860.2clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X5Y51.CLKnet2260.717clk_u_proc_BUFG-2.4562.060-0.396Hold Paths: COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0 (SLICE_X5Y51.A5), 1 path +1.923chn_bits_acq_ch4<2>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_00.173clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1>0.000chn_bits_acq_ch4<2>clk_main0.317chn_bits_acq_ch4<2>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_02P137.PADP137.ITiopi0.763chn_bits_acq_ch4<2>chn_bits_acq_ch4<2>chn_bits_acq_ch4_2_IBUFProtoComp52.IMUX.18SLICE_X5Y51.A5net11.495chn_bits_acq_ch4_2_IBUFSLICE_X5Y51.CLKTah0.155nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_00.9181.4952.413clk_u_proc_BUFG38.062.0clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit2_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X5Y51.CLKnet2260.857clk_u_proc_BUFG-1.5821.7550.173COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.480Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (SLICE_X8Y56.D3), 1 path +12.187chn_bits_acq_ch4<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0-0.413clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch4<1>clk_main0.317chn_bits_acq_ch4<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_02P134.PADP134.ITiopi1.310chn_bits_acq_ch4<1>chn_bits_acq_ch4<1>chn_bits_acq_ch4_1_IBUFProtoComp52.IMUX.17SLICE_X8Y56.D3net12.286chn_bits_acq_ch4_1_IBUFSLICE_X8Y56.CLKTas0.154nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_01.4642.2863.750clk_u_proc_BUFG39.061.0clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y56.CLKnet2260.700clk_u_proc_BUFG-2.4562.043-0.413Hold Paths: COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0 (SLICE_X8Y56.D3), 1 path +1.888chn_bits_acq_ch4<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_00.156clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch4<1>clk_main0.317chn_bits_acq_ch4<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_02P134.PADP134.ITiopi0.763chn_bits_acq_ch4<1>chn_bits_acq_ch4<1>chn_bits_acq_ch4_1_IBUFProtoComp52.IMUX.17SLICE_X8Y56.D3net11.467chn_bits_acq_ch4_1_IBUFSLICE_X8Y56.CLKTah0.131nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_00.8941.4672.361clk_u_proc_BUFG37.962.1clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit1_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y56.CLKnet2260.840clk_u_proc_BUFG-1.5821.7380.156COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.465Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (SLICE_X9Y54.A4), 1 path +12.202chn_bits_acq_ch4<0>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0-0.411clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1>16.667chn_bits_acq_ch4<0>clk_main0.317chn_bits_acq_ch4<0>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_02P133.PADP133.ITiopi1.310chn_bits_acq_ch4<0>chn_bits_acq_ch4<0>chn_bits_acq_ch4_0_IBUFProtoComp52.IMUX.16SLICE_X9Y54.A4net12.200chn_bits_acq_ch4_0_IBUFSLICE_X9Y54.CLKTas0.227nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_01.5372.2003.737clk_u_proc_BUFG41.158.9clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y54.CLKnet2260.702clk_u_proc_BUFG-2.4562.045-0.411Hold Paths: COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0 (SLICE_X9Y54.A4), 1 path +1.843chn_bits_acq_ch4<0>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_00.158clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1>0.000chn_bits_acq_ch4<0>clk_main0.317chn_bits_acq_ch4<0>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_02P133.PADP133.ITiopi0.763chn_bits_acq_ch4<0>chn_bits_acq_ch4<0>chn_bits_acq_ch4_0_IBUFProtoComp52.IMUX.16SLICE_X9Y54.A4net11.400chn_bits_acq_ch4_0_IBUFSLICE_X9Y54.CLKTah0.155nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_00.9181.4002.318clk_u_proc_BUFG39.660.4clk_mainnb_mem_cont/nibble_pack_ch4/chn_bits_acq_bit0_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y54.CLKnet2260.842clk_u_proc_BUFG-1.5821.7400.158COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.088Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (SLICE_X22Y4.D3), 1 path +12.579chn_bits_acq_ch5<3>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0-0.429clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1>16.667chn_bits_acq_ch5<3>clk_main0.317chn_bits_acq_ch5<3>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_02P62.PADP62.ITiopi1.310chn_bits_acq_ch5<3>chn_bits_acq_ch5<3>chn_bits_acq_ch5_3_IBUFProtoComp52.IMUX.23SLICE_X22Y4.D3net11.819chn_bits_acq_ch5_3_IBUFSLICE_X22Y4.CLKTas0.213nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_01.5231.8193.342clk_u_proc_BUFG45.654.4clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y4.CLKnet2260.684clk_u_proc_BUFG-2.4562.027-0.429Hold Paths: COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0 (SLICE_X22Y4.D3), 1 path +1.582chn_bits_acq_ch5<3>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_00.140clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1>0.000chn_bits_acq_ch5<3>clk_main0.317chn_bits_acq_ch5<3>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_02P62.PADP62.ITiopi0.763chn_bits_acq_ch5<3>chn_bits_acq_ch5<3>chn_bits_acq_ch5_3_IBUFProtoComp52.IMUX.23SLICE_X22Y4.D3net11.155chn_bits_acq_ch5_3_IBUFSLICE_X22Y4.CLKTah0.121nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_00.8841.1552.039clk_u_proc_BUFG43.456.6clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit3_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y4.CLKnet2260.824clk_u_proc_BUFG-1.5821.7220.140COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.132Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (SLICE_X19Y17.A1), 1 path +11.535chn_bits_acq_ch5<2>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0-0.490clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1>16.667chn_bits_acq_ch5<2>clk_main0.317chn_bits_acq_ch5<2>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_02P61.PADP61.ITiopi1.310chn_bits_acq_ch5<2>chn_bits_acq_ch5<2>chn_bits_acq_ch5_2_IBUFProtoComp52.IMUX.22SLICE_X19Y17.A1net12.788chn_bits_acq_ch5_2_IBUFSLICE_X19Y17.CLKTas0.227nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_01.5372.7884.325clk_u_proc_BUFG35.564.5clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X19Y17.CLKnet2260.623clk_u_proc_BUFG-2.4561.966-0.490Hold Paths: COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0 (SLICE_X19Y17.A1), 1 path +2.294chn_bits_acq_ch5<2>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_00.079clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1>0.000chn_bits_acq_ch5<2>clk_main0.317chn_bits_acq_ch5<2>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_02P61.PADP61.ITiopi0.763chn_bits_acq_ch5<2>chn_bits_acq_ch5<2>chn_bits_acq_ch5_2_IBUFProtoComp52.IMUX.22SLICE_X19Y17.A1net11.772chn_bits_acq_ch5_2_IBUFSLICE_X19Y17.CLKTah0.155nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_00.9181.7722.690clk_u_proc_BUFG34.165.9clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit2_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X19Y17.CLKnet2260.763clk_u_proc_BUFG-1.5821.6610.079COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.238Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (SLICE_X18Y7.D3), 1 path +12.429chn_bits_acq_ch5<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0-0.441clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1>16.667chn_bits_acq_ch5<1>clk_main0.317chn_bits_acq_ch5<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_02P59.PADP59.ITiopi1.310chn_bits_acq_ch5<1>chn_bits_acq_ch5<1>chn_bits_acq_ch5_1_IBUFProtoComp52.IMUX.21SLICE_X18Y7.D3net11.957chn_bits_acq_ch5_1_IBUFSLICE_X18Y7.CLKTas0.213nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_01.5231.9573.480clk_u_proc_BUFG43.856.2clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y7.CLKnet2260.672clk_u_proc_BUFG-2.4562.015-0.441Hold Paths: COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0 (SLICE_X18Y7.D3), 1 path +1.687chn_bits_acq_ch5<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_00.128clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1>0.000chn_bits_acq_ch5<1>clk_main0.317chn_bits_acq_ch5<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_02P59.PADP59.ITiopi0.763chn_bits_acq_ch5<1>chn_bits_acq_ch5<1>chn_bits_acq_ch5_1_IBUFProtoComp52.IMUX.21SLICE_X18Y7.D3net11.248chn_bits_acq_ch5_1_IBUFSLICE_X18Y7.CLKTah0.121nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_00.8841.2482.132clk_u_proc_BUFG41.558.5clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit1_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X18Y7.CLKnet2260.812clk_u_proc_BUFG-1.5821.7100.128COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.536Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (SLICE_X22Y7.D2), 1 path +12.131chn_bits_acq_ch5<0>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0-0.436clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1>16.667chn_bits_acq_ch5<0>clk_main0.317chn_bits_acq_ch5<0>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_02P58.PADP58.ITiopi1.310chn_bits_acq_ch5<0>chn_bits_acq_ch5<0>chn_bits_acq_ch5_0_IBUFProtoComp52.IMUX.20SLICE_X22Y7.D2net12.260chn_bits_acq_ch5_0_IBUFSLICE_X22Y7.CLKTas0.213nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_01.5232.2603.783clk_u_proc_BUFG40.359.7clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y7.CLKnet2260.677clk_u_proc_BUFG-2.4562.020-0.436Hold Paths: COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0 (SLICE_X22Y7.D2), 1 path +1.894chn_bits_acq_ch5<0>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_00.133clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1>0.000chn_bits_acq_ch5<0>clk_main0.317chn_bits_acq_ch5<0>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_02P58.PADP58.ITiopi0.763chn_bits_acq_ch5<0>chn_bits_acq_ch5<0>chn_bits_acq_ch5_0_IBUFProtoComp52.IMUX.20SLICE_X22Y7.D2net11.460chn_bits_acq_ch5_0_IBUFSLICE_X22Y7.CLKTah0.121nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0<1>nb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_0_rstpotnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_00.8841.4602.344clk_u_proc_BUFG37.762.3clk_mainnb_mem_cont/nibble_pack_ch5/chn_bits_acq_bit0_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X22Y7.CLKnet2260.817clk_u_proc_BUFG-1.5821.7150.133COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";50000506.085Paths for end point lock_rst_bar (SLICE_X14Y22.AX), 1 path +10.582locklock_rst_bar-0.502clk_mainlock_rst_bar16.667lockclk_main0.317locklock_rst_bar3P82.PADP82.ITiopi1.337locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X14Y27.D6net32.216lock_invSLICE_X14Y27.DTilo0.205lock_rst_bar_1PWR_5_o_reset_gen.cont_200MHz[15]_equal_1_o_inv3_SW0SLICE_X14Y27.C4net10.447N88SLICE_X14Y27.CTilo0.205lock_rst_bar_1lock_rst_bar_rstpotSLICE_X14Y22.AXnet10.720lock_rst_bar_rstpotSLICE_X14Y22.CLKTdick0.136lock_rst_barlock_rst_bar1.8833.3835.266clk_u_proc_BUFG35.864.2clk_mainlock_rst_bar4P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y22.CLKnet2260.611clk_u_proc_BUFG-2.4561.954-0.502Paths for end point lock_rst_bar_1 (SLICE_X14Y27.C4), 1 path +11.307locklock_rst_bar_1-0.497clk_mainlock_rst_bar_116.667lockclk_main0.317locklock_rst_bar_13P82.PADP82.ITiopi1.337locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X14Y27.D6net32.216lock_invSLICE_X14Y27.DTilo0.205lock_rst_bar_1PWR_5_o_reset_gen.cont_200MHz[15]_equal_1_o_inv3_SW0SLICE_X14Y27.C4net10.447N88SLICE_X14Y27.CLKTas0.341lock_rst_bar_1lock_rst_bar_rstpotlock_rst_bar_11.8832.6634.546clk_u_proc_BUFG41.458.6clk_mainlock_rst_bar_14P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y27.CLKnet2260.616clk_u_proc_BUFG-2.4561.959-0.497Paths for end point pps_rst (SLICE_X12Y26.SR), 1 path +11.817lockpps_rst-0.500clk_mainpps_rst16.667lockclk_main0.317lockpps_rst1P82.PADP82.ITiopi1.337locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X12Y26.SRnet32.257lock_invSLICE_X12Y26.CLKTsrck0.439pps_rstpps_rst1.7762.2574.033clk_u_proc_BUFG44.056.0clk_mainpps_rst4P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X12Y26.CLKnet2260.613clk_u_proc_BUFG-2.4561.956-0.500Hold Paths: COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +Paths for end point pps_r_0 (SLICE_X14Y26.SR), 1 path +1.602lockpps_r_00.070clk_mainpps_r<1>0.000lockclk_main0.317lockpps_r_01P82.PADP82.ITiopi0.773locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X14Y26.SRnet31.191lock_invSLICE_X14Y26.CLKTcksr0.025pps_r<1>pps_r_00.7981.1911.989clk_u_proc_BUFG40.159.9clk_mainpps_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y26.CLKnet2260.754clk_u_proc_BUFG-1.5821.6520.070Paths for end point pps_r_1 (SLICE_X14Y26.SR), 1 path +1.623lockpps_r_10.070clk_mainpps_r<1>0.000lockclk_main0.317lockpps_r_11P82.PADP82.ITiopi0.773locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X14Y26.SRnet31.191lock_invSLICE_X14Y26.CLKTcksr0.046pps_r<1>pps_r_10.8191.1912.010clk_u_proc_BUFG40.759.3clk_mainpps_r_14P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y26.CLKnet2260.754clk_u_proc_BUFG-1.5821.6520.070Paths for end point pps_rst (SLICE_X12Y26.SR), 1 path +1.859lockpps_rst0.069clk_mainpps_rst0.000lockclk_main0.317lockpps_rst1P82.PADP82.ITiopi0.773locklocklock_IBUFProtoComp54.IINVProtoComp54.IMUXSLICE_X12Y26.SRnet31.445lock_invSLICE_X12Y26.CLKTcksr0.027pps_rstpps_rst0.8001.4452.245clk_u_proc_BUFG35.664.4clk_mainpps_rst4P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X12Y26.CLKnet2260.753clk_u_proc_BUFG-1.5821.6510.069COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.685Paths for end point pps_r_0 (SLICE_X14Y26.AX), 1 path +11.982ppspps_r_0-0.499clk_mainpps_r<1>16.667ppsclk_main0.317ppspps_r_01P78.PADP78.ITiopi1.310ppsppspps_IBUFProtoComp52.IMUX.2SLICE_X14Y26.AXnet12.423pps_IBUFSLICE_X14Y26.CLKTdick0.136pps_r<1>pps_r_01.4462.4233.869clk_u_proc_BUFG37.462.6clk_mainpps_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y26.CLKnet2260.614clk_u_proc_BUFG-2.4561.957-0.499Hold Paths: COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" + "RISING"; +Paths for end point pps_r_0 (SLICE_X14Y26.AX), 1 path +1.955ppspps_r_00.070clk_mainpps_r<1>0.000ppsclk_main0.317ppspps_r_01P78.PADP78.ITiopi0.763ppsppspps_IBUFProtoComp52.IMUX.2SLICE_X14Y26.AXnet11.531pps_IBUFSLICE_X14Y26.CLKTckdi0.048pps_r<1>pps_r_00.8111.5312.342clk_u_proc_BUFG34.665.4clk_mainpps_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X14Y26.CLKnet2260.754clk_u_proc_BUFG-1.5821.6520.070COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";10000104.828Paths for end point nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (SLICE_X16Y47.B5), 1 path +795.172clk_acq_ch1nb_mem_cont/nibble_pack_ch1/clk_acq_r_0-0.490clk_mainnb_mem_cont/nibble_pack_ch1/clk_acq_r<2>800.000clk_acq_ch1clk_main0.317clk_acq_ch1nb_mem_cont/nibble_pack_ch1/clk_acq_r_02P111.PADP111.ITiopi1.310clk_acq_ch1clk_acq_ch1clk_acq_ch1_IBUFProtoComp52.IMUX.25SLICE_X16Y47.B5net12.557clk_acq_ch1_IBUFSLICE_X16Y47.CLKTas0.154nb_mem_cont/nibble_pack_ch1/clk_acq_r<2>nb_mem_cont/nibble_pack_ch1/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch1/clk_acq_r_01.4642.5574.021clk_u_proc_BUFG36.463.6clk_mainnb_mem_cont/nibble_pack_ch1/clk_acq_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y47.CLKnet2260.623clk_u_proc_BUFG-2.4561.966-0.490Hold Paths: COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" + "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch1/clk_acq_r_0 (SLICE_X16Y47.B5), 1 path +2.085clk_acq_ch1nb_mem_cont/nibble_pack_ch1/clk_acq_r_00.079clk_mainnb_mem_cont/nibble_pack_ch1/clk_acq_r<2>0.000clk_acq_ch1clk_main0.317clk_acq_ch1nb_mem_cont/nibble_pack_ch1/clk_acq_r_02P111.PADP111.ITiopi0.763clk_acq_ch1clk_acq_ch1clk_acq_ch1_IBUFProtoComp52.IMUX.25SLICE_X16Y47.B5net11.587clk_acq_ch1_IBUFSLICE_X16Y47.CLKTah0.131nb_mem_cont/nibble_pack_ch1/clk_acq_r<2>nb_mem_cont/nibble_pack_ch1/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch1/clk_acq_r_00.8941.5872.481clk_u_proc_BUFG36.064.0clk_mainnb_mem_cont/nibble_pack_ch1/clk_acq_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y47.CLKnet2260.763clk_u_proc_BUFG-1.5821.6610.079COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.021Paths for end point nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (SLICE_X16Y46.A3), 1 path +11.646clk_acq_ch2nb_mem_cont/nibble_pack_ch2/clk_acq_r_0-0.490clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r<1>16.667clk_acq_ch2clk_main0.317clk_acq_ch2nb_mem_cont/nibble_pack_ch2/clk_acq_r_02P117.PADP117.ITiopi1.310clk_acq_ch2clk_acq_ch2clk_acq_ch2_IBUFProtoComp52.IMUX.26SLICE_X16Y46.A3net12.750clk_acq_ch2_IBUFSLICE_X16Y46.CLKTas0.154nb_mem_cont/nibble_pack_ch3/clk_acq_r<1>nb_mem_cont/nibble_pack_ch2/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch2/clk_acq_r_01.4642.7504.214clk_u_proc_BUFG34.765.3clk_mainnb_mem_cont/nibble_pack_ch2/clk_acq_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y46.CLKnet2260.623clk_u_proc_BUFG-2.4561.966-0.490Hold Paths: COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch2/clk_acq_r_0 (SLICE_X16Y46.A3), 1 path +2.226clk_acq_ch2nb_mem_cont/nibble_pack_ch2/clk_acq_r_00.079clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r<1>0.000clk_acq_ch2clk_main0.317clk_acq_ch2nb_mem_cont/nibble_pack_ch2/clk_acq_r_02P117.PADP117.ITiopi0.763clk_acq_ch2clk_acq_ch2clk_acq_ch2_IBUFProtoComp52.IMUX.26SLICE_X16Y46.A3net11.728clk_acq_ch2_IBUFSLICE_X16Y46.CLKTah0.131nb_mem_cont/nibble_pack_ch3/clk_acq_r<1>nb_mem_cont/nibble_pack_ch2/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch2/clk_acq_r_00.8941.7282.622clk_u_proc_BUFG34.165.9clk_mainnb_mem_cont/nibble_pack_ch2/clk_acq_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y46.CLKnet2260.763clk_u_proc_BUFG-1.5821.6610.079COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000104.711Paths for end point nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (SLICE_X16Y46.C3), 1 path +11.956clk_acq_ch3nb_mem_cont/nibble_pack_ch3/clk_acq_r_0-0.490clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r<1>16.667clk_acq_ch3clk_main0.317clk_acq_ch3nb_mem_cont/nibble_pack_ch3/clk_acq_r_02P123.PADP123.ITiopi1.310clk_acq_ch3clk_acq_ch3clk_acq_ch3_IBUFProtoComp52.IMUX.27SLICE_X16Y46.C3net12.440clk_acq_ch3_IBUFSLICE_X16Y46.CLKTas0.154nb_mem_cont/nibble_pack_ch3/clk_acq_r<1>nb_mem_cont/nibble_pack_ch3/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch3/clk_acq_r_01.4642.4403.904clk_u_proc_BUFG37.562.5clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y46.CLKnet2260.623clk_u_proc_BUFG-2.4561.966-0.490Hold Paths: COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch3/clk_acq_r_0 (SLICE_X16Y46.C3), 1 path +2.027clk_acq_ch3nb_mem_cont/nibble_pack_ch3/clk_acq_r_00.079clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r<1>0.000clk_acq_ch3clk_main0.317clk_acq_ch3nb_mem_cont/nibble_pack_ch3/clk_acq_r_02P123.PADP123.ITiopi0.763clk_acq_ch3clk_acq_ch3clk_acq_ch3_IBUFProtoComp52.IMUX.27SLICE_X16Y46.C3net11.529clk_acq_ch3_IBUFSLICE_X16Y46.CLKTah0.131nb_mem_cont/nibble_pack_ch3/clk_acq_r<1>nb_mem_cont/nibble_pack_ch3/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch3/clk_acq_r_00.8941.5292.423clk_u_proc_BUFG36.963.1clk_mainnb_mem_cont/nibble_pack_ch3/clk_acq_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y46.CLKnet2260.763clk_u_proc_BUFG-1.5821.6610.079COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.877Paths for end point nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (SLICE_X15Y35.A1), 1 path +10.790clk_acq_ch4nb_mem_cont/nibble_pack_ch4/clk_acq_r_0-0.494clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r<1>16.667clk_acq_ch4clk_main0.317clk_acq_ch4nb_mem_cont/nibble_pack_ch4/clk_acq_r_02P132.PADP132.ITiopi1.310clk_acq_ch4clk_acq_ch4clk_acq_ch4_IBUFProtoComp52.IMUX.28SLICE_X15Y35.A1net13.529clk_acq_ch4_IBUFSLICE_X15Y35.CLKTas0.227nb_mem_cont/nibble_pack_ch5/clk_acq_r<1>nb_mem_cont/nibble_pack_ch4/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch4/clk_acq_r_01.5373.5295.066clk_u_proc_BUFG30.369.7clk_mainnb_mem_cont/nibble_pack_ch4/clk_acq_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y35.CLKnet2260.619clk_u_proc_BUFG-2.4561.962-0.494Hold Paths: COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch4/clk_acq_r_0 (SLICE_X15Y35.A1), 1 path +2.755clk_acq_ch4nb_mem_cont/nibble_pack_ch4/clk_acq_r_00.075clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r<1>0.000clk_acq_ch4clk_main0.317clk_acq_ch4nb_mem_cont/nibble_pack_ch4/clk_acq_r_02P132.PADP132.ITiopi0.763clk_acq_ch4clk_acq_ch4clk_acq_ch4_IBUFProtoComp52.IMUX.28SLICE_X15Y35.A1net12.229clk_acq_ch4_IBUFSLICE_X15Y35.CLKTah0.155nb_mem_cont/nibble_pack_ch5/clk_acq_r<1>nb_mem_cont/nibble_pack_ch4/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch4/clk_acq_r_00.9182.2293.147clk_u_proc_BUFG29.270.8clk_mainnb_mem_cont/nibble_pack_ch4/clk_acq_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y35.CLKnet2260.759clk_u_proc_BUFG-1.5821.6570.075COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";10000105.861Paths for end point nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (SLICE_X15Y35.C3), 1 path +10.806clk_acq_ch5nb_mem_cont/nibble_pack_ch5/clk_acq_r_0-0.494clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r<1>16.667clk_acq_ch5clk_main0.317clk_acq_ch5nb_mem_cont/nibble_pack_ch5/clk_acq_r_02P57.PADP57.ITiopi1.310clk_acq_ch5clk_acq_ch5clk_acq_ch5_IBUFProtoComp52.IMUX.29SLICE_X15Y35.C3net13.513clk_acq_ch5_IBUFSLICE_X15Y35.CLKTas0.227nb_mem_cont/nibble_pack_ch5/clk_acq_r<1>nb_mem_cont/nibble_pack_ch5/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch5/clk_acq_r_01.5373.5135.050clk_u_proc_BUFG30.469.6clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y35.CLKnet2260.619clk_u_proc_BUFG-2.4561.962-0.494Hold Paths: COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP + "clk_main" "RISING"; +Paths for end point nb_mem_cont/nibble_pack_ch5/clk_acq_r_0 (SLICE_X15Y35.C3), 1 path +2.688clk_acq_ch5nb_mem_cont/nibble_pack_ch5/clk_acq_r_00.075clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r<1>0.000clk_acq_ch5clk_main0.317clk_acq_ch5nb_mem_cont/nibble_pack_ch5/clk_acq_r_02P57.PADP57.ITiopi0.763clk_acq_ch5clk_acq_ch5clk_acq_ch5_IBUFProtoComp52.IMUX.29SLICE_X15Y35.C3net12.162clk_acq_ch5_IBUFSLICE_X15Y35.CLKTah0.155nb_mem_cont/nibble_pack_ch5/clk_acq_r<1>nb_mem_cont/nibble_pack_ch5/clk_acq_r_0_rstpotnb_mem_cont/nibble_pack_ch5/clk_acq_r_00.9182.1623.080clk_u_proc_BUFG29.870.2clk_mainnb_mem_cont/nibble_pack_ch5/clk_acq_r_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X15Y35.CLKnet2260.759clk_u_proc_BUFG-1.5821.6570.075COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING";10000107.179Paths for end point interfaz_spi/controlador_spi_esclavo/MOSIr_0 (SLICE_X16Y11.AX), 1 path +4.821MOSIinterfaz_spi/controlador_spi_esclavo/MOSIr_0-0.434clk_maininterfaz_spi/controlador_spi_esclavo/MOSIr<1>12.000MOSIclk_main0.317MOSIinterfaz_spi/controlador_spi_esclavo/MOSIr_01P99.PADP99.ITiopi1.310MOSIMOSIMOSI_IBUFProtoComp52.IMUX.3SLICE_X16Y11.AXnet15.032MOSI_IBUFSLICE_X16Y11.CLKTdick0.086interfaz_spi/controlador_spi_esclavo/MOSIr<1>interfaz_spi/controlador_spi_esclavo/MOSIr_01.3965.0326.428clk_u_proc_BUFG21.778.3clk_maininterfaz_spi/controlador_spi_esclavo/MOSIr_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y11.CLKnet2260.679clk_u_proc_BUFG-2.4562.022-0.434Hold Paths: COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_esclavo/MOSIr_0 (SLICE_X16Y11.AX), 1 path +3.457MOSIinterfaz_spi/controlador_spi_esclavo/MOSIr_00.135clk_maininterfaz_spi/controlador_spi_esclavo/MOSIr<1>0.000MOSIclk_main0.317MOSIinterfaz_spi/controlador_spi_esclavo/MOSIr_01P99.PADP99.ITiopi0.763MOSIMOSIMOSI_IBUFProtoComp52.IMUX.3SLICE_X16Y11.AXnet13.105MOSI_IBUFSLICE_X16Y11.CLKTckdi0.041interfaz_spi/controlador_spi_esclavo/MOSIr<1>interfaz_spi/controlador_spi_esclavo/MOSIr_00.8043.1053.909clk_u_proc_BUFG20.679.4clk_maininterfaz_spi/controlador_spi_esclavo/MOSIr_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X16Y11.CLKnet2260.819clk_u_proc_BUFG-1.5821.7170.135COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING";10000105.534Paths for end point interfaz_spi/controlador_spi_esclavo/SCKr_0 (SLICE_X20Y8.D4), 1 path +19.466SCKinterfaz_spi/controlador_spi_esclavo/SCKr_0-0.436clk_maininterfaz_spi/controlador_spi_esclavo/SCKr<1>25.000SCKclk_main0.317SCKinterfaz_spi/controlador_spi_esclavo/SCKr_02P95.PADP95.ITiopi1.310SCKSCKSCK_IBUFProtoComp52.IMUX.1SLICE_X20Y8.D4net13.317SCK_IBUFSLICE_X20Y8.CLKTas0.154interfaz_spi/controlador_spi_esclavo/SCKr<1>interfaz_spi/controlador_spi_esclavo/SCKr_0_glue_setinterfaz_spi/controlador_spi_esclavo/SCKr_01.4643.3174.781clk_u_proc_BUFG30.669.4clk_maininterfaz_spi/controlador_spi_esclavo/SCKr_04P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X20Y8.CLKnet2260.677clk_u_proc_BUFG-2.4562.020-0.436Hold Paths: COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_esclavo/SCKr_0 (SLICE_X20Y8.D4), 1 path +2.480SCKinterfaz_spi/controlador_spi_esclavo/SCKr_00.133clk_maininterfaz_spi/controlador_spi_esclavo/SCKr<1>0.000SCKclk_main0.317SCKinterfaz_spi/controlador_spi_esclavo/SCKr_02P95.PADP95.ITiopi0.763SCKSCKSCK_IBUFProtoComp52.IMUX.1SLICE_X20Y8.D4net12.036SCK_IBUFSLICE_X20Y8.CLKTah0.131interfaz_spi/controlador_spi_esclavo/SCKr<1>interfaz_spi/controlador_spi_esclavo/SCKr_0_glue_setinterfaz_spi/controlador_spi_esclavo/SCKr_00.8942.0362.930clk_u_proc_BUFG30.569.5clk_maininterfaz_spi/controlador_spi_esclavo/SCKr_04P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X20Y8.CLKnet2260.817clk_u_proc_BUFG-1.5821.7150.133COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING";10000106.292Paths for end point interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (SLICE_X20Y7.AI), 1 path +5.708CSinterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1-0.436clk_maininterfaz_spi/controlador_spi_esclavo/CSr<1>12.000CSclk_main0.317CSinterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_11P97.PADP97.ITiopi1.310CSCSCS_IBUFProtoComp52.IMUXSLICE_X20Y7.AInet14.191CS_IBUFSLICE_X20Y7.CLKTds0.038interfaz_spi/controlador_spi_esclavo/CSr<1>interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_11.3484.1915.539clk_u_proc_BUFG24.375.7clk_maininterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_14P51.PADP51.ITiopi1.126clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.278clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.105SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.562clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-3.884clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.503clk_u_procBUFGMUX_X2Y4.OTgi0o0.197clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X20Y7.CLKnet2260.677clk_u_proc_BUFG-2.4562.020-0.436Hold Paths: COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING"; +Paths for end point interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_1 (SLICE_X20Y7.AI), 1 path +2.894CSinterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_10.133clk_maininterfaz_spi/controlador_spi_esclavo/CSr<1>0.000CSclk_main0.317CSinterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_11P97.PADP97.ITiopi0.763CSCSCS_IBUFProtoComp52.IMUXSLICE_X20Y7.AInet12.551CS_IBUFSLICE_X20Y7.CLKTdh0.030interfaz_spi/controlador_spi_esclavo/CSr<1>interfaz_spi/controlador_spi_esclavo/Mshreg_CSr_10.7932.5513.344clk_u_proc_BUFG23.776.3clk_maininterfaz_spi/controlador_spi_esclavo/Mshreg_CSr_14P51.PADP51.ITiopi0.887clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.245clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.130SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.391clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.662clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.262clk_u_procBUFGMUX_X2Y4.OTgi0o0.063clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X20Y7.CLKnet2260.817clk_u_proc_BUFG-1.5821.7150.133COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";90000108.269Paths for end point we_bar (P43.PAD), 9 paths +8.398nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25we_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd428.283nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd254P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25we_bar3SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.CQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.D1net51.741nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.DMUXTilo0.251lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0SLICE_X2Y23.C4net10.374N22SLICE_X2Y23.CTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet12.884we_bar_OBUFP43.PADTioop2.381we_barwe_bar_OBUFwe_bar3.2844.9998.28339.660.48.776nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42we_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd427.905nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd424P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42we_bar3SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.D3net511.363nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.DMUXTilo0.251lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0SLICE_X2Y23.C4net10.374N22SLICE_X2Y23.CTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet12.884we_bar_OBUFP43.PADTioop2.381we_barwe_bar_OBUFwe_bar3.2844.6217.90541.558.58.868nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38we_bar-0.258clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd367.740nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd384P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y15.CLKnet2261.179clk_u_proc_BUFG-3.0882.830-0.258nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38we_bar3SLICE_X6Y15.CLKclk_u_proc_BUFGSLICE_X6Y15.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.D4net51.190nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.DMUXTilo0.251lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0SLICE_X2Y23.C4net10.374N22SLICE_X2Y23.CTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet12.884we_bar_OBUFP43.PADTioop2.381we_barwe_bar_OBUFwe_bar3.2924.4487.74042.557.5Fastest Paths: COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point we_bar (P43.PAD), 9 paths +3.484nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4we_bar-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44.196nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X1Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4we_bar3SLICE_X1Y25.CLKclk_u_proc_BUFGSLICE_X1Y25.CQTcko0.198nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.D5net40.352nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.DMUXTilo0.183lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>_SW0SLICE_X2Y23.C4net10.115N22SLICE_X2Y23.CTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet11.810we_bar_OBUFP43.PADTioop1.396we_barwe_bar_OBUFwe_bar1.9192.2774.19645.754.33.438nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29we_bar-0.396clk_mainnb_mem_cont/ram_control/addr_erase_aux_int<5>4.151nb_mem_cont/ram_control/addr_erase_aux_int<5>we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd294P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X5Y20.CLKnet2260.494clk_u_proc_BUFG-1.6981.302-0.396nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29we_bar2SLICE_X5Y20.CLKclk_u_proc_BUFGSLICE_X5Y20.AQTcko0.198nb_mem_cont/ram_control/addr_erase_aux_int<5>nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.C5net70.605nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.CTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet11.810we_bar_OBUFP43.PADTioop1.396we_barwe_bar_OBUFwe_bar1.7362.4154.15141.858.23.177nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1we_bar-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd13.889nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1we_bar16.667clk_mainwe_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1we_bar2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X2Y23.C6net190.307nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X2Y23.CTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<2>P43.Onet11.810we_bar_OBUFP43.PADTioop1.396we_barwe_bar_OBUFwe_bar1.7722.1173.88945.654.4COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";50000108.621Paths for end point ub_bar (P6.PAD), 5 paths +8.046nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25ub_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd428.635nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd254P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25ub_bar2SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.CQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.D1net51.741nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet23.861lb_bar_OBUFP6.PADTioop2.381ub_barub_bar_OBUFub_bar3.0335.6028.63535.164.98.424nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42ub_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd428.257nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd424P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42ub_bar2SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.D3net511.363nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet23.861lb_bar_OBUFP6.PADTioop2.381ub_barub_bar_OBUFub_bar3.0335.2248.25736.763.38.516nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38ub_bar-0.258clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd368.092nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd384P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y15.CLKnet2261.179clk_u_proc_BUFG-3.0882.830-0.258nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38ub_bar2SLICE_X6Y15.CLKclk_u_proc_BUFGSLICE_X6Y15.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.D4net51.190nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet23.861lb_bar_OBUFP6.PADTioop2.381ub_barub_bar_OBUFub_bar3.0415.0518.09237.662.4Fastest Paths: COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point ub_bar (P6.PAD), 5 paths +4.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38ub_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd364.882nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd384P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y15.CLKnet2260.559clk_u_proc_BUFG-1.6981.367-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38ub_bar2SLICE_X6Y15.CLKclk_u_proc_BUFGSLICE_X6Y15.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.D4net50.701nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet22.405lb_bar_OBUFP6.PADTioop1.396ub_barub_bar_OBUFub_bar1.7763.1064.88236.463.64.224nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29ub_bar-0.396clk_mainnb_mem_cont/ram_control/addr_erase_aux_int<5>4.937nb_mem_cont/ram_control/addr_erase_aux_int<5>ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd294P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X5Y20.CLKnet2260.494clk_u_proc_BUFG-1.6981.302-0.396nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29ub_bar2SLICE_X5Y20.CLKclk_u_proc_BUFGSLICE_X5Y20.AQTcko0.198nb_mem_cont/ram_control/addr_erase_aux_int<5>nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.D2net70.796nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet22.405lb_bar_OBUFP6.PADTioop1.396ub_barub_bar_OBUFub_bar1.7363.2014.93735.264.83.781nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4ub_bar-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44.493nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4ub_bar16.667clk_mainub_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X1Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4ub_bar2SLICE_X1Y25.CLKclk_u_proc_BUFGSLICE_X1Y25.CQTcko0.198nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.D5net40.352nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P6.Onet22.405lb_bar_OBUFP6.PADTioop1.396ub_barub_bar_OBUFub_bar1.7362.7574.49338.661.4COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";50000108.246Paths for end point lb_bar (P7.PAD), 5 paths +8.421nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25lb_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd428.260nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd254P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25lb_bar2SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.CQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.D1net51.741nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd25SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet23.486lb_bar_OBUFP7.PADTioop2.381lb_barlb_bar_OBUFlb_bar3.0335.2278.26036.763.38.799nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42lb_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd427.882nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd424P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X8Y28.CLKnet2261.106clk_u_proc_BUFG-3.0882.757-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42lb_bar2SLICE_X8Y28.CLKclk_u_proc_BUFGSLICE_X8Y28.DQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.D3net511.363nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd42SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet23.486lb_bar_OBUFP7.PADTioop2.381lb_barlb_bar_OBUFlb_bar3.0334.8497.88238.561.58.891nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38lb_bar-0.258clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd367.717nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd384P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y15.CLKnet2261.179clk_u_proc_BUFG-3.0882.830-0.258nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38lb_bar2SLICE_X6Y15.CLKclk_u_proc_BUFGSLICE_X6Y15.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.D4net51.190nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.DTilo0.205lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet23.486lb_bar_OBUFP7.PADTioop2.381lb_barlb_bar_OBUFlb_bar3.0414.6767.71739.460.6Fastest Paths: COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point lb_bar (P7.PAD), 5 paths +3.987nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38lb_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd364.635nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd384P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y15.CLKnet2260.559clk_u_proc_BUFG-1.6981.367-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38lb_bar2SLICE_X6Y15.CLKclk_u_proc_BUFGSLICE_X6Y15.CMUXTshcko0.238nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd36nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.D4net50.701nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd38SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet22.158lb_bar_OBUFP7.PADTioop1.396lb_barlb_bar_OBUFlb_bar1.7762.8594.63538.361.73.977nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29lb_bar-0.396clk_mainnb_mem_cont/ram_control/addr_erase_aux_int<5>4.690nb_mem_cont/ram_control/addr_erase_aux_int<5>lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd294P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X5Y20.CLKnet2260.494clk_u_proc_BUFG-1.6981.302-0.396nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29lb_bar2SLICE_X5Y20.CLKclk_u_proc_BUFGSLICE_X5Y20.AQTcko0.198nb_mem_cont/ram_control/addr_erase_aux_int<5>nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.D2net70.796nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd29SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet22.158lb_bar_OBUFP7.PADTioop1.396lb_barlb_bar_OBUFlb_bar1.7362.9544.69037.063.03.534nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4lb_bar-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44.246nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4lb_bar16.667clk_mainlb_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd44P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X1Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4lb_bar2SLICE_X1Y25.CLKclk_u_proc_BUFGSLICE_X1Y25.CQTcko0.198nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.D5net40.352nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd4SLICE_X2Y23.DTilo0.142lb_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state__n0467<0>1P7.Onet22.158lb_bar_OBUFP7.PADTioop1.396lb_barlb_bar_OBUFlb_bar1.7362.5104.24640.959.1COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";40000108.489Paths for end point oe_ram_bar (P5.PAD), 4 paths +8.178nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2oe_ram_bar-0.251clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd278.423nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd24P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X2Y14.CLKnet2261.186clk_u_proc_BUFG-3.0882.837-0.251nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2oe_ram_bar2SLICE_X2Y14.CLKclk_u_proc_BUFGSLICE_X2Y14.CMUXTshcko0.455nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd27nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X0Y29.D2net82.148nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd2SLICE_X0Y29.DTilo0.203oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet13.236oe_ram_bar_OBUFP5.PADTioop2.381oe_ram_baroe_ram_bar_OBUFoe_ram_bar3.0395.3848.42336.163.98.403nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar-0.258clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd328.205nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd324P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X4Y14.CLKnet2261.179clk_u_proc_BUFG-3.0882.830-0.258nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar2SLICE_X4Y14.CLKclk_u_proc_BUFGSLICE_X4Y14.AQTcko0.447nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32SLICE_X0Y29.D4net51.938nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32SLICE_X0Y29.DTilo0.203oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet13.236oe_ram_bar_OBUFP5.PADTioop2.381oe_ram_baroe_ram_bar_OBUFoe_ram_bar3.0315.1748.20536.963.18.917nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar-0.319clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd37.752nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2261.118clk_u_proc_BUFG-3.0882.769-0.319nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.408nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X0Y29.D5net71.524nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X0Y29.DTilo0.203oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet13.236oe_ram_bar_OBUFP5.PADTioop2.381oe_ram_baroe_ram_bar_OBUFoe_ram_bar2.9924.7607.75238.661.4Fastest Paths: COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main"; +Paths for end point oe_ram_bar (P5.PAD), 4 paths +4.313nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar-0.331clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd324.961nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd324P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X4Y14.CLKnet2260.559clk_u_proc_BUFG-1.6981.367-0.331nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32oe_ram_bar2SLICE_X4Y14.CLKclk_u_proc_BUFGSLICE_X4Y14.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32SLICE_X0Y29.D4net51.165nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd32SLICE_X0Y29.DTilo0.156oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet12.010oe_ram_bar_OBUFP5.PADTioop1.396oe_ram_baroe_ram_bar_OBUFoe_ram_bar1.7863.1754.96136.064.03.961nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar-0.392clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34.670nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd34P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X6Y17.CLKnet2260.498clk_u_proc_BUFG-1.6981.306-0.392nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3oe_ram_bar2SLICE_X6Y17.CLKclk_u_proc_BUFGSLICE_X6Y17.DQTcko0.200nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X0Y29.D5net70.908nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd3SLICE_X0Y29.DTilo0.156oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet12.010oe_ram_bar_OBUFP5.PADTioop1.396oe_ram_baroe_ram_bar_OBUFoe_ram_bar1.7522.9184.67037.562.53.521nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1oe_ram_bar-0.395clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14.233nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1oe_ram_bar16.667clk_mainoe_ram_bar0.317clk_mainnb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd14P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X0Y25.CLKnet2260.495clk_u_proc_BUFG-1.6981.303-0.395nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1oe_ram_bar2SLICE_X0Y25.CLKclk_u_proc_BUFGSLICE_X0Y25.AQTcko0.234nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X0Y29.D3net190.437nb_mem_cont/ram_control/ram_contr_cur_state_FSM_FFd1SLICE_X0Y29.DTilo0.156oe_ram_bar_OBUFnb_mem_cont/ram_control/ram_contr_cur_state_oe_ram_bar1P5.Onet12.010oe_ram_bar_OBUFP5.PADTioop1.396oe_ram_baroe_ram_bar_OBUFoe_ram_bar1.7862.4474.23342.257.8COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main";10000107.518Paths for end point MISO (P98.PAD), 1 path +2.482interfaz_spi/controlador_spi_esclavo/buffer_out_7MISO-0.278clk_maininterfaz_spi/controlador_spi_esclavo/buffer_out<7>7.479interfaz_spi/controlador_spi_esclavo/buffer_out<7>MISO10.000clk_mainMISO0.317clk_maininterfaz_spi/controlador_spi_esclavo/buffer_out_74P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.428clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.646clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-4.718clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.577clk_u_procBUFGMUX_X2Y4.OTgi0o0.209clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y8.CLKnet2261.159clk_u_proc_BUFG-3.0882.810-0.278interfaz_spi/controlador_spi_esclavo/buffer_out_7MISO1SLICE_X9Y8.CLKclk_u_proc_BUFGSLICE_X9Y8.CQTcko0.391interfaz_spi/controlador_spi_esclavo/buffer_out<7>interfaz_spi/controlador_spi_esclavo/buffer_out_7P98.Onet14.707interfaz_spi/controlador_spi_esclavo/buffer_out<7>P98.PADTioop2.381MISOMISO_OBUFMISO2.7724.7077.47937.162.9Fastest Paths: COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main"; +Paths for end point MISO (P98.PAD), 1 path +3.912interfaz_spi/controlador_spi_esclavo/buffer_out_7MISO-0.351clk_maininterfaz_spi/controlador_spi_esclavo/buffer_out<7>4.580interfaz_spi/controlador_spi_esclavo/buffer_out<7>MISO10.000clk_mainMISO0.317clk_maininterfaz_spi/controlador_spi_esclavo/buffer_out_74P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X3Y0.Inet20.235clk_main_ioBUFIO2_X3Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_1SP6_BUFIO_INSERT_ML_BUFIO2_1DCM_X0Y0.CLKINnet10.342clk_mang/DCM_SP_inst_int_ML_NEW_DIVCLKDCM_X0Y0.CLKFXTdmcko_CLKFX-2.642clk_mang/DCM_SP_inst_intclk_mang/DCM_SP_inst_intBUFGMUX_X2Y4.I0net10.231clk_u_procBUFGMUX_X2Y4.OTgi0o0.059clk_u_proc_BUFGclk_u_proc_BUFGSLICE_X9Y8.CLKnet2260.539clk_u_proc_BUFG-1.6981.347-0.351interfaz_spi/controlador_spi_esclavo/buffer_out_7MISO1SLICE_X9Y8.CLKclk_u_proc_BUFGSLICE_X9Y8.CQTcko0.198interfaz_spi/controlador_spi_esclavo/buffer_out<7>interfaz_spi/controlador_spi_esclavo/buffer_out_7P98.Onet12.986interfaz_spi/controlador_spi_esclavo/buffer_out<7>P98.PADTioop1.396MISOMISO_OBUFMISO1.5942.9864.58034.865.2COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main";200001035.651Paths for end point clk_to_acq (P80.PAD), 2 paths +4.349clk_mang/ODDR2_instclk_to_acq0.165clk_mainclk_to_acq_OBUF3.336clk_to_acq_OBUFclk_to_acq40.000clk_mainclk_to_acq0.900clk_mainclk_mang/ODDR2_inst4P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X1Y0.Inet20.428clk_main_ioBUFIO2_X1Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_0SP6_BUFIO_INSERT_ML_BUFIO2_0DCM_X0Y1.CLKINnet10.646clk_mang/DCM_SP_inst_ML_NEW_DIVCLKDCM_X0Y1.CLKFXTdmcko_CLKFX-4.659clk_mang/DCM_SP_instclk_mang/DCM_SP_instBUFGMUX_X2Y2.I0net10.577clk_mang/c_16MHzBUFGMUX_X2Y2.OTgi0o0.209clk_mang/c_16MHz_BUFGclk_mang/c_16MHz_BUFGOLOGIC_X12Y22.CLK1net21.543clk_mang/c_16MHz_BUFG-3.0293.1940.165clk_mang/ODDR2_instclk_to_acq1OLOGIC_X12Y22.CLK1clk_mang/c_16MHz_BUFGOLOGIC_X12Y22.OQTockq0.722clk_to_acq_OBUFclk_mang/ODDR2_instP80.Onet10.233clk_to_acq_OBUFP80.PADTioop2.381clk_to_acqclk_to_acq_OBUFclk_to_acq3.1030.2333.33693.07.035.575clk_mang/ODDR2_instclk_to_acq0.169clk_mainclk_to_acq_OBUF3.356clk_to_acq_OBUFclk_to_acq40.000clk_mainclk_to_acq0.900clk_mainclk_mang/ODDR2_inst4P51.PADP51.ITiopi1.310clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X1Y0.Inet20.428clk_main_ioBUFIO2_X1Y0.DIVCLKTbufcko_DIVCLK0.111SP6_BUFIO_INSERT_ML_BUFIO2_0SP6_BUFIO_INSERT_ML_BUFIO2_0DCM_X0Y1.CLKINnet10.646clk_mang/DCM_SP_inst_ML_NEW_DIVCLKDCM_X0Y1.CLKFXTdmcko_CLKFX-4.659clk_mang/DCM_SP_instclk_mang/DCM_SP_instBUFGMUX_X2Y2.I0net10.577clk_mang/c_16MHzBUFGMUX_X2Y2.OTgi0o0.209clk_mang/c_16MHz_BUFGclk_mang/c_16MHz_BUFGOLOGIC_X12Y22.CLK0net21.547clk_mang/c_16MHz_BUFG-3.0293.1980.169clk_mang/ODDR2_instclk_to_acq1OLOGIC_X12Y22.CLK0clk_mang/c_16MHz_BUFGOLOGIC_X12Y22.OQTockq0.742clk_to_acq_OBUFclk_mang/ODDR2_instP80.Onet10.233clk_to_acq_OBUFP80.PADTioop2.381clk_to_acqclk_to_acq_OBUFclk_to_acq3.1230.2333.35693.16.9Fastest Paths: COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main"; +Paths for end point clk_to_acq (P80.PAD), 2 paths +32.071clk_mang/ODDR2_instclk_to_acq-0.290clk_mainclk_to_acq_OBUF2.011clk_to_acq_OBUFclk_to_acq40.000clk_mainclk_to_acq0.900clk_mainclk_mang/ODDR2_inst4P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X1Y0.Inet20.235clk_main_ioBUFIO2_X1Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_0SP6_BUFIO_INSERT_ML_BUFIO2_0DCM_X0Y1.CLKINnet10.342clk_mang/DCM_SP_inst_ML_NEW_DIVCLKDCM_X0Y1.CLKFXTdmcko_CLKFX-2.650clk_mang/DCM_SP_instclk_mang/DCM_SP_instBUFGMUX_X2Y2.I0net10.231clk_mang/c_16MHzBUFGMUX_X2Y2.OTgi0o0.059clk_mang/c_16MHz_BUFGclk_mang/c_16MHz_BUFGOLOGIC_X12Y22.CLK1net20.608clk_mang/c_16MHz_BUFG-1.7061.416-0.290clk_mang/ODDR2_instclk_to_acq1OLOGIC_X12Y22.CLK1clk_mang/c_16MHz_BUFGOLOGIC_X12Y22.OQTockq0.425clk_to_acq_OBUFclk_mang/ODDR2_instP80.Onet10.190clk_to_acq_OBUFP80.PADTioop1.396clk_to_acqclk_to_acq_OBUFclk_to_acq1.8210.1902.01190.69.40.886clk_mang/ODDR2_instclk_to_acq-0.219clk_mainclk_to_acq_OBUF2.005clk_to_acq_OBUFclk_to_acq40.000clk_mainclk_to_acq0.900clk_mainclk_mang/ODDR2_inst4P51.PADP51.ITiopi0.763clk_mainclk_mainIBUFG_instProtoComp52.IMUX.24BUFIO2_X1Y0.Inet20.235clk_main_ioBUFIO2_X1Y0.DIVCLKTbufcko_DIVCLK0.122SP6_BUFIO_INSERT_ML_BUFIO2_0SP6_BUFIO_INSERT_ML_BUFIO2_0DCM_X0Y1.CLKINnet10.342clk_mang/DCM_SP_inst_ML_NEW_DIVCLKDCM_X0Y1.CLKFXTdmcko_CLKFX-2.650clk_mang/DCM_SP_instclk_mang/DCM_SP_instBUFGMUX_X2Y2.I0net10.231clk_mang/c_16MHzBUFGMUX_X2Y2.OTgi0o0.059clk_mang/c_16MHz_BUFGclk_mang/c_16MHz_BUFGOLOGIC_X12Y22.CLK0net20.679clk_mang/c_16MHz_BUFG-1.7061.487-0.219clk_mang/ODDR2_instclk_to_acq1OLOGIC_X12Y22.CLK0clk_mang/c_16MHz_BUFGOLOGIC_X12Y22.OQTockq0.419clk_to_acq_OBUFclk_mang/ODDR2_instP80.Onet10.190clk_to_acq_OBUFP80.PADTioop1.396clk_to_acqclk_to_acq_OBUFclk_to_acq1.8150.1902.00590.59.50clk_mainCS6.292-2.894DATA_INOUT<0>4.440-1.842DATA_INOUT<1>4.790-2.068DATA_INOUT<2>4.645-1.974DATA_INOUT<3>4.773-2.073DATA_INOUT<4>4.834-2.135DATA_INOUT<5>4.683-2.004DATA_INOUT<6>5.011-2.222DATA_INOUT<7>4.791-2.009DATA_INOUT<8>5.916-2.696DATA_INOUT<9>6.074-2.753DATA_INOUT<10>5.982-2.754DATA_INOUT<11>7.691-3.780DATA_INOUT<12>7.196-3.503DATA_INOUT<13>7.201-3.481DATA_INOUT<14>7.132-3.461DATA_INOUT<15>7.503-3.702MOSI7.179-3.457SCK5.534-2.480chn_bits_acq_ch1<0>4.341-1.731chn_bits_acq_ch1<1>4.578-1.907chn_bits_acq_ch1<2>4.386-1.744chn_bits_acq_ch1<3>4.505-1.822chn_bits_acq_ch2<0>4.569-1.984chn_bits_acq_ch2<1>4.579-1.962chn_bits_acq_ch2<2>4.911-2.089chn_bits_acq_ch2<3>4.465-1.842chn_bits_acq_ch3<0>4.465-1.818chn_bits_acq_ch3<1>4.807-2.066chn_bits_acq_ch3<2>5.509-2.506chn_bits_acq_ch3<3>5.085-2.309chn_bits_acq_ch4<0>4.465-1.843chn_bits_acq_ch4<1>4.480-1.888chn_bits_acq_ch4<2>4.577-1.923chn_bits_acq_ch4<3>4.954-2.133chn_bits_acq_ch5<0>4.536-1.894chn_bits_acq_ch5<1>4.238-1.687chn_bits_acq_ch5<2>5.132-2.294chn_bits_acq_ch5<3>4.088-1.582clk_acq_ch14.828-2.085clk_acq_ch25.021-2.226clk_acq_ch34.711-2.027clk_acq_ch45.877-2.755clk_acq_ch55.861-2.688lock6.085-1.602pps4.685-1.955scl_rpi4.954-2.053sda_rpi3.976-1.530clk_mainclk_mainclk_main3.803COMP "DATA_INOUT<15>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<15>7.503-3.702COMP "DATA_INOUT<14>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<14>7.132-3.461COMP "DATA_INOUT<13>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<13>7.201-3.481COMP "DATA_INOUT<12>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<12>7.196-3.503COMP "DATA_INOUT<11>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<11>7.691-3.780COMP "DATA_INOUT<10>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<10>5.982-2.754COMP "DATA_INOUT<9>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<9>6.074-2.753COMP "DATA_INOUT<8>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<8>5.916-2.696COMP "DATA_INOUT<7>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<7>4.791-2.009COMP "DATA_INOUT<6>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<6>5.011-2.222COMP "DATA_INOUT<5>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<5>4.683-2.004COMP "DATA_INOUT<4>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<4>4.834-2.135COMP "DATA_INOUT<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<3>4.773-2.073COMP "DATA_INOUT<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<2>4.645-1.974COMP "DATA_INOUT<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<1>4.790-2.068COMP "DATA_INOUT<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";DATA_INOUT<0>4.440-1.842COMP "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";sda_rpi3.976-1.530COMP "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";scl_rpi4.954-2.053COMP "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch1<3>4.505-1.822COMP "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch1<2>4.386-1.744COMP "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch1<1>4.578-1.907COMP "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch1<0>4.341-1.731COMP "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch2<3>4.465-1.842COMP "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch2<2>4.911-2.089COMP "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch2<1>4.579-1.962COMP "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch2<0>4.569-1.984COMP "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch3<3>5.085-2.309COMP "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch3<2>5.509-2.506COMP "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch3<1>4.807-2.066COMP "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch3<0>4.465-1.818COMP "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch4<3>4.954-2.133COMP "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch4<2>4.577-1.923COMP "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch4<1>4.480-1.888COMP "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch4<0>4.465-1.843COMP "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch5<3>4.088-1.582COMP "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch5<2>5.132-2.294COMP "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch5<1>4.238-1.687COMP "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";chn_bits_acq_ch5<0>4.536-1.894COMP "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";lock6.085-1.602COMP "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";pps4.685-1.955COMP "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE COMP "clk_main" "RISING";clk_acq_ch14.828-2.085COMP "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";clk_acq_ch25.021-2.226COMP "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";clk_acq_ch34.711-2.027COMP "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";clk_acq_ch45.877-2.755COMP "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE COMP "clk_main" "RISING";clk_acq_ch55.861-2.688COMP "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING";MOSI7.179-3.457COMP "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE COMP "clk_main" "RISING";SCK5.534-2.480COMP "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE COMP "clk_main" "RISING";CS6.292-2.894COMP "DATA_INOUT<15>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<14>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<13>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<12>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<11>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<10>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<9>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<8>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<7>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<6>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<5>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<4>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<3>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<2>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<1>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "DATA_INOUT<0>" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "sda_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "scl_rpi" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "we_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "ub_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "lb_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER COMP "clk_main";COMP "MISO" OFFSET = OUT 10 ns AFTER COMP "clk_main";COMP "clk_to_acq" OFFSET = OUT 40 ns AFTER COMP "clk_main";000010930038478.000125.0007.69135.651Mon May 23 12:38:55 2016 TraceTrace Settings + +Peak Memory Usage: 242 MB + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ucf =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ucf b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ucf new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ucf (revision 224) @@ -0,0 +1,247 @@ + +NET "addr[18]" IOSTANDARD = LVCMOS33; +NET "addr[17]" IOSTANDARD = LVCMOS33; +NET "addr[16]" IOSTANDARD = LVCMOS33; +NET "addr[15]" IOSTANDARD = LVCMOS33; +NET "addr[14]" IOSTANDARD = LVCMOS33; +NET "addr[13]" IOSTANDARD = LVCMOS33; +NET "addr[12]" IOSTANDARD = LVCMOS33; +NET "addr[11]" IOSTANDARD = LVCMOS33; +NET "addr[10]" IOSTANDARD = LVCMOS33; +NET "addr[9]" IOSTANDARD = LVCMOS33; +NET "addr[8]" IOSTANDARD = LVCMOS33; +NET "addr[7]" IOSTANDARD = LVCMOS33; +NET "addr[6]" IOSTANDARD = LVCMOS33; +NET "addr[5]" IOSTANDARD = LVCMOS33; +NET "addr[4]" IOSTANDARD = LVCMOS33; +NET "addr[3]" IOSTANDARD = LVCMOS33; +NET "addr[2]" IOSTANDARD = LVCMOS33; +NET "addr[1]" IOSTANDARD = LVCMOS33; +NET "addr[0]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch1[3]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch1[2]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch1[1]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch1[0]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch2[3]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch2[2]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch2[1]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch2[0]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch3[3]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch3[2]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch3[1]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch3[0]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch4[3]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch4[2]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch4[1]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch4[0]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch5[3]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch5[2]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch5[1]" IOSTANDARD = LVCMOS33; +NET "chn_bits_acq_ch5[0]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[15]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[14]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[13]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[12]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[11]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[10]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[9]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[8]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[7]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[6]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[5]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[4]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[3]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[2]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[1]" IOSTANDARD = LVCMOS33; +NET "DATA_INOUT[0]" IOSTANDARD = LVCMOS33; +NET "clk_acq_ch1" IOSTANDARD = LVCMOS33; +NET "clk_acq_ch2" IOSTANDARD = LVCMOS33; +NET "clk_acq_ch3" IOSTANDARD = LVCMOS33; +NET "clk_acq_ch4" IOSTANDARD = LVCMOS33; +NET "clk_acq_ch5" IOSTANDARD = LVCMOS33; +NET "clk_main" IOSTANDARD = LVCMOS33; +NET "clk_to_acq" IOSTANDARD = LVCMOS33; +NET "CS" IOSTANDARD = LVCMOS33; +#NET "cs1_bar" IOSTANDARD = LVCMOS33; +#NET "cs2" IOSTANDARD = LVCMOS33; +NET "lb_bar" IOSTANDARD = LVCMOS33; +NET "lock" IOSTANDARD = LVCMOS33; +NET "MISO" IOSTANDARD = LVCMOS33; +NET "MOSI" IOSTANDARD = LVCMOS33; +NET "oe_ram_bar" IOSTANDARD = LVCMOS33; +NET "pps" IOSTANDARD = LVCMOS33; +NET "SCK" IOSTANDARD = LVCMOS33; +NET "ub_bar" IOSTANDARD = LVCMOS33; +NET "we_bar" IOSTANDARD = LVCMOS33; +NET "MISO" SLEW = SLOW; +NET "oe_ram_bar" SLEW = SLOW; +NET "sda_rpi" IOSTANDARD = I2C; +NET "scl_rpi" IOSTANDARD = I2C; +NET "clk_to_acq" SLEW = SLOW; + +NET "clk_main" LOC = P51; +NET "clk_to_acq" LOC = P80; +NET "clk_acq_ch1" LOC = P111; +NET "clk_acq_ch2" LOC = P117; +NET "clk_acq_ch3" LOC = P123; +NET "CS" LOC = P97; +NET "lb_bar" LOC = P7; +NET "lock" LOC = P82; +NET "MISO" LOC = P98; +NET "MOSI" LOC = P99; +NET "oe_ram_bar" LOC = P5; +NET "pps" LOC = P78; +NET "SCK" LOC = P95; +NET "sda_rpi" LOC = P83; +NET "scl_rpi" LOC = P85; +NET "ub_bar" LOC = P6; +NET "we_bar" LOC = P43; +NET "DATA_INOUT[0]" LOC = P32; +NET "DATA_INOUT[1]" LOC = P33; +NET "DATA_INOUT[2]" LOC = P34; +NET "DATA_INOUT[3]" LOC = P35; +NET "DATA_INOUT[4]" LOC = P38; +NET "DATA_INOUT[5]" LOC = P39; +NET "DATA_INOUT[6]" LOC = P40; +NET "DATA_INOUT[7]" LOC = P41; +NET "DATA_INOUT[9]" LOC = P15; +NET "DATA_INOUT[8]" LOC = P16; +NET "DATA_INOUT[10]" LOC = P14; +NET "DATA_INOUT[11]" LOC = P12; +NET "DATA_INOUT[12]" LOC = P11; +NET "DATA_INOUT[13]" LOC = P10; +NET "DATA_INOUT[14]" LOC = P9; +NET "DATA_INOUT[15]" LOC = P8; +NET "chn_bits_acq_ch1[0]" LOC = P112; +NET "chn_bits_acq_ch1[1]" LOC = P114; +NET "chn_bits_acq_ch1[2]" LOC = P115; +NET "chn_bits_acq_ch1[3]" LOC = P116; +NET "chn_bits_acq_ch2[0]" LOC = P118; +NET "chn_bits_acq_ch2[1]" LOC = P119; +NET "chn_bits_acq_ch2[2]" LOC = P120; +NET "chn_bits_acq_ch2[3]" LOC = P121; +NET "chn_bits_acq_ch3[0]" LOC = P124; +NET "chn_bits_acq_ch3[1]" LOC = P126; +NET "chn_bits_acq_ch3[2]" LOC = P127; +NET "chn_bits_acq_ch3[3]" LOC = P131; +NET "addr[1]" LOC = P142; +NET "addr[0]" LOC = P143; +NET "addr[2]" LOC = P141; +NET "addr[3]" LOC = P140; +NET "addr[4]" LOC = P139; +NET "addr[5]" LOC = P144; +NET "addr[6]" LOC = P1; +NET "addr[7]" LOC = P2; +NET "addr[8]" LOC = P21; +NET "addr[9]" LOC = P22; +NET "addr[10]" LOC = P23; +NET "addr[11]" LOC = P24; +NET "addr[12]" LOC = P48; +NET "addr[13]" LOC = P47; +NET "addr[14]" LOC = P46; +NET "addr[15]" LOC = P45; +NET "addr[16]" LOC = P44; +NET "addr[17]" LOC = P26; +NET "addr[18]" LOC = P17; +NET "clk_acq_ch4" LOC = P132; +NET "clk_acq_ch5" LOC = P57; +NET "chn_bits_acq_ch5[0]" LOC = P58; +NET "chn_bits_acq_ch5[1]" LOC = P59; +NET "chn_bits_acq_ch5[2]" LOC = P61; +NET "chn_bits_acq_ch5[3]" LOC = P62; +NET "chn_bits_acq_ch4[0]" LOC = P133; +NET "chn_bits_acq_ch4[1]" LOC = P134; +NET "chn_bits_acq_ch4[2]" LOC = P137; +NET "chn_bits_acq_ch4[3]" LOC = P138; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "clk_main" TNM_NET = "clk_main"; +TIMESPEC TS_clk_main = PERIOD "clk_main" 16.667 ns HIGH 50 %; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/23 +NET "clk_acq_ch1" OFFSET = IN 800 ns VALID 800 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/20 +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/20 +NET "clk_acq_ch2" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "clk_acq_ch3" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "clk_acq_ch4" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "clk_acq_ch5" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "CS" OFFSET = IN 12 ns VALID 12 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "DATA_INOUT[0]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[1]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[2]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[3]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[4]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[5]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[6]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[7]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[8]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[9]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[10]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[11]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[12]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[13]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[14]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "DATA_INOUT[15]" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "lock" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "MOSI" OFFSET = IN 12 ns VALID 12 ns BEFORE "clk_main" RISING; +NET "pps" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "SCK" OFFSET = IN 25 ns VALID 25 ns BEFORE "clk_main" RISING; +NET "scl_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "sda_rpi" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "clk_to_acq" OFFSET = OUT 40 ns AFTER "clk_main"; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "DATA_INOUT[0]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[1]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[2]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[3]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[4]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[5]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[6]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[7]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[8]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[9]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[10]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[11]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[12]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[13]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[14]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "DATA_INOUT[15]" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "lb_bar" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "oe_ram_bar" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "scl_rpi" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "sda_rpi" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "ub_bar" OFFSET = OUT 16.667 ns AFTER "clk_main"; +NET "we_bar" OFFSET = OUT 16.667 ns AFTER "clk_main"; + +# PlanAhead Generated IO constraints +NET "pps" IOSTANDARD = LVCMOS33; + +# PlanAhead Generated physical constraints +NET "pps" LOC = P78; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "chn_bits_acq_ch1<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch1<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch1<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch1<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch2<0>" OFFSET = IN 800 ns VALID 800 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch2<1>" OFFSET = IN 800 ns VALID 800 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch2<2>" OFFSET = IN 800 ns VALID 800 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch2<3>" OFFSET = IN 800 ns VALID 800 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch3<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch3<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch3<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch3<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch4<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch4<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch4<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch4<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch5<0>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch5<1>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch5<2>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +NET "chn_bits_acq_ch5<3>" OFFSET = IN 16.667 ns VALID 16.667 ns BEFORE "clk_main" RISING; +#Created by Constraints Editor (xc6slx9-tqg144-3) - 2016/05/18 +NET "MISO" OFFSET = OUT 10 ns AFTER "clk_main"; Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.unroutes =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.unroutes b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.unroutes new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.unroutes (revision 224) @@ -0,0 +1,9 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Mon May 23 12:38:47 2016 + +All signals are completely routed. + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ut =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ut b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ut new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.ut (revision 224) @@ -0,0 +1,30 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g Reset_on_err:No +-g ConfigRate:2 +-g ProgPin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g ExtMasterCclk_en:No +-g SPI_buswidth:1 +-g TIMER_CFG:0xFFFF +-g multipin_wakeup:No +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No +-g en_sw_gsr:No +-g drive_awake:No +-g sw_clk:Startupclk +-g sw_gwe_cycle:5 +-g sw_gts_cycle:4 Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.vhd (revision 224) @@ -0,0 +1,504 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 09:45:49 05/18/2016 +-- Design Name: +-- Module Name: chn5_mem_spi_joint - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity chn5_mem_spi_joint is +GENERIC( + --Tamanho de palabras de entradas y resultado hacia el multipllexor + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + RESUL_MUX_SZ: INTEGER :=16; + + --Tamanho de la palabra hacia o desde la RAM + RESUL_RAM_SZ: INTEGER :=16; + CHAN_NUM: INTEGER :=5; + ADDR_LENGTH: INTEGER :=19; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3; + + --Constantes del multiplexor + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16; + + --Constantes hacia el bloque selector de entrada salida + RESUL_IOSEL_SZ: INTEGER := 16; + + --Tamanho de palabra de datos desde RAM + DATA_MUX_SZ: INTEGER := 16; + + --Constantes de bloque de memoria con datos de cabecera + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16; + + --Constantes del bloque de controlador SPI + WORD_IN_SZ: INTEGER := 16; + WORD_INT_SZ: INTEGER := 16; + WORD_OUT_SZ: INTEGER := 8; + WORD_SPIIN_SZ: INTEGER := 8; + + POS_WORD1: INTEGER := 16; + POS_WORD2: INTEGER := 8; + + --Constantes del bloque spi esclavo + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 + +); +PORT( + --Reset del sistema + lock: IN STD_LOGIC; + + --Pulso por segundo + pps: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + --cs1_bar: OUT std_logic; + --cs2: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT: INOUT std_logic_vector((RESUL_RAM_SZ-1) downto 0); + + --Senhales interfaz SPI esclavo + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + MISO : OUT std_logic; + + --Senhal de reloj hacia el bloque de adquisicion + clk_to_acq: OUT std_logic; + + --Pines para siguiente implementacion de I2C + scl_rpi: INOUT std_logic; + sda_rpi: INOUT std_logic + +-- Senhales de interlazado entre interfaz SPI con bloque memoria + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + --rd_req: IN std_logic; + --Hacia el SPI_Controller + --ld_ram: OUT std_logic; + + --Senhales del bloque de memoria con el controlador SPI + --Senhal request hacia bloque controlador RAM + --req_ram: OUT std_logic; + + --Senhal desde bloque controlador RAM + --ld_ram: IN std_logic; + + --Dato desde la RAM + --data_ram_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0) + + --Dato leído de la RAM hacia el SPI Controller o cache + --DATA_R : OUT std_logic_vector((RESUL_RAM_SZ-1) downto 0); + +); +end chn5_mem_spi_joint; + +architecture Behavioral of chn5_mem_spi_joint is + +COMPONENT i2c_inst IS +PORT( + clk_main: IN std_logic; + rst_bar: IN std_logic; + SDA: INOUT std_logic; + SCL: INOUT std_logic +); +END COMPONENT; + +COMPONENT u_np_mux_memcon_seliobar is +GENERIC( + --Tamanho de palabras de entradas y resultado hacia el multipllexor + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + RESUL_MUX_SZ: INTEGER :=16; + + --Tamanho de la palabra hacia o desde la RAM + RESUL_RAM_SZ: INTEGER :=16; + CHAN_NUM: INTEGER :=5; + ADDR_LENGTH: INTEGER :=19; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3; + + --Constantes del multiplexor + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16; + + --Constantes hacia el bloque selector de entrada salida + RESUL_IOSEL_SZ: INTEGER := 16 + +); +PORT( + --Reset del sistema + rst_bar_int: IN STD_LOGIC; + + --Pulso por segundo + --pps: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req: IN std_logic; + --Hacia el SPI_Controller + ld_ram: OUT std_logic; + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + cs1_bar: OUT std_logic; + cs2: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT: INOUT std_logic_vector((RESUL_RAM_SZ-1) downto 0); + + --Dato leído de la RAM hacia el SPI Controller o cache + DATA_R : OUT std_logic_vector((RESUL_RAM_SZ-1) downto 0) +); + +end COMPONENT; + +COMPONENT header_spi_interface is +GENERIC( + + --Tamanho de palabra de datos desde RAM + DATA_MUX_SZ: INTEGER := 16; + + --Constantes de bloque de memoria con datos de cabecera + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16; + + --Constantes del bloque de controlador SPI + WORD_IN_SZ: INTEGER := 16; + WORD_INT_SZ: INTEGER := 16; + WORD_OUT_SZ: INTEGER := 8; + WORD_SPIIN_SZ: INTEGER := 8; + + POS_WORD1: INTEGER := 16; + POS_WORD2: INTEGER := 8; + + --Constantes del bloque spi esclavo + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 + +); +PORT( + + --Senhal de reset general + rst_bar: IN std_logic; + + --Senhal de reloj principal + clk_main: IN std_logic; + + --Senhales interfaz SPI esclavo + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + MISO : OUT std_logic; + + --Senhales del bloque de memoria con el controlador SPI + --Senhal request hacia bloque controlador RAM + req_ram: OUT std_logic; + + --Senhal desde bloque controlador RAM + ld_ram: IN std_logic; + + --Dato desde la RAM + data_ram_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0) + +); +end COMPONENT; + +COMPONENT DCM_fwd_int IS +PORT( + clk_main_io: IN std_logic; + c_16MHz_io: OUT std_logic; + c_200MHz_in: OUT std_logic +); +END COMPONENT; + +--Senhales para DCM +SIGNAL clk_u_proc: std_logic := '0'; +SIGNAL lock_rst_bar: std_logic := '0'; + +SIGNAL clk_main_io: std_logic :='1'; + +--Senhal de requerimiento de lectura de dato +--Desde el SPI_Controller +SIGNAL rd_req: std_logic := '0'; +--Hacia el SPI_Controller +SIGNAL ld_ram: std_logic := '0'; + +--Dato leído de la RAM hacia el SPI Controller o cache +SIGNAL DATA_R : std_logic_vector((RESUL_RAM_SZ-1) downto 0) := (OTHERS => '0'); + +-------------------------------------------- +-------------------------------------------- +--Registro para detección de flanco +SIGNAL pps_r: std_logic_vector(1 downto 0) :="00"; +SIGNAL pps_rst: std_logic :='0'; + +--Senhal de reset interna formada de rst_bar y pps_r +SIGNAL rst_bar_aux: std_logic :='0'; + + +begin + +IBUFG_inst : IBUFG + generic map ( + IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards + IOSTANDARD => "DEFAULT") + port map ( + O => clk_main_io, -- Clock buffer output + I => clk_main -- Clock buffer input (connect directly to top-level port) + ); + +--Generación de relojes +clk_mang: DCM_fwd_int PORT MAP( + clk_main_io => clk_main_io, + c_16MHz_io => clk_to_acq, + c_200MHz_in => clk_u_proc +); + +--Generación de reset +reset_gen: PROCESS(clk_u_proc) + VARIABLE cont_200MHz: std_logic_vector(15 downto 0) :="0000000000000000"; --"0000 0000 0000 0000": 16 bits a 200MHz 5ns*65535=327.675u + BEGIN + IF(rising_edge(clk_u_proc)) THEN + IF (cont_200MHz = "1111111111111111") THEN --"1111 1111 1111 1111" + lock_rst_bar <= lock; + ELSE + cont_200MHz := std_logic_vector(unsigned(cont_200MHz)+1); + lock_rst_bar <= '0'; + END IF; + END IF; + END PROCESS; + + +--Deteccion de flanco de pps +pps_bloco: PROCESS(clk_u_proc) + BEGIN + IF (rising_edge(clk_u_proc)) THEN + IF(lock = '0') THEN + pps_rst <= '0'; + pps_r <= (OTHERS=>'0'); + pps_rst <= '0'; + ELSE + pps_r <= pps_r(0) & pps; + IF(pps_r(1 downto 0) = "01") THEN + pps_rst <= '0'; + ELSE + pps_rst <= '1'; + END IF; + END IF; + END IF; + END PROCESS; + +--Generacion de reset a partir del resetbar y flanco de subida del pps +rst_bar_aux <= lock_rst_bar AND (pps_rst); + + +------------------------------------------ + +i2c_comp: i2c_inst PORT MAP( + clk_main => clk_u_proc, + rst_bar => lock_rst_bar, + sda => sda_rpi, + scl => scl_rpi +); + +------------------------------------------ +------------------------------------------ + +nb_mem_cont: u_np_mux_memcon_seliobar +GENERIC MAP( + --Tamanho de palabras de entradas y resultado hacia el multipllexor + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + RESUL_MUX_SZ => RESUL_MUX_SZ, + + --Tamanho de la palabra hacia o desde la RAM + RESUL_RAM_SZ => RESUL_RAM_SZ, + CHAN_NUM => CHAN_NUM, + ADDR_LENGTH => ADDR_LENGTH, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH, + + --Constantes del multiplexor + HEADER_CONST_SZ => HEADER_CONST_SZ, + HEADER_CH_SZ => HEADER_CH_SZ, + WORD_INT_MUX_SZ => WORD_INT_MUX_SZ, + WORD_OUT_MUX_SZ => WORD_OUT_MUX_SZ, + + --Constantes hacia el bloque selector de entrada salida + RESUL_IOSEL_SZ => RESUL_IOSEL_SZ + +) +PORT MAP( + --Reset del sistema + rst_bar_int => rst_bar_aux, + + --Pulso por segundo + --pps => , + + --Reloj principal + clk_main => clk_u_proc, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1 => clk_acq_ch1, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1 => chn_bits_acq_ch1, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2 => clk_acq_ch2, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2 => chn_bits_acq_ch2, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3 => clk_acq_ch3, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3 => chn_bits_acq_ch3, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4 => clk_acq_ch4, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4 => chn_bits_acq_ch4, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5 => clk_acq_ch5, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5 => chn_bits_acq_ch5, --Nibble de datos provenientes del XMEGA por canal + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req => rd_req, + --Hacia el SPI_Controller + ld_ram => ld_ram, + + --Senhales de control de memoria RAM + we_bar => we_bar, + ub_bar => ub_bar, + lb_bar => lb_bar, + cs1_bar => open, + cs2 => open, + oe_ram_bar => oe_ram_bar, + + --Direccion de escritura/lectura + addr => addr, + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT => DATA_INOUT, + + --Dato leído de la RAM hacia el SPI Controller o cache + DATA_R => DATA_R +); + +interfaz_spi: header_spi_interface +GENERIC MAP( + + --Tamanho de palabra de datos desde RAM + DATA_MUX_SZ => DATA_MUX_SZ, + + --Constantes de bloque de memoria con datos de cabecera + COUNT_HEADER_SZ => COUNT_HEADER_SZ, + HEADER_SZ => HEADER_SZ, + DATA_HEADER_SZ => DATA_HEADER_SZ, + + --Constantes del bloque de controlador SPI + WORD_IN_SZ => WORD_IN_SZ, + WORD_INT_SZ => WORD_INT_SZ, + WORD_OUT_SZ => WORD_OUT_SZ, + WORD_SPIIN_SZ => WORD_SPIIN_SZ, + + POS_WORD1 => POS_WORD1, + POS_WORD2 => POS_WORD2, + + --Constantes del bloque spi esclavo + SPI_DATA_WIDTH => SPI_DATA_WIDTH, + SPI_BIT_COUNT_WIDTH => SPI_BIT_COUNT_WIDTH + +) +PORT MAP( + + --Senhal de reset general + rst_bar => lock_rst_bar, + + --Senhal de reloj principal + clk_main => clk_u_proc, + + --Senhales interfaz SPI esclavo + MOSI => MOSI, + SCK => SCK, + CS => CS, + MISO => MISO, + + --Senhales del bloque de memoria con el controlador SPI + --Senhal request hacia bloque controlador RAM + req_ram => rd_req, + + --Senhal desde bloque controlador RAM + ld_ram => ld_ram, + + --Dato desde la RAM + data_ram_in => DATA_R + +); + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xise =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xise b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xise new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xise (revision 224) @@ -0,0 +1,420 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xpi =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xpi b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xpi new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xpi (revision 224) @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=YES Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xst =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xst b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xst new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint.xst (revision 224) @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn chn5_mem_spi_joint.prj +-ofn chn5_mem_spi_joint +-ofmt NGC +-p xc6slx9-3-tqg144 +-top chn5_mem_spi_joint +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_bitgen.xwbt =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_bitgen.xwbt b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_bitgen.xwbt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_bitgen.xwbt (revision 224) @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.ncd +OUTFILE=C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint\chn5_mem_spi_joint.bit +FAMILY=Spartan6 +PART=xc6slx9-3tqg144 +WORKINGDIR=C:\Users\Francisco\Documents\Francisco_ROJ\ProcessingEngine\Projects\chn5_mem_spi_joint +LICENSE=WebPack +USER_INFO=211109259_0_0_038 Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_envsettings.html =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_envsettings.html b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_envsettings.html new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_envsettings.html (revision 224) @@ -0,0 +1,538 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
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XILINXC:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\C:\Xilinx\14.7\ISE_DS\ISE\
XILINX_DSPC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISEC:\Xilinx\14.7\ISE_DS\ISE
XILINX_EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDKC:\Xilinx\14.7\ISE_DS\EDK
XILINX_PLANAHEADC:\Xilinx\14.7\ISE_DS\PlanAheadC:\Xilinx\14.7\ISE_DS\PlanAheadC:\Xilinx\14.7\ISE_DS\PlanAheadC:\Xilinx\14.7\ISE_DS\PlanAhead
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Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn chn5_mem_spi_joint.prj 
-ofn chn5_mem_spi_joint 
-ofmt NGCNGC
-p xc6slx9-3-tqg144 
-top chn5_mem_spi_joint 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc6slx9-tqg144-3None
-uc chn5_mem_spi_joint.ucfNone
+ + 
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Map Property Settings
Switch NameProperty NameValueDefault Value
-olPlace & Route Effort Level (Overall)highhigh
-xtExtra Cost Tables00
-irUse RLOC ConstraintsOFFOFF
-tStarting Placer Cost Table (1-100) Map10
-rRegister Ordering44
-intstyle iseNone
-lcLUT Combiningoffoff
-o chn5_mem_spi_joint_map.ncdNone
-w truefalse
-prPack I/O Registers/Latches into IOBsoffoff
-p xc6slx9-tqg144-3None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-intstyle ise 
-mtEnable Multi-Threadingoffoff
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHzIntel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHzIntel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHzIntel(R) Core(TM) i5-4210U CPU @ 1.70GHz/2394 MHz
HostLenovo-PCLenovo-PCLenovo-PCLenovo-PC
OS NameMicrosoft , 64-bitMicrosoft , 64-bitMicrosoft , 64-bitMicrosoft , 64-bit
OS Releasemajor release (build 9200)major release (build 9200)major release (build 9200)major release (build 9200)
+ \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_guide.ncd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_guide.ncd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_guide.ncd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_guide.ncd (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###5304:XlxV32DM 3ff1 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f28eNrlWXtPI8kR/zrYlnbdr5nx+A7hxSY4azCxze6iKBoZMJdTdoEDTllFo/ns6fdrpsf0yPkr6Bamu6t+9ejq6qq+x9vix+5Hcff0+PbxZSs+Xp6+f3zZfS+en16Lu3/i4vfHt79n/ygapn78+bPISLG83vyCj4vn7d2/ihTfjh8PBUqOCTwkmlARHVLF5KAqJv8LFbODqpgpFeHovaDFEA3fT1u8vL49P70hEM0CEI7mKdZfIUrj2aJ9ACJ8AOJ9ALQP0mieeGNghDFQSomARxHwKN5XqIOvkOMrHGEMjjAGx/uKRMCTePgkAj6Jh08j4NP4nU477HTaeaezCGMy5avtO1gIY/llePwuyxWx0B924EkilAIxSgEpYBQhAMYIgFIAQDCeZxihFYrRCnXYC6Sv2fcrhY8jzFYFG4jRCnewRPGQCEtIjHuJ3vR4HtSBB3fgSTrwpBEOS2IclnRwWNLBYUkHhyke0oEnJq2kMQ5LO4RwFiMg67Ajige+q1cg9eqe2NX9KOHVPTwm6JBo0ixwSB3xQXXUeRAdUsd3dq7vRhM6ZodUMTmoG3VOGR5Sx+ygboxrXUlE60riW1fSoXUl3VpX0rl1JRGtK4lvXUmH1pU0tK4gwhgYYUxU60oiWlcS37qSDq0raWhdYYQxOMIYHO8rEgFP4uGTCPgkHj6NgE/jdzrtsNNdWlcS0boSp3Xdjp92BSO83b48WN/F8tP1GRo/PTyg8fP2hf56fs3Yr2JOF8TXC202H/SXPMVqCRyn4qsYqg8gP17fdupDMj14Y+ARQG+MvDH2xsQbZ8n45Z5eLH/cy79KTjZ+2b3u3orfdo8fmKsKOBxenP+HmkN1Ci0p5lGAAgyP4TC8Jk0Ady0kL29hdNCCrppzHEYH7eiwBd2UgnctJG3oqAVdd9hhdNSOjlvQ8X6/43Z00oJO9vudcPRQwIFwwAHtl9swRQs0DEND7ZTbMEULNApDI+2R2zBFCzQOQ+tqPwiNW6FJGJrs9XX7NiZh6GSvr5NW6DQMne71ddoKnYWhs72+zlqhR2Ho0V5fjzh02rxaDIMrwbxOO5vwUgsXDC+h8BIOL5Gg7jC4goIrOLgSlpMEV9LgShZcGaXj17vvxcvz7wCqr2LOaoiPrF4AyJtkvzaU536reMSXx+NMcp5s/ErLkbftY5KM3/74DWCcjP+8ZRXLrfzLK5dk/O+dmBR/+WQ6/nmXvH7/OWKtRnm6+Dz9UkznX+bTWQ4/DHM6Mb+UE8WnmwLmZ5PFesbmaeNZXJ1P1rNifT4/2+SXy0s+X5zNZtNPk9PPOfiWT2frz7OvxWT61+v1Jif59GxdnK1mf7ueXZ7eFBdLKmax/JpPF4vG6fVaDDj29HpzU5zenC5mxelytZqdbubLy3yzup7l681ktbm+Kr5O5hup4ZfZ6qY4n//l3ACLlZJZefZNWQlILsYX14vN/Gpxk2Np9dVsNV9Oc5B8SJI0t00dApj9fzqrg6/g/bjU7No5V5P1WqgzL+aXVP5GCWRx2ETGiSjt1fVmrWgRw17Nv8wmm83q0/JbDmC+Xsy+0l/UI+vr9dXscpojavGGUi/p38vpZDXNF19OL5ZrxHracjHZnJ4Xy1VxdpbT/9ar+SX1i/gzzNc3l6cFQ88n7JOq9/B+FsGxTwioC0GYstCQoQwXs4t8NeH/+O6uVwuQlMvk1+HPofdTQjAu9+o/bKGRJD5Mg4a0GynD/p3DU3ZCyiX59ejoqJrg/oT0BhPc67MR6E9gb3DE/qJer1eCe0U6ASeVWEP0Hx5QLra+ra1XE9SnsC4zUszAZoZ6nfQpxwmVWdLeSU4ybegv2Kfsfc7BFTuaQC5EgPRKNDIMkBuB+hKQa8sGzD7BD/tSQa4BixjFKwgZOicWrBWboriDSiCUEDscdHrAsaQk3JemZTbZBIh16gJXX9w/kiZxf2soMX+i/CnmKS++d3npPNMBKCooFCdyL+lkT85KVG6hoqTW3Bk8IqyR1gKNZMZmQ6XO2mvSOWBnrStEbR3Tf6QJBtKDkoRw5wglmdO10pKEr3A39KXuOnp4TNFdQ7bfZdgwYKU8dJYGIkSdSRGYJbizJ4kEAtpKWwa3km27OC6GcyB8jbm/uQa2NBkrsD4pVcjsSSFC2sGyhF6qhA7S3SpI9TZxvUpamsixAuKuSvWs1FP40GIn/EQCIsf6QEqAkZ5n504cUnFQjJLi/PIAxUpJEQvQsAfDoK8cR2zaSjmjfLCmWXCUAJsZblEl3GlkYbVn8ERYu7OWqHB3TJwx8481Jty70o1D9QFKuXcTqL9IifhqInIu6KtkpdJvIpMT+5D5N2GhTvHRtpHTeE3m7x7fPX5wWLxRfyS9kjzUmAXDkcwfCoqDKH6VaWvUho7+CAnQM4zRYGUDlEmEGSOTl0VJlN2uVXTS5O3E5G097PFAl8nE4FUqQ2hE5E4qh1UiTgUWz4Ul2jlYQgWllhgx9Qw7uzAVAr+2MguA5zvmSc+FnKGNlEhZ4vaipMglxTJKkPRrJRyLFZWx2wmNk0o6uiGZCgczH7DawsAYMfJcCt0tmhOutSwHzO6URNOIkBOaIOkCGRIDE+nq7CNnHtsbXpKhiykTqLDL3XQYWuZp/0RepXY4Nh+rSmyFdJTwnv6E5hOIzxI/BPFkWaBKCln/KJ1kzSAtUKKZ0bsQYiUiShZaKjq9FRmdJig8rl6Z3DYIkArr8DK+Mz7t1Y+tAe4bf4uqBAuHJ3cBaZUdYprTnlPSXB5rN+yx9F67uKpJXtUi0JNXE0dGjeLE4ai8VNacnFQkGFJxDZRp0oSt4vvICTSzbwN/y6w9s5lUQpCykUrtwQBxBPObwb4aGiJEu7jlImFmbhukWXVD4pTw/oq/ad66ScDm2CVi/3gZQBrCRSQtuY+61PeCn4e4cYek5FuuFeuV21p2wMZCZIXeQJeVOgqw6XlcWDt9mkClVZvFaechzTyoUcK+r3EGHY1N2LJbyOxz7fpuDEIvlxjCyqN09pMG4LauxH4h/v7IgqRmgWtyidOaMKfI0jGjO9HAagsSkZc4aUSqrfpZzE3Qg6ZcXL9y+IebKqxsbeFQcSQorgr5tzkP2XHm3Cai+G90kLrMgFVx4FGdEvdroWc34jrx9q3Ey58KdjUs7azEsqu2IA9+iYfNAFUQoapBJD6EXwQ7V8GRXc/ojeQu3IWBKscCWfAgP5QG5tnD3qyBHRHmEoJ1dnm01JZhK3JLcl8jd+5s4Kcm5ypsuI5lOaErwszHl+WqXylhH7LyMP1bxCrQ69BuLJfY34QT3fyY42Gi0ASnCgyrwuw1XEPyOmlwW23FcaVzn6C+Ns2Hx/rsVU78mkbHXCJy6FSa3g3ux6SniDwZ/FlKNDjIywPEPw1apv3s2JRB7GbSSvvMZreI8eryxA4553o3B0QkF/uI6B3zc4pzgpP6XbQ3pzhlajNC9R6IKqhEc2aDAYjGQryy6hHjjBIlNZBKHB0dlANTjFnJwuudqnpy0RrZl7l7wJ1Uj7ceIhrUuxoHt6npkU9VhNTBmk9l1XQsK33gnZcH9QSmcPWjg3lPwz399IuGIVprJ5z7zno54k/ExrMt70f0h78WlIkVEKascBlkPJ9wFZuqAKejR/y960S9d/lJvE0If6p4B771YoDRfmhdxTopxnl3uG1CcTsm/TBQ17Cqq1jZOo5cdP48gXtuZeu2i6FusSSJi+W8qtqnrnJiHJllv4WRgWd3ZV7g0CD0ntZUTzGoFX1+2GkHeinYvvXdk9dW+1e1DqNeBlemfHLK6vrFaSO7/4+soYux3gRDRZTz1uQGh+lAAg+UVmjqfWp2i93q1qtu2y36IcgPIjsPQ3+fGs7fScO7oqHliNn4v8s6TwQ=###4492:XlxV32DM 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1174eNrNWltv5bYR/jN+sM95Ee+6YAEbCYoESBu0G/QhDwF0oYC8JA2CFi18rN/e4U0caSjbe2y32WAjneE3w+HM8OOIyeXyvf50e7s88NPtgzjduld5elB35wd5d1oe9N3d3fnWjcKAOMHvs8c9SHiqsx+HPxdmuwsytXiMOgV9MHURIgP289w7WLB7G6Vh5gubsRZAA2qBqSNCyoyQ3kt2Ck48CDCuvGF2SpKwnAT083szpi+YSUFJC4mmNiJsLscxzssLYGLg7qLmg8mXNYS3UUSWAEIXE7/SCPNeLG75i5e6GabNDAnlXXRIlGoZksNOTnmN3Tn6I3wCkt2kdlEjsR8Xv6yRKxiOnipcYv5nWGY2T91fXm1/ZzauWWH7UpXtL7HYtrl+YOcQkhAOtAuE2dop1M9GHIvYae4C6LdazrNbRdx+m9JK6lxs1VVYWZwvergP4/J8ml7Kjg+xD2QK424RS4jjJoRhgmUTwlSkotmpH4UvRn7JoS/qLgfKr9ZdDpSRLpc73ZjTFPlT5DE0hYo8FnN0UUMcQxUbfZf3S0x3oJQ1qykdONPeYZT8uPMltR6Nh+SdiUlE7avZTcTcuididkP5iS7cWp/D6wBAeLUtaMzDKSBp21w4K6Bw4B2GH2PW7bczFNMst6nGhvKWjLmkHp1v110q7xBoi3l5MoJZyK7HoH2yLjwdzWsYFxSitCGxWU4V1H6hbNyBMNOggzsNp+1xWnNXIcRShKA5CkHKPUda1Hktau/lhfUIsLOed64zvBs9xzbE2TAIhue/sDVMOZp74TkIJRKuk1zWLeF1Lzb/dONo2Fm5sPW39qlyLBH2y72rrwvv6fiCT8qw0Xx4Loofg8+J6WVqIPBhumYqjfBT4m+pS0bLOrdps2eGWZsKVNfYUO7/QmZW2t6g8vmaJpMnetTwZ3RjkxArCbA1we6oZG2z+FCEboOQ0aaAPmPDLyLXbbEiaWKzvXMiV3kIQokopSEfq3JlanWMQsst1S82hHbzfjzm4dDAOY7PxfEFWShkMkxfHjofD937IT6SoeWZhAtVgPMT6vlUrliRu/dCIvIJGlx5CaXO6SDWZRTJVxm4tl65TApxX3aZswcI5akLnwVbAM5dcRZf+wnRFBApvcWxmF8SN/e9WpAqzORJunhwQazQZgztdLkbEPUG5L9T9Wu+uff2j/qfHoPwB1G2eyKVtjk5iElDUMUDHBXRsvtoij1KBqoycNn3ReYZ3NZisyJxz7ttllOtz0Us7ayzH0WNM26A9/upeYXGEvdD0fr9+i2QI736UxONg7rJPLqgvhpdhay7NSd2B8hz7cbyPqPJy5tkwX3shSksXlN4yV5s26PY2l5m9Nv3S7Eyqkt070Gub/oS/YI58qu+MMc7l28///Dwl68f/vZ1+y3/yruDRN/9/as/f/9ZiKf7+3/oSrPu/v7fSov2T61u2eNnzvpWaNZKBj+F6KtqaHmvbf34ixJNyzp49K3ubpQwrRK6ewIVXVKZm+6zkFPLuJVttRmxnVciI6aqD0f6oxFoaCe3ABC2/JkFgMtctAp6hRtmGzc2dL8INbTKSCHmWXU3QvVBDm+js9DdwFCrtOz+9YNkoOT/0da+MA+YGfrur5KPENMnePbueSO5gQEwzyvtEQA1cUbFnR3J3JtystG91S7iUqjkZN39R3LbCutfJv/ynWQ1rPyG675VA+A5A6Pd0zcSQvOdUE07PN6ooWph5dwFUMD6WjPBVDr+NPGp4nOMzz4+h/hs/AQ3kNRBuwmgP/xRcVj4I2dzy+zYOqFwLg2tCLPaVa0OVp4Gly6IHFjvdSub/vE3Cd+Qv0nYyaDOux+Z7VvzyAbwY3CTWfgL9kfI8QBZGOr26WelG8g5JKiCBNUQJT63VfeNAl76p+RNC2dwByBDQIyCNAFxClIEJAjI8BVk2JFPpiKggk8zARV8sgRU8GnIoP7Qp4aAqE+mJiDqkzEERH2q5QqqxZFPNScg6lPNCIj6VFcEVPBpyqDx0KeBgAo+9QRU8KkhIOKTmVycdkLYRIpKVTOWhLwklCWhLgnrkrCnQqFmKpRjYSLOBiL8Vcm8A6Uqxx5AkoAYBQkC4hTECUhQECMgSUEVASkCEjMBaQqyBGQoaCKgmvpEp2soiE7XUxCdbqCgkYBGChoIaKKgnoAsBTUENFNQTUulUFCGomhFCbo+ti+pMxerLQ5dUbGCAaQIiFGQJKDCdIKABAVxApIUxAhIEVAu8xWkqaWZgAwFWQKqKWgioIaCRgLqKWggoIGCegIaKaghoImCagKyFESDSSoYGkDKqE46UamZeAHKLaNSoQr6qqdHxxmmUkUpPRIGC/0tb6cWGjr9CO0qa62BpEoBzbBk0Ly5pltx3nL4fv6Z+UPNPd0E4Olk4u85PG0V5DbgeJWeAc+ZjM86yLmNzznIfc/XDbqq/UcBWHv0bshxcE5x5xRsPGGG4BWDtvpXyfysT4P1u0ZgtcklSbdayagK/0qqDV2QZCyYUnbYeTDJrQd9yYOZeDBpp6aDG3P4Y1dfptf50ux9mV7li9r7Mr/ZF1cv8GGAjNqq+1EC8dWPFpjNgmUr4C98/1ggVguFZqHwnN7Tbt4wW+XKQYUyYLEcNI9PEZ+xjHT0phrjc4pPG5+hDOVYxSeLTx6fIqxC+uMDR9Ty5I+A8h1Uivy+Dm39qsjXu8jb/q2R/z0Y5Y+fXChhJd0nJ4FhGJP++I1jEKXuk/Mc/PF6Oow5OFjvfoJd53WQPYh898lFBZbudFSF5qpm0NHGyX1/ssotyJn0covlU/cTMICXD1g+gnxydkIVrXMrZ6f2vqrkq/JLi4vl3t+4Drcd3NLiYv08/kyNemGNVZDzJOfYXoiZSvYGbE94vSrreXvAcM5vf+I6v7f2Km9PhjFHXsie833mddaL9px/3AR78BNyFgaVl/Moh90VnQjysE5YnuriYoNcRjmfu5hokLvtChQO27VB9N64UjQbjlev5vgbCUuRE+teJHt4Nl9E+sqaF0j/YLMNlPTfTrn6Ovq3b6R/H1+hVFd0Sl11DvivoXc/B+wz5wBwPh+A93t4jvCEdz7BE95B7+gcQBWj/jfngAo3kl/M736rvze/J/5wIQr8DpLE7zaPRX6Xid9l4jiAI35HHAs6VeM4sfHcjudB3K4ElmduVxzLM7crhuWI27GviNslS36yxJ125fYpcbFK3GlXbp+z3obbbeJoi+2FeI3Jnsb2ArePWQ9xe+ARLx+wvcDtQ7JnsD3P7f7rIuptuF0hbg+Dgav1htvtKjeY2/1ig7zG3O6T7Ll9djf07dgC2YvE7X3g9kjrmtB6oO+x6b60h4+833eH/B75PACt7jCxi6uI3TdpbyH2SKa6TKb8Kob3nda7N/jsKmLn4xuJ/bnTxvpebCwwvAGGBzZ3H8hQvRZ6JQtSy6HbB52X2P2I1d/O5rMvQH5Ey0yleErRb0KhNrWCKJmndte1o56S3T2Mp+SZR8pyIrcj/f7E9Ac6mHYTxXlbuKUesRzRrsZyRLsKy1faDcXg/RkjfXmnPb0mqnaFFujLORfoNR0TTg/Ta/qkcC/InqfX9HngNhGy5+k1fVY4PUyv0iS5wfYCvc7JnsD2PL2mNt3pbei1wfTqBwNd9phevRNBPmB69Yv1NKphJ+xvQAbcHUtxRKOme++rkMiesivdiTTX3InoaTy8E1HP3InE/SBL1KCrq7jTVB9wOaKrq7jTVPr9m2LtB8pNsZ6mVk9Vq6Eu9MThyeAp4AnvoPdHuhxpXnU5oqvqmubZVP0bm+dnSvP3YN19hQPUU7aT7G5J/JZ3XbRbQuiiTRXpycFLtyReJ9ySNPGWxHCN5sqUbrjC8pXSDZdYvlK64QzLV0oP5bTOvXbSoXa9rzpQaVjs5pbE7QtPpWGxfp5KZD1E9WFfejnH9ja3JLri2J7welXWQ1SvpyH5PWJ7u1uSBttzvutZZ70N1Y+I6sNgoPQJUX1wIsgtovqw2CCfUScdEh2PgJrckozklkSaDzgHvvyWZJ6vaaZNZd+nmS4eCGqerjoQGPuAZnoerzoQmPqIA6E+PhCg19GgoKEw9ATHMXz6aigeDZ+sTu8PdEsyD1cRPWve/5YkGPUcUUd+Z83+lsSNhVuSeUj8zhJnuv8XLPM74tgat+uG92gezO14fsztNZYjbjdYjrgd4TG3M5X8VIk7a3JLMo+JO+vE7YxnPcztjCU5w/a2tySwfZG9wO1z1kPcHnjEc77F9ra3JPOM7XGvN2Q9zO11hbg9DHqurhnmdrbehtQccztbb8BrgbndJ9lzu+GC3JJM+JZETu/3HzifvxNR+E5k7q+icTZ9wGX33FzF3rz6CPaur2FvPfcfwd7z4Q2ItsDUUwNsXcOzh78W/rqWfv4/3oDo+fkbkP4VNyAK34BEg46m5kC3ek43IHpObd68uQFB1DZvKVUgW5hS/Zb+LySzBb0=###4416:XlxV32DM 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fb4eNq1m8uO5SYTx19mdtmYOxyr998zfIuRsMFSb5JFlq28e7hUYeCAx25NMlLsNuby/5WhirLPa3mR1/Javn5w4l/c8fV/nNE1/HW8CFN2/SEofZFDr39xEu57rf9shFEezlhdT8Z6cv2TU/k68n8eWuFkx1bM+klcrPeDU/1iQq3xgojNhuYJNs9i87xuXuWWsUnGFTbp1k+66FgzHG0+UpNbtDa3KFw8aXS6OzrpYXudx+/TyWSU6KvW/bL+nwfx+otp8mLyeDFNX0yFMSge/mbhKF6x3j/dAHK3S2SQtVMiMgtJ4cjgyOEIo1l2ODo4ejge6T6+L3AkcKRwZOVhUJ21PAE+37XW1lnL63vWcp21vP2dTyXVvc4tt0yWbwn9O4w4wqdfH6nxcH39SaXOJS6XRGMH1utHuhRGE0q53M7CYMj1IyILIHJNKEwVgq7QJnWhRNhoURE7Y+wVBrV+pJkGZ8GKeKbT2U+6+FCNSV91tph43eSOTBm8gsGTWMLZ3nSkS0e6dKRLRzo2GDXzND6UvBx4B01tWl8XemwoF24HjiR2E67BbS4V+lLI6sI9ieOVOCKiBOBvC0WbsIMlaOIPhXFdidjBEDzX1FXNzH9hsYRRVg0zASNe5BJeUPK6t2xtg72Zujdok1Y1U2/E+VyyVLpzb07nElLqkLq3JfWmsTdd90ZTTXJUNaG3OA5q8oMc/hQrlopU4KAgrG04yFyQzRLgiBVZ5YIDCuix4kMcCuIMXFRYFvxrfxHz9Sdn4VyrOMPVmibkxvPso1Q2M5rvtprRgUKajoFTuSGICBf8km/wsHQuZwtuX+MFLMCJbeDoYc2Fv6krFb1ZQ0GCuoaVbe9Wtn275W+XpVvZdvdbVzbTrWy7h5WNfHcJd69vBRYJ+X8XWFA7CSwI/a5Q/63Igi3yv4wsVBzmPogs1BdTMkQQIYpQKhzDuQrNyHAe6vwqqphFE78litgmUQRh3zNNYJwWzlk8EI5Al5kZXb22j88+iwD4NyMAtuiyou5NBACjD64pGCZHAPFSjgDSUgj1wsWxlw+doUe35WwrZ3vr5fnZW+3lWVrz8gC3iZdPHenSkS4d6dLR6eU3VskCL78XR07rQo8NQeHptiw48nRb9vLF28XRnIV7FiELLQkeL1HN3tyjx/Pg8SKD7M3ZwquajTdfaDWcxpsvxc+Hs6q37M0d9ubq3qBNUtWsvTk9jkpf482XojycVb1lb75jb3vdG81t+qpm7c3t0njzVJp8syWNN0+DzAW09uaZVXLalKRwNCx1DF22zt5aWPTWfP2LsTQj/uAkHTcuj3buMr7gxBLrJ9we5qbIc5OSvb8flg9meJnnZUmTpeon9IgjJXUTLDchTel7L0MMolMF9vUROw9X1494JZ78jP+LNwD9qCYMeYU7IzGu3VkWL/2MNwRgfOc9MAPA9itgankEjO9iCozdA5ZHOgSmjxGwXCEAi50nYPFKBQwGFW6IW16WbhBvwNTSACPUi56YzcTCrLoitj0iFvqRM2R6v4cMxjpmpkfMoAaL+wkvM7V0rcKGI4tstswNbu7AbQ04JlJB/IfcNnjSzMntky9bw40J32OggMGdG2GJYlRE6VqUuechBTukkCsECLHzqOEjXqkQhCkKniPcEPoL15ctizz6h2MHkfrq4dDy0cPB5DKdTvTes5FHOn40/BjKAVDkkh+MeKWCAoMKlg9q0mOR72yfCi2bp0K5vP6EiYnAHMwmcgmsfypYWQP44BHg5nq94nt7v3LT9So/tb8GnJWNAasR4FwhAI6dJ8DxSgVYOYUQ81MHdybABnx5VHoCDuCPs056lOMNQW+EL9jeT0mf4XNyMSWFWGZTct/uTcnc83hKshGcXCHAiZ0nHfFKBQcGlW+op6Tgqhd5gMjtUqSdirQ3RaaexyLpUGSqkERaEBmuNCIxFRROWpG6E2kWWHeuLblNRZq7IvVUJBmL1ChyQ5G6FbmhyK0TaXqRBESqS5H7VKS+K9JMRS5jkQZF7ijStCIxVA4nrUjbi6Qg8vpxdVOR6q5IO41Ij7FIiyIdirStSNx9hJNW5NaLZFkksZcip7HALu+KnIfdfixyQ5EeRW6tSNzQdbGA4P3qmvcGoRl6KfKYihR3RU5XV+PGIsvqeqDIbnU9UOTRieyjOiNA5HIlUs5dCL8rchrVmX0sEqI6IdGF8CaqExjAxJNWpO9FyhXCjkuRZCqS3RXppyK3sUiPIgmK9K1IgiJJJ/LoRUKim10+rilHNxZJ74qchqLGjkUeKJKiyKMVSVEkbUXKfvNmMD8gLsNN9Sg+F9LOwkdl74WPeaRDKEoOoUiBUPIi/BGvNFAshoIqx+f5zi4+V018LqTsgWF+gF8C0w+BbVNg5i4wOQUmxsAkAtsQmGyBbQhFI7DtHZjugKkeGKQHxGV6QJuHwKYZKKXvApuGp4qPgWF4KncE1oanmP+LagDYewZKmw6Y6YFhXoBeArMPgbkpMHUX2DQKVONNi8QoUDoE1kaBskCxCMy9A7MdMN8DgxwDPy6BPUtACcWmwPxdYFPvpcYLu0TvpRgCa72XYggFUk/5zg7Y1gHrkzIGcgzcXwLbHwLjU2DuLrCpJ1RmDAw9oeIIrPWEiiOUHYHxd2B7CwyyuxUwzAu4yxQneQhsmmRRNzOceaRjYMPUXq6QgEGSRailBVaSwgSBDZLCpANGe2CYY7jOotOHwKYpYbXdBUanwNQYGEVgEoHRFljJBlMENkgG0w5Y7yUt5Cu4uQTGHgKbeklN7wKbe8nxhlGhl1ToJVXrJRV6yaAGgL17SVjWTmC6Bwa5D36ZWH5fk34BbOolNbkLbJoQUuPNp8KEkEIvqdqEkCpQOAJ795KwrJ3A+rDCQh6Fq0tg4iEwPwW23AU2DyvGG1mFYYXyCKwNK5RHKAKB+XdgogPWvzq1kJPB3dsEmHwI7JiuYcddYNMcjhpvihXmcNSBwNocjsIsuZII7HgH1r66ELr3khbzO5dbI/VwL6nnryLkTWB66iX1OBGt0Utq9JK69ZK6eEncS+qBl+z2kpr0wDBXdP3m9OFeUs9fnIq7wMgU2DipnSokYOglNWmBFS+Je0k98JLdXlL3YYWFvJNcLoE93Eu+ZzcKMH4X2DSs0OMEucawQisE1oYVGl92KdxLQmqiAdbtJXX/NYOFHJa4Dlwf7iXfsxsFGLsLbPp2UI2T7ZojMI3AeAtMIxTcS0JqogHW7SX1m5eEfBi53Bqph1sjPfeSd/Nheuol9TgfptFLavSSuvWSunhJ3BrpgZfstkaQdqiAQT6MXD9h7iGwqZfUd/Nhevo6R4/zYRpf52j0krp9nVPeJSuHwAZe0nXA3sIKyIeR662RfwbMTL+I0HfzYXoaVuhxPkxjWGEWBNaGFfiZSFSTgZn3LyIgNDuBuR4Y5MPIdgnseAiMTIHdzYfp6RsYPc6HaXwDYwgCa9/AlK8Y1IHAyDuw9hM2wlj+qQx/CSSGH90MEmL9G4xPkX6gEAiaZ7vx0K+ZIdxOhO7yC63cKhu9PtnOl9N+/vokDH8vbc13XuOoZXPlRxv2FRpafwYY6TPPjDSVGPgMLN6TXrak0vrDQ7lXzZyvW/5m+LOiiDZ/KJabS/a0/Czs7Cl6e0K+TvhH9mRP7TkNHDdx255qak/52J7zV0DjsH2zxRCqs6co9pTFnqrYU8zsqVp7YubCsGJP+W7PNnVB2dKbE7KJ9Jk5n8UclE8XuO1mkEY5nRrz1lvq05gZwtiWwwBZ4Q+74iAqUwLNeB3W0HhDsmMsqj8X8/RsobEivtYyEPfkpjoj7p0R39ZYyHBS98iI7qERp3HQdjMfRcUyNSJ9asTpAiuPayOGQTRG1GhECLUoftZG27VVeXO20BgRX+Yah0Y83o3oOiOazogbZF3p/siIz2IzKqYz0R53jTifictTI043EtL/wojdTDRgRIEzUZSZaFoj2rOFxogGDQXxYW6qM6LvjGh7I0ImmG6PjPjwJw9i+jrQurtG/BcNyf00###4204:XlxV32DM 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1290eNqtW8uy5CYM/Zl8gHnj7ppfSZXBuCqbzCLLqfx7ECAhuHb7dk8WyfWIlwTo6EXbhxbm+YcWx0OodX3+YaR8iGN9/iX25bE8/tDSP5TRTyCITlCFIDMB/qr2V/cOvnQwneCez59awBTPf/8RIh35S/76IYRZMw/i+aeUa245jp015Bmg4cgNScuhQUNDyg1mw6nksj7ksuWGJdVFxDBkgSFbbTFsjN5gjFhrS6KWra2/GGiBf/cWYLmtKNtANQxUMFCBRCIODcD4osuQCC2q8OfLkB9JqzpW7FUEs9TBtUFDA+yGXhYSzWdmsmgi6bJNug8o+yp2ENnt68AFbPgiilxp5E9Ci6yL9y0XbbJY9y8q1lJ2Cf5XWuzQUjiu0u6BiwIc76E2aN5QWI51rmPYH4n7I6HLXrusw3Jl51Q9Dz0cfrlhZb3FhKEFBJZlwUWPlw/OUMI6MtSGvMkLMpHF/TekdX+IR3qoR/r1t1aZBbmvoE/pIcxe1UlK//yZN64pCWmRPiRpUSWk44nq1Hosz0Gv9CFGvdJH1sSf+Yjb5KE3hNIzdsJaCHsnbIWQOmEvhKMTIhASXLW8SNnQZ0gbSACnvPwqgurDPf/W0j5U3sUKJVqOUMKQw44yI5SoGWwYlphXWJL5Af405+dAfgJCW8ajxo+foG2ZoE2niUF9lNWWttoK+2X6aiZrUVttw9WONEgvZ9nUIMoorCVhGV6mrWkiLM+0Oq0N+2ATGApkVT76AIYbXT9rAyHNEU3VNZipqlrp0FVN8rW4mkpjeQMpdoob0gf0AJ0hOsOOurVEJ+Q4wsbppOLHFji9cCqLKAenF0ZFUeLElbiIV5V4y/r8EHCJxEJqvKEap1M1XgYVfFevxazXCzt2sbv296VaT9q8kzZPSryeKrGflcbgNXb3SiNnf0DMSpMGpdncqDQMMuy90nxBCDMrjT5RmryquQSG9R1gmNiRo2j6Eg/8vWjueeE/qXMYUHiz9QADG1rQLPIAA0L2ASMMrLyBwcCKMGAaDJQODAY20dcaYWDlDR0GNoIHN8BAuRSFjh7M7irTpg8YPIgYeUMHgo5d6CaUDoQImWnd12KQkJneeUNhYilYcTSsyBDRpgOMknHhGFL2pmJIkCcYEhBDjncxpEEG97CvXAJ5Ah3ZKS0js7/b/hKEGAEzZI+nE0QhEJaY5SiE1AmpEI46t3UVQ4K4xBDxPoYww8v1KyyX0LG80K87n8KeIkbQo0RGqLaYOF5IdAOGE2IENSGGwG0T6R3EeAcM/4H7WS96UDzeqtwUuq5amI+3aIb0fQALt3pUVRvIR+7QEXTTwqAG91oG19fiHrl0kjdQnJYwtINbwKEjYFQUxAgdUvUB58FHaTiBjiCQ6WWEjiD6WgN02J03dOiIgkNHma5CRxWyxLNtbwp0xFSgY3tkBNoIOmKDDrvcQYeY3Q81uR8NIV5gSEOb2f3wbbG1+Q6m/juFiimLb39TxQXRMEfsJxg0AEmYoaaD0bJPYNTQKc34NYBR/tuYsWtzcNIlOKn3owIjZ50WoxewX6KUvNdpexsCnbkD+eKss4y+rnoQNGqHi+78xNAq1JPV24YzbhMALrLOmI4PZzzMPGNsM6bPZkwFRc5Ber89WX3MJ7u8dl2DvUTr+IHr+q14L+/afA7Ctl3bP9q1f+LW4BymBujPOA/4D+BD9JoIs75ALDpheQMGe4HeXHCTvdj6gNFeKN5wZi8cQq+d7MXa1xrtheYNZC8iuppw66qQYqcUocn0VDOEP+Ci1w/oWT82njyMaOWgA0sQRuH5VB6n8jiVx6k8TAVbGdfmtpaewFVGUKCjTQJ6WSIjLNA9SpHW1n8vS8fU6bX/Xo5qI7d4Hx1s8m3T5GDvfcBoJTVvOHOwEzrY++Rgh77WaCUdb2BWUg0O9k5WUg9W0qKV9CYf9cPCf2Qjd7SR4t1M26Fmk2ivI/JuIzMX/iL5pSMhpDffTn598eb8tTfXIaW7dbArZXt9SQPT2cf96HSWY4mY+K50Onp3SE6nk486cjodeNQrp+N5gwVZahxkeByU8KDk3UHd+y72LiUKB/X7zsvkT3h9lfXUOxkyb68O3j3vTL6/zXryg88Wwl7Y/j1+aqndhe3fw6cz+gvbv2+fzrhe2MV9/dQuasT5dbSLS6czuxg3spf+3MTkg2kGxeGHx4+hPkU6Ch1OTUyZyuNUHqfyOFU3MRtx60YTkzqdm5iV6HYwMfve6czEeN3mBzXgMIO2HegMZjqc6CGVG/fI6Scwo8U5zGgxwkyOGEQOmPSjR0wHgozuIPMuuHwzLztgR2YGdk1xXdT1Vpqe3tQBr6V8dcHlVdhiAmmhtYNzexOljDCzcOc2qqvkigmooXpZvx22fC8vG0vopk6gy0hzocUX2lu1LjsmcARVx/LkXMck+l6Zzi50lRzoqmYW6sDi4tYzkG3STPoBFHCgoC30tjafK/Stz8ddqlpdLRzWekvrQVe/Fmapg8QOpAPGO1xycK1kNMyDqoOKp2TFVmqS2V8SqBxpacrh1KAco11lVnOf64avyoTb1woDGtyf4jiasuge48PNkYvpBPf8YpL/MqKY6mB2O9+XdkutQfXSKgy3dDSsePfwLuY9kna++e0O9ucQ2n/fkCCzMLOfZ05tZiqs6DhgwTdn1sFf1DPE0Ws2asAGOadX1QwW+qLQafYv7kArbIhEu74cV7vuvgUFVrq5etJ8DmF/8xhK5UPxmQOyr+nSjI76aVR+9nzFlSKq/vUDrlFe8vnDlsRU+XDl40/4HwJU61kACnq2D8eRyhaJqKfHnh57krG3S8MgkLEa4+Mo9Njp7OWKxVpwpdP7EyuQLgfnQGPoD1egYGNhoGCjxhRuYQ6wEW5lxUaLyVdoa/PVdXRFOOgK65eJWTUKAIt1UNiBqlJWtmC8dqBilBUWVxzcFY2RL0BHk8A2CaxQvY3hsGyF8VrZqQwUOHVlkTwKLiXhqUA8jQOexrlQy4oqyxs42t9fUOQiF9HnUgUvZSdshaBmRGWYa2bMrSA8hT88NbvPdaJlTs3quU50UGq2J28xlgo2ujGGIkiRB2VJd30VQ5nZufHP74NO1+uOPk7pGSMQfaJ+yxHJoq2zaAFFE/eiqfdFMzeimVm0iKKpd0ULk2iYAZU9zfyGaB9Evm4UbXIHKAYUUb7nPjrVwgu4mayW7Qgx44BDDmtilU445ND7g71iGUxH+FTolPq028HplCu1hK6FTm8fbWTzFzyDTah45kTjCUgsUCXLA7e8GBy4E+3DcsvjhMYZhlSnU4lzQ+lXJ2nXVv5e0OFjg0qnB5B2S5ze7U+wnN7tVfSd3qQ1iN6Y66wn0E0IljErHQLRVGxStJ3e5tK4cyry9elFpBML7odmdjHfPMh1gVv9cGQHJNqB/a5MZ//XMl2PVwtby8OdFZ+spwd55uptr3++nat6UZ7qKszcJYNXdExSusV1Oot46CK5MRnpxMbpPXmJaubGZKdDR6nSKfdM6u2m5KXTUIk9Mrj03GVSeMJpsPRheiX54qXlR6Y/DKY/TRXVlsR8aZzFtXHuwZUr74XdmU1OFFTEdHV57PP3LZl+dXnKmZynJUXYLmKEm9jAmXRh0fTSZRZfLNqdWryw0UwbTGzOKUjGQoXKVbmViVfc6H079OewjY+VoT+DZ4sPtCq9GyMbOb0X6Ba38oZudTbD6WS9nFbIkG6YCpxVTNWuM8tiCrFgJg8GMYB2+Ky/0ruptZrTCeidEZzeTTYWxyq9m2a9cTq+SsuXwBsoVMQHBFmk7BqV/RiU/fSh1oTe9jaXKF8XKuKMF3trSPOT7aOVMr4TKWxzpKDnSMFQpHAaIFzUSfiDMjEHCpqw6CY+gBiDai2ESSFeGDS9UXZmv8Qkd/Vw09/mK+3LmosrmnWaNGIlko/SFa78wMCeZluovBT2KyfbP2/fvb2MFkpR4zQNs2+/K1i6CIygQoFYu9wLdvWA3nxTwvnRHcVDrHL0oYTHhTURiTYvHN+uDPqrJ8GvC4Ju/fJQBcOi3f+WhL22BQpQI4hN4odqH+sQU6gDYTrvDjdOUnN6N04BXcSQmk2BmatNWdHeZBKLT+y2crY8suWRLY9s9dSZlH0ZFrpYfBFR6T10EY7TKXRxGJBVOoUu6iDx4uBxkpUrdMrhdytX6N0DjrTuPljLwOhtm8j0rrjGNphedQwyU5hjyZsO+2BhVzw6+NlGT6qpQ/H+ZHkpOVfpLDk39O+WnSx4kbl792SpC7179xikV3r37jF8BHrbC4F74dF1WceguPhe7cqUfC1sVvtQ7WO1g1tGXlC+sXWZlWJvcuXKbe6ek1g5vcf3cuF09KjAyd3o9bgkZ8Q0Z8QvX5yRKZQU7z9vmZ0RCDZZZXOZHYZXLoX6f5KPZP9VuLT/KwW0+ov9v8sX3j+2+WL/9Zh5unpvKcL6YSii4xx+BRSVUHv13/5drn++/QDxJpGot4s3HCKEj2RuSqggv7I2lcuLDJEQqoneOOBTtRcGVqujh0d7ztLABr/5IhdoCZ3eIpaNIhbPxxCUO3twes9abZrTO5zi28NK71kxnTidZcUQV1QYoJ9gUIUBBslUqDDCpuT0Do8EsyoMJofgVA2vCHvYWPp306UYPy2D1n70/G8Qy1beru+QFTsIuCy+xHCXSbGLIEqdOz+IX2Pm6+wHchg7vfyB3FChOf25K0vkXNRd7hCvl7g50GkOeP/bC3l9/UK+R2j5sMpvQDiu/gfOn3Cm###4676:XlxV32DM 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122ceNq9W8my5KYS/Rl/ALOkq/CvOEJIENEbe9FLh//9MeZAiRqu+3nRfas4AkECJw+ZVFz2P41yX0bZ/Tcj45fUwe2/WaW+ZNz2H/ISX+Ir/5Xtr0p/fzNq/dJ22XOBboBBYC2AxQK7738ZWZr4x0tx5GeX9E/8nV4avqyQtRvqkr0bXj10g7X+tD/4Wt4xN3ZMDx0L6ZOmHVtrx6zTvWPG946p/YcSR+mHUlv++5c5jt6Wz68xtK2ttuWE6G05sPXax1Q7ZsLeBzeMSZUeC+hxNqOlb/GtxzG2t5j0YmrKm0aXuaG4fdRon7PbR4F9lv6266l91jgsAmlrWzqG3tZ1zRaB2bnB2lwrNrV8kOvL1bCQ1fBzMbkx9ffvpaup4v6HUiEB8YwMsBmICZBiEwRJLWVky21ZyaroDFwZcIYBpYYvbZW1iIjIyJEQe+TX6wykR5KB99/LxORPfygRStcPVlflumdtVXckrZw6KGEK4qEnqdk0TwmRDbEEyQP6vZSlVVibXEiTedCtP2Xk6aMDWPV2GwJ2TK3VsSciSN2/tj7CAqi9dzcPRKhcWYWTPaPhmWxboesLsOOmToe8sgnj4QlQ3iyvbJ/oDwaoDFxlzi0DdAayqUNcGGAyUBfDGhiSlokM2WIhAOBVb6t22EuGlMbaHAiG5MbSfwXRBKmDPI86fMU6IHIdXzoQWWNllMWqwlmGlCp1lr1jSDFZnix1VgMko1uYg9SzvMU39yXTt7TLZfz7T6PTFxWWvWx36da6t5Va979SlxsrTf2NiY7vaBMl39EmMTLb0SZmfk9z3tryHbCJgnPBiU/6UnBhwVEKAhZcpSBiwZYLgsCCc8+MJ/EtrhRUwk2LEoGlAAYLdCmw7clQyDLtv/a3kmcj0USmB1bMjiJRBhZcpeBsT8KArJQFCFhgSkHEgmSUPGsrJ2YTm0hQB3jnQ70rEtbPnfIyOOVjpha2CGpBv1YLM0dh9lfeUI89dEMP16lssJ/KhuOaygb1UjZY+aZs2PxENjgh/4Vs0PeyYXNT2WA+lQ2FCO9lA6yGdX1bNuj93bGtzxYB88pr98pp3MQrp+/gXRLCXSG6BEGdPSN+wSQFypNSBVQI0RoFAN1CVEEB7kRIAYhcWBxDiDxBqZPmhni39N0ThHjd9H0D5Jo4/AIUh5+W6MThl2c0PEMc/gbOuCBE3RwnvHrl6qZsuI40dZPKurrZPGmyqZs8r2USIkqYYgUQEo0TEAHnm2qDFRLTEodNNEYCiC4gqqQA4K+JjikAOOUQN/b2W1VSqhAhsTmGgO8nEqcAoEqiv9hbiFo6GQBqSZ0rEwtllppY8FksmPwPpAJRCFUzaJHd+dp260a95Q8rszF236SKoQ6s0bFc8BS3vqab3uQgf9rWTf2oiCdIXhYJ2YARAEAeCPEgQHrH/kf+LxkhJscuv65ElQFssHW5dKAxUofFKDJkM8b3xcYoMs5RKaCWEBG0xI2EiNaPHrt7FwM+7Jwe7dzD+f5bbifaY+J1nNSfep2oBn/ZvY6RV28rigd/+VoDPfMpUQAhREW5X4rgCELIn5wtoqLkTzR/VJT8ozkZAOQP6zcbkizfqDyWEydWZ72UN6IsFStPCoNY7a6wyOoAAGFHddByoPjqKaAc3YNozNIAcC24cyuQPWsS/2mzZYvIfDT5WmCzHX2z+enZBA8WVEj0wwmeVkL8/LSSN0+IciK/tV67NMvRuvvNs4wCZ30ZF3ktyA1dlbCSck+p+9IbllMnpU9ajl7NrLQcvUqf+loODipqR8vBPUWtaXn3gYkAygs4m/o+wecDm44kytj1GZvaT9lUDmza6DWMZ7iRVl2Y0qp+QquTg5l7eeyxt7Tqrimtfizmo57SanhNq8vLCN/Tg1tiJRA2qSMzftUzftUzftWMXy1v6oZfk0Upv5oNyym/utDLQ+PXXLHxq0Psnl8LgPzaN18tv+HXUn7HrwW449cCIL9KoX3RYVTRnX3/XZRgQ908MviJomstkTWnmqJz4buKToNuS5+qogtVCOtAkKrogueKLgO3ii4BVNFJYR+NcHUjBGqEl7LW+qmsFd81ggUjWM9lrY0EuZe1dmYEOxrhOnMgUGU7NDPEKLoVYreCu7MC+txr4+E1c507I2tzeU7W5lo5WZvrmMfZfih5jfE1ExzE1xiLm6A5i5uwcBY3wQKL02ksQUc6jWfoa/n41jR6mTbhoBnSYa/yqMOQ3fJ2UGTZX/kK/ZavSB0bYncmSazWMVizq37/JDDTMMu7/dkG44fmvIyNvRch1fSNkQq55Rbqd3OKJoJwsaf5xMX+U2+dPPK7Ur0eaNAQyMlGqYGE/Eh6VeVXT2CWVLKCIeByEnIxBHyOlJdjCEZ05GkYghGdGg1HBGNQ8nR0TGdG5MW5IFUmXKAhkZGXJh2sY86kwNRfCXMxhERwrGcIRn3qvCOCTkuemiHotWouAJHutrLrF3RMSHxt53YEyfIfrzfkNwU0HxrBLYLR/EMyouYNqvmHHMT2MgfhIQeR2o6x8RpRp0h4qF9vMwlNlnomOplwbbmGa9SpYYwLxEqrbqmUJ4s6uYvgG3ECC5j/kAXMKGGbkFYnxOsjj34/CwTzfIUU6yhqdRutAYK3kkXwBQvUz0L67WrAcLAsdwVIbF8WVXsXITdmg9Gdbx8g3ct8yVvO4GfeJH3LLVRt6w33/Frirn+kpVN54iBVGPWZHm7PdWo0uD6DJCjsyZ5R8AylQ82ekfAMIcZCf/iMgGcIRUKoJi+ueiqOcWQ0w7mOMJph4lyipRyLoEuhCUKi7kZIBkDAVx8nAyAUy0jY0egtI1THotqUNh2Naqtza4Hd5LS6eWpgN5sv8eGRQy0nkGPs5ChfRVrEEGlpgRU1xlH0GJwxY+ilLshbBvZjOvjcX1Hxwam4pZRpOvj6r9LBz0IJcQwlyJzkldFNokzGeKDk+I002r+LLqSOnTNfoSDSuk3vhtmX7PXgNMz+Ib9HP8n2OhE/zPYmfT/L9urwy7K9Ms4viV2/PNsro51le238NEBUjn/mzpcJWKaRK4dn8SD79MaXEZBSFSzXmjgMVH30LH1YZ7AjNX2Yy1r6UELuLH9qQjgZCNpF2NJgD6aTS7MlnVzqkXSyxHtoQnD5D4K9Iug3URFXhBwz0E+lLcjcAR5ACgIuJEZeBZwOcWAFwORwOl0RhLm2iHUmyeEKFDceZ7fB6jManiHHhOjIVBB3S4RJdDQSTc5y0bFcadqKBKGXruTJh07yvujuCwJelfju6GgWl/ju6NhtLKIDoqPBdqKloqPRdtWkVMu8VhO0zKsyY+YVgjOLYXHy5ohcDdIotw2xDWXG7ep6bOP8XoiKHLRT4+Sgnb4vBCkHtdShihiC1F3lVn5ezVVgL/3jg0+D/Qo0VxBlt4F9eVGN6Y4H6uwa5jb1kwXJMvjzh2hTP2n1+NSzS1zZv4fjIVbYb8ngRW+7PpxBBv+icDzoTkKZInuXoFKQAIjhlTcxb105DuWWsLtxAOqwkA3z7GVPT4qf+PqfeVXU1BK/zivleiBAWDSeGy3HK8P9okbg13/hZkfg93ThinHgt4JDv0ET4GpNoZ06J6Xc1xNUWlSFGOWKFeiFUnAeAW9oaLiEomtLhWwD3u2oXNvv+9YngK2kcpICwFaqhbYKebbmCvOEM83ZVz4dONh0qm86d7vpnh0DHq6HivkxADesD5vlSwzvO24Gltj5sMRmynd9KTCfq5BslWrGzXLXshkEaGK03xuq5ZhIhUW32dvrRLUcE7WwJDbLEqlG2DGHEXWfp+V2nh62GjuDZWG3jgTVzx8oom+E3TuBBoPXJgS7YCWVVQShDl1hlk6wO064qhvSzZgcZw5wVacBt5uj6XYhd5dmFwXedxLsNvM6P8Ye82Ps+5eZwdGnEW56sjccJmiDn+2Ndf+c/G/PXGobfngCuS+bieKjM4UsCezbE+YKvnE73j76uv3fnJeIJsmDpPpeLSD/ciYYtbLuDFEAKq9xGVeE3PsDTVQREgeSC0NQ+ON2qQjGgaoCRARVrnIHGQ7NKNa1VBHdjkJlyNWlqsUTmNKbjAygW3NhCP6QAtLeDQGOg/x2A5DkymjTFnbZIa2wn23fz9urOJXap2pwdiPIjTtejDtePvx+Ydjg12yDH+MGP9kG/39FpZIdVzULLTmg9mN9He2fJSNf/7DLPP/9odqWaYxpBQaQ04s0Dx37lrRN3XDTQNLxYSBJbes0kLT9skCSWvU0kKR+eSBJrXIWSDLhI9LPVNY1QW71NtCi2m39+gj9NR0EINTW8wjZEvcBCLX1fER9BgMQdWPUPmiW21QLUqNj4aU6rx2p4SW1rT28VCekN9k4Nfe+cyq8cVt4MEJZhpCL63JjCLoDIXgd/A2cWRhA4kCRAcRRbfQtNA6kNmxsZTlbdEfZkuzHaeDcKoJnEnRuFSE/dYP0R0XAeej1ZACGg7xlAFGPK0WI4lQtGtSiLnXebROPsqZFkrvx4G5cdzfHVFY/+I7BZaj93RzHNv/JW/cdJLkczDPX0QrMeFvS7m/ko59cmzzGTIYfE9bnmLB+lp8OmJ/OSnCbHEKU7xcqjX4juvz012FyEaN2bZdztFiAmg9GzbfZXhqDMev0N3FwSVjIl1mS/wEIFD9O###4776:XlxV32DM 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121ceNqtW0mS3LgOvUwfQBxFVYav4ghOiuhNe+Glw3f/nAACSimn+ouqUgEUSXDAewApoby7/WOk/BL7dvtXpOVr+ap/Rfn7j5buSxl3qwI5FGoq1qbQU6CbwEyBvd1+aVHruv0NQqZYntbys/z5R4v8ZRZx+09L+1V+bkWyfwm1ibv+sNpJx9TLHbPYMd6fUJ4U7Y/r/bHlYfRHB+iPvP0rF99ak3LrdXmPdaXypGld26hLrVCXtVCXO5gi0JQhkDduk97bUC7QXHTlydDmQm/O7GI0p0sP6FDK4wCp49jq49jejVi0xxGLo1mdcMRWaDZdj9hvIbdcnuSfH63WIr/9lGIrGuP32khVlAkqFdx6kfr0Uy65FFnThkXSVzGtFXHtqRSRrf4cWRmFZVQto1qZuGIfqkZXjW6a4EBTOjF61zVtpkFT7Lr1Fsrk9CodqbIMHfRebr1ebLHshrK+bz9FClWzkHqrRlRN7JqFaWTVpKZpozs1qmrqAGW9MYWuir0odsnrMkWRe8dTJpra8fKK75qImtR7JsvObXOImjKSw5ql95lrWm3tnSVmpmnWyK5xTNOsqfOknGGKZk2dDBU0U1Rryq82DZ5oujWxWiNTb6SYYHBFlFf+BifLgHyJrexisf35T6vyjypz3ha62Hxf1VK62y8R/fA66J/0vnD/pHfLN7XeD5ta551vO70L7kH1XvbhrzINo7U0FbGVzCAwS29+nyVCFWTSwVTr2ve+H5dlvlp3f5nRKVibQI6SaipUU+gp8E1gpqC6/LHZy6YPqBC1f1LGKRBNkOarqQmmSaL1S+6zRBmvIMTqOYzofR0w4iQ4IRdfhhF39L326B3V0TuaI9CtDOiWJR698wA6VYZheGclr7zzXfvu7fbDEWgDtA/ooLJ6eYTWK6C9Gxj3kAG4NtuW9EuYMXMZAdcZ1i9xHJdHMPa8P4b057eTw0nVjjUfAV7ag/eoQ0lwQTmuMLfmR5grrprucPbqcSO44tpId54yNHmk8gpcsrr7dZdUXsFKVmcfs6Dy2iVZXX1MrP7aI7l3qBkvtB1D3GkxLzDN9KfoaLuC+FO/Ms302tJrppkYID3vwMQAGRQbRoIoPjMNwfNtZxqC4ohCXbNUzeiBRA2DwaIxTIM4qFwgCgKDKlJrCKIUazZW18TnifZdA/j8N+RYUKZshfKDUGMAasIp1Igjbsgj9iiGGxxZ5CR0IW+W70P0oHIz4J9kvNqH6rgP9e0TAv67jkEbndofOqBi26aCrMI9GirHZbvDeu5yXOh78FSOa3aPO5XDuqyzYu9mxcKsRDIrZwhX0Ykh3AC0dIS8BwhXUTLktgTP3KTc7PPpMcfpUU+n56Hb/p0b66/D5QJzk2WlTgVxPXOeXKCuas6TC9S1zXlygbrCOU8uENf5N6itsLavXCIRsfSJ2ncJ85RgniyjOToFTnN0iuc0RyfHaY5OG9KcMvdC9zdEGmvAz51pbmxR6LzyRaGz5YtCZ8UXhc5zUVS201qhbKc4sI6ZJgBm+vUKy+3nWK5PQ0AhDkG8zh764xHDL7mFue7Py+zrqmOBR+A6R+gYBsK5vBlMNz7YUUP/X8ceXP+ui2s4elHXu4HQT03YFHGEdrVIqbGHL1RNkXgRnmlwQ4hFWqbBLSGk5bXhphDSKKZBRlHeyUxTgVB2iDKW2hSrRqRmU0JFYjZZHpJVNeM7YmWaGTovUjMNAWrL3yHgbiTTEEJgE9MAuNdsRFNVL7Cjt17BC+TprXlUJg/YOcBUHYMwfQzk7qIy19bPjM7mrt99eyMeo7M0Ss7Nvm8Yth2ite6ccvcCBZcvENuqBRl9eJk530GCeQoJPMSQm+aZIL2P3Jlx/q1MUNm5dr/IC6qZh4MJfSugu/Qkj+BuTZg7KaPOaGuOTENIMK7SrpkUROxMgZylMELk2sV+lolZM9EQCtozY70yTfNh5RXePiHumyGakY+qb49IZ11IlS3PVRb2wZm0/s1MFdnGTYOZKpU3pphEWAhuLCaqyv+OaYCi/w2xxFplT/uvgvUZN7iDDb4/3+DPOPFCgGRsZ7prIcnycNfS/X2XbMlmcIvT3ApLoahRkuRWzDG30vM0bpTMg41QJvokxTL4Zj5mZXiK5Zdsc3ILcbnyOtLssDGTe+51Xj84ID4mxngAdHAxZe9cuBgYmwtXE5dD4IOeRtrlGwap97xnjHeHBbJ3Y98/NWw9GhZgptJzw+5ImEN8eJZ50sywljXXJ+cDhXl9aJi7ioVMfmDYs0yRu45QTzJFxbDtYFiJC7th6SPDfkfgd9XC5pZrG90rR8hBVFE/e7DVJ0el5juEYEZwyF0+U0xmp3KkkBGyWF0+U0xmo/KZYhJ1AkyRly1ZLCt9LSu4P5QZHw9be/hZf9UmoKpS4O5wB6vyUJWHqjxUheAWIclfdy+BjmgClSPYRCupHNEpSkPliLcxgLz0pCNgNs2EZZbvM1S7OmbIgW6lFDeaROVIcCPw7y5HshwhA9nlSK+jNVSOdDhaP+Vj1Tjok1HUPsx1RZFBzqhBXPcpH/ZFqAsSdFVEWEE0ntaFBCgGSeVIf6JZqBzZT7SCymcGJm5noL8N0PfiVVZ/nxGz5+Sv8f9z9A+3w5mLvx1oQDqeucQjDdjuaMDFycp6PFmxR/RX76L/co3+D0E/XYG+xcODtL0cauhr13vwuIp73HyB/rv7FEryJfjL54aZ72Q9zy3cr1jA+pmFYb9kAVY9sPD9axSn9rQEyin420/t2a7A3+oX7Hl+nvYQ81vC/xTzzYeYjzhaFvdAzR0AdYEHwXAUUuG1AMFRBJo65xRoIHnV5QSYLJXfA1CXTwBa5ZQPcFjugSYzoJkAmxnArmLKB2jtUNcG1KWIKPgCAPZ+TQCEcLYOIQWmCfqZgf4kCZmRhM1SOSEVCHCJAdymqfwM4BIDuAm6iYMuKT/GIsNYTFBMNO+AtK/uB0r7ViIfcyRwXMHuIqIUEiher2tSPKCKXT6p4uapfFJFoJxdjpRz8ru2xD0scQ9L3MMSB35XMV+eYL4HzJdXmK+uMf/yWsUF1CcO9ZCvy6Pko1sV/irQt7dXod6/H+izAP81zB9158cR/3YZ8W/PMXK9xsjLOJIhor/C/Pgp5vsrzJ+nFW/Y83FcHK6gPnxqWLgM+MM7LO3to8GDYfEK8/2nhsXLgD9+MGPPL9PoJ5F/umIB27dZgAcWEOAB4uuQOAsAZAiRswBE3MBZwELlhAVkKj8LQwMPQ0n5gVYYIhp8x1+wAM9YgE1TPuoKGE5DKBrCKQuI/JpIdFBXGcJzFuA5C2DyyQJcpnLCAnD8NsYCXKRywgI8lZ+xgI2xAEvqGWPh71nAdsoC4hJ58mef8lEXpik2eCckxgLsQusiLMBROWEBksrvWUCXn7EADywgwAPkfULiLKCsmwL88qvwPYMsIAALUIwF3F1TP2ED8joDcJf/nzzh5FxvP2QADml+QOjHl0FILv4AyGke9//qRysTj1OjCad3HS2GwWl9doX//+4VUyM6Z8d/6jJ4vXL44u4WPkD0ivmGnZv4qJ880y6PF9bFAF4j37ziH+V6BAI1qgrp+Q3/5fqGP7nYH1ur5gT9TIjv3Ot/5Tp/lO44OBYG571JJE5fOuZoJISvEhydxHylBOch+/X4H1XSr9FHuENQdaO+tcnVrI9epMDb/rWOdtm/l0BXhZ8M9AISCqCPMw4iQrne+zL950dd891zSQsPjiWq4ZpHFIEe20Ztp5wgYloklSOCpmUYWVsk6NadQZPrPpitS30wlZs6ijSATF2OyNQ3MMonklkmn8inDZVPVAKk7HK8/CnHIXoDqTHU7ZZ9ZT+iRHryy6GTj+Dk9dt37NV37thXJ7/2uEfcnXRipgmP5Kxim3thH+fw3S6Pu10cv+fJR4e70A98olgvk7AZ/YD9nAU/uNJOrkJ0qtpWKPuIIgrYnsK0HVtmfcXVo7q8LrT2IiVEbTliAQUFcP0NYIECEgocFiIWEFDgfkX2AmRF9p3QNsZ4qa3ItZDlsgxjXZQLrskEa/LynoF4Y+k9ST9sx5OG9PTrjruThvDxSYN/76TBH0nOw4sHzz7pSDP78K9pVOAW1nZz/Wz1ix2P6cPrF2AfrP4TWFy3xDF43jtI83jevR7ygV2l6nasdpaOEDsmtKN9+eL1d4+11/YNnjnJS9Q46Jum+osEhcgYOEf38VmEe3gWsbaPBcxJXqIGft807PhxDX7E4udXrC9cgH2Vuz2x1C9HxmjB0vgtS3+bdk2lRHF1RxTp7UddL+NhHw+l+frws/4qLAsSD1VOeOAKZ+x19Bp1qQU6dVE70ZHAdjWCypHrrVZT+WR42lP5/KBGSypHYreqjcrxsiwGr9XsxvOq2eNh5LJb78n3qJC/qAVIfsb6jVbloCoHVTmoClM9a0DrRpqklWwjtcY0dSRNY8VG5ZjWsfCxZ5djGshKTeWYNlK7pXJMt6yQJqm9J+mZNeDIKuhrxr76qSOk18K94S5H0mtFonJMxVgpqRxTN2pn9WCqZ4XUUB1yQp7XgGMhoK8J+7pOHSHPVigqRxZjhadyJC9WCipHzqJ2R+XztoPtVxxT/eRk3mHOg3oE+eQ7oPtbD/bZd0CDkwxv8j/lW2mD###4788:XlxV32DM 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1260eNrFW0uS3KoS3YwXwE+AqsJbcYRAKMKT64GHN7z3xzc/tFTqsn3jDdzdJhGChMyTeUg9zGGfz+9yNw/x+GKUf5hD1oYFG/Tz+UPuW24ogqP9TqL8/qHUWv+v1N5/p/679gtSKpn/cPmf+PeLkSmP557/GGUfRqpnbjkeUnvz/LIo9ZDHWl4hxrv1YupkJDbo2qCwoc1fY4PnC9LLwhekF5cXZGQZ9Pkrz1CWqWqc4SJkm6GKfswwT4zO0HRlLFUJOJYQRQ2GjCWXsVoJY/HV6j7W+Zg/pQrlL/Xv16rLrJ3nt/KjSNajS8p78wjPb1n/TRKZZCmSI0uMcERQJpUFaxYcSpC3VIGMWxlL7GOsoqn6lnwKqiQmJslvyeeiSCSOliVttL2OpjbHZqbLBPYmCWyd9RnZ3uOZRBWJyhLtFybQRaDrMi0T1DmbOjOZmKTMOf/4lTevqDM32Yd9SP/vP0bn/+istbqRTrdNU8pna4jDGkT/LdFcFD+h5hD8hA4LIyZnX5tcQMFWe0Zs2GvDjg1rbUjYEJ7DbHtDfIL9flcCZr6IMg0lFDa42qCxYakNBht0bVj6WKn5BGn677X5ABXjlQ8w6AOODz5gMn07m76ZTX+ZTd+/Nn1VR3Mnpm+UGxNb1aedk5tnqG9niFvPJyZnn+TbxKxYx8RMGBNTRflbd7xrG2vbYCw9+aQ8RBtLg3+zdozlpzXJeU1qXpOoOhXjdbEcxoW+LrTXLfn0ttcZwd2pmlX4SmP6XGMxzBqL/bVLBI258dr9WmPUR5STS/wNupUmABelV8kE4Ij0KpgAHFE+Vkww/BDxaU1A3H2k06IuWm1mSLIu+zOBQ0RRUF5idrey+Ptlq6hXH5GPrItn61L++pYtmXv+NmxdbuSev0mqhqoXl45PpWqijVb1jRLAEYSeJkAYUTsdjMHIDurLh6VOLbuyLHH7CuvSdWZf65Gsc8zOrT6cIuujoU9BI6GbsmHtcWCrME3ZcAiy5rpKm6Se2yEpuNrekI2jDbmTIctqusorAKvUtJBfs8B8OjBlzMxYFAow7QOYtOjAZBCYGBClYwYiNQPRZ2M/Xw3kc4AUOCAtQsyAtF4DEgG118hkZmRyMzItp8i0TlHrhg8UdSkVsKHOQkVsSM8Xga6qyGBPQM6q4fd0Cszv/adxrYpTXGuOjiGL1295xBwju0ugXA8ASvFpoFzm1fp5tfoaKC+g3HL1A+xYtd6r/z62cNfq5/NYrnDIq7e17iatQzbhd9D6dqX15TZ3wkW+SEA0OOFyCoh7dgQeLPXBNDFwzNUTPGoShAd1CDYacddhJ88wFAg4mqPZTIYuKuFphmASSJp0XJkAciaSs7SpAUocSjIBAYmQmKQMJpYGEpZIOgpknfeJq82DeLkA7GzYHbDLcwSw1baxJYiyhKapNTFJ1VRomlJMUvSuYlsD7q+gIUr3dUMykOzANQAO5sa6howhTaLY9mOgQrJMx2MNzGWbBGINGjcIGlu1GAAFmEk25EcJRHZ5ZpJJRgRXknqfG3IAnf8B+MoOvgsB3wllvivZoGKRoUFEGWiKxLtvyCsD3+DvfcMY8tfPdIwdL4Pn5ue38qMo1BsiKTuTD9IOBwkENN7zgkjw7P0K7ij7lh7qkUAFqqvA0sT4ODrgihmrT9H8DsRJenkK2tJMoC3FNWj3HvI50Jvh/MEigeDdNiNeGL4XmJxt/TTiIcDc4cp5fiO1usACdQACJ3c1H//8c8DTMwIvBIF/umMYfZkq88XJEQl1rEJxCRJYQgcmQf8t1cEk6K+IC9GK+zhlmAT8oju61ZftbshyHLVdYTvx3j4G2g7+ft122g4A4Uc21NoB03QUtB2Q029s/DLPHD9nA2x5pM8GCMyU1t0AHTFAbiTDNrhJdBvZ59CXBbQ/lHWDwdVTQi/1YG/AEhbJ+APK3kznTL6mD6S6OufGCGBQ4yVXdBdFI51wFuqsSIKyM4z5fdFGyee+Zf3M3OR0hGsQpPszLctsffAwtyOLfRT0ITC88j4S+uABb2EV9hHQB466SrLnl9n2hrTml9bX9DKfpIwGcLpMO11esvRSzNkk1fmUXeo7mrNkqCfZZZwyQ8pubnMyuc/J5Irs5g+ZGhOJsCRnsFEzLBE42q7hiCWZniaZHJ/EnFQeMz7td/jUMe5gkJbN07PgwurtgmNVO+QKabnCB/t6M0/Q4AO1qmk+ZteVOw1IPiUmjFOoM9T4OuQJtsZwbOijrzTBSpfls3ymOWYXoaalmkQ9lE3HnGiO66IERGNe0N9LNE8DAqvjRb5rBPjJuFxNw71PN7yE/zyfcOG3tYX5hPX+/F0xBPr59ok0/ERuM4zZcSLTH53In3bZmvctpz4/9fxaXlb++FZ+kNytddhGBwi9re7AU9RI4xN90HZw+HbEJ60dwML5QNsBaPTO2gGk7CCbWztEZnYl49f8rk64YmGBiybLTS1JsHWRld7siyxJSO1AUhI7MvxiQiSNd2YfL4uMyjWWtkPw5CzrD8GWs4q2Q3DmVk3bIZjTI14s7TT4W2RfSGrvrRMmiaczG+0gRwfIWa0fM8+qIPmvHWFE8dZdrWtXq7OGDqrHoMCQOKNoBzM6ALli09BLii1GyfhX2tWObyUXCk6vtB2yZJsCbYcc2eGh2Ogdh02JtmMaPjLQ1g70gUptnEoj9UXUQKScIJlD3PwPwpClhyHqNMht3OvS6KYT32OXccNlNI8Zp8hvGdx8GYsEfm732I4GUgJVv52Q8rbH5P6elJ+pt9d3wX9AwY8w6pNR07vMO94J/23C/WOikp5nJSZBXTLv/h3m/XRHbi+RZZBXPLtL7zK+5ppnd3+DZ7fP36Qfgr+k193foNdf5WXl9e6KVXf72zq+ZNXX5W+w6h90bF7mnBH4DHNBrxflM3rdevYI0uvSSyY5o9fbaEivy5VOgNLrcsPRJnrdayJh9MwkIfR6YgJkgYonpVNDel0GJkB6XW58NUivt4M6JI2aLqenT1x6VKo7p9eLPTd6vT5H+FHp+RKQXpfAnDYJoZ5sZBLM6yVS8kExer05tCEZa5C4BihuCpLR6xLrocxEr5MJcnpdusQkSK/Ljc3vhF5vgjN6vUmQXpfARjcJodelL2VXKVv3ATDqOoyun4fRqytt9Xk8vSMf9pvSqn7XTW+yG4WQBlBtl0AlfgeorlI1e4dY6yVixbe96XqFWD688KZ3AOHer+2i6R655SirZVa8oYdaqb/TSOVlAStnJG515SWQxK5WXu5i+Wi0RCYxCbHFlY+G9iuRgAwrt/mAZrqBs1jBWeCNW2BRODXvjZdI+oNJINBn9s1TA+ISaC5RDsha9kyqcoGmwcB9N/DttKryFYmoTkjE/0PIehep7ieR6nFEfv+HdZBY1XdSHXwVqtmXFFzeiiuKyLY85b+O2S4r8lbxtpe5ZJcExNiFxrmL2e5CNf0qVMvGhPgaWPX0sRIBC26MYRJyPwBXt02CZI3nj5CQAS3TMD4oW9nCJBCaUD/Iq/vkaomEhEL94DRJBJcS0KUYIibBF3UpkcdrK3+E1NmlyCTI8hCXwmghffQVFXOiVZDgV4uAxVPDfTcB9XQbFWBQojfbYxLZb0SONArBw3BZdtxzM/9j9o37H7NH8D/sPsHsK73eloZVDRC/Y5LlqbJJmqfKJjnugExa+DWCSXiNUEIRMSWaZu8kurEGrrfDHWwv17A9+SpznlaK+euQtI1pQI1a8J9mjfX7YcTVxKZSDZPimBjUg6f8ZGjoIYPtI7T/myi6zxAWkhghpwtCLgGnoTH+F3LYX55QflmRQv1pacsvhPpTYmVCketj5jiEYrkkCUaEYnkhCW2EYjZLQhuhmJ2T21ChGNcaNBHQJdkpwCprimIUq1DHJiTPuTAkEpI7Q3cwCSkR8IpJhs8thXuFVX0sD/WwEKWs3eTjxyoffkUnpiu6con34YpO6ynsBhCTSQNNaT98aPTJAsgU50+P+v3Gb5YWOSxUy0PT0iJSRVWYZrwCyHFdE5Sl9rKw3GOUhaUVpay+bhSINAFYCGJXHQWw61fwBeQK80o2a+ubtZ8yxS+uYD8Eb/3G9UWJUNnfPIk5vgIiaQcf6i+v4Ja/cAVHj8BPb0bxiIk0OIl7wnai95gMbQe1Y/GLiTQuiSbSdrCqaFbaPuww75K1H3Yp9F1Kl7v0+c05K9uqVSunexK3F3vy+a14VQNVFtw0YRlfFpPAdrYDlraf7IB15ztg3fkOWMd2IEqfte+yU3OwA7HvwHFnJ0jHX5a9Q5WQr8GkOSsSOsD/WHlxKV9u2GcOHm/cY83Izj6qVA78ptze+aiy6KUqrIxNNsoPtCnrIWU+cYTkpT/ZqLYhuvWvl3atA9mxFQekO7ZL2g7YpZImVTptsHo3FnXZyaNYE16O7f1yTFzV6Ijn3ceJ9nmTcHeqbWEfiQwCjaDhaQ3m/fXNOEEDLUOsHObpx4IB6Pmkf6Pw8upTg/cKHUM7C2fsmU7re3ltNPPHAlKNocJ7n/lF46+q9AJc0FhzXxXDldOrY8xkkTWSOfWywcI3fu6eWXjjoqRawKQsO5S1vfeFXxxxSvmDxC9x3IjHEb+UDt2Hm/GMacX6X0tL+7QrGoeyPl51G7qXAJau9co+8ggnBzYH7aFHD3QgOtIOanTAko+KLdBBjg7gUloUZXKHfHDrxUZdQfnjf1wkJhE=###4876:XlxV32DM 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12f4eNqtW0uSIykSvUwfgD+EZLmfU5QZEIRZb6YWtSzLuw/Ox3GQQpHKHGurlvJ5iD/+njtElO4mmL//EizdP/9Ep27sJv5+wBflM853V3DdcX1TnN/LA0JsYNN+2Piu4Te64IziCnCVcS5SpAYJBpkNdncUF4ALKMhwinPAOeBKU5wBzjIuUu3ELyGO3FC5lVZ9fgbj9hvPf9zMjR9//6tk/kPKdP9H8XRz+/0fLUTulLv/5hH6dP83V5Q//1HC3dQh7gCIAcgCyAGYAqgB8AJoBNJRgNABzVgBYqttHz/diyENYCvAMYAIQGIDCPfc8gS15c/jKGUKxkdl/g6AGIApgByALYAagC6AHoAqgGuFp/opPD7Aoc9CjC7y8gsRB8AKsI8y9wKkARwFOAaQcteEqbVqDoXfg1HQE5P/sb9lCtVh7/9VwtwUkzCpR57eqOu08jx+dDqlNvN0Sm3n6ZTazdMptZ6nU+q8An7n7QDNyctLwRc72qMZr+2RBtsTtqk9bK2Nt5Xwql1ybZdZ26Wndm0w1Jq2S9R28S30dinX27XT+fVtfreyqLJHoDMAXVbzFGgW+hSo6ylw6xSYtav2cgrUPAVymQKu+xSo6ymw97cbKN9s4JaWueCmz4X/0Vz80RGmWf79gPnO6P0DKoMvv+B/n3/A/RV/CXhx7nlHAb6ZhufRK84dHqjO3bgwbMW5g1P9/COTpLgCHAjEuoPiEvAdyjkExQXgEZ6X0/Mc8NJWySjOAPfQSX+MTgJx1bYOBjOFjfAB1x9w8IArLVe9ZFV6+yu7ytJyN/DaUwY0Zo2gOPSUqYLvFIeessJiylAcespEwafnoaeMlxGOfVb2RrlJl1nR/XneZ2XHWfHDVik3sdI3TvFCubVvieKFcctgpQkvjLuXWdkoXhgXZsuIneKFcUOpF8dItDGNvtRrB06kgdWc4igNrFEUH8pACYqjMrDKU7wrg88gY8pMb+Ef8vzReF4+5XlCo2z2Ap20xaoE5MrzalUCetIKgXPlZvc0GGsb7smeuSe1uid56Z706p7c6p4scU9/YNzKgJamkpmU4SAGMpWcu9kydB7f1GTB6cy/8ZMFJzRb7GRBsZctc2ld7n3mYd0C6DoPui70+Vaszbca873wax+rL8zdb17EKXz2FRMm4dVE3KTV9kWrUTW3r2rOo5qj4k2uwkutak6v4q1Ist+NJiZp1mRVWJVYXJXYPgmvJs26IgMhZosA4zyeKTAjdV/PKTzQ/8sJuFijUCt8k7RWV2vV7kAOtROHPuVOKKt45WeaTXHckdupYNDv78gHRaOwt1MnS3CjnigrEUxrmJJqaphcC31jTFWcx1Rz2YRTXhNtHIzv1bm5lyotvVRHKZ3V0pNiJ6pMoABVedy/OsgPyl3eT7v/OLY5zty6J4li8TG2iocyHuCsPqDtRMdkQ3ND1YDCRxL3FPPiAcVibDYkxccPiketHD7C4NYMdIJV41QDp9pmeNRaOaqi4YSrAWVU87SjR6L3CBUYZ8Zhy3eqDpI8JgPKiePYJgPqD869JZbKH7tf3bemeilb+GRBhcW5TZMFNVn+2xALUXGFC+ioIukc3E8GwlPeTBbCbVEQSxFhdU7qDPJtJxNF0iXZMo8QKqVsiZMFtRVnjk0WVGMiaZLPqNNX8hkwD5nqQo4nCO/xxnv6SufwReccZtU57P6cIpsieqBIT9IYV3wXn/IdW3MTJHsh1+yFXbMXeqVIhRSZWYurJ8y4ECJHQuw8uGQmEmYmip7zZ3rOYTTn4pcd20O4qe4nFClfuvPjCGvE3zMR3CF5iKldlI/PqMqcUJVca9u6qjXIHWziDjIKyzLsZEJGQSztmNkl799wloSwncMVP01CyMs8kP4SZR+HP8s98A3FkHxYDEtz7P1CHT2rHLzojo6+RtIfZWBIpJl9j52eEfgMRqnUGxcL8dObmH6t8NfosWUcjCEbCfJiCIGUOvlrEj546pZpxOGpV5bREQOJUYbvh/VPHOhwx9WADJdr19SADJcNjhpGhB3NwAm/yWhJzys1M7ZGNJ6mqSdK9IsO8ZOFxEfb/BsaU8neMj8rFheoYSiWqCmOqR1kd8CpYEE6rj8g6mNz1EDUxza1CTWHSKYxWnbZfRXpGstZiNy5gVjOIaeJxmnmitPEZezOvhW7L3HfEu7ta7jn13AvvKC/meXMynLyMkdPWG7Ef53t+Na4ym9nXGUxVvPujKvMZaSjfpZ7yC0M6SwWEwljMf51B/rlhp3wWtiXmIi1ONNwhnEmRrfiZZxZvJl6wpFGYsxqzMSRfOXIFwEXcOREiX6l5EaJ+tAYcW0PAuAsnvpq0OrdOmKxVav5W5E5uC2Uw7nUmq7mG00BlwkqOeDyCAmUaoRXHzmQ6PxEdDX8Gs9IfIZQnkcZ7/0cmmzoocPeW1ctg7dCzdfWGoANS5GeFNlCCmh9DymwxrwbaODABjEXCwkcjJ8syHskTiuGZ5FdMYzIjs9FkcguMmKZIruAUVoZSKI3Rvzmt4n6SKxTLIP6SDRaLIP6WJwtSH1EKRQDkRBhMpDAzkdiIRpCJDszk0dmYsBhN38TN4+8JBsv2R/w0tUZMntNR8dCMpVToLn7mb9nIzZR3/D3V6ek6rWbZyU4kU/cvIiYcjtm3/T0fI3I37FuodtUE46VxhaJN1YamzVe/jsSC1V5uNKgGqq+xuKsFprRnn+DS10es2EkJNjhJwtZtyj/qmUkwRMH3ZQdzm3H1ana6nRv32xYRVJbri9uNjwRSZMWimsu/EmOYNxwGOvYbcfZIX8UGFWlLx/yq/cPcBeVUrID9unyxUxp+voZjjnbV/JVDpMziUkrEadgh0k2WUa0w8Q+WcheGFmpYsG9kPhBDGQrJNGiB5ggst4TDxTHHZL4RnFc7LBuCY5L3TFSzrShZZqaShhShsmCDJkEp3WMY0Jnc5RxS3nTJNw0um2a7d1jwoNfHhOuvv0qjxbWTfNwT6hfIHqVaQvrPaG8z3LXwxk9HF1sK8G/vIz15cHHA0+8zmE5686iAcewgfKav5Z2ufevmNBbPn+cby4YRpBoGucZxdHNh91SHDdKkJriuFGCdBQnYmbvuKM71Fk7cLJBY3L0edzrzguK4yYZG8466k8iOyiO3gT2DmknSc+QcaB3AY6p3r5tP0OEg4m8CdWNM9yFpu1C/3B4O929E+tWektIiXGue7bZnp/nPtl1/nLX7eN2Xo/Sc9/DGbt5vDKW4hm72cuDsGtxZuimi2o7OVqVyb13tBrVcbJ/9cgKb+r7+QZ3vzrzfM3k8eHIs1+L02p7L1iNqnESlEnu8GCoCuNaIlV4gJ7ooW6ElUBvyOwTToQmt9SA7qGupIbXG7pQ53LUWH9EbtBO+Lhx2+/VQBn0GrA6On70SmKrZOuZUbBNajp6akBHFPuFqIoTmcIdNQxPpDaKo+cal5YLPjxLECx7lrz3SMRmm2MJxLGMa6wvrka0o6F9vU3x/Gyo35Hol1ZzW/h6wN5XGz/eSyYFIZZcUj+r18G+n0vSYt1IjOaSglDrjUXdazPXqaRvHqYEIdfhMn240nubE1ZBWR5QJrn2WDtW8HoRsDxQF3Md4mKrp70fgNQUTuiSGGytPFvwNMojefaRaYIySqKpPoEpekxX1QdEfwDz5dpilYIm2NG/lGaCfyldGP5FNBFQj45rqSWbEfMM5P3AIc3OcXO4tjniRcB4nr1gT4IWvtv22am2zlAnQ55CI0W3pLDbQS3f6Vb6V5ia0nZczvtAHbpL2HHuKE72wdM7K73tY/k7txylEp2Mh4ssXB2lvrqQEmLa14401k3qZK2/vBMMJaY13dy8TZLfLfEhgd1Su0l8s8SDrW6sbfHEv1ViI4i8HWBllI0Gs0fYs1F+f0D1B5BFHe8ilbfzy7x4Ae8HcvA8EbVx76+mpH1+XyYOHPxHxsu7Mrsa5VMi3tkonxLx1toDg1XKyYu/4P3dmjwtFeeFInc9nie+rjoK3dpThEhK/cvRvkAV5FWgXY4qSPo9FnbGolwvyvWiXC8Kr1zHvfciJSqPYr+WXEooo5RC8VqV6IsWakNSvJaFUOOWZ+A2rrts1Wdtk8/6/3oafOPElmSifrJReUw/e5PClvT+05c0Rlrpu0WLtejYi44/LVqevc4Qf/ZqyR/T40sYGbI4jG/rDyajrLbyQP0i+hdJ15+1vhclHk+SsCjfi/K9KN+LGidLdhutIkvZWtdxRh2BsXLgxBGYUY6gG9ja0PFJrBgbB04cQX3po3WhvPQBDWtfRP8iyWsgn8FYkMXZAeW4G6/HK9/2UZoibvWKwR9OtPNGUycb7uGVMvfquLrvxIe3wlZd/bBFzbqPgKbbCzaD+uKks7/6spMtbmzWG/9R0jyUb/dJdCySwtj9zIts9ofvY61bHZJ5rWjx097rtffH1Hvxovcj9KDDkE5fSzM/HYaHG2k4wvynw+DmYYCDfDoM/HoY2DwMx5l33vRPh+EhdMMRZj8dhrAMQ45B6TCwd4dhpVbyYpz6KZP0N7ua7/wwJVUKwZzpZ+ewGinLdPYxPXtaD/5NpxKD/plXvL+t1fz5ByC9jn3UQd/wkv0dOrvP3IC4pgkT0zO9ptNYdrcF729NIScV0dr8VcVbmwS2KYy6J77q793Z6ZJ05ZmtllVfLrT9LcPOM9C9hsiOHB1R/QubXkk0/QU0N+lbY/pLcXbSt0ibpifHa4yN9Gj6e+s1JjedTk17Xb38sA2B5aNuSrXaja7WNwhtf5WwC4yyWioiO3J0RPUvkwg25hhdehAhWJ3v1flene/V+V6d79X5Xp3v1XWhAgeVubz8Xw7nM440H1qIX2n+f35tUc4=###4984:XlxV32DM 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124ceNq9W1uu4zYS3UwWwLcoG72VAUiJAvKT/ujPRu99+KoHacm+VxkMguQ6xxRFFll1ThVpbZfn82+5m4d4/GWUf2jrK2AJsM/nTyNlBp5/4r7t+UNpLn7/ZWR6WLE9/zHKPaTanxk5HlKb5fmXVeohj/35txK+PJr/hvZXreXvTxNC71KWLh3rUtrWpVoidLmv0OVahldHk/+q/lfP4zf9CzYPN84jTfOQDuax3ZrHr10t+YP9/WPf4iO3fuYPG3zY4UOqH/5T/pMfCWUC6ndtkDvKuFwL7lzH5fbIsyztVW0vOa4Lrmv7g+Om4Kbgeue4Lbgt+MLaZ5v0Ear2bnwmtr7kftS+HMdzXzKJ2lcivPe1QV9BwPy2Nj+Z2vuH+ckyLlnwFfrKJmzt92qnRfN3y4JvdawDrgq+134OjuuCp9oe7RegfbXrunO8tm92jRyvtqh2VQfHiy32Ni/WT7dFBFssij9T51DnbAzge18jVe3tBeG9r4R2hWcy1PaNa3aSvK+yD1Sb98rxsp9UtV/QHC/7SVX7LZ7jZX1UzLgNB9/iAbZ4gC0eYIuXIYn86uxpyVdPkw/z+x+jZfartXpYeqTuX0r558+80t1n1+5n4G9lTzxjEnb0WHP47rFS3/TY1KdZ+ubbLVjCi8UzXs2uVoaTGzezIM7nnrf3I491yf/B2e999p7Pfgt99gIiljnUE2JdB/TzNOiZdIxR3BwCo3ixLPQdqUGsDbb+xU5fbPWLRMBegQMAK2rfiY1zzZE1O3brK8X20uPoxhf0pHkWQBKwVEARoCugCbAVMAS4CtizPfJTSdP/9j1UqSX/v+vtqh88o1flDQvfS0vbS9oE2EvBDpQjBibh66I7iZ6QkZ7Z1bB1QTLySozDsTka9uGsfThGiavh2OdMicM49TzOd2SvOUkm4WayV+By6h7Ze5kmshdr69IkJHtzQJd+nKo5Zsur5zhnk+Y5i3nOsk5RdB2g5DzF2MWHP8D02Zm56fVsejObfFrfJJYr0ZTj+i07JuGv9IsU96KhD53sindkq5eoVwi+LRniRFypk11pwEk8rRwn8WILrgHXmSqy8ZmKWQ7FHxQFrwojBQivjqsILw8YmKgMmQcWKh4IZ0rFK8knguzvQaW09qR4wkLvbTSQCgt6MRgK1UJzY8RRLXi5chzVwpIY3sa/1fEDu7fx1IWI1T6R46iCvNw4jirIy6E9qaC0wbz8oB7sxhfIwAKRnIQdUh6sBskBteLIi0vHZZURKRLO5G3jS9MNW0RDfbB98IxB8xTYHstOW3poAgzEUR5hM91xIENjzx569tAzcraWjfurIu4TtYWzvc6L9Mga5kGMnTpjr58YW1wz9sDURN2Hm6lbjjG5yoBzDt+RwwdSvybzzt1E5uYIJ2SebeAv+dF95kdzzY8DL55mbUNkvUrfvLaXjGk/M+YyD9A+P1Gnv2byE+r85TX4cB4pj01aEM5jUxhwjEHkwxVHH/ZacRx9nmJExSlGBMNxiikJ2/shBkGGU3AWs5rhEacYJyLHKSZC1thwirlacxxJhUio4kBCf2LMy5X/cVk7SIeOeXTHDKeOKWcvU7Nj6tntTiU0ue6cpcyy90SRTkpU9f9XkZyyxISckBGQKoB+bGUVzor8WIoKkCiXRdW8yFzjRrGFbmx21B3evlRWhi2vZrd5J3/eOkVeQ3+RwsWbtaNYl+FMocbtZo/JXGi1GO9K3nhR3zIpfF6Fl9BkPoYmN6/CMqxCWi+kYwz3lGP0nf/LcjChFGuaZgveuLc1qB+ymfuHldNy3HscLA2YZIgbewXXgAbiUd7rLH7FGKG956l9hCpMHRKl9lGzflg8itpzHOMXadWKY7yLu+Y4xse4bRzHeBoxPkJlq1Va4qrJDkxSYQWmmTSASQOYNIBJUUNFHfgrsPizHJbjWPyJm+c4FpHiNrTHQhXJ7V4A/E8rUsVdwhRWLjPjagknFZk35na8hvggeoiPn0K8nEO8+ii15hBfWOFTiGeVDTmXKVghI8yFjGUuZGgsZAzVkQ/8MYd4HS9DPMYr774cXG7onim4XFXpwno3IF8VIYK/GZCtmmsQPec323bDZv5jmUXPNjOjza7KA2G5a7Or6kBwN0P8doDT+tGZJeEsJaQ4lSxEJQcfFvgw5HrR4yuGLDJuiXBOCcguyQKXOPiwwAc/sguo4LwF2HmIt5Jwlk5Gv8OrhwpA3HbeD6tgWI5j4kxRvuJYKqHQXHEslUQP7JWGAjSySBkPZ0HsR8eBBTfWD2NBYi8dB5baB5yxlOc4smDcAseJBSlLiIxN88bMsV8+yq7LXweM8bLH+I1i/Pu8uqfR74K9vs6rS4xf+l//mlaH76bVNWnuaTVk04U3zMAf7yvhLwSyzASi/1UlXIU5vYhzNrH1lpR3iB3zDkg3CgUtnIqy0noJ+aYFG0oyTIRgo74QvkIqb7S8RzgRpvJ8jqFfLBL3mrAaSsBjgBa8Jhzqgp1xqqLqx3Fc8YN+frsMb8+qxrEezp1R6W5v0kJ0c4+p9yjurtQxr9QBporfX6lerD9dqWGBlpnAJbx1+bxAn0WPfrlDMKyLuRAkOYbeXJcXAdBXejtursshxnXBYxZltv/Fuqi3pyqhVpjPFJYy/sYCLc9P52ru3IOOC2G167sr9SKs+tpv6e5KyWmlpAZT7TdWSg5HkS+Oc3nVBg8a36yL+3zMebYK0VyI0V3dFKOuy46yHEUe/ShWLMcD5bsutcpc67WJ8v6eka4OnjODiK0Jgf5duynKpj7MUmVMWRtOqXI9hsAHDTxIOTNcaCkj7W9cCm4kf1DCg9NNi7U8CPo500H7EEFIB0j4Iyjq/FRHoDoQzaCx4aJLe285T1FVKMIFkdpVs6hAi+Lk+2Wh+ppm0SpQcJgehulhmB6G6WGYHobpYZgehkk6fe06vbTkkt95GKbrw8wEBMMUMMwFhokL72HDBMN1c1wjmEPwE8eoD1geAcszXFSKVvIGChqQgof6TcMxQ4jrRobuM6vKe8WZoVKvG2UNNOM+8treLdS+WyKBJSwumAVLaLAE3KQqEK+LrSs8c/DzgVhvkGnAqyUWfrAQzcEbKGiAJxJYHGw4nmBEqfiDBh7Eo4+4LvBg4ufRUW/wYIIh2aFmZ3beQEEDSlugCNhwSlvqIQY+aOBByo/kwpfdwLJjoqf7UW/Nm/rTtuKh40nARBse2Slk66zhW8fVAbHBtgSqHoOEh2c3ioLq+dM+5E+3Lg6pIUuC7GibDx33/sVpDsSzJEyG7LeKZpDqTCUy/a5E9qWMJs0nKebNSUomTH+VCmhMBfZwRZhfvxd0rl+iuMgAtpvXRkKt/Z8qZ738H+YjL5TzJu7OJ1wJTe0/z+dNKe/iEvF4nhXV1VnRcXc+V2dFSq+f53Mp0MzHi19jFTfqqyOidFOyrXDuEvUgvQwwcIqj4pIcJ8VlDcdJaCnBcTyciI6173IQuXCFs6a8ji/XU0phMftfV1ESPij4oAddZTR/PR3jSCS/wAuO0WnC+7DUoKnw9R5e7+H1Hl5PesmjzJSDvjGCv57kixmGxeqOB8dJtVjFcaprQn20xBXO7VZwnChdKo7j7YfoGN7NIcEcZuHPkK4QuHOGGwrRScJ7XwJ1IKovMagfPcyDxI3e+DuYwnAcJ2HhhzGRsDA7x0FP/InelXroUv5FMtedzNN3Lxu9FkXdx0sO6uQELI/KXVz/MRtGoTV++fqP/nhiYr91hP0rKKjjO8elYVCe4+xWydD+5BTXDae4YRtw1H8hbhynWzGQIhWc6u9/4nqUy2T1X1xf09f3YOtL10J4rZWuh+SOygz0KTHghSc9XiI4oS/+W55fZXB11KVzdnAbIJMqOIulaN2GQ+wtB2ruZRfbNstDnM4yzJdfTqXbUIR+cxumi7pRw+VRLdMdMbx3QcWa611sn5fk+uVLbG/PSn8Vs/XTn2WwP9xdKDi3/yY5jtxHu9gunCtp19uFcyt5iV04WZFXVRyKA1mV5A0hc8ahcqYP6+v6+sqvHtm8XIVk0WkMSj2O2SFsYTICvwcJNc6fBqmA6ivp+3cU/fnwTk5zh1/INe/RJ6JdpyvVfiGaAlKZa7dcf5TOJyctHxiV4W9RalNSKAEpzkkeGpfdcxxDo1RwS7h9QbFRDTjFRjjjbDjGxoDKzMnhRl/ISaR8xGyqDXfV0neVutpV6iPnie9fsGW3PthF22NKbfkl2RqSYCMmcbURHeWIy5d/TKK/f+HLvlXzoWbrpzvysN/akZmG3ERDlD9iSf1YXmjoynNGVt8T8IvjqjEoxXFUjSucthec3bElF9j3wQV2hjOXoR2aBHcNcpkkuGs0eyJOnoEekMTgGVJznDwjsfc2997hV5jkZUkMXrOqWgDSpQBEl6R89xs9+M3oBKycs89Vm+ufe/Eb4mdn2lMtZmD4idjll2sydLsVj5v/trVUlmk9vsTX7m7O4o+ldLz6xY6nHQcFimxUI+djTPQQdBD/9XwXBlt6VnPPCdgAe96+fmBEPftaTNFnR68Svdrtw8HRy++kzHCSRAdFPqr5/BD8nH5edIx1iHfKaPnS7+DWmkXbk/qQ3v/dMvh9vvKFp2z0SzanX07ZLn9tNs7PHG+PQ/1ur6o6+PsvI9y3q27mK1W3X772ZXKYzLs8W+T5o2zK+uG/kceNfw==###4884:XlxV32DM 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12fceNq1W0uy5KgO3UwvgL9xZvRWOgKMHVGTrkENO3rvDwQSgrTTN2/1G9xKlyxjQP+DvBr9sDI+/yr//PvLJ/MQD/XPnz7Zh5Hy+ZdSa6avyma6LnT1kMk8gaFcZIYdHtT4oMoPikx3S3lQbvxBjQ/q8mAqDFvgDAoZVGHYCoPQnEEiA8wtwitkY4iyjRDrUH/JBK9Qss0t1jlk+g4PBv6gwQdNYTiAQeCDAh/UZbHb3ulll/5cjXy0nZK23iskE0J5xme6DUemm0pXIpRnFF5ouPhLiTot1bdSprKVKsAWi76M9laNb1ULvlW3t+4WnvH8rR7f6vGtvrzVw1t3HEHhCAbWenR6eRnsVpHwv7+0THAvswrcPAv0Olae+IHiyvR/42riI291ePiH3P/52+j8Hx3W5x8mP3GY5x9WlZf4548s3zzEH0b5hzn0sxDKrpRf3W84uGE6QQDBdoJ6Pn9K2IRyY+s3VuBMnbABYe+EBIQDCVbA4LvoHKEMvlsYXAnZOcu8lFCdEICgO2EBgukECwTbCRoIvg1e5vX8qeRa/69i+6UVWWnKAyq1G3v7ZfM/8nSVgxGj38p0Xf4T/8Dum2N5/m2UyzqhijyOLJmsuCARmXeLS0Tb5Vwi2vpRItqaUSLa5r35acBkn1khfJmv4dPwdRrZe7RZmAVnkfiOhLZA2JGfWWPriH5T48KskLgwfb+wrmp9uuMKl3mFfl6hGVe4jyu0eX/rCt13V6jnFUZcobhfoZtX6G9XaOcV6mGFyzqvcGsrtN9doZlWKC2uUL5Z4eXCcD3TMuy4jDAtQ7q2DPOtZWSnHJvDzuupDju/ozlsszW3mkngbrNlFnd7yP5M8ZrgQ5mDr3QW/A5O71HTRE7v4RY8CNFZ/C4rt3k+2SJrfMiKWy+yfNtFGCKGCbiEtS1BrhTpaKiAQwUcKuBQPeQtFmc1RejI6SyiK06XhV5W7XfN6fYJkamM79pU80xYeFyN6PxVQmWqTUK0U7rtoNAwp8TpZcezRRe64/SyswIC6B44vUhUWEqpiF4kmpW70Bl/05qVkothfZSo+LQhXbZ1QyBe9dHpbX0Jx1oM7kniiUrNimgs2HNY36I5nZKhniRtEudkhqwL6CAjWZIAl+1EPrL8H7GlAEKamgLIYt41B1iKrYpms9y4r2y6/DowQIz3U/SMDiQaWLDZEzqqnUw8oImHz2fQ3vRDOVNdQXUuPyyE4WdZe5zi3b7jFI7veZlqbjmLLcsr5vRneQkzrgW2ozHYkpFVBjJkJZv2wAgOJOgy3almAYWfaYhDyygXoFUwIGiVcke/x7RBuZ3TSXuUS5xO2qbcxumoPTm1PFrKmRPjdhNSUSWQbpEOKaezWcEeS97zlRLOgNqmWMZJsuM5laCcqhHkE5OrllSlJ2ZZJbla2m9Nspwt6qJ5SGmxX6ce/CNKW70Jic7qeShdhzIh4lALhUQ/hUI5x3gFoU/g4HYOfRYHD21wI+MQb9/lC5ryBRZfnTXzChxuxlWecKHyRaZVOfKYLHjWdQDdNsXMDFUx6wbCvVbHFEqtY5wV/V4bbwFFP/p4LFh2i7I1NDQGirJmo4loHpW7rdpW+8EEu63q5jRr5VRHBTVOOf7LXDaphyc1jq1uil2Lf8otNI/EPddLHTWUS6ygknNBpZgoZQL1znNxc+2A6ZknP+r0oIsvswEVHJTUHLOSilmxJNfapPxVCeMTam0uxW5LmKFS0XPaa+bUedTrXwkzszIfgEyyDIBuke4qIpL3r9AXVXWg0AF1KA8yV5lc5AwaGchn7tJyBoUM5DyTdZxBIgN50eRknxtADOhFFfOi9SFQP2+K+rnyR+q3NfXbTtXvndqpW7Vzcx2fVSFP4krgJlHN6u2XBe5uBf62tPtVNqVmOGaU/H50OsvG0mE5nQS+HIrTSc7JbpzOxLtyes+s0moLvJL34yEXklNqckoDvCJm+XSB7ccsMDcLTMwCk2+Al5/yOFoOI2YE5CPQxM6giZ5BE8BAECxRCJaEAQNp6MmAmmxzhOcwykukb4Q962Raiz4uZzoZPerkrgedFLNOvsMfXqpzc1udDwhL0Ykh7BLCovf0UdjN9pfGtRLwoA0BD8F+ea33SIS9zizOsBYPFelyksdojdm1UeJqgnaeoJ8nuLwgCl+ZV3YUZLCBo+rMgQSeJngqe4FOaYUPgtN78W4spxNosBzDOAQaeIMof5YoK0mXPXV6dWjHQWlLCRdZmVi24oPh4xNSXXWu8bPCwYfI31v4hYD5eE6nUtibgZ9KbS8GOpXmHhGJSqcSvBopzMfVvBAWAjKo0bbd4856UZxOobPmfkQnpyzVvvEb3YtTrF3dEOat43SMwdliS/GSUz3zCOTD9+bD99OC5QQMvvRix5t6peUNZ/XKfnxWryRbhrRn9UoMlCOaIUc8gfDUlcGJIRMEuZ/hhSaulAkud3jhpXXbs3omgVGf1jP7/lk9k9A/lAtWzyTU59T8BjA0vbWoh1loUM8USq1numpZx+uZZFr5UVhr6jk6kqbExKGRg1xQghhADAoZyHdRbVQZJDKQ86EaCCZeaiBYFK+BNKuBUnNpJQlVEUr5/EeGcTTDOFgS+qXA38L5u1rfzLX+PmUAxcryrLaLoGN2OsNY45eDzv0JxP0ZyzJEH4Kh80xZ9AnRdTqLGiEmTu9VL6WpQGdRyXA6aUJQntNJAYIa+DFqZPnaNMs3CoRqxO8LWH4uYCg77H4l4M3+FwJenr91iPar7Fvd0DxTfmgfVKfzswQKw0A/ETDQmYAHfnYyP9D7mYRwnN4F7Iotj1hclChgN5Qnai5PXtwyrzkIm2DYL2K+25z+mualD/UhBGf2+awS9cARBOfiFQT3tVDmIOWxZ/WEIyhOhEHZvh3CHMSX09rgkB9Ccobw2g1Tvgqh7Z1eYTezI+yG6V25qHCdCQTXSQStq84BE8u3GKq9NwwOGCjvcubgDAYZKAFzGF3LxUunhm5TBpDOhDFAmQFrjhigCjBTjjNK/S1JwxVquL4qwNVtAf4C1LnbAlzzAjwhLBPnhoet3Ujtd59bJGrpXvseSruDGexrl/6q/nUrHdUuV87R3TpHc+sc7bvoFxtYdqrj/rP6V0o4Ths8wNEQx0S9BfZ4AT4HEH44SeJo5jafomPfwirI8NMVBq+fL6dRDKLE/LJIi9U4VXiNDgZYdqsa4C4XvDfUcFLEZrWwHa1wiXBnk8MdOpbNz7jhDh3k7nhomjCnqAe/VDTVGRNASZltpXdAE6u1SicvsWM3VqWzoixyOvkEqnRhI7rJJ7vwedLB64G5DCysorzQNpUw6UqYdGUbBN9hWctUaplXqfryCuQj5iqGGqOiRs8xdkaNboC1N6XZdq+7maB5abZq1sw0RNEfFgCJXCCKF2Na8PiSIHd9eVDku2GikhaASs0RrxloVhsyUP/1I1GcbRlaz0PvODQVoWYbgv9XhxZu3gl0BSuFTpcukgGzT06snH0wXyCWqXgmX+A3HPy4TAL0bUOPOS1oVzO/VeFurb8liGwNzUzKyhoAgwdzaSEcxPDejGpBptBbx2IRZ7sw/PyaWisrZ0DOgJzdjMH6GmfpeAXOdmF4I2zCc+nCwNohUytO6yug7BYOy246uBF4spOXy7xFx5SAzrwdDaq4r01O8QEVDkjus2NLwg7uTalOb/ut2n5r5bgHggHbGU94Kb+oL8PelF+tlvqkvm4V2219DVniafnVg+51+eU/r6/th/V1Rx3jWF8zOq+vN8HpJ+UXJrJzfY0Z8FxfA/2kvgZ6L7+SMTOwGC0K+LhEFgdpfXZQcgIxGnsBMVptP4QYjZu7FhrEaDcCXpx7gRiHw+XzAo1Diy84psWXOErL1o/rMX0OKS4XkKLV5lNIET1uHnOAFBE2bGeWwNA8sUFPbGzzbYZ8m9H93gApqj7eOZJo8BQbTzerWi9p5QwKGXqzxIrOzbhzANFYBBCXsT5bBgDR9yaK48UAXDMAqb4Krf9eT1DS4soA1PahAWh5aQDyjQF81BuUtL40AHFvAPft0+eWoNWVJaj4oSUoPLzSarAEjRqtW59lYWiWoFH1srSqJWj86CGpvd/jlqBSH+/cErRslqD1uSXo9gFLZeiW4OmV8twSyjTBErQaLcFzS9AaLcEmCf0cqvdzxAUtQfOGDiou1qFCkHs8rRAsCP+soV9fJfM3mbYF7TlroNfhWyP+0kfDqspki3Rz1gSNy0kiffiIxuKHN4WfA0VbOwspdEgiy4MsiST5wIuKfAoDk4/Fj2uADjPZYz3qMC+5mMdQvXwKhTeX9QYKb6nXPudzx+DU8rTs5VmH+QYU7m6hcHPbkqPHsw46Wxi/X1tjpw9QuOb0s7MOew6FK3sOhSt7DoUDnZ91iCzcPRtgL/dXFLC/bOgbwL53gKG+7dhxZx07ozrdtMo0pXn/xVH0+rJDZlf/l+OTe50ZOmQ8QM3n5zvxzQTvmkXMJ5+f5GoBvynUQ5vAGrCN3kquuR57Vguda3o/lBliBTvEkcN57aE5vX8oEgKnk2WEuPB5Epbote101gzHDoMk7xHpVYoeWhB7VaOHvoteBemh76JbquZtF//GNRQXmoWXvehBNkat3+udjbnnab6Etvb2POoVgu8B9D0UP6B17/C8+B7Pm6P0xXeE8C3LfxZF7g9USxTBVPiHcmv9FlGGSw+xflLhX+JgH50YrGG/SGHsd79JNPMJMuJ5Jn3hBPnlkOSlk1V/AGEMKz0uUiv7zW8T1xguvgW03/0WEOqlc/iHepLW7T9MOe5P38fPH+Nx8d2g/e53g64d15ShISvMlgKuFNsIteCudF03Tmftfwun93ZBrIi8/h/5qEFw###4680:XlxV32DM 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RwkWXyHeQHyF+ArxFeJ3SDUgDiFYaV6Hwzr4QhY3+gzRRSRFQe93A7+lbpsrpNL3QuAOpPTa1xFuQJQUs12IPifteGoXhDM23c9GPijrZvWoxOqdqJ3gSGeCd77aMGfrKoVTDnnhRHbAuaETFb0NbTiu2LUTnbMWp8Uk+Thy1kzSA+w8JO1BzAoKlc6nm4HmcPqssEeFPTTsoWGPDfaosAfFZZT7vr4OclF/jOI5HMdq/R1ih7Qd0gwecyAKxFaI3SGWQj7Kjasom/AYpeTAv3TyXSy/o+tCZJIQ8jPcXtzduPk/7E8088do14/RkB+j5abbsvaEUxu3zgHTKIiF2jt1xgjCgvBChFNmK/7j6P6ckUHuiHi6xqywg9JYTm/Wj9GjM2XArXfrB7r1Tnkznhhc0ngijXlxPGvD4JdlUYBOO2aZfcgH1gIRVBWsHvJkb+aZcJ2IMG3Ewnh3MMJ74UCff6DPP0afT5DDmD1BVAx5zHZYJp0KZEkGhBiTGv2+AF2wAFl2hJCYPJBhvALT9sNAXx0sBa+cLg3DDgf4Qe11mGzwMA6mDdDaTDcGPTBxTz9SHP0k0RfpNRAsO7ghPMFcecgeoamnxBHmUR6t8H5E2MSUQYi6rRz8D7goYYs=###6860:XlxV32DM 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MlSGJwHlgn2NitQVPdq7vkF0D6LDYyf9ilgUZQSUkT0Y6cHIDPI9yG9ONcirM0pbrtZQsEokcdKQIXGJ03+Cfgo0guoMqpqrpJ1t2o/g/SCnOv0GwjgpcDK9PUX7ve7Ns/037D69Lcg5mUE/B5rByQhOlsbsp0uhPD1b8PTtzgyevv8R2B5REuPuIfaqgAmbVdkc6hjqX89PtMO+/AT9HjRuXo2yUD8R6idCff16deKH7vGqxRYE856CZ95brLQYGQ4qwXDdSTI3/1ru0mgjVCxwTwTuKb5qe3zVFl+1iDU+dSiE7SlOPmJ09SAFRdatlcMoWi3dHURArmvZtu9s+xJL8LpHoT2z3O7hFdgGnYTl2/LA205pByxC5fwQIe+A6I5ZBL0VsIhjI6DVqE8vmCQklAzQHYEe7aXmvC2P3zSRtd1KHoI/NawjZSxrI0xSZC9sHoCkbYsy0+bWpqohfs681DKqxDNGtQfV4VRN/1NYjNJaoaAbVJ2TTu/x5k0C5p0qKppQUXMipYehJlIYo/8E2fEPWzY8aaZCRu3DUNTArFrztF/TKNCd/7jHqmi2NQ+X7vHP8rRbGwnnMF83vTvT2RzB5gw2V7A5g80SzH0MR0Zv+eVD5itElINCObtQznY+F5ZRw+lU+Ax1nKpq939ULbzIcepTDxXNLK/INaqF9OX3s/LF2SN8ykbxwILep2Csc/w6A43CLweeDSwC2jtSihmBvqnE3u274mSfIJsCDc5wo9TgpVDyAeMkgu2MD7JdpXRqUo/gZAQnylN27qTvEebsKnQL7mbwlAPpsXKJ6+zNYKoGUw9M7TA1g6kv41rBVNQgaca04C57vG3Ajn/+HLBEYr5q0QNuyQ8YoZ/+W3fwLedGzysQyysQlq3eHsX5f2eaplwkS9dvkcFUpKXI487HovonCrLywf0lP4N8D/IjyOPCxQWYLx/Bxw75O9z7RiXkhxE7yrb9xi96g3HhvB5PNOwnPX+VKrzxNoO3+LoUOPoKMTMYSYFGfHH4vrBuIs2Ufwjd4Zgfm7D3xRvZ/zVUn+HsrWBvBHsT9ji4/AR7TzCVA03Y0w1IlECdvcn3rwI0DzrTT4qjvWGHJwGaLB2XJkvXT7J0XHRFkTXphWOj48iasugpU3D4BmjWpN1ZezzaPW272/jJo4SI9arQn3RYslV/8qhvEgmVciKFp6/3KS9abZbXpA6aoHSk+X2xdb0szZ7mT4olRKwVgfYT5UTQl2J9k8i1lBOp21m/gRTwjkaTBX0kmY4QBRfttNrUIJyMvv1kX0LErsBvB8qJoC+xyqRoWmZ8sh+hlEy/zgUNcO9Kc2bxa3nVP27+DWTnZI70k04JAwpETzQxUyIy9CVmwq7NJkOzi+lafy6mM79jZm49M/e5BlyXtOTn7y//X0U7TyrFu0d/xjisXmK3nIni4eaThF277ox7TxWuXixpXPozbZA9/Iu8v5qql5NWUEzaDzp+mvQ0wqyEmsf12xm50xK4876IUrUx+F27jmprW6vq0I5kz4RtiP8rRYKj0o976N932ScJ4/ZMblhEBO3stb3ICFUAIabu3KHxnGwddeiJH7QL68xBDe6pM2ByYZ05w8E9dQZMLqwzxzu4p64ADnyrnPzDhXXUgXe4rlxYLy6sq7Y9+Jbaa6c98z7sg3vm1y/YUT6FVqlM+1Dev5sya2PK1BTuqJh4U7oDfti1nxOyU+n8tqGTrGEyXTy7vHkvFfoK1Ve8B2CtfrQ0a/Xn8BYx6/Cj1U/Lh4L0mO21zKQCaAB1snpVL8dsPYuZ5sVJ82KmeXHQs1gBONKt4lEfehYzYNK8KCP/D6Imiv0=###7060:XlxV32DM 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1Uerrd7/g7qjwfKg1wkPy4NIncQvWU+UeLLm9+4lMwsR/LlEdtQdaegf581Hvny2EjeN84FxngOvZUBf89KhAHVHw17dJkhb4OrttaumSmLyd7jJ3+EmXgv0LWx0dCjHUcWXr+IL+jSe3s/16UucN/FRll2YjNavUru94D2ANH6wL4Ca6q+4arevpFI4Mf8CAcAerAw8GbVPET3jNvwNUrEPgHKsfYDoH2Bz4aZkiijIQpyDJ5AKtiXyYoVkpbKSPZgcC849HCYNVMV8DWxW/mREQvtpX4W6PLrhtGRYWMPLfAnWCQ5rgEkpceuuTAe/fS89377CgKNp3/z0aV1xJ5+3vvMOAxubd359tj/9Nc8e4dtXGCLpvJE+fXY4+0PY1FBStja15JrccJiHkWL/Zzdvyzi279Tfw7HhD8c8j/t7pWX7c0c8v40zuwlkMBNLgS/GPc+swrjqyxV9ucvrMJ7tD6CvEWwS2aqI/FUE+y5TUqVZwP/P/VFSQcLRHwubQrKj7mhSScuUdH+nDirk9zQsO+qOpikpU0mbj4AVaZLWlDQopyvJuKbnoySoP+EdORT3c0aLRExJ11cRBX2qpFtPj8JaamYeyBNCh1mjqRl/5FvPsVcar9BtI22U9ZmFemgUO3TUDzwGLHw5N3+3aJtB+nnoRXpkyj9qDQYpf8zofNUdWZcxZH8V3MxrT9wH3iaUXk2ORDki5VAzlImWbp8oOWsTOAkyTjcqjflB0kiBtijH7BwfcszkSNYW9J7nt8pjKR4LTHTLdD+4uh9cna7RpBiUIlKKQSmKSzEoRaEUBBbBnAd5yjzhjVSbFvrIMPX/9Wa960aaTzOWatf3NVD7vZC8MtBYBrUCccMgrZXeHJQJJJ/zdPwJ8Og3uFkeCwRis8+VMEgdsA/KBPqw5ga7saoNsmJnIBBKoyUOit9BmUAfNT9I0cpzbh1k7xYCgb4VoeDWlNnX6e5FBWtAT/aoQp4tDehJ3hhhEAXXWE/YLTqVNagneSRklXh9yFL5PMDewcOd7vRwZw0aQub1KsOmLOGnacbCZwXJfqHBIO3L4UvzMGO4/kMSNRN0Z/cozf2huQtHGc38o6lGabnLzOTrBpDl7X1gpaecH0kLMHLGDXGn59sn1/QkCRC9Y+frw06OCst+ZqZ/CWSXGzvZmqeGD0lNwWT+YieZGpDcLHjw+r5xubJ8biboSjKS5Kaib1fK/JI8TN8u5pgzwE9KvdXV9CG58QibUp4fSej5fNKDIH5I/KAyfmr+0YSiD2hK06dPbkv6TkXnlfThZ4qmXzR+k7n0DAB+5UNTNY2krtDEC65TFjWd/ofmYco9A4Am9onNa+gDzf6leZhW969XmJbPACB5fUhuDjKSPKRNG4UkNzP9GeD39XTHlvkjaZpOj5NcH5LpMNX/+3qbVYdMoEZW1ofm1dgnRnYdbIVrIYnVAlZuQCo9EnbpX161MdmfYLcX35nZaO0L4UvysG8DaNpdSRaSjEqyfEhul2QpyWy5/WuhQC19JlNAovs6eL18HbzrN9paAKaP1PnR5+s/eat8+6SgtTrst2lilXwTVmDFCRb+jO8hX1VTdzVdH9pX4/yptAfV1Kn5Qc2Pr+YrSQYl2UiyU/PDNX++JA8JSAklIjWqYDtJ03z/kFTNR3rmppfi6x+UUrjexfVitC08wmcabdP8/aNtmo+Xa75/+2S9+pOoal7/QiPftMl3km8AJf0WAuRbGN+qfJ8PbdV8pK9uEb/4CTvVvNEepC0Fqgg/1fDWELS1CsZHdza/cZCu6cCT2FIKP0EE7UTFmbgRd6aW0o+kPaw69CTXGT9xddubuJmARihRmi0gkbYuN+UPbVGFTdM86sUDoeI+IC3mPy5mXRveqtTKUvWml7JpjaNFO6fVL0n1pUydN0QoRvJh6GAk14ek+tJWkUIRz+kk3ZeaC22sc7EiYZGDpsP8vK64rto0TRTU+e3r/F1R3Xq7P+z426HF8I3etVUGTY+zix+S9s9hdaVgs9vfkYUk5fjrlmj7/0qdxL0=###6932:XlxV32DM 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DBlltGhnU8N6QW/2KQz29t7sM13tsIONtau/dbBXd7UbD2sWU0msa0x9tsuUWA4QMsq90k/1ym91UmLmNr9vXDwd8e4RWqDtLEIb54dYvY/VRcNULjI0dZHeNSZeUomPzelY3dQr3Lb/23kkHtZT3MDlaDdx401syGedpmeyb9JdLM8oP1lpHauBQH24fE/COmf+NZAjcvTyBa1H7HQXQM+jEln4FBl/fcCB08CG/XT5tq4U4LTbgz16+bI2LOA0omJvn+GmBESFvVoJEad+EiVy4q2VE0O5hHtRvmBcxLsqM+JQYDFQ35ImA8Zkzw1EowGAunh36cs5rWJUZDHKfFbzB4RyTl1F5JqWH/P5rCiZ93KdvQ0BFbSP7kbUPHFmrKBkTPQJu5nEVQnalawLEAtUqNkbF+stcP2XS32W4+tLqF3c8vgXQIUyLsHscv/i0pczJKS929Yr0JYo1hfAFMBntUKN8rJpYMOradSXRjf5zVXml9hwaCgxPxcUEh0oKoMzMM405xoAWTL79qTiryBh8guqU1NDx2kAio0NyZjpG4kKh/HNOzSEWTINyvRSprBkuinJS0kGJXkpyUtJBiV5lySekkhrxrD2Voj0UiQLb7XKYku2uhuip4nFScuSfRAeULDxYAdJsyXzR2sKlgyNhLjVrtWPMZeUnWfk2JeTjC0K1f62LV5YF+i1xCtrX+q3+8Wl5zouPWl5tkP9WusXmqonu6GrEs2T6ALRIKDPkekvBu10pRajWQjeV9De6w7SEMrV9fZpK95veXlrN35dWS/Gynk2YDGxW1lCFVSF00tbphe2NGs5ng3dGKmwkHqF5b80kLkQ0pyOx8IcPHqxNg9ry8alPr+4LC/4rkYfC8NC5jvMwwbKBU4wXGd128aG65ceKp9/8SONG2vz9ostYc0f/hVvvau7X2g78g73wRd5N75wKn6L0MgbQYJjhbkzPWbW12fpg3smdKaRdC3tFxwNsbRVwaPLWncloJ4ISRuxQXFBLzvlxekrpId1TrhcIL+1BPTFeIA+DyqQdJ/hqVQbbgQroWq1sDJfMxFjW+VUi4Rs26vNDiAKpobj4wQ/iKEEqnVDttdZwbNYr6QZo7LVscT3GGflzVo5301ZniVnO3CqQ30oS13PLzxerKppsjx73MbpfM6l9YtIcly35BjlxcR3Lp4B0upZj7e05n2A1V9I+FuSAIyn+CdW0Da4bzKL8wMd4erMWxeb+Rbd6wjYwgoAv2/K2JisN4IF5qH/GqBHLPAiGzgRNiCo90L62XCTuLlcsz6MPN+QwmtPrk/DwT+yAtsR4OfXjF6fl/RNFnpOhrL2lhxhfePdPOmGJXvMxHZj8mKsrNV15LssShFusi6a27l+RbycDA/IEX6lsCzsRxpMs0Fz53buldvRTTzRIKn1WvmXS2vXCnQA1lgjZS6tegrqIXG3P8D+91/jr5ElwBNa6Vpxbe6TaX2hnaevdZwGq09r8oO/W7beN87y0TEt3HPg9GSmiKRJ6zdxyB3X5hcuHjidz1+LZ+Lpw9paxVjrwz1vL6G7zwrFxZ7tCa/CgIfL3M2To6DRKAT0Dt2eTZQscIS52yoNuNmMdEd88Y2oQuKKLVvuQOHwADDf0hQ3Nk7n19qmbslOA9snqZe+zEoV/qBk4zwLBTKu8C8/LQD5yh9OXsXVQ5aXrlZ3eWtrsce5MNasDDmf4Xcxy569vY+jsZhZNwvwAzeC/aogV500P8Dx+MljpbFd40vD2s9We5Yt0lzhwKKzK5GVUfkkoUfJCRqVVaZQnFgp37BS5V8KhkOrNDoSb/76Z95jrmPclh/RZybzjflFP5EEcaZdZT+9XRbDVh2XRWvnpaa41QzDNm27uIizi6vRmgkdDrXygk3s4dJCtOyyxJr4/wFPCQC9###4964:XlxV32DM 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be0eNqtW82WpSgMfiUhiWDPc8wDVHm9y97Nqk6/+6gIBkgEvX160VUWhPCRfwLQMCDgjEQeZ3qTB6IJLAz59/WnNzqc1m8TLuvvFgysc8mv/94IYNn4104HVzoGXP5dpGN3OtvPo0KFmlTsttJOBT+gMiVOoMLFduMyMlw+oWMTnRyZk44pv4t0BkYHH9M5T9uo3LgmFQCzjpl3KvCYF9zlbf4QGUhUjIoLdlDxiRf7AZWcl+07Fvq40HqaSPvPij4W88wm0bjgAnjMCzQCvXIsZXTfRIT7iYb5+5w/f36Te02/hl/jz2+0469V7/75Dy39sv/8ixbX3+lnYxe+GHkbyRMcWwBxC+MuHMI8dawgpkDKIVBbxMNauxGpj3JVpP0obJOOZSYAVX7aAuqY4pqKit+58R2iFXdlyGf4nhS2I7bruciYQiFaif94nuuoRTlTJ8+sBM0navbKMETDSkbdd6LH1uVnt6z73PZqRX6DQTlnTvu8bTVi8wKNQO8c67KxeIyleuyqMBbN4ZwgzYqKahOF61nmUE/O11LOaqGu7CXIxsjMjklyYgs9DWNp53o+xx6naQSMqNrtrI4t8WR7DOboazVHFMwRzENmjgz6n3XrJjNH0w6HF+AAdlymECCTZkVBMJvIiozH0S6NCKMdOYH2lMaGv5Nq2rCKbKbOKCvMfe0GyShUfJMKHvGREYxaULEnMUDvyYj8aDsJZlPd0Um1NBJhB4cgr99B8bcgnqIuVXP0u0Fov5nQOtMrtJKLHlUdjhsaSytxiKGVxfD4u2YhqfQ5Nw/fpXDJfCDOPokzKVR6koYxJQ0kYKGhrXkNhYvgsRqiOGqiuBqFq5gJCg/LTM9+5ofVPKhYUeGupCqztPMqtMshtF8+E1rE98/GTBX44WG0T8cgbQIrh4WHE7kWRRRzvT2Tu3n4dcCBYDrEGZItqwVxO4o8B1Ts6r7SK+ZZD3mxLGNEIWDs3hPL9FChYjuCaZeC6edUgmTMF1lnz44oUdFxGTp4GRIvcqYHfwUX6MJF5uWe3AUqr0SFmZFEoaW5gzAvOpkzZKuipCqYhSM/dZmbqoPZU79Fk8Vcm2IXnpjjTjRQSGCBudwuFAVkTLHyUseRPXiKsWovjySkcpit8Wxv06O9+SKB6JMwzJ2iki5pMtxOyA48jmRaCbW6drMIAZrsFfVT7fG88qm2PS88mnVPl9vJeTe3G78hhHmxuJu+8rh7HLe422YhjEuCI7CY0r+6DrAvmZI/LXwx8jx1rAQJVKYu8fzA1F3utzPyPWl8EoL5iormCqeUUWhYQAcvkHipKyGn6bAXkfiknCaxCD5markCjafEMEEmMWZvSORpcILAL6vAYxT470zgv+cfGDulfdvbuJqt5UirpTn875JzHB5LCqZARUr6e6mksoAQHuQ6gw2dmTpPZBKR8PFs3uvZwHE2yys7Gz/8rLv+uuZy/UrkG7yaIkTTuQ1XRaDW4nKbptkj+kAHKekgHhgtA6/uQW6wydSFEtp9AvXXkAr1kubnYwXGxVtU7LhysCzXAoVK+6JgYFSMCD92FFVCKeGlXDekHcUriUYBXkK1LCeLO+k+S73AHO+t2jU8p84NUaJhEdYt3o5o0UQxNqsYT0GMCXJVt/57uzPL4w5Mmh7rP3qwF8ZSEeyRyjZktXrtOlG+Ru9LKzGllc+pYBJHEPw6/hXP0UuF1fEUZYcOZcdU+JbKPL1UNGW/R6VuU2jJnoZtKVuyZyFWg9QQjEWalmkpr7oZvw2Zpnv8NjTo2pSVxYDGaoo5611tEBCBJiIgNBtUXv4SBx09uLBVbc527Q+m0/IIoLgqISdHABpjEwuRNchiCD5cZMxX4gtN8fXdQHomGLYhGFruazv43f+vwklxtDRKRrr/TNQeH42TZ/1B9xwQJQckVWp7DW3R2RNEGs7AH/2SifQXhKSsXs2fhr+Bfq2o0r3kwFJMU6WjniWu+k33NtJ1mwvXYaLlU3f3++UC0siRnjOknZdSLDz4LHF+NXE+Zt7AOe6MLk275uZ7MDEME4qYEMckj0WnVfpIlL4xSnH8/8JajFdjBAtQ5wqjaCng0hq6pi005S3PDSSLLsqA5MiQnPLk1M25dOWrzUeRYRbTeGFsF5IaKvI4OYh4gk4RkgZsHMcmd9tbwkOi5uGjzo1jppKJSS1LeMgYb3xbxM6fJFln10+jE+UOcsiQS/rpOXJ5Q5Nzms2ix8gpOexFAIfNMpBUh4in1Eq1TCrTJUQmjgjm/pJyf1kjcq8AriEyqvdF24yp6wYn9KGb4o5Ibn6jNJYaSMse03Tciys+84ujPeaa+5I01zGfeU/+nGKhgN3/1rhM7G5Ob0ukCu07utuDn6i936zgvtgMvWX8AV+VefBC2mQZGstbRlUuTbqRxMvWVY7VVXvshV4/1LX+qybNe/dJehEJPbRNQ7JNKQaYz/O2L8rO+7VGmHlHVGjsIqUVV1rRi/Vcd5dXsWGvp0zkWZmIdDoPG7Oj5bhucotXGG+c1t/zqzmX39MrjW7XuLNOk3Cm2y2xi92ZeaOb+aat5IBVySH2Wc43K2Zy/53NSs+SsrZXAyGwvlgtQTcIZoTYIQ0XCfuN1cS9sdUae9PcHrHw+jpYNrfOQrs+ePbULKD1Up4wUfdDqCEVOvAxFa2JsUT1k87eXlwg4cLKJcupjhbycol9vbfLk9zK1g8SgOXgg/DAg1gWPrCYDMRnJCVlqXY0qM8eKFUX5VVk7uXL93Ps9eW7/FSl5Ie99KrGVi/J1LGQ8q6esa57LGaPZAZmsOqaFDKDlleloPNpDH87V3JzvuFscx7GYjE2Pu8ZKs7D2PjgZWAR23CH85S9DfKTupS/9Vz/lc/WnteBW3gLD/2a8/nIdocqndJxqcGjEm329BuPySyjUNfpfY7YeknMrVGr5zjyA8K5+k4qPf3lfe4m610OJv7NI67CxLtBvh8PALmsu2oRuqswPc2JSRNofTmi1/I3O4ukSK2OKQb5lV96lTFW796ksfxhWkdr6z46voNc/gfmutdW###2932:XlxV32DM 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.map =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.map b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.map new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.map (revision 224) @@ -0,0 +1,168 @@ +Release 14.7 Map P.20131013 (nt64) +Xilinx Map Application Log File for Design 'chn5_mem_spi_joint' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd +chn5_mem_spi_joint.pcf +Target Device : xc6slx9 +Target Package : tqg144 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Mon May 23 12:37:57 2016 + +Mapping design into LUTs... +Running directed packing... +Running delay-based LUT packing... +Updating timing models... +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +Running timing-driven placement... +Total REAL time at the beginning of Placer: 7 secs +Total CPU time at the beginning of Placer: 7 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:30632a50) REAL time: 7 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:30632a50) REAL time: 7 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:30632a50) REAL time: 7 secs + +Phase 4.2 Initial Placement for Architecture Specific Features + +Phase 4.2 Initial Placement for Architecture Specific Features +(Checksum:446118e3) REAL time: 10 secs + +Phase 5.36 Local Placement Optimization +Phase 5.36 Local Placement Optimization (Checksum:446118e3) REAL time: 10 secs + +Phase 6.30 Global Clock Region Assignment +Phase 6.30 Global Clock Region Assignment (Checksum:446118e3) REAL time: 10 secs + +Phase 7.3 Local Placement Optimization +Phase 7.3 Local Placement Optimization (Checksum:446118e3) REAL time: 10 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:446118e3) REAL time: 10 secs + +Phase 9.8 Global Placement +............................... +.............................................................................................................. +...................................................................................................................................................................................... +......................... +Phase 9.8 Global Placement (Checksum:452aa732) REAL time: 14 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:452aa732) REAL time: 14 secs + +Phase 11.18 Placement Optimization +Phase 11.18 Placement Optimization (Checksum:40b4b175) REAL time: 18 secs + +Phase 12.5 Local Placement Optimization +Phase 12.5 Local Placement Optimization (Checksum:40b4b175) REAL time: 18 secs + +Phase 13.34 Placement Validation +Phase 13.34 Placement Validation (Checksum:1bf721e7) REAL time: 18 secs + +Total REAL time to Placer completion: 19 secs +Total CPU time to Placer completion: 18 secs +Running post-placement packing... +Writing output files... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 0 +Slice Logic Utilization: + Number of Slice Registers: 564 out of 11,440 4% + Number used as Flip Flops: 564 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 739 out of 5,720 12% + Number used as logic: 731 out of 5,720 12% + Number using O6 output only: 536 + Number using O5 output only: 34 + Number using O5 and O6: 161 + Number used as ROM: 0 + Number used as Memory: 1 out of 1,440 1% + Number used as Dual Port RAM: 0 + Number used as Single Port RAM: 0 + Number used as Shift Register: 1 + Number using O6 output only: 1 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 7 + Number with same-slice register load: 4 + Number with same-slice carry load: 3 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 337 out of 1,430 23% + Number of MUXCYs used: 64 out of 2,860 2% + Number of LUT Flip Flop pairs used: 850 + Number with an unused Flip Flop: 375 out of 850 44% + Number with an unused LUT: 111 out of 850 13% + Number of fully used LUT-FF pairs: 364 out of 850 42% + Number of unique control sets: 28 + Number of slice register sites lost + to control set restrictions: 59 out of 11,440 1% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 74 out of 102 72% + Number of LOCed IOBs: 74 out of 74 100% + IOB Flip Flops: 1 + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% + Number used as BUFIO2s: 2 + Number used as BUFIO2_2CLKs: 0 + Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6% + Number used as BUFIO2FBs: 2 + Number used as BUFIO2FB_2CLKs: 0 + Number of BUFG/BUFGMUXs: 4 out of 16 25% + Number used as BUFGs: 4 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 2 out of 4 50% + Number used as DCMs: 2 + Number used as DCM_CLKGENs: 0 + Number of ILOGIC2/ISERDES2s: 0 out of 200 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% + Number of OLOGIC2/OSERDES2s: 1 out of 200 1% + Number used as OLOGIC2s: 1 + Number used as OSERDES2s: 0 + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 16 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 3.79 + +Peak Memory Usage: 367 MB +Total REAL time to MAP completion: 20 secs +Total CPU time to MAP completion: 20 secs + +Mapping completed. +See MAP report file "chn5_mem_spi_joint_map.mrp" for details. Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.mrp =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.mrp b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.mrp new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.mrp (revision 224) @@ -0,0 +1,291 @@ +Release 14.7 Map P.20131013 (nt64) +Xilinx Mapping Report File for Design 'chn5_mem_spi_joint' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol +high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off +-pr off -lc off -power off -o chn5_mem_spi_joint_map.ncd chn5_mem_spi_joint.ngd +chn5_mem_spi_joint.pcf +Target Device : xc6slx9 +Target Package : tqg144 +Target Speed : -3 +Mapper Version : spartan6 -- $Revision: 1.55 $ +Mapped Date : Mon May 23 12:37:57 2016 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 0 +Slice Logic Utilization: + Number of Slice Registers: 564 out of 11,440 4% + Number used as Flip Flops: 564 + Number used as Latches: 0 + Number used as Latch-thrus: 0 + Number used as AND/OR logics: 0 + Number of Slice LUTs: 739 out of 5,720 12% + Number used as logic: 731 out of 5,720 12% + Number using O6 output only: 536 + Number using O5 output only: 34 + Number using O5 and O6: 161 + Number used as ROM: 0 + Number used as Memory: 1 out of 1,440 1% + Number used as Dual Port RAM: 0 + Number used as Single Port RAM: 0 + Number used as Shift Register: 1 + Number using O6 output only: 1 + Number using O5 output only: 0 + Number using O5 and O6: 0 + Number used exclusively as route-thrus: 7 + Number with same-slice register load: 4 + Number with same-slice carry load: 3 + Number with other load: 0 + +Slice Logic Distribution: + Number of occupied Slices: 337 out of 1,430 23% + Number of MUXCYs used: 64 out of 2,860 2% + Number of LUT Flip Flop pairs used: 850 + Number with an unused Flip Flop: 375 out of 850 44% + Number with an unused LUT: 111 out of 850 13% + Number of fully used LUT-FF pairs: 364 out of 850 42% + Number of unique control sets: 28 + Number of slice register sites lost + to control set restrictions: 59 out of 11,440 1% + + A LUT Flip Flop pair for this architecture represents one LUT paired with + one Flip Flop within a slice. A control set is a unique combination of + clock, reset, set, and enable signals for a registered element. + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + +IO Utilization: + Number of bonded IOBs: 74 out of 102 72% + Number of LOCed IOBs: 74 out of 74 100% + IOB Flip Flops: 1 + +Specific Feature Utilization: + Number of RAMB16BWERs: 0 out of 32 0% + Number of RAMB8BWERs: 0 out of 64 0% + Number of BUFIO2/BUFIO2_2CLKs: 2 out of 32 6% + Number used as BUFIO2s: 2 + Number used as BUFIO2_2CLKs: 0 + Number of BUFIO2FB/BUFIO2FB_2CLKs: 2 out of 32 6% + Number used as BUFIO2FBs: 2 + Number used as BUFIO2FB_2CLKs: 0 + Number of BUFG/BUFGMUXs: 4 out of 16 25% + Number used as BUFGs: 4 + Number used as BUFGMUX: 0 + Number of DCM/DCM_CLKGENs: 2 out of 4 50% + Number used as DCMs: 2 + Number used as DCM_CLKGENs: 0 + Number of ILOGIC2/ISERDES2s: 0 out of 200 0% + Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0% + Number of OLOGIC2/OSERDES2s: 1 out of 200 1% + Number used as OLOGIC2s: 1 + Number used as OSERDES2s: 0 + Number of BSCANs: 0 out of 4 0% + Number of BUFHs: 0 out of 128 0% + Number of BUFPLLs: 0 out of 8 0% + Number of BUFPLL_MCBs: 0 out of 4 0% + Number of DSP48A1s: 0 out of 16 0% + Number of ICAPs: 0 out of 1 0% + Number of MCBs: 0 out of 2 0% + Number of PCILOGICSEs: 0 out of 2 0% + Number of PLL_ADVs: 0 out of 2 0% + Number of PMVs: 0 out of 1 0% + Number of STARTUPs: 0 out of 1 0% + Number of SUSPEND_SYNCs: 0 out of 1 0% + +Average Fanout of Non-Clock Nets: 3.79 + +Peak Memory Usage: 367 MB +Total REAL time to MAP completion: 20 secs +Total CPU time to MAP completion: 20 secs + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- + +Section 3 - Informational +------------------------- +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. +INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: + 0.000 to 85.000 Celsius) +INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to + 1.260 Volts) +INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report + (.mrp). +INFO:Pack:1650 - Map created a placed design. +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst_int, + consult the device Data Sheet. +INFO:PhysDesignRules:1861 - To achieve optimal frequency synthesis performance + with the CLKFX and CLKFX180 outputs of the DCM comp clk_mang/DCM_SP_inst, + consult the device Data Sheet. + +Section 4 - Removed Logic Summary +--------------------------------- + 2 block(s) optimized away + +Section 5 - Removed Logic +------------------------- + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| CS | IOB | INPUT | LVCMOS33 | | | | | | | +| DATA_INOUT<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| DATA_INOUT<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | | +| MISO | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| MOSI | IOB | INPUT | LVCMOS33 | | | | | | | +| SCK | IOB | INPUT | LVCMOS33 | | | | | | | +| addr<0> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<1> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<2> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<3> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<4> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<5> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<6> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<7> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<8> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<9> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<10> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<11> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<12> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<13> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<14> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<15> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<16> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<17> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| addr<18> | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| chn_bits_acq_ch1<0> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch1<1> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch1<2> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch1<3> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch2<0> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch2<1> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch2<2> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch2<3> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch3<0> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch3<1> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch3<2> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch3<3> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch4<0> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch4<1> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch4<2> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch4<3> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch5<0> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch5<1> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch5<2> | IOB | INPUT | LVCMOS33 | | | | | | | +| chn_bits_acq_ch5<3> | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_acq_ch1 | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_acq_ch2 | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_acq_ch3 | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_acq_ch4 | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_acq_ch5 | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_main | IOB | INPUT | LVCMOS33 | | | | | | | +| clk_to_acq | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | ODDR | | | +| lb_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| lock | IOB | INPUT | LVCMOS33 | | | | | | | +| oe_ram_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| pps | IOB | INPUT | LVCMOS33 | | | | | | | +| scl_rpi | IOB | BIDIR | I2C | | | | | | | +| sda_rpi | IOB | BIDIR | I2C | | | | | | | +| ub_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | +| we_bar | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +A logic-level (pre-route) timing report can be generated by using Xilinx static +timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the +mapped NCD and PCF files. Please note that this timing report will be generated +using estimated delay information. For accurate numbers, please generate a +timing report with the post Place and Route NCD file. + +For more information about the Timing Analyzer, consult the Xilinx Timing +Analyzer Reference Manual; for more information about TRCE, consult the Xilinx +Command Line Tools User Guide "TRACE" chapter. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +Use the "-detail" map option to print out Control Set Information. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ncd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ncd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ncd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ncd (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###5360:XlxV32DM 3fec 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10f0eNrdW0mO3bARvUwOwOIk8Td8lQCiRALexAsvDd89nKpY9S3F/r9lBMnCVjdL4lh8r6b+Cgc81OPjKxy6Pr9Z1Z4/YzK5/LCUf+rHP6xKD3voj39ZsA8d00dpyQ8w5ig/HeWn7EsX+9G72tN45tG1Gs/zob6nZMoP+seXZOFRevn4Z/3v5/dsVt6eantq7wNvz7U91/bsWfuhSnv5r7SLfg6o7VD795q369quS7uDbbaXWdb+lzauHe1lb9o8tV7aPHfenmr72t7XvD3X9tDmyd+v89R6a/OMvB1qe2zz5OPWeWq9t3myfto8tfYfP39GUHlphweP5Uc5s/QAveWPdoxQumxnprX7+AZtKuVM8ji7PM4u97PTSo0njGc7szrC+qQeZd1NPYyxqB6buUM9cjr6MtugXT9y1Q9QehOSqiE5tU+sEFQVybl9ojKXtM1XVUlyjkJQd19B+wS3eUjqPivdJG2bUdI1Je/9BIIquw/+4R+w4hlEhWew8zPYl7Ehr20QHOO7Yx3PMJ7beMbxHGd8vHTG5dm+/6YBxtOPsw/P0LD7AQ3bgme/qBvOvo6ln8facCx/+1j1S8PH2vtYzkQcSy1jrJTrFvUjKPeu9xUW7GurvVre1zH6OgL2pTXO213Ot8wPaH6u/ORO7pw7Vuxzd2Iv/nzt6nntGde+0drpPm/Xa/8+9rFdi5AFoIcsBITcOQQhIKjPm+WCiemgrPhkonfepIDgvpyJYhIG7DkQjhR168MfoS9FCUldyrG2UUAI6lKOrQl2LujD702wCEFbSuyDeCFpS+kAFxJKNs0BrkgM+6av5ahrWVpnhj7JH1+a4nAQ1NvK3ylTGe9MOCy/zwU6iYebJsnxqJTT+7EoBiYuWlE+hC4J8zAVSnyXODZYXU1/p/HZd+d3nG4dsNzAIVW1B1X3UI/NbciMU9YdiU3Vh2ckBkTigyPxe4j6LosiwpYrtI5nGM9tPFG+dwRuhkB9uoHE1lyiY74bHZt1csb4Ohgay98zloUnNCqa2dHImleR2PonJC663PtK8C4SL/4JidE4dsfyWSRu+irWbhCJw6tIvNC9Kr32G+ddlxDmlJ/GjSvv9Bs3Nq2Jy1GMO2493XHrmHj0a5vEbKxfZsRy0LEeQWfx3ABm2FVf6di1eG47FwmhT3uHrG2GEnXKHSXqiiZKlN8JnIs2T4OtdrswCTPyGJ43AeEgw/MmmJbkBMAqmLjLaKYJGJqbICTMxLWEmeWuM5wH5R2TMNZgBNgEjIGsEBADMV6uAkZmQXTFidGCkBAx9mOuSFyMXDzhgcRVdR8Qq2NyEBJrROJ0ahP/FRv4v4bYS3wGDjSdbTzIbcrvAQekSzI47iaD5hOcksG23z7WfkkG8CoZaLgigyO/SwZgL8kgfZYMmrt6SgZWvUYGDH0AJPqA45JT7AO4wD4AaTaqQRxV03ms5TC8naz1JbrZzkxy7nVXnJgAw4lEAxJJ2RFGJOV3stubZNKQAs2mziiA8UcZevBH2V/BH0CejQZOPoy5NCBz1ZE5c4FlcxqUWwcYlKvnlHfJqRqYZJCxhknGC9va6VRNVul7znwnl/necuqwQnDGEO00zhiiCRhDzEgLgOQ04J0xTmPM1YYn5iq/k7tTumWGDCNbAE62evSFPNTUoPMQ7GvlofRYy+ESDxnkofy/G5v5Nm59uf3LOzxV9ia7i9iOXQhsvb0F2LXaLgjLaoo52OOmscJFbMer/UUS6Zt/FtvxM070IolA9lexnWw+SSKQ7VVsx+aXSKQQUluJOyFQa8nzUYdY+388M06k7c2zlIO1FOuL6y0x5bwhXu8J8bp0xvB68kHVnc4HdSc5H8AeRTeJuiFmMCt6UvVqiXDU6oRk5isODEXXG8LgebJMVcE+66o4PLZTwY31OoNvRbKLyR40WcpkACTHh56sm5QWc5rQrNXOJNxDgcynwsjdbJtYOVkD42pp3PRGdbWtU12OSUxi0lMSO8boKYmRWMQxy22iiKNZKQ+wpzYu0jDsgT6xInzVgUzTuTDTal2pt0PkdJI4jG7EtFfIiDHrxr6d+Z3vAyz6TNB5b6o5xMmzTWQRuJyD2KZJ1h32sUce7ZvWVltbm2h/h4w+PY5zBN+6VDdBFBzc1tc4uJ5kcwXL3keiYDso2KhbKfivuIKTet+j3ALLcJVGsSvBnb0D7mLe1TO7DKY1QNm6lN5jF1if+x5saAOxuLanjHA6hmDFuj3+hBXtQu7PAWLer25NvMpzG3A4RMh3kA50lSy3rA7KwMBglqG3U4KX8K62CwBAkG8fCPy2XEAsVIbOXDC9kr4KGnu6UNCy8vXi1xOus/3SzoOBg9mRFOorHSsb0HCAX0ScrZMQSjhUdhOZxhvktkhyO5KYk6I5TQ+0H0NdUFF6TlSALmgXEKsazHTUdsZfJvDVMQeGUTqI1JOJlgm4NwtpYWNPfpqE2yc1k0Jdq2iQSVBlHU5IpsMHSYmJTY+vg+CUTCuka+nsjewFPZx/QvUFwdtBrSxID/1IBN0OoRtugO53ITVZfZWYjvHWmpUylL0sjwl/rTxGy/IYz9vPymO0LI/h/ZyWx2hZHsP74eUxYbaflsdYK8tjNG8/KY+xIlCSsN6jtZ+Vx1gR0skYzejtrDxmme28PMYsVX9j8YhGFDpnUl+N6mt+y/xfNWzvMb9qDhl3ICM6vm5yzsKV5/eRwvycCowZ+ySKX+CeiGz+pbgBnUBHbmQsX8YerYBoRg/9Xtvt6KpdTwILaKoueSKQQHZzNhgrK6+UHlvQaWdSTpgzGpSN0JHNCQGLFM46gmxkvG6m5bMRZKqMEpLJvyyUWhe0VQk0Y37GybIVCzIyipatiMDOuFu2MgJrhQD5ryU8q3qDrra1IYD2qOFmAvQLtrR7xaae4SkC8j8MPym7Pht8FH4im3hbP2PwjXipCIcsw+LLr8XU46LThV2tE0139e+F/ptLdpaqsIYiVmCEXf07e1qp9blPNHbVjDKFF4CnXGFSRLVyI7XrdPNwR+Cjv8Lt3mXecsd97R576dnFhUdcuNo7flv7RZmjKRptZpcVxsm1iG0vKvF2Mhh9zrx9VuXoCFMgUrITzuwq4hpdr1Eyrn9dGqbbF7be5rGXK1fnptlQzG5cZsGMXYUNiPlXnAOL+vsoJNMG1FGJ3siU0NshHHi1zmRuwc0acK/J3GkGLogy9v8iiP6nfG7TZUEkIYq7J5CtXLzK8gbKNvq7xroKmju/vJp5dekqaK7su5lXpy+C5l59Nmje7YLToLn3rwbNW7zOnwW2DZ3ZFj/BagVKpwXhRayAGyueG0s8DZivSmkchr7rfohUqJuYEWQxH7OB/KVF5aUV5kBIiCJYYtVRoN7pq3JGR7FUp2Ve2lIw1WlZzugop+uCrFd0iUlG3tUlyrs6zbpETGclVBNu0xMZZCYRSW9Hp+iiKDedhOgij9zmZROCGfleRVeT7lL0QsCSrPYQElaH6vjwjPJStGKRLLsx7WqbhNvqVyGYtb6MPZOI1a9aDMIT2XP1iUeT9JZEPajTrB60Ku760I9AtLUibTlmHM9an1dzqVidafRFjMAFihEEfVN1proqFHEvVw2aWcCmZNWgoZMwpPIG63TDapiUIQ3TEqNlNcYEJ6M5IuQsPmGG3qqFgECLqY/R3CljxqThRcM/Y24+s1SFgKrgb1SFPP4e50wTKEa+7reE+tuazhUhvlgxhGmm2ievucA/e8kjuNteeNKBPOKFzyqQKYTcHfMs3v/1/DOGgJ+OP2P4+On0e/uvh9+myM5+kFEuJgkAnf6Gp79wLzm/a1f6z2lNC+eeFdm5QAV96y2mXu6B9TNrx22vWjthvVT2dK+yj0M81XYPL//ZChFTIB+t9I+K7ZlUmFFh/mGH5/eEMW0Qfm+atlNYpXavQsBDTlZIZnSVEjvlCJkZRjZcbce/mfDShAtyfswcM3grk+KZj3n7WjvRbULLobfPiucjsfZpjk00SIobYxM9khJhMExs1B864tRV9XBuj2tDqH/gMXPJEW/yKuJdr3qgr8W9PokUfxovixnihcPpLYH8Gm5BBvAX0TIP+6vI0FJKZ+EyCzTtbX/HX8u/JtPRFbTh7h25wkoPL2NlvPpDEqvtp3ak1p4gfVMCcRSlYMguU8Yv9/KijbfTLabEUcas4nCqMDw0BHSNE+YuM+ZHxzUG1t6vMYxr/L2rdJNFlCH2poQwAp5HxzJVC1XNYs5PmoXLVcCcn018wZ2fzQgJOT8p8r5kuM/MKfNKK6rs6gLycJbgefvMzKWDtTP/hoJ5XUDeVYqRt5NrmchqggsygE4BfePVvwGtTfL5###4512:XlxV32DM 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ff4eNrdW8mO3DgW/Jn5AG4iqSr0rxiguAB9GR/62PC/D9fHYFay7awSDEwfbGXFY1IUxRcRXNKb9/8qrt64P97/o1h645LJ/CnkT8m9/ymYeWNv+Sp0uX5XZ/37x2X4mT+o/I/9nb8Y35R3rSqpr1HVxUdV+v1PHlitigfer6JVycSosnwwWGVsVYroRpXuwCp9aFX52K+pV/3Pt/rr0D5/EH//oVO+MPP+TbAr44bLhpe25NLv33jyGdf+nHiurZQXBb8C4rzgvOIScVZwVuvxgPtU6k+1/IF4LHgseLgQDwUPtZ3UnrO3M5iK84nXdvLQylvEecHrc6UTcVbwq7bTzf7J77zgR8Ftr1/b1j+tA4UuMcNmrN+79pE+Ea/3rn3kLeL13rWPogK89pGvfZQ04qWP8n8/flyl8/gbv950rubvPGDiGxe+jpj8SbM2YIQ4fn2g5KftV9Nx269nv7p+vfrV92to30v979QHaOr3Te2+eTT0K+9X0a9XTzfbr2e/un4d8Vr/d6FrOy9tSlxj6uieOsmM1DnZkjqvpcylY3kUibcY3HHFV7nDPiY6cQclehQ3JPplhNxwitTUaqfuuJU29uEd5OHf34G96x34h3cQ5HgH6aV3kBlnZFOus2Z4Hks1i03H8+O0DM8FRoaLGWssKCqL6IR4YUFxIas1vLCgcJXVsHzJ8DzOa4ZHxGPBLbG1LG0Nla1bm4C2xaDb/GGhbTFxpO3AEJ+07TXik7avC3Cg7WARB9pWiANtEw1bpG19nRMH2tZeIT5p2zPEgbYT4LWdoXW4RLy0M9QODwbx0s5ga3sG/ecOR/o3g8oz3/TBET7Qf449pf+KT/q/LOJA/1jPM/qvONB/5uBM/0ehf0P0fw36F5+n/1+n+yjuoP3vosp3pnO7pfOYbqKSpHZ07vlrdK6tf2ytG62Nd7X2eGztNVrLXmytLn17YFVhtPYcVXESn5+PmtxKPhSAbw0s2etK1DcZ2EKJ+T02SsxdBJSoDXEvXyhRd8da+iG3PJfnJR1N7S/Z8JKh9YvAjUZwLMBGASJJwyIUyDnbCgBb1iygAnEUmLSZrtlmoE0dyK0fnY5ipRY7yucR2N3oQXQkZwwpVV+IT0oNCz4pNZ6AA6WmBQdKHXh+MYtzpvKDOsube3TOG+q0K3UO2m44UKcF/KlzRur8S3QPUFWxv05RKNWUxMoDOf8jQvWDUOUk1O/cd3/82jiuN3jIFD1sGfnVEO/IlHarqnGqJ4I3NFw7Dp3exjnhMF1hiM9On1M9tXT6nBoq7HSY0qk+yPN/udPTmYqO6aJjlro99G5X/uvd/tnpzGd1LF8r+V7RnZvXrSTpmdJ3uPDozGZuIZwYtzrOO26Vrg8S6tutDjPduOm3ysK9F6VUnbJ6IkqakXKIXxClKUbp4o8618XoSHpU6dfVlF9+cPb44KlXfYjXpiHp7BRXhsjMhr+kWXDKqpIkgFNWkR6Wl1L1sDQS9DC5nqYFb/MdXri3dVPFm062L4oWO0asUfUfBVFVDpMLM9brq7gPsz6QTy6cHS08mn62ElM/Tw0Fin7WAlM/U6CmHiibKYjRJwZnFXE46YKDBMaQECcJTOeFOElgcljPlMDkFOIkgcmdiNOsIvk43x0wMWfJwkudVJwDBgPExXIsTzWcuFhcBgSt9W8VtNLUukRkcIkoDm4N/7/c+r2n1M+WijIx2i0HB+Lg8x4OdhsOVlyOW8l4Cwe7uONgy17kYJe2HKw/y8Fyy8HmqxwsthysXpsRxUpzx7OFq0Di48InWpmpiajDYspLYyYOGS+NRZwSHijFIaUgQ1jUCWAIizrB2ZEwQIKDJGSRUyYt5/HRaXlZBEoXKYscCiKGgjg7YgJVZ8pVHr9drsQqV72ZtUCVnowM6RnP1oWiL58lpwGfy23JCcRpeS6dAXFazouXmnh9af1hzjjbtEhemh3wXPJK1zXJW9bV0tgOKa8VlCv5a9wpodKBcrlVuXB4TOUCBXSogKBcblGuE+ufSif6WtXQFUm6kqquiJyIXJCupKErEXXl924lgC4814M84NluFV4SSzt5B0vne+1WRqQU994rpUcrPdmMbnWJFzYmMzfIkeJpzSzrEZ+ZpS3ilFkpqYlDZskx3mtHwWoNZyZCBE1fkkuAFksoR+oLxqQKa1VEYJzpAyMzPzNbLneB3GbHuURobZ2zU0MDFrLmxxKhvMsdzJYIZR5n6sTIzO3J5D1CbEDc3wMj7cs4LBsLGSo+MI18DWzka/pX+EDzyhZi7hPLdmsxiYzhcRMPmJ0zFBfZNcNuutfWGh7mNWuY+0htvOGRzs95w9y+sDOHUXzNHNZxvnGH6lV36PzDKxt8KuXcWr5lqS4msgMeaTZGh/ikWSYQnwbGpYkDzcZ4QPm5vxhjQDwUvE6gU0KcjBa5tzrGqn2rPQ7+rY8YMcoUB1cx1enTBAqH5hpbFbWh+aOnsEXjSG60VlbtaK0B6ZxsVytTfFcrg8RuJTQPzFz++4SWLZRvSKXMYtdybQIiYLTy30TSVi365c7lKx+9XAs8MWc98HEdolcFEmFJcCzD6UF0Fwam22+jfQZoBkKmuAdgkWKciamRZV1jzGZ6i0EJp6xbtk5DjFwisFh/ggftL6ea0DZMQ073SJLGu6Qdy+mXT29LvrbUkITZuD2taEJp71mDrU16RnSa69eIjrM6pX42D1aCxMn5z8yDo6eRcAmkJM6chMhCYtcSINaDIXqJxY1yjoFHviq2Mz8zTjIZmziuiQozcNNntOWLjUM9xND2CZrqCoO0QSTa8IflzoGjGx1J2wLEGDM1WmA43pIAvri6s+ycXJQCYqQAX04AvOrmHg+C/czF/aYUq1b6mWnTdafozhTju5MCmodXU8x98Dy0Mui/lGKZCY4t6ei7SUdtSce8TDpySzr8a6STM4lS7HjIJIWBeT7pdIhTTpIxqzjYCEG7IOJYkn6cl204sUR7SR3vzDJ2wdOYHZYPLcZHLMbxJHzZVU+MeNUF9ARAki4sS0KTVl1A34FM7MKyX3JFCCy+hxiJH6uK2wMDJOKT9Pix+JGI5acdAVblx2pHAuLkRmKiF6KeLzjysT8m1KIFnGbgY3mziUd0AQPgyl1aAiRQuZvcEpma5jEwZbBQ+FkoPM9P3rgmCpeDwsXXKfy3UTNncsfNx0kTO3ndM8mtK1PPyPmQL1JR2h6V1crcTaBiS6D2ZQJVWwIVXyPQlIhd5JJ9nPElgpkvwxKh1E+RLwHKfc7mjEcu2R9pGXw9vpqEnHhn0bHjEBNR+LLjgP5sXaUHv7UcYgWDJlcxOLEiEoNzTinlsc6Q5AGRPtnNA3dYYDm/KJHd0fEt52hhAl6qaXS27p+wSU5qpTOPgUlnixNXK2vhV3A9ASy6AgbMAzwPoY+OVA06k/9KR+q2jpTf7UjPrSMVLzvSuHWk51cd6bklVHU3odotoR4vEyrfESpP9znSc+dIz40jPZdN17H0V/HnjvRcHemBOHDpOfHOpZYc6bg5d8ORnuRIBzeXX2ChIyWLk0fWxpHGnSONW0caF0fqGQQ2jtTtHKnbOFK3OlJ49o0jdasjTYgT+ydGHG43jvQcFG5XR0qLiuMc1EdHyneOlG8dKV+5XUMAHSlnvlhS9ybeHDH4MRhc4U7Rl3doHw2k9xviyH/QUZ2bdkmqJZfPtks9TZuvZRdin91zG9O75eRAdBBYNkTtEpiLXGFW5dcdUX9CBDJZJrUEKPWl1UsAV8EPjMAiVFPVGZlMxSNbInMZ6mB52vgW84CZ67B6DJjj1gHz2hZflDshUvOne5HfcvRLHZvdInGRs5fhlp9AsLFro9ZjKgfgmOrSIj6HGu0KqWPddeKAwzEb4RGHXSSF+NxFkmP3Sp7rSB6jrwSWHfTxG4UWwB0YiQEYyGM/oQZwMZUOVMlFcGPEmmAQc1YFrBxrUTSKzRjFZjnQMn4kpZffrqq28T1revITIz3PR6ufm5JRZXmeKa/50zJXmI4/R8pQyBGNq98tMAUm9tOiva5g37+V/0oncMeKf3erf7ejG+yzcwL3ngf4ziO/ybf/A1n8D9bEMjk=###4568:XlxV32DM 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11c0eNrlW0uS5CwOvswcADAPuyrqKh1h84jozfSilx1990ECCeFK/1PlzFnNottZkhECpE9C4Lf3n8Ycb+oNnhGeh9Yq1x+2/lN//mXrHzb6939bbd/M4d4rpbzppaj6K9Vfxb//1EmhCJ10fxp4/rIKn3+rTO3qr0XK3JrMRR0k03iS6aqMWLos1WXpJisrIAQpau/qbTuJOpJUL6YmKub+nET/k9oR+vGyr9z68stCfe1h6uv7ffjz1JTWh1sT9aEW6mOvK6VCXzHfZG2Bp9mf5iaZJstqXjrnXjA3v7XewV7Mnw/stdLff1SFKqccu2DUhsCIlZFKmRgaGEdlOM+i6mTU4VWGOrCTLcsmMUGT0Lo3ok2dgsrRvnEO5oTef9UOOLicxAGVe4+mN1RTQwUNVeXktE0MUFxpbLICZ0H9HDb5APvEtjq1IajUGjeGBgbMxlI0D81VZYCRQWhWejTAedUJhhw2L7WolvhDlwxdmH2dOAU4pXXOUw7WgMJim79VCQ7OEvyHnGXioMZttNsqhgKLodPaGFoyQLO0NVlRzk/VrL8CKqa9veKn7nDmVFsPPS1+hsXH/pReJ04BDnao1Gx8sIYG+jHdKqvwRItUh1vxxO1v+i1XD8x/qqtUFUzVHb1Hu725ijHu/Veznq+7Sl21/vfan1t/7v159Gfsz9TaZZRTFctn8Ok4vFR36s6c3TPgk106Qz3BsmFY1naC5Yd4IeDZwajcA3hezIDnfdL6i5CTXTdm6EM4RnaR6Ek6UvWGOBoI1xsm3hjsrGU1zVxBUrNWeEFYq5F9SUs3epEM9o28BqJPDghmx3Thfm3+mM7OV0KQdPaS4ldBR01jwaFESQdFY0Y/OKQf4PibH/jqEm8azEEr9oSdPOF46Anpmx5hX+MZ3p3N1pGNhZtm6+3ZbNnZ/FNmW0WbSyfb7mqrL51sfdLJfI8L0Id0Mk8QX4czO1kZDWYn85IhnMx3J6uSmpPBC5OT5dHX7GReMoaTeXK+uozSyXBVkU4hNlnULZnRYApx6yYZw80YGTzFMXhh+Js2Y4KcdLiq9C4ZoHT9DzwxkieaLg4RwBxJeihOXvfQ8sBDD/LQ+EIP7allTTEp1Vz7c+vPvT+nzcMvgxMOHpovPVTftfl06aHqSQ8N+qRtNYYmWpeb2gZ10pYy8UXnZz2UHC4omXe3LpGum7HX1UCbzm40EGn3yK4bg3Ol4aFBd2MPakqzTLCjL5mZGVMkg/P1TCk+LOPkoZQd+zx7aFajweMkFBmPPDSTh6aTh+bR1+ShZpcM4aF58tDEHtoGifuaPnnooXFDD93f1vofe2gkD00vjaGu032Pjab9nbunKtefR/NM3T0a0ehpD6/PLt/77vHHpccvdz1+v/R485zHx92ftQ1NdFEXe26azou9d9zDWeLRJOZyU+LxKW/ohYGc70nM6LWPcS7dxbnlEufik2t0nGc0LX386db4f0ffgRBEA2hWhATkBLdleisleIeISllCHeWEtJRuBHtC2jAaTEi7K8l4hLSWkHY5Ia0ffU1Iu2jJYKSNlAuB/bRB6p2LLK7S91Zj+QCTbT/gzfYjyPJLpPgAL4gSy4HYw6IciXIkypEoB6JgKqPreRW+CVpVoMIu1kHHLiqQAd3SKHbf30+4VOsx6O39hEvlOW/b5/jC0H6cMsB9NJjji5aMR/HloPiyn+LLOvqa44uVjBFfopriy07xJeopviwUX9Zq/PrNwz+OLomiS75fq6iC3UWtAUCnO5vVT9QafoPuOAkrlrt4heIWB11shCMV+BqdFyjsRdJ5faLaBH0sS1Re0mlVIFinlk47mU5nms7yVOnnyeB8Cq6hXJWCbOJYYM0zpaB4LBcRMcW78cteRMR03JXoLiJi2u9K9BcxJm13Y4wmzPRzjEmDLmJMdBx73GO4rgvTwdnSD0c//AzXcYh6CNcoypEoR6IciRJwzdraGa6PQZdw7Zi+THC97YMu4DqULh8sW4IBxUmgCzBgp290BoO4bZL+GQyQ/gAMGn2AwZG3CgZrNYWRt5cOBV4PKLidp3dXrx3t5+Me2497RqFJ0ZFSzR2vjffIVym3O8ahmpnSuYfKj3TuyFebbHewi0V3J507cjwPPNDA3bfOubpv1FAMk4meAMKFJ8Bq4jIDXZhdGx7S2y60NcSkrs2m6UIr6QMoFs95jrwOXpdnkR6GPJlEtBMZ1LAVmPsbbKDtMIdegGwCXxiW6qwl0VMyYaIROUOTirmBSwHPMer/mkw4KzLhIk24r/qIUl8qu1IU+6VL7Cat+9M8imo/bSvvHm5bzivfjco7NvkSPh8ok/GQMdVB5vN2g4xonG8q+3W8Jh1BsjtLXrtkLimrdXLLL0q2u7uo/+oyRJfrs2/yqeGmbvsUWnv9V2ee0Xh854je5U8F8B6ttX9yZnE0y4NDdJ0tL/+UW17lkAHPbeyfD7CD2sH7Byxb/2Hxxw+LFeEGEf1NhAh4s/+wEisc5nb8pqM3Hb3JQdHFjgIwoha0SkT6NujivNnR8VOj86mxS0TPUxC1lPHC8iI6oQKITna31KalCR9gVg2dHJXKcDKavNaPbhgDr0L/KFiU6B2ew/ALil7gUr1LfQOIL4wKvUsL9TiFdUvhHly+j2DpI3BJDZ5AQhMXUe5uCiCgeexEL7Df4e1O1h3Rwjoh2lcPkDqelB4HS+k2rC4Q7ZSff7lIhr5x+NWe83a6q1K4grWpZ/J2j9cIlkd+G+33ro94LEY8uu1iin6VtubisouOy3e1XU/aUuXJjBres9qeAxftDnQ030tZfOmJJ5iEONLyhBFIH57nqWbf3mfP85RxwPBFnciTRyJ9FJi8j5LOFSlPBfxG5zs6fhXy0YNhEpoH+0Q6lUVuYRhrwRYRYmGZ+49FYq1PmiRMBSVfDjkqLnL5zLPm5b0WT2eOSB8Xdbw/JJ0R14dF0hmh/eoGvY/W0GipotRWhkHT0zFLo+MWJaGsZdC7LE2yyibHwTd3fEw0H1pEgr9HgFoFpHJvgZHPEPJtzx8jYAenW3RUW/d8gpz1K26Kta5gzzUXfny0gy4yX17cMBd4fAqSzsk2m36YC0iewnWTz1U3drlwKgj5Aqc3pTr8qAflhWZ9n+LNdy8unOKJ+VY84Uw6YHx6ePcxcyq57q+4++gxND6q3uixEzwlhP8lEQz6uEBsq1j7kJ4pMrp1J4cqMh1sXeOaH7KSzzcP4X0BVIGukcH7EpDoZkKjM/wGswm6KPyrxUvGwFlvJJ3xOigqgChNKFI6igRlxeBG3qgVVzWUniCJLlw2OgeXYLSkM7QFlQV9BKlARfdG52AUVJB0uo5RV9oaKK3Gt7VOKruSJVc6pnpKulla/V+lfO4Vqd9w2bBdAG3NqTlNeYnLBjTOh5tjUXG9tYcLYb9IZPU4jKTAdC/ZClgIfbgBTfuz2h8Xia3OPDEhPqW9P9/34MRWVJJvah8vYFNnnphwPDf3n05xKdFN61Pajzo2WCfmhLDQ7Ueds06ZssQlEzbWkQvwdVlL+gDfQAlGaODeJDfMdISnlSQzTjxZYbUcqeVILUdqje1/KqMbkYw6OklE+khGXbKSzslooBS70TkZXTIPY5vyFUZxpHMlcKA40jl/Civ3u8toEIKgt2lyHFos9eGm0LLkRY6ZE1fHuVjYpwhiKYLAbddRGFiy1GlEFi4wNLooMCgpf0QujlAwZlFO5UiE9JEb0rar0cd5QlgGvc9F5rkg83PzNgdzi24yWHPCycIfYFyNskxphxeW3Luh3VRYd2HNIzNwyUv6+EgiJUmnjKE6rwp8LdBwsHUUbOMrgm1JT9VNKBj6sl4GQ0bJrF6Tv17d8NHHdjN/VZ9CeSbtGSWdfUkoV+HipFMfxy3tu/kukD36bqy1iTRW+lAF6QMq+bQFGja8VtM1kaC5IQFXQcBR66A361eBc1kn2gwQDCZK+tjBey37GDtouu3S6AzKQR1SjqgQGMqh1wk0CUCQLm4bGC3pYzNKoNzoA1gIoJp8ButR/ynTvRXeULT3BegLffo+oH+o9PfQyuE9wwQVgsIu7+mwx77knuGtO/o3IEJLqLh7L7HOCV6LfYgt43xxNy/5LlD5y3144kqpzy/q6ziXTGM/N/XL9w6MtQqfrhSmfhKn1L0T46rfp4OjjoqulOeOjNHOL76N9Oab30YqGy++jVwKb2G27RUVLwYH7FTEcP4opzM46Ne/k+CICgUDSm8yKgWETI0hv46jKmjn8NVARnJ8BaEcp3gqfISprfiyjj4MwRWXH0GqwJrAJbsWOTrHCA4eWyHN9ob0eQb+at9jKs5JK5E+RFSUlfZPPBV/MArSRDjgY/XOKO9dXfFNJJ/Nt3fg2KsPiaNE/XsoPn0Gw59bIUNksvx9VmdwKtvuDTJj5LL5sBNjfDmj7DFxOIXP+2CU6VtJ5fPEGVcRlE8TZ3zoqYISHPlxqHJlGsz40IY/+kVh4vKjMmbicCSr3SwTR1xlsP2aY1t5z0d/VYHlQYALFODc/2WAc1cle7Nz0HHfCjr/AZpA+5I=###4536:XlxV32DM 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11a0eNrVW9uO3SoS/Zn5AO7G3cqvHMnGIOVl8pDHKP8+UAVVhdtOeu/e0tE8JN7NwlwKalEXfOg39fb+XR+mPX84Bc/fu1Zhqb/aP/XrP07lN5e29/867d7MWt5rSXnTNrRfR/1VQm0jHdhWyv1ZetuqP+/78vWXlX0l7MsHP/pSS+8rl/fvRi3QljEB21oXamurv5xs68C2gjKjLWPGuP3teOv49GjTx/rLyzbzaFOPNpOfZPHpuXt7nnsZc3c0dzva3v489+O0ZofBtmyhNXPuBWv204fUhv3rGyxeHdL7N5hK+/WPUXutUv9uQzG/EKnDrIgOgIR9IHXIdRAVMQsih0Bqdw1p74RS5CsHAKkCi8oToBuwA7BMgGrA1gCjp95LA1bo3doJyQ2JgDge14Ld6+PAEUeBwIj10ecSCNmwNV1yG8AaSHgbDOAb7DEYiq5LVV82W5R16uh7HZiHUihgRwKOfep1Q0LXK3Xth+g7sgmkyRZ7cP1FH0WTbTZ9XWERCqw6SQFmdKDkQIUZORqCkvMkBe+7fFKTT4lGADCv9l8FlkUCIJRUoPs4Aa371ASa9zCtjm5NJVy3feoEVsfguOzUWBtxOqAxN70CjWkY1zbNsY3r2GAm69Q9zKRtQZNQKnVZDK1f7b3p6mLfdOWp+u9XVdH8pk2O76C1OgRUUWP8+w99+K6CAdVe7fB0RxPGO7Z0YrwFtV4vlhjE/Z1BRpNNOAsJZ+mqW8eBSBRI2xYVCcQIBDAP5H2RbdVd8U/7rwoh5yqtt6OyXyYZrEMGC8vguy6dpkqnqVK6LFR/6v40UkY/Kt3g03TZmbU/t/7c+zOBLIuO50NvEL2jwyOurzj0il5ueD9o+yjvb+V0Pg3ed/oYbW3pifPpZ06kpLUTwcf1bysQQch52yeACDlvaQKIkItaJcCETHuqSUtuqRy5XBwsuH5Q3skLXoQB56QZw+Eqw0xLAJFo252inGgX2XuUC8pW0UuA6J61CYHGNOUABagS0W9NCRZSgG0oQJQkkJa+vR7abrWDfN7QoVsENo6dkfUrLAJa3danoPlcApcLMs9lFeWC/ZWX5cS+tBxYTkSei5XtM40XJcvHWVE1DzqYWWcfQl//DdaBv69Zx76YdWAI16zzsLW5q1vWyV9lHTqCayc3rFORa9YB4Ip1AGDW0VNTV6xTpSVYp6jA5ZJ1zD7K98467cXOOpaxa9YBgFiHtj+WX7BOK79kHQCuWAcAZp1SIhgM0vRIQwE2yToZN7YGuv1oeoyGxG7au+UR8nOWBzbZBl1/oN2RDZTvXI5WR47TWrXyC6MD2hE2h1b64+yPMfv9IcNLx1vDSz1reGkyr3ScDS+dBHJteOl4Y3jpsxDWtQpAmyaHLoZS1JBCGlKwH6XwPCn2cj1IcIgifoYkhdTX9ST13Y9Ntz0l9dpmOtt9ew92uEAOfrCvCXakc2BlL6Mv2jX2RYGVFM47VPe+PPWw1zf3rui77S3gYrvt6ITMW6mKn7fSTxvJLa991feGo2k3crLTMhzJWqV2hawVBSx4XCt1TAgRed3F24QQk2u9WokIj15HPSHs0et1nRCOQeho5Zy2huht1rT6stA0u5GVnOI0WTtRNMDyFFBqmxDhwTMRpNnr16uWiDgKdFQTwmeBXqfW6DCo/ayHnBPTSlc0WnOiot+7jQexhyESzYM+jolEu+GKulafa39u/bn3Z+pP2HE/dElXdCJsqofo44cJrtMHHMhXcU2nEsXI1IvUT5+trW7YmURxzX2KG/6hLX+2toYqO6a9Y4pr/nHcMr4J5tZV3NC5lcYZX+EltK0zNqKTlp2NFMZLHqJR/9Q1Q+1ZxCsTISgKQiY/YmRQh6lB6VXWwVhbqzORhJrqZKoj6AJIgescVEcEL9lZriuPPlBJZz3XMwMIPdeT+3kwP9k5rpiUQEQs0hYzARQGs6zkAFCAaqImK2NaE83YKdYnycTKWJ9JoYe7KpWPpcBwVxNfnd7WnN1ElFEGZeSv+7rPUs2zlsyFm3ft3mk8Va+ccOd2opz9JZSj9/WO3gyFglx+UV/xJm0TVHkwbaP327SNzU+mbTQEcq/SNr4cX0zboMV0mbbx5TFHuuzHaerEvoq2xz6dSH9l2RETaW1L91nH4SW3xZN5AVyAgWBeoJX1vICmoHj7hRZOkwG1y7CRvjHniaBZyBPBeyJPpGPi0U5mXbQSYOInQwcBaTzyLNaZzsisBIQpsOzTK0yaTMAIcMpH77tAJDWj+iFyk/JBoLyjJK9TPlAHjjOoI42/3Yp1EMcFH6ytioibsYWOAGdA9O4FIkJ2Vb7T1GU2h44rROhU4LMHuuHcDJ89CFCATpxjiFBokG0BHDLFBk1aZD4FRQAHTMn6nE4hf3ZRIqhHLB7QrzUhzDGNrM/aaId7mZ5z6jkWUdsWvlPJjsvB8q6DgXIt6oMuBT/FOlp9UqDfe172OvEsI5pFj8nrlxyt7nTUfcrq3nP4ECHpvro1ZABr93ejlVk9w70EfxXRNhTB3LdnSD27NupwQcRmo9HmZWr60SD50pmj9TURs1sYEIxWYpDlRIGUCsVyDmoush22ccvgWCwnuzaPHHWm5DVG7cNoJ0S0xusegIEenl8QNMMsnjkHqijNa7ElIL5M2dOEvBcc9yWYQxudJUDMYRJOHois92dQEerC1BWs/0gRzFAEc6kIn8yjeHPaGmPXmZV2XY5f2xqdp1tfExl7zYDgb8qfYzmnqWlrQPnHtDqUi6w6LRyUc6LElnCOlBY7pGmvpHkjvQK+q7sygNlQfNTCGeHwNF0q0EYVBuRpZ0a4HwHeuLTLSpLXEKqRZ4zrvFpIAG4IwMlM0ad51H/JVemHVx2ZVzf7MYjcy1eoqvbhytnE7eFtv4QHc0UaDohLtyQStfrwuptJzXhoE5B2prFk1bQEDpttlo0qs02WHm2ajpBxSGd0B9icPJwEhAVKO7Mj7FDXPTQhbG5hmGtMRqYDcAcA4lU3yGHCeJ4YGwUs06VHmgChB8ZNCBEH56oQYeqgpFQHmDtgttUkC42NI2mPH9rj/38d/jo3W+4c+sB3I91LnGzj3a1DTxl8d7yoL3vr0G8POvTG+1uHfn3SoTdO3Tr05osOvbH5zqF3+SG2a6wxfKHW6qU3bPpdSawiWIodReNHvLLN+9pRNH7EPaGOcBRxjyJzqCmzYCwzh51iALhmA8EYgPF+xABQ/KPJTjlt9J1yDPXonWSxks0EEPGVI0wAX6hL0xvMrlm5CRDOepoAQeFediKddeO5MT+lS5iqmxiF5cm0jwDZqkz7CLB1yxFWQJhW7XJMAHvsW5gAYcM4IxBh9pi0SscYlxwjr828gchrS0cREYdBxOHzdtzzyZysX3SR5qGkTzM7wo3haXa6WVMeMTxbm8eZKNbugAI1IrGFidhuCC3DXY/rO/bE7fuLuN3ls8U4LhkZ+zKL8bjj0GV52GKMdzmpWF5rMVZlIoVzWWZnLAf6TJwCjcYuApGePAp6NDYMs4NZklS4Fn44GwYw2a1GyVGIhBNaJoyQWy+t0DjFAfL0hgi2Gj29wqEGe1CA1Bw9FpC1JOO2jydiBY/K9jfQ51deErwwHF2eqZdtTZfnU0+XaZXorBPc7/J81AmTO8yxT7MIZHIgzcazmm1xJwFhvsO9BJpuO46hikiz6WHhI8D305HieITC6BauR5DHg0nbiH4co6dB9eGDv7oMol/+VX/VxTt/laN2X2af5dZfjQ+zz+0tgZXTaOlF7MPe35TolYywzIzgWEkiccxCHKOjeHHyGvUi+ppsND0BYncLHZozxHKH2jsfeM5Dp/kNYaVZJ2YkNFUyxSk6uMUJEQFFPb3DSiWZIgqd+r371C7ElWYkadKd8T1G3Kdbwa9KFz92c8WndOOc2WN9zDnzsEf9hW9mC2Uczf5332zsajZpfNpvzAxbyIVM5SuK7sHWvbIy6kn1mJ6HD8mEcammXwmHu3j6GUEsYCZeJhMy2VvJfSVivIwA8GLmT+VGTD9ATJ9u0uAndBbL276HFz98MUcV1KjAX86pLCq0c30x0xd0+GkdVcijAhkm5AG37QwOcFtOwW2+n25QLs2jtI/yfskaXjSI5YEldFtbCXqtPh2MCWd3iXoMBG0GaFgYD32bjQpqVCCzoytkr9CEARXYYlnGlSGskEcFMnZMnxN6bdi8gfIk7tHgGsAJHzz4chCUZ5oan0zF4+tBtUd9Orojfr4dvejt7ssTzqOGl9yzC8CQVx6ZOchVsJehprNHFsKHuPrwyA6KAu3pK/TV1vDm0nzcn0sw0wetTegiWkFfwGI5HZ0+dh1rYxEJaTI4WrnQyRC0qM+X8oMvg2h6PAheBJ1cRlaprY5wGug7XhwTHdq+RzCwnI9s33Whl5MVvIybLFjO9sK4JNx+CLs+BDOYCWNQMGhh6ITxERqWk5mD6zVebDwAFdjaCePTVywnY8d05kE7HUHQ4saioMVWavH47ivmyVB/NCT+mMH+P4Kq7O8=###4448:XlxV32DM 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11f8eNrVW0uO5DgOvcwcQH/Zkcj9nKIAfSygN1OLWjby7iNRIkU5wo3MiAAGs6iyk5RJfahHUmKU8PGXEv4mbvWpXHv+Njv8/fUnFltf1N+f7aVSP34pZ4HukO5uRqgPaFA/r7wkxjdJKCB9NooREnhm8oY8A/Jipeu/oanM8gMEt5dfSsXaQKqwtBDYQrQWAUTsrEEqo0F9qQ322sDvmTc4sMHRGmy1gXWpNjC1gZG3OiUffQTtBUYnWndF601r0IdRX2AYMlugK6SrPi0gqk+L9JMns2rfKJiSzOmy0WUf8cYZojEEjMMyehtf+68pODj9aPQDFChOz42eK10dfRB19Alns3boKzoTbrL+cauU8vd/TJUrtT4+/mXEcdtCfeZSB2U/fsvU7aYqGs/Sn1mMpxxPNZ7beO7jGcYzjmcazwx2KA/Vn2XQy9BTuh4lxHjK8VTjacczDrtG+97Gcx/PMJ7YDvT8rkYOf5ve32hBXzN58TfMgknuo06MqYus27yUOkOb7DMji/v2jPw2vcdfVUX7wHMVoavQjlR4u6jIP5n8qcrZNmrLVcWuSu4RVQmDqgKfz4c4gfNURcNCLBN14ESZ90yUgzXnE1WtdkyUefdExdNEZY0TFV6aqD92Cx2M2mJU6sdnU9ZefrX/vv60TQi7FugTeZ3Vg17nASCmNegQ48w2eQAxbWt//dHZcDqBqjeJ0wlKXSiMPhHUFd6eAeeROT03uidAHYMEHIW+Thx1gInUwGID2xpY6LlFyRJG+6tCAfSc0ftIRQNTLwunt5GC3/EqcHobqQAsFZrRAUtLATpvD1haDpjhHVclDOA/FKzKwNi2jceqBFoVP3kD+DOMTXE6AH8fW+R0wH2YrMDp0NcMq4W+uNNbX/MOqxI4veE+WJbOGullzGnyoNdMOnNQXhycTg7KK8np5J9cKYw+/ZMXntPRP31FHevfdUfXf+RtyvA24qG3+dF+jlLCrvSP4HufkKHfABl/2lhgkKCUza6OgjHY9EqJu3BwZgQgrVw4NMX1G885c5IrxywcCgMqZ5FGgcBXnSC7NY8fmsePuAZGjDWQcw2+PSESNm57+uc8//D41x4+dk/dAfYJD2+Gbfgr1+60RdsI/hWPVXW0LzTX4bsOuxXyI3rxI48D8mbL4SJOqP9Qln2L+6u62pt54M1VdKirCK7rGzL301xUW+/uW2SUqRzKtHf9rbJkl5VLvogE1IxjYn7Htva7w73jy2lXme7CYGSQmLR+MW9aGWPjdQa53xql0IbcIUEa2VAux/wAMKR7kpkSjG7Qtu+etjMO7mEnhoDy6Zsn7HQGOfOBLTSilkn1JhQHVLuYPQ/cR+WSFgY5tRLdwiAvKKUzjNMRM/szYCnutaXUx8IhP185ceFQZFD/1ozDYglAPzarE2aP7BcGQ2anFw5Dc18YB0KBviZ9BaUNbKFY6lg5ywxNf105+8IhD1+HlBcOxQTqUCy363YHuV1bh4r0sUa1DOnlQHr1urdliP89hJcl/yS3+62kfAX5GwL5q2hgo6jebO9A0BK3c6aFSZ3cUNVxLKq+D87iLDtjUEPgLNMCpFfDkCuwVvPertI4T04mv5TGleiv0ji5o4q9vAO8K5AEQrSeuHzCEFlgXzeZWdoUakNJAYedxuGAZAr/uh1gjTYETTrNAFAMtJfACIlJXYCJRYae4w8PJj2HHx13xmDh5wS5ZpMMKSbuAGNCedWuOIOgvDIsZ8yEJvpJZ0Cu48ZG3pGt5HOw6vnZ1IL9/uRw/cJhoa9dvlnCZYE986trNhtnTNccHadTJl04nXtm8jvwAXez1nIGc7OW92k6V3XoAd3dd7gNsRuUVPB2LUzfCLzVAG/9VvD+Ubj+g4O5uIK4dAOUnbsCZU9huDPvCWt9vAqh1UEOIL9JVziH/mmkF1JQ6I/pxVH+MfT36RyOZ0xVKI1QakH8h/1dkN6fvchAelto3pN9zkPBKeoy9jJkW/mjtKftL4p0HN5ESMfPmGCq4ZAJmrAYuAfvvUkiaPcLtPfImtq0ML634SDvKEJzfo067QwUA/auc3xiHLgNAZoZHzrPRI5o0dkZLc60Iy4xoZiuCDgsJlR+4RDSsxC8MR4G7cAgpOfxb1yDdp8ZZwnaPQXgMNnMw87Q3LkF7FkY69wC9izRcG4Be7EtnAn2zDc6tzhN5mfdGrO7nXGY11SHWbHYExaLhtq3uqS3QEisBxKbtyLxgrRNcbhCSjHDV/EW9BLgufUDpFSJ4sC4oMNVEDZtqQ2ARyZz9cUp0JirL9ZIo/69M84SawimhscA02CAsxyZpYVD5qfLKmzmfyL6hcNsiYKQLmyesuXcvHeuFpPJYsywGPv8pdqzPjtuNl1daiVFJ1/hpZMvcewXrlYlOu0Jbzl5LQVT8qaU496ROWPiXsED8sFghkcZd+eQ4eWcGIPZXR4J92ebVWZcOW+MPs0xZ8fpZFk5R06fh/CJyWG7p5S4jJo8RCnbwiAHkfPBezqP4Tetq30e1T4Psk877NP972LL2q/tCvAKhWv5LeHapu1VZLhRtJbfkpRubuBEGx5zhpvNnE5YFHfD6WRgoShGnwYWsHKj05kXxOXXllv2ps2kM8NOwfL2tEc2Wxh9mtc0VG35LowpcTm0CZvVsX6yTJbND7+lCotetPevmNphZTVfc5OC7NcN+/XPX2E8W7SAuU7t2HaFs4Fu9sP2Cs4m4S4uGPSx/eyCIYl0sQXsPFaybwkv0t1VANYhWLP/LD9IImJd0c7vZSk7aDM0Snr25XycwoK2TBxw94VO+6pkw+m0r/oqD3ov/WkqT+f28BEvzdk5fZby4FVpk8Hri0RCekIl+1Cyb3ryllhp85xBOzjhHXenT7eYLaPPHdyNjOi042cxFNDnjgx1Q8hbnQ0WIvuxITe2IWeVzo/u7rBKp+o5X6/VwXQ7kuVnOXbI5ZRi4+2Ujf65FDtAmZV9cNBp5yXacxl2OMR54BoHfvxsA4U83E6TycpNwigS+2wvYHGtQbe4PlmNl/v9xmej9Mw2YKDUeKzQL2B80+St9X0jAW8yIP/uLeisjrJ4aNCSeGgwD86sJpXlvqxPj242DIAhTAxQh2WXJV0tJHlpl+28TbbzNkkmvA0T3l+K2c3Jx7jFd8hje1TIhudlfykZlkI15fo5mgd9yxGRxVhpXgocj+x37em0383c3WFQ+EU5YPLP2G8K4dzb4bYOc2G+/1he1STGs8ThUg79rMS7Q7dxiHWoZyXmM8aMXXvIpyQOZK4W3pYf9k5bNOa0hqfFBhIbzFqeNLZyawB3E9VCW3SGh+2tPYvC0oa1piGsBbD7pDdIqHQoft3llM8d4JanfO4ATUE5ucupFg50LJaty9LpEnzTrmZ7Bl9979vRH/D/IeJLwpe81PbuYqpgB40RtiqJsijKoiiLoqh6LW00isijkoQVXiABZunYAIi6h4UQZCwRAJFvsfGtyrjNO9u9w9C+wNB74YTqXz0c0dgHG7Ut40sVox4OMh8Wo84TgmdFl7PogqLTi6KNuKoMTa+V0P5xmBC1mWHG4dywv7YYYG3QoL+U8WIEtz+vPYoq92fmJMqjKI+iPIqaZ+jazV4xU/baIj1zIHBaTDoDAjflFL6BvR4RctPLy131PukMCHr97BgC1M9Cx/pLGS9NFFXUfkWnWjwq9a2GqVRpaMLYR5GniMMJXrhpTPnq/pIX+0xe7Df5aN9hhHuObO/2obvfLAYLkqd/25ZI97uV2wqwao0c/m2UvpOvdx4+nMMFp8MVVOz+xeLy+/28oWj14ui1Oo9+X0avvjv6eFla714c/R3k4E2i3OWro7fn0edl9PK7o09XgLvbV0d/l0UJFC1eHf12Gn0NifjoxXdHny9/LWBe9QlY7j5Q8NNp/EmVw/u+ZnvcX6AfcXhw1y8rHToFR0grO11h+4I6FOkIUwc/XsELkrbrF5QnuuJHDg4PGR06pIqgQJdIp6I4A3rLpPc+qUJ92qZu7nkU/hhBLTV73WPsQwf84kLjTy/QY8Dw4GW4js9m0oMikZKX32moiN1YIlWn8JcCeolUyQE6PJftCTA5Ooc/KesJs0PH6MYvyeBDnIJj6uZOU9o51P6zCo2/r8BQAawFXkbM0DvaKRIpSzjrVJpDugsnSJ1HdR7VeVTnUZ1HdR7VeVSHIQfUuxzNYddcu9LJYceRf8f/33qXN5Stu3h1KWJmDUt8Uw2LvKyXofM1c7xJl7isl5E/rpdRV/UyRjxdL5Mu62WOl+tlwlW9jBM//JmAiOd+4kGmMTOtyt+qDj3PgYjxonTTGMqr4jsKaJfqHkHVPYFnJppK89uYWRX9cuMfl+o+vEsDxlrGdwx9TVjLQMfHvKJPx6XNQW1mcZ84ySnUhhfRe94GSo56R1l9oqeSRq94NQ2vaVJU05Qua5oU1TSlU03TLMpJa02TmeVC4lTTpBgHa5rUrGlKTCTWNAWqafKzdF4upRtlFu7EtQoo+oVDx0R6t5zBioB2vTDm9ee+iFqKgDLjLKWzs0rVy1MVVl44vArLLhxWbysk57B7F1afJa/KsORacLvOGCuf1fQrBBe4r1aHXyua/gsNAeI6###4672:XlxV32DM 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1228eNq9G0mO5DjuM/MALdbiSOR9XlGANgN96TrUsZB/H4kSKSrS7q5YMIdMOyiakinuotNNZvXx9UsVfxM39fuHUunjU4oY+8BXdLu5yZtuf7//3mS5Sb2lj/9sotx8u+bjppT5+CmzqRQ+/pLZwlWJ2K7wvKjPi5v4DU9tyX1UQttNZ9/oHJWi0J2SPEJ70nUKCij93Hb4/fWrk1K/P9tNhX78qJMCvEx4farBbYUbmxhcVPy6qPZOec91QPqbq//orfJ4q3z9Vj9lUf038Kv+PlL/feRxLeN6DC6IcZXjqsbVcC79VFKO6+CeDP23Gr8V8sSP6z6uYVzjuKb+nN2A+zm3+bcT7ksZL7iPKzvfhUpS3pOMSDI8R9LrBjCcZO4ktyMjSemQpKn8TYPfafA7i3HtfNw6vytp1RAtJ12QNIlfkkjaMpLpOCNdr2pMoQZDYrpnyIEM2Z9kiCx3q85yrDo5Iln+iSHnq2eMMU2SHJ9C9SnU1MtYFsb80RTfGPQryyas+vdn2+eK9fHZdqXdVIWUDQH0sSpqYyUodtUDUuCtwusUTYE/m/D1m4o5VfpXNnZSABNQNajC+/ZXeLupC6qm4UgNH/S4LanpfpW2z8aPdlMtoKsIqVg+tcGpDU5t2tTN+ugwrE97u8reNjW8VC58ioJTlDaFB4TIEQ5EOBrCDgieIWQxEOpNRQiAYDmCRIS2BtXY4rIfa6sIfW12a/C4D3jFB7Y0nlWC0U52wUqqIQN8z3YQ3gUQSkMo8KCfTAA2VosIW2/51gvc+vYKQsCDbmxc5TOz6dkrhMth0wswDVfe4B2/KMAXkw7zAarsw7HVtxyTd4cXmMPrbAN/15gub/mmbpk8QxmeoXDPQJb/jyz+s5Y8ertfGbCkUU9DeMWASVEubUEqNId+iy3IY/9gUiZ6UpiDjbTdgL1pIyIsIyTedWR9hjRDCmn4yFSqOuKXEdLHOpKWETIG3qJ0183gViQzeF+xUKT6BJ92DjSe4FMJimLwqXZdvwmO2taMd5XjW33F6mMMiekxxPRYAhg3NmIf1zCucVyHGOf8SkDzcqDi1b3HS2GIuTtQBDf9opiHOzFHVVIpvVXMq9aaSwe+4VR1f15y4OVCaTeIZ97owJu4DXdRuM56S/JpuHuZrq/Ch18qXHGn4wIEgQjMs3mG0H1jWXwjOXBAKIhw4l0BISMCKXXO03YErtXVEmk2wvT6yNsyQIp9ZL8MkGYfaAn6wFTto8hlgDzpUZY5pit1gUKZsQlVt2ET5ITDYqsuQ+gTOFw2eIJ4JXO4aPC4GDk1OF1tBcx7cHhbaN7Bg8bFgxb0oFKFljLa6kIt2iYjum3axZ8nV5gc/bUBdz8aYXuRzZAnFNu/Z5JIEJbqLpKZ7SmKvyrFYcthtSwSAbbgiOOxS/29sWeWzFZ3Ie4DNTAfD9e7H+0fxsiIArExoLDguP7WbOYZTbXsvoZlt1Tz80RbJcdWydNo59E8N/K8lrmJNcrpKfyZad405alFvMM0t1e+K0iMdM0481BBIm7quCNFJlhTKhw3vuorE7uhtjZOMHOwqcThZA2kipkPkGHRxyDUFsdstT52hj9tGiuSWC40nU0DznKyvlO602n0+4MgU2A+u8yOBfAwTsWND8woTkX+7tN41gHHB9DcfsWQVBXbUllfSGzVEFv1utgyMX00irmKMLShQNrub4kwYGnbWYRxUIlA5iXCOJ1iRhQh6XuSmAYYMofVlnFx/pfIoW0U7GCjzSMHhQmo8jxyiJivN3wmI+Eww5urHucPBAoYwqEmQRYnRJTGDqfwgHnHxfl3tg44UxPmHRfPP0MjtTh+lzj+fSZNcNJz5mUXr69KYl62vzR42c4pX53sTiqghwroqQKvWuw6z6VljgqFYj/eIdL9lc4ssy6PWeZp1RpNZtVIvtoNs2qhHAhfzGzE1DOqxSxTKTqqxfpWB+vZwJSHgOY3Km7K6gSaw0neOtsHHMwsvElTnqr7yYP5q9mfoM3fxuZvfPP/cAtmJOYfyxbLIjR1Ye4+i7NDWIKgDMu/ksV5MFLn5wnpMfftU7oX7ZFzmp0CSiPfYq3BHOiTONNs9jHRniLWuN1lMjWZ9GmBN5lMTSZ3jyawvi9PEFKacBCxRmHY54TmsYJYqErRZtsGCDbhmalgu5BsMlAkCFP7thGcsggplOUDlHb4tPNVU5oihXd8gPIaUkl4/f6A6DMsA/CA7JSWAWAM2PrkJnwwRhNj6BnNIvXmjyPopGIhiRkqad4akjxYP4QY9dR+H6QvNr4nJIkXFQltZg3HvKUigWFxm5PFFQHLwLAdM/jcg+VwiitY8hx5OJEwIwM4CydS4nAKJ5i7j7zIwJLtYw0zGJyHGSpy+AwzJv2Du5WpVg0+/dBudw4nv8XCmIP5uep7XVWm29FciuzyexwYTlgUX/39mPfJg0484PxjMY77fhebRtNlK8pnDx3L3aFjHNbfGgpsSl6k9U8VQd8fOsYDSdNqS3zJDepvh44Sp6A0OdYH46ipRD0I9H3bQDAhgMXAU+dFoueJTuYakHJmcFax2xf4PIKKksNJI3Vi9LuRra9Ul9vWpFELdPNMFo/UKJto0sCO4KZW6iW4mkG1XoKr5Bd80iZNPkcXvibd5tCWzT3LOjMB0Esk2BSK8HlJZ753fbeQ8aRyRqzwbrNZIbrmWKpChpsi1cRgz12rJiv9PxrUydNy3Jt7G544Khh07chMQrwyCeZZkxDu9RbD14NO8qV/pWofoNaxLNphjk2mIYUHcuzKh3tTEP3gw/YcH6IGr8Ip7h//3aqQdbIUHGv/vb7ATig2eWVhN4oHkn3Gwsb9vm4b0/3iHtz7TdwFL2Szt1m6MW/Jc/f70k0SY/HqWcE9rrzBlh/xBt0KmWqFqnJBfN+kq9/sDm+WiH+GUJWDp4emdXHM0EWHKfXueAru9c7pzEoNOQOAkyOaIV2Ds0oQzQvwE0cEcOaIGJ1h9I/hiJrtHWsdaVA1QuAMtgnv7SYWiqNBsHdmjovKV7pXjz6bHWDJi9+wfKVDr4dVK0xlLXpQ4IOUDkW3zwdZXsVcX+BpVTToZtoGn7qxwPM2qp81fObGuismQTEoKAYFxaCgzEYZSquqXWCM1rA5Yo7x8ojG6bUGvnTqPRXznj3DYt+tcFrk3aOWkxaLieOOmxkSz3WjKRPOWlACtqC0rWAHcap0FkJ6Pfapt5oU3oICi+olvBZc3Ko39NW9U9Joh2v3L9VxHqvfPO/a7TMuvMqMvqgTqXlwsptXAuQIJfmzs8L0ZFNegPOLsxYFNc+oXl20uTiOTP7ZRZuL9iGl07sWbS/6H1mv4oOLtvfdE3gQofO7Fn0fQOQR3ST71KKrRRTDIlbJ6/bPGryxeOOWvAVdW0Pg1eijoIUxS06hA4MzyyYch5P1DNg/1OGzuCwZfi8uWzusahQGxzbuoUI6OJyqiFHaCR+0DNJCl95A3LKK5f2mJdYO8TfubKKIbO7p5MKxwKeT056vlZwlFeGb/WEVUsrtAD5Lh1Sc73CqHIbkOZwKh1GaCR+82Iivgc9NVduA+XQTehaWROknfNByxFc8xbBuCUvEzmlR6BOxKAtwVs3SieNTCBWl4PgUis3oEETcoYg7FHGHIs7T1wPOqfSNOu2NGy4u8Lrot+aPC1eDnfH32eAeLkxnFE9mQXu8sGvheJZiujA6oTxndGgHG2kWiHauD/gSuFLwHXmfNHVaNzaOKB8TgH3ptI6uTArcZkFASBQMUjBIgVk9PCJrmDOuii5P+LQWX9HVaFve6my3SCLkuwgF/VA/0UMiRX1HDsyYOfuIIquLNqF/3LfZgORgP8zZxxRZvko63pPGzxKyeJV0uiONctyMyyukf1lsDGicYcJhYW9Mg/fSX0foNxFvFjlzmDs0hG9fFRAph6QcknJIajbDaDVXxRyZw5SikWIOyyo34SzLsljeh4mm+jnMJ9u8TF0tHhPAeqZ6Gx/mK0BbGCys30S8SaxP7CvammL1npmDtGgfWuTe1zDADqr+MRcg7bKQx5/2zDiqX/l39LECCy6+1EnhuQ5CCw2E5uzMy1ElqpQnalxjk+vmt2Wzjj+dh81vc7OzL6fNhLNIwqG97fBZEMGop8PJ+zuMwgA+owWqULf1MOWwWFiBdU49s1EhnRHBwINjrWyMRaYaO+Q7nCJZi/WBDp9tNqjjAGdtNqhQHT77NlBhO3yef/V+4vq+N0faEUaYwj9zfPYYVooSL7+xiG/+xgI/J4BJl28stp2NLN9Y+LiMsG8sdrGMsG8ssEWwj/BvLPZlHv6NBR4TjREsF7Zv3vy3A/Q4diCfftHg/x9fNkSvxUWXiN7I+9v3dIlIf2UKN4oGcnrLAbrEuqH0y8E0plqwHexgmuqD0i9HbPMLM78cTGOKCfCz/jfp14NpyeGz632nOqZYut6FmPCl691y+OwOmcduYul6R08NcNZ+Ijn+TDlZVVuwOulX7CXetR9vfCe9F+5eX2yxCoe/bFoy721aGlXr06Yl/2Q/XqPJfEc47ISzwKq/JcC7ePYHwYpRP1MbY1s/+3n6wCxdHAuc9v4ogcHn3lMvaYfT3s/m1MMve59rbi9vNf5pHUy0++N78v14qpC7PVnQlY8Udv8HrNUKbQ==###4712:XlxV32DM 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1250eNrNG0ly3DDuM/MAkuKmdvkrqeIiVeUyOfiYyt+HAAESarcSt9yHOSSSIQoCQBB7/zTK3NTt7adRGa6/jNZ09XDNeS/turR/6vd/rNputti3/1ptb87YtwbZb3pRa7ur7W7bAVPoGA1i+GVX/PtPQ1XbjZWoHKGqC6NaFKHa3dtPXTZEpcver7UTZ5VmlPDASZSeURpGWR2j9BKVkijb1RBqw6i3e8YDMz6oVQN1+gvjFWV6QBUZVX1OhlWbexmuzLC9JsOCNwcZJkapvyfDotQ945kZN0/KUNV7VIVR7U/KUG33MqzMsL8mw6rVvQw3Rum+J8Oq9nvGd2Z8e0qGH87DWQ6/3+FQt1Vv76DkeAMqijewZR3SBE43O978aCaiIaloKMxvhDfUDa49wFEEAG83jXp60eAzlDi+UxH0DpAmPXy2zmeED+DaJNzx37i2iecNMcNNo6S/GecXmxwBrho8rEm82KTVF7SbH3rfQQ6OX8QFG8C3Bs87sQZCQFL0Zhq8nxCE684aSqmzhgcSidDEWoMwa2U+I3zEWiYK21pkDTAja7oWpGSdX0TWdM3IWhAvAmu4AFmrCT+Z+JOGWKsrIiQ47HgnpakjwHeG7501VAlkrdtrQ+oCrAGks5b3OJ8RPttZi51CWIusAWZirb8Z5heJtb5rXrwIrOECZK30XfP8YiXWCuya2ToLDY/hr8GumV0xvLKAO7zvZtMWwzrV4H9yKHCAw023I9IOWFONxeEJ226JrIExrrnGfq7a+eJzFum60jXRNdO1oCsNxSP+eZLbd/EkL3a4gbb90khUsjv39ufvRuOjs9JkBd+Ebf3RtzTkOOHAdoMXXG8lHI6YQX0rh/VwxAyoWVmVgMMeNeZhc0uR8A3gEfCkXcIrwAPIPC+2yVunW2xGe0h9J6nrKfUvy6DpNf290jXRNdO10LX29VsPgPRO+PedAiJFV01XDpTcXcDkn9GCX8bj+zmhSPyD0MVYxdqw2oM2PKcFOQd/7+gohCkz7FgOnoN5O3GdKat7ohMTrV9FdLgnmmKGUq4Sre+JJudslu1FRPtPYRk56Ub8RaLNHdFsLMyyv4ro5Y7oFoZ3otMloj+yJjMC1Hdv0r5B3mQhkwSg7uc9eKBU63xHmKTM8QTCpynJ7PU7fJqexUo8w1RlZSR8mLZUMGRr9LRT0jhrtDbN6zdtN+lmwZsf8B98wjALRoY+Pa4aqAKjCowqMKoRRWW3MVVKOvisrIBPv5456urw4ddT2SUe84beDvCzX2+UiFAmm3Wu7zsEpNIOaX6mZTyVlRfwGUalfZfrR1yWqlyPO6rw22qTeGbYpZcJJ60xRFPai+RvBEiJHROYUeK78yfgxJ9n/hzHMw0kYyC1CFwz4MiuyG+MSCVxcNbhM7Lh2Kvj4QClneUmEOD4trZzxE7OK3JyRoQWugQ6w885fl3DF50dvbfXJ53eVWdnD04vIH/hgdNb7DDF3rwgBMpxtfd5E2XKcGg5y3OHLO8ku4txvbfu7PX0KAWgzRxU/4u6FXUuPPBJNg03t+6vEMSq9EkCudSzMODMKaGaSVTtQPRcVE8/F76ShKca752PJlR5yNSYvybh6rhNCZXfPXCZLo9qQ7mUhCcMJpcHrtLp9JQMhXVsOA9+kC1X7Qb5HSCWLKqbz+gdi3D2Fo114dtaFrb2ZApwgNWiFcMrdlnRm2gngZxuJ1e2h3CDz0CF+JnhZ/qzC7Qdjg4P2eg3q/R8bmFPBqSJFIHzvw7fieTp4MPqJlnCDVHKyQ+m34o1SPjwQ7FuEtHwQ7FQ6gqmA1NXOPjC6cSVBAMLYGcon4+RhAnrMdtq9hgRKvmhCh+qx+wsSIcTchDw6XBijBI+HM7qrIQPJxiSgHd6SsDN05N+EVzEskz6RTASS5UCHA4+ekkP8lU6X4uEzwx9NyIT7x/pmfhCmXiL+EhDeyaec3eYQOZwmJocpn2pw4zPZYt7ueJAv1EzWE4d5rC4Sb3CT4Si7z9FXm5x+rW+OeDBeOT9FqdeWglpqlRPiy4jj3L5FUWX5Ln4kau0xmvyEj6LLlmsPxRpKh+jQ70z5CThw56JIs1yqKjlfa7vZmBHM+aDoGcUYxpcSfiwzCmvEj4zrlAlX8O3hDTMgJbmcHUCLnIVYd4ORdCQteB3mk9RZFLSfpe4S/hwEKGsUm7TP7gq5TbMavRawqdZLWbChVmNPgn6kc6KHi1nCR85W8ibhA8zLMz/seg7i2eLNLfCDC/S3Ioi3yLcS0v4m+D0Ld7MLQ6jasiouu8XODnab3pxX9ri2M5uM+LMh9juS2dONP7KfS9xlEeCuhSST7UC3PI4crgAbKHX78FXURRjAbxXusvh3Bfl5QLFC0QV1U3M4mCVNUr4gyoqwsfBNbsVfrR/BP0oVAdgw+0tjQ1faMP9pdqqPdRYKS1s4bE6axLr+mxeoM+axNldzQuWsyZxtt/NC8xZk1iX5/KCHkFj/Ks4cDYycJ6lnmpk+aKzh/CFQ/lRPqlc0qmKkwrNSUXZ5jPRwkkc9QE+YRZnawdwUFKxPGzh4IIewi+HFs4ysg59DBCdaOF0rKTA8ZMCW1LgKBSYFPFyXSKV9TSx9U8qcEmnia2+qMBomR4ntuqbClzyaWLrnkxsR0mu4ZSJLdtVuOn62RaQfhZWiLKSfpY09DPMZzLpLX7iOya9rJ8lkX7iihmYDP0sifQTFkzD6xau7OGCYXjn2SwrnU1gYZ5Ns3uZyeBnUYG9BgusNbQV7VBh11U4rwcb/JztfTpz6aW/0e+662P9tB1f9sbeW0uy5TrOeYN4OAp/bQsw5j/Z7Z9KcmTbTR3JjNm/UpJzaDEe2XRT15FBLFeOhDefUAcWwHRm9ut9kSkAr+N9J4pqktaNCpUp3wmMHGriww5dHZUqbP9d7ht5ZM896NDpWL4loA+PrQD7+x20EFswsBt042UvZhSc+srAKwOvnAUnrM7QyvalvpJuPN78sBiwe0OeFISIlgpRoaXyhpIjfGc2VLwmKwV7K2pCXtP0CsAxOgSkIrsByyAWKF4wwn63BbGgGaO+YOYRXie5YOcFI6HwxjA/jvlxzI/emB8nowmvBD8imfFG83rbLTWc5m6pvaZIGEDEq5Ohg9d5vixCDa/LJFAEEm7zAmHnzMlAwtAQSQ8Y+tu9ohRFpakLFO2w21vq146FuflhhT0FEqusJw3r6o/TAVt8aC3drk9a7Drpk7PwTytpThrgOqlLKD8Wp1nOvZDb5INVWxqReYdvCqV2NFKD64Vy9KO0EBxOEL44T9BwlPghOIywQB7GbZtf7JRsEUt++4obpMUGBdqg9LDg9yWr1fCmkzELW4exsvob9vAjcD8QviXqAjXlCRd1hDrqGnuSp2Smd3uSp6FqgV8cgqq9hM9+Y4Ve6S0douZIssxPKfvJqAsanhE9/zS+zwrXnM4OgxiZfWoMomIN5eFhEBOkz6Es/mRWQxt9FWU+maTQRl0bpagrzw42oYojWANteqUgukXFOIeY1YSL6HvMJgCePs+ZM90UzzeHYLYGy6g8fUJjuQKt8kDlGJVjVI5RDS9dWaVhgRwW5ZIZYhhm4KNyRwM/MQ1VTWL9NFQweAtmY4NGgRq6vpKul2+Nj8VLY2RcEqmfQz22O2kUHTiHvRaH9fP/qPiwbM8VHxqqelL7d2sYVfKXtBm6NXs4E26fbKVWDisAp3Rf7IVAQjTefOhBahXHm/FQ4uWKXKWgjExwe+HwYNjsvs0E71PPmkPG2ZisFMFRuWMY9EqB2zDogeGHAZW+Owiv/JHRrI3LfCaK6o3iIB+MuLPqJOEj3GwvFPFAjBSzm+nwEX5WZyScI8W2w+sGOe/WUoQ50+kTHcr6f9G9uzjraS7Neg4HGY076+Yt48R6/ZLxF4z9H3bzlvzaFltE9Xw0XwnsvSLEatyok2lI+CnNSz5Rcz3z4Tpe8+GjQQP7Lhs3nEt2+LALUe8MV7IDAQeKvF+Vvr2O3zHkKmOBkNXEI+pfNTsJH5WzmjYJnyOYK53wyCakNyIzW4rINocGK7SAi4ZjDxyYzvscfsBnAMIWB+mZZbhhNzt8ToZwlBHZpFGDTw++zKHRVqOAi3kHbgh2+Jz7YD/T4bNxyTkxwEWjM+1SbrNBmXYn4aNBGbnu0PVhzoMUqT9iHoTz+g6fjUs27R0u5kHKhB8al1rKRzQupXyGxf+TVwvVzIYktv+GZc9UzTTX07TPqchVC39MYa7Oa/w79bncIr3zCLaehImLG3XMLX3HsK3xrEQxByCeS3eiLaeTIsNUrvUlw4vxrBgy50WfJT6dzp6MUHfNLyHe15NM09arxJ/+hMgNV7uW1xC/nfhDWy7+OiCwGbXp4DbsOuHCbYy5k75+jp/hGF7LQ0GzMesELek3vvLNJj3NypP7uHLmm9FJkuaISd2UhM8RQRskScPTrJzPAn6RiUQ3WCjSc1SeKejwGZzXLOHDM40IAOHTkxX+8USHj9g8WoFHeKbpKe3hN3ShVAkfHqgfFoYLD2SjhE8PZK2ECw+kJ1xOJPqV5XYoNK6LmnBRB5ieCfkdHqtOOSTpWVfLo56+yvpDtOxx7eH3biv/uAT1Z0ZUY0Sprx8RUrRuwkXEtjo18TyqxnTVDay6gVU3sOqOYGjlX1/gglmNid4IkuYwSK2SVBE88dxxh/fg6X9cNBy2###4656:XlxV32DM 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113ceNrdW92OIysOfpl9AKCggLTmVUbiV5qbPRdzOep3XzDYuJLUOd2VrFbai5lUf6EMGOPPNiSLm7h9/JJZzk/VP//SAj4/Y6q5PWztn/jzLy3KTSf78W8t9c1s4qMh9SY3sbWn3J5q+PilhAVRSu1DlIe/P3+bPXVRf36kGm+t1cePLrw//FQitgaphtZA/QG8vfbxU2YDeEG89S/UfFHt8F3C7yJAPzqihYTv/PpuytOAuyWvzbzjvb1UweEIU/tCfMwWorcQrYX1O2uQ6mzQHn72/9ocdUbRvUHpeGn41hTW8SZHoVT18fkZc2iPt3DTt/CnqbX9sfnwAZouamhVKfPxV9PEXKChVVnU+Lu4oW1h5meE75Xcx98yjL/3+f0OeMypr4p+sq5S1JN1xR6er28T6e5FRhRZror09yIrisxXRYY7kXlDkemSyN85xLHoXanMbrNViAewzZ9N+9C+LBzat9WhDWKGHNggXaXzweND4FsmW4Gi/OxChm7iZeeiDIoyKMqgKNNFwWhDXqLGqCSMdqfRutFFsznA05r1wPOYXVrthzbKMPVdNFNv9uhuspCxx2ns2zL2X23PDONOdRr9cy+1NoWfn2F+xvmZ5mc+bpo65dc6V1bMTzk/1d9vKjU3nfLzM8zPOD8T33Qx5W4pOzfjfdicsg5tzhu0uf3rGiA/nZ0728/q4n5O2d2POuCo/btG7c9chipXR+3vR11w1OFdow5nXknlq6MOd6Nu9DBHHd816njm+NRFx5eKnl7GoXNx6FxcwId48DKmTu/gwsHLqG0SZ1u/Qai1QvvC8M7EbbNC+8Rx2XF5iCEAVx1Xvf3G2kMMASNUo296x2E8kEDWxnHV8Qyy4sKnLI+yDHpR55n3a+8c5tcDg1qgPXKHcwfu2ATrG9pnD2M94F1POYCcxMcKEQsQhCT9WR6oZBMYviKcrBzHKTZKJXEcdDHmxeRMXTjSa+V9UzCUwc0CHuYaqQSy8sKnrIiydol6ipwzsypcVrcDBfMGW0W8z7s5a5AjePtuTwr0txnevnTcHTjZIRU7pGIX8CEyTu4xnYGdJm+aaC5NmtPnMd093bRQRZ35dLldDVUMkrM6mNuuFs7IfMQRiK9tbBb5q7u5+07y5WY5yec5e8Nnn+x0YHl+fpX053vZXSP/ETH/Jev8vuYXgwL5pYjbli7PPgkCNk3EtMuDi/+eZsjVW5iyfcLcmybmzukdXeW0nTG4VNe40MICHhg8D5G6EBeKiCLNl0ffRi2Rbsv9qDFIcBQtpcAV9M+K0GdBgZRXUxVzxthSXNv/bp/uvVtjU1t3yZ3Shs4JX646TPfeG3DaCjvHF13LmSADDhl0Lpy3baj8xT6ACpwaLDqUjfOmzQnbZ+CE5pgs4HbhjJttLnwixHcOeXm0J47Pu179suzGJq4oVgHImePEjzbvHCd+tIHhY/zJwkJINh7QQ4Z+o+M48b7NnuPE+zbz9oz3g8d5mQNfSs8XSOICUQCV0UL6izxp3YkJNM80c3ALZwHdYAg9FTtSV40PhuewNjMb65WbJgFCjkzhQJmqq4k4iSQblGxQMrHUJgfbQQw4JwqpqK09FS03dVscVSZH7f87jmrjMqccsb+ZI6o65QjzVo74bSvaeuuT7+GSF8728NqrgNNeXbYOONm6LZXhbG9E3n7tpbX3AF97L1B7w/eqxdi343xvV8Xx5QuS4/jyHZhPAL58U7dGhpPzXc4acHTWnzG6XjRsrnZv/5EB12nA9qkBf7eicrHMqC5VSChIcmI7qZToTCyq5St5cPTmJKqOF5P3CFXhZzFQTBclBnkSTMR4NahyJwUGXcKbFBv2k3AlhmvRStSTc7qGGTkHSIxMx4e/Hw3goWluPuycCqKbPqU3YDQVHeuCxR1OzL3dLZL5gmgdtjc8gYqY68KQVgIVKpPD9naohuPLF2B8BPjyHdELjpOvic5znHxTIF+D9YORz0Yjlh4YjVOeO1RqUaUWVWpRpcTboVreBaXYNiqGrxQ7OsNxStWjO7SncgAL8UaZ5ecoBXTvN6ew89AmGrXwFbl0d5ke3WUQ0126/567ZDnmiwXns5yyulN3SY5Cq9d29VkRIvirzu0sZQzumkQn6knNV6f0LjWcpXfBXlXDWXYX9ovu0iXcAIeYP+qycBbSrz0fFO7wDR80Phxi9aipi0MWEF1cOHOvy1MHhX55wweND4egPXqJHq3yCq4TZeEsHYg6YNeHDC66wOWsDDQqjlPiQx4T8JXqkpsbOKW6USMThEPJjDxyHw/PZMldVndgFMfkMEZZmXJ1R49/wJnHNwxfjBKd5e2JUcKKXh1jpmaYzY92brjJ9jWdSgc5/aU/HNR9Ny/Sd37zuzU8eXeQ9+banbLfDF/14aAv2gdnqceeXtGrmPG5LPULXiLA2bLhEs2sVK2qIVSD/rkYdlcEC+DZn55KrmQzxpe8JlTbn5FHNhe9pn0gDzcliqsaTvca9qiG+KqG9dkJqrbv0rA8IdOsr2r4genSkJjqVQ3new1nVEN6VcOnp73avUvD6YT583ZVww/ML6aGy1UNlzsNN38z1ZBf1fDpyfQ6S3hRw1aeREJZXYyE1OS8rmq4FdY1NG6FRTxp7jODU8be/0wtzIbvyUMEBQHm9gfEwL2v/jLLeSj3AHzlPAGIC1/s5dbRYCU/eP7bRzp71MDOhfdYsMe7g0nfX8TgrTnb8WAxitsxc7MYzrW3JoJpnpWHAA/PhUe/uXcHUQqep4KoodFMGqXJz7N16EaNAFDwYRocpsFhGhymwWEaHKbBYRoc5goSzQwSe0ueziuDw9xwmHgdMMqMw9Q4TFp4jQazSx60RePwncyPK0JNuDwZl+dwrh9F4Q0qNljhIybigK/wNBq/FD1nBqM3NDPFLzNGY9eM58jHoujVfmoikiZowRRqQqAm8OJBh3iBw+z4TuJF0wAXLjbEQROaV1ujSLxBxQZUpqUqD+CrrBtSZS+OvaN5PTgajS9GfpgVqscXIw5J8eJLFIE3qNhgxcxYzQGcxczJsRfHkBQPzgMEuLjso8Hhfsomd3YRdLytALeIZ5zowB07whjCBu4nrhI6FTja6Mnewy27oGbwHv6Pb9kFSKifxrMbxbN+fy0WyCfxbLp4xhugaPo0RNzsuwZdTkLEJK4O2p5FXZt716DrWQW8Xh30WQVcbf5Ng7birAJerlbAsaxsxTEgIV461F6p1AM4q71KyXEKP0LOHKfaa1Ss/QySiCHwjntfo4cT317r2TNGGwUfKkYb4hBtCMGnQcFNyEQJlteAohILn8RVD5EGdW+we4PdG+x+RREag6/WkrF+qJl1z0mdD4uXghIf7uJyUTlOJEAlq777GeNFkTlORDeYkHA6KI2S4VMdBVdJaPbOYtuQyHIOh5lRloVPWZlWHGOS/fDDjFD5PBblB/zhBfTBeXfj+KJbfRjTOvQQgePIsp/R9epUv2J2s0Rx26S4+Pr5fZO/nZzD9+LA3MnGvuNw3Bcsd6qNBzG+GI6zQ+FD+ycHR+pwcBTsAV+RivUcJztwGMx3fJUpP6OP/c7E1v+RzvXUeWI6X0fAB5pu78u7XxIt/0vFoHo4gTzVWZxuoMtkJ0MBI/yOM29Guhw4er9mR3J7sCMz55Sfzulb9cEmX9/ZEZ26rlT/PXbUpzLWTeqDTvDAsuNMJ8EWjhMjLDuSmjPIsjupOeMsO5Wau/Bl14BjItl4uC2SbNGpalkh6nyfOi8v1ZaPt2cDOLSnezhQCAGXJl6+SzPs7tmP5LYiv/cjuUBuWM7funXhd+bdH5gbpsu40HSxqyf3LAt3IdYbjpMLmb9/wy+WD/HFc5x8iMcjk4GTD/EUVchyuLgSfMtTbrGpKtHa27n29fW1Z/euDinJsgmfz2xiXynC9hab8OHMJqr5lk00z7ndi6IcgUqQcfuK5ww+oifceIThc+U4RRgeD8s6zq5uLZPzh9+jBc9wZqLLInzmprhM1GduikN7iDNLJIvz+WCJWXB8HYp51u/YTh5/9rGs2ueDlboMKfTWU+h1X8ANO62C2+mwApYif+/86iH1VS+dQ/3S4zwtuv3BIU073w3FL9U+3m9GS0HLacqo96XlZcdkxvrrOQ2OsUuu95Idek2S7L5eBmeSIePdnh3pSNp7yh/K4Sflb7c/DBL33rqDHY9Z4xc9hIfkxzzJy7f8ombd/X0IOg5Yl/JlfeUGvfPqLJte193TK1cufju456NbBNF/9p3dx49uMfDQVdcffmqoQTq6MuAVj30cbLOt4W4c9UMDFuw4ulXl6rx6DNV3lz1/UeCLFA15OFTHBr2CCA1WWOQgG6UGBRtQfOTSLBB3Yx0S9soTNYc32QFfSaLLlr0Ik9or9+UuZXzx4Dsd3tHoOPhCV/8DFEsyyg==###4580:XlxV32DM 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11cceNqtG8uS3CDuZ/YDAPPsqfxKqmweVblsDjmm8u8LQgLZbe9M9/iQ2CPTQgi9BfmhlP3498cn9RAP9feHL/mhg/v4KZOpcGNjhesOV8J91JfSX4IQ8PJTia1hiAUx+PKQMVW4cg3uE8JteWih8Id91qz7twbqs2bV4MHwWQ3NamhW02Y1QPdGdBfCIGHWOOFtsjp9XZho3xa5wre6xPQBZMmkAN5xVcJjhQfV4f+2IPxDPuqv6iP//a+W+SGXNXz8R4v8KLI+U5vEfPySMVcU7Vn6Mwl8Snw2Nn/8rszFvwM+V3xu+Iz4TH18Vv3vgvhLx6+EwKfEp8KnwSfg+62k7X8rj8+AzxWfGz5jH2/h95t3bb72W/EXVquj/agM0HUPVFt/5d0SdOeALPbrHNCd0spc3UjQfArXp7COZhALzbDytTmk2XaMwXWM3pUj0SsRvdxF9HYkekOi7ZtEe3EkOhPR4iaiF3skuiDR5l2i5YHoqjBItLyLaHcgOi1ItH6L6Gp0PBkqiQapztENUhABDVIFgTmpmtB+s+b5m2YVwEYwAwbwumMV7sEsRQ4vDR4Av+d4RIOvMN5yuGxwMKqhscVUeqqWdPtXJa+/1N3EF8ctYoB1wxIsLkHaYckHKkeoHKFyhGqY9LCQU3ClU1vtE1DrGbytrtovgBcOzw0egHuC41EfYHkb/gVJrZRw81/SHN93qJGKOzQ4JZCDVT/a3CuDA02lAHzh4xtnwQn41XF421EBc2fF8bQ1lAxwNh6lxg7nuVufbOsD6QiB4JnW3dcXJxzXt9L6Fkk8Wbkj9skxXLC+WGC84HPAHgE/YuJwoAnWnTLH09ZX/6tOzmRbnVwl47GhixNSo4vL5OJ009yEGvwlTa7PZefyDq5ps7ChK7dKiqxSHhpuScPd6xTgTL+Uldy2/NI5dhtjwCLsDCPZGFPeMzJd25a/P9rymjb9aJMw3XIQ4uCASgkNGHqsJAoPYLCwgUvDnFEB2ngmIJYUAxA2oQKEIFTKxvmNCYOyG4cP4VF2ZfApbMoGDifhqZFTxIiqxn34MQE8UaSlEN4jKluZLB/VxD7CiKdWFLbC4qmxdZ/GK3oXt1jRRGLhXkP0HV3SdNAOdzSX/+PjrBRHVLKj0utGqJbh48yTPFZ5k4RKHX2ZIlQroUqOu8vP3KOV8kjdQgu9cuoXItv2pG9uxcl8X6ca4KoLVhvQBaszBwQCw+wG6WG2FWl+Q3wa4HHiY75uaoTslh0HDCept0GI4E6V6RqmJkDg1LVFZhbYd6wghrG6b1mjevXwQww3FEM/xfC3jA4tzUuWp9o8EMs6z3IM7gzGSX7YOFl2MvSlmaZsxWyuInWfaIqovhGK/YkU7LS5miBUdXcAVwRfYO+rureNTqr0fWnwttHwQ2Z+EmQjY4CgAcMOJSCBBtQd7wOmQUpy4QMyDRiWKeHW44D08ZMsU2GWqU8LIuFFE4nmCu0QiYgiEU5F4ktcrHiv9qcZAdwfLb+zP4307trFbn/SGiechSGJ9KnDx7a4tXD43A3ySADnm2A5fIYUyaiWN1d39JBucDMhN9dd3vyqYpn+LJgnl/Rifox5saK82L2SH9eVNblzZ7u5+ZH4lN1uvrbCYeEbE/cWnvLjJaeXLHyVwfVINeaYix45ppV3UO2BBnfi6pZlhFQp3jBVFfshfq6LPUblUx0cdxduZC8NznIwkzh85mBCcfjI/dzG8bDcT0iCrzyzcOs64V09Sxzuq8LbTvOCmpUc/yiodYHA8TxDsJ7NC6auJKDHcPjMaMRu/MiYXORwlmFRYtnhI5PqugD0LD0+gIXAHnQLj9+46VGFwae57jHAgA8TI9W6Q8RsUubw6VrkwhGR3a/q1ILQ6vL1Yx0WKaNF2k4jT/9WBIqe6SwCzeW1CDTJhtKcRaDbCBuV2EUPX4waEsx5VsDRWxhRw/KdAk4C9TyNUHN+LUJNpOnthUWoiSQzoQWAASiBkiSqbghEqA3SI9QpJPWFRahJYEDZhkLgkvYmAcVxjBA0YhiTBKaWBrTIJR2sEEW7fUCmAcOMjKgWCG9RLSyKRbVKsKg2oXGqIu6yh+Sq/hsiXlDEIwth3nV+LocL267zKNkad4dtd1Sra3My2766ZcKZTV7dyuEzt6CQpsOnzScbC3BWp8uGw8emhLwbTza5+ju5Hnm+CeR5uoHnHnoTpzyP5l6ee0l+qs7JeB5MmXDG8zD8DsCfed7hjOd8/OS5jzv49Kdx4fDJcyvcsYiwyc5zSQYFo8svpWmsREWlqXAMvTSarqJerCKIp4YBZoDajiqCctdVhGfbbcF/m7MY1A63EO1OJL5osy0s4zTmLPLVqsIoGQWKVnoVYJvwXjkQ26gcePrmseIgqELfqxSQ7HfpgUEsVGCFtQ3LCG3ADBmsiHyApAEjdrDkTtrLUy90QZKhziDc3iLLXbnLk0VueWxNhJoASDlkVZGsijsyoYT5aPIvdhblTuYT4DvNbOyICMJyS2aTLjOb4l/LbKSARHCnXwHLH2n0/OT2eYWFV1TCESW1EcPIlmJ4oVrHApi0z8STmfAewKQRQidN33bhvhQOtQQW32Pc5PuXvPsyGjH1y7L7Mlo3idokkRxkb/XM+LpRPOsnM3RK+3rLCOzTvkZA5wv6ymf8PhKEtKtBzKQo7ZKiJDWnc7RaMjlmWFgvQsFBgEgRRKQIomoK6KpihwAihhFNV+sK5GOrQfFo9W8Laequ14/l3dnL/5KmjV7+oRHyS3fN3WJ8UgtL3YiR8JeTKvFobKDc1bXocnQRqGFSDK8j9NcbG0RkK0uII2pPqIf3EX7nG7+IOsZj6jR0OQzvo8KprzxWRaM+Ukk67COh2t7ykcnII+qNGBC+xdsqsyjMjXzMqKninpaR2EreM+1yritc40mZtkP4InljaRzp6SMdjXQ0cihbL+ziyEpdH4kvEl5+ajA5Sa1EleDHcGIWEw5evm0uZl+j+hupPFyXy3R62JIOnzZJEVJduEVMsjCEUC1uP2RGbhSDo+JGKKYy4Z3fuiC/F7VwOwGUYKHYPUX8muyEuiPkhyjoNOSfLu2mkH+Wdvw+zWLwXZqVOPwk5KeQ65BmeYrVDmlWhz+nWR0+Q/5UFftQvdkMMT3eWb4R6qJ8YxbzYvlGLMeuH5ZvTBzpslKfl2942eapIqQI5WhvQl74ulmDqulZucYs+tVyjaSyjN6XayjaERTt1AFo3gSZN6GwXCOGwRBifmPlmljKxHdepRELVWkMl0sXLBvQqzRm11rUFP6I5bw4IxQVZ/Q+FdC74oyZLcf4JMGWJLjcKMExpysJVvE1CY45X0qwfE+CYxGXEiy+J8ExlysJVttrEhxzpOCxcAnu1Dd4wcNAbUCX4M4s+E1Cl5fp5GnM2/zGJTivE9+pBDccvUNaxKkEwwDweWXfHNdjynwqwUBmk2BYApdgwyS4TwsSbHyGDqmaHdLNoQRLwVukIzC2+0Os2Z8GvsaXi5Ogy1Ww+kkkaYK4OKa5rG9h/LNk9HyN2La7NS6A03Ued71NycIy49l4XkvwWB8GeIuo4Iczohr7AxO1/WkD2P4YOuEMcKAk+17+lU+BiScLo2+p/6rL+q++u/476q1qX4v0E76rRQoOP6v/qtNaJMBPapEd/lyL7HBW/xWpMjxXpZhZYyCmmxuOkry9WeWyU53VrZtVeZAva9TbvXKxOrRqbXmsbBAMnW4UeXdOV6QJ5z3i2evcWUfWS827rs0mOP4hR8E6Dh9ytzrN6RwFH1fUhLOjGrPWDfOOnu/sO5TdMZbZpyi7Pursa5RdH3XqQeFt1H9bsM1o1ASq2o0yJHglCba3HIY6uIO3K5ZHN3Jx1wH6GG9rDgVSv5S1XZOSu9SkcK8mBbtdeELz7p0IcewfUSFEJ3M38fHC6Zo370YE5y4uLpg3Ly44cOPnufXozht/CztcvLjAYN68wBAUVpEbavD8VUTBeFhyTmlnPExgcH6ARXP4dJYU9TY4d7pWzXn55Yi48XmZEY0cPrP+2XRN3IjOGwqWLiZUSH9xjl7i7oaCogtkziEr5MrjgAZnlyB8WPgUhqYwNIWhKeZ9CmqHwsgRZ1WubhPOIr5gxnGkjV928EJMOCtEu23h40eVK+jI4fNSQQwMzi5Z0Fluj40xupQRNYePLkHQiejfeGQa6NgUsGhGuMGgi2t2kLsyurrS4MyVTVeTHC+2BbNy+LyYMEKu5PaubAcfrmyGYsntTvg09WjV0tZvUzPJ3siXuW912/TBl73VbWP3+dI37/XJw/0+962iQdBPV8Sw4z271IeawaeX8dZjmZyOPotRhpDiS0efD8V97+Tl5cTRP9y2790+01eXE8ubvkw/+TLsm8ym/asc3o4cpnaJSN/l8HJ5kzLcxWFzdZMyv8vhp9s8ETGGdzkcjxxOxIb8XQ77y2uf600c1uLq2md6l8PHzjiVFq1/l8Pp4oijEuW7HA6Xd1S3uzhsru6oxjfvqBYKLjSejmkc6kVEX8ZNwEC3Bw3dHlR0+bOCeIiW8Z5EQwNlwvZjGf8Ho43bAA==###4528:XlxV32DM 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spzUqwsjULXl9bWlBxg5X+pWyF/dCo6uLb5pKO0U1WOygOZVhk9Y+ahGMFVleC5UGY72Cdz6V+DGJPf8Wjh2+DgUyXVFIgGO5MjI+CMmQqgwshymwTdmqtQP5GXHj5UIUAVQTbXRUKFSgJBkVCX8R1U4M7aDPZhom8pUAFETI2SN3ulUjp/lwGP71lYipQPYGcigTAAipuKiwOwo0IiLod2D8CH+6cqbdTmmM+yi746hHPW9UQ8VCaIn+9O+WnZk+f4RxrtAc69MT+1Sf9+lHi+Yenvls3fEz1fMBl1tB0yH7pMmywFvFDhphG91kBjAEdYzHcCqS3MuzRmaMzQHOm103PC+QUcTHUl0dKK3cwIdlXSMSDqCgCT0IwjopCMEEST0mMPC2s0Q1wgK3wQFEmQCBqCLsibKoihrIiiIoCY6ooAmgqIIaqIjCugiyO71fpgBN/Rmkn5nCSWOwaOpVBZFI5X561ieDzN3DcmkcNNQcdAF7L53Yf+G+CHbWHZTQfK1XoW49toH8xjfHzvLt7OpWJuVd/G6kU9EfRO7FDU6uekJix7a/U/TAytihgMJ2LDrZTUrjA3ubpWfN348lNYuapMI6sRB+4Vl+0H82NtZgWlRnQwAHfwLwlLH/sa9ijUj84sALgENALoXIuVwqsYMoAHgHIb4MzAnA6ABwJwgyzVY8waQN3eN/SuI0yxwN55wfnEzZzc45wFdx0pzAbwFxuvI3qBsQqWaQA4UkByZ0cuxfQB+6hrpGrk1cnMksALhSWKP+Zu/Ezfjj6CIAsAQoP7mZ6i/OSM51UtkT35XXqMpTWnf4AV3xXRNaVN0RGQlcf2HoJy+NrAT6fOiBShuAegMILorlUdZ5GKbf4BfB0qlDrZB197bde3VtOZcEhxvOkpoqF7qt61qqF4KodRJjEboW43QtxqhGdSjt3ipS7eqt3gp3lInMRqzlxqzlxqzKUMgNqq3ePdRd/UWRx1gch6jzu2Ao2ST4ChZap0mKDOfjWy7WyAb+yqHFSbuLXd0z91Ec02VfFRaO6pqKevefXZKdHubDIpK16lEWlSGKXkj9C6GTaDcAOtZWelD7+VxKzhleUBP2fQkkdE38rqRP0KOtJIHc54ghK2KyjXvcv/YZYwgiuqmaO6Cxu4eBKPqBfaSBs4q9z3t/IK+imGbNvMZZ9pEenp4p5doyJ/8RRISpcd3iyMbFcvmXpmhpOZd3xj8LSWQQGXdVPZNZRFxVcQ1VU6SAGQz0z8CFrjO0xZ3PxgLDRaSqvlN3mz+XJEt1fdiyvk5+FZ4jXAQcEvwJDYXtZvm7onsjLgb2wYMQNqiTP62dtF+PpE/sj0H80335P9C91IiuRaNsBPkSQyBH1U4h5JE92R4+4RbgBwqNXWWvBin18YkQnO3+RatNknKD1qXjJ69ib2pCeCWab1ZGq5sUrEw6YIX8ShcwxFVIemanQTc/h8f23Qw1PANHWYHhRI56yyg6LD20QwdzT6RWydy60SGTuTWifi/ijNTE61mguTeRXsIQqIIqWo2WyJEeXV3SBf17Nn/nDZmFR7Vx0HaI9IekTZF2iPSpgd7p4I9phDQQjs9jrsk7XzJWfH3OO5Wt1iSD8PqdFB1GjbNmwW0dO8xbm02ALBfLPkPF28g5zFX3+0Du83yUyPfrZef9oHv/oRIBF5zbU1xX1NiO3mTzCsTHliB1nQKlUOfroFno999AbCPR/xszJa59mmO4HtQFN6pN95bNQfJqHwirk1GpEYT0diIphBpf3HJslL5NEbwKFLdHNXNUaUPcshisdVAV+HR3JP5sWRW97pLRvdvBW5U0X85Dng7UmaDE2YPqriZNVNxn+zA8v/N7i5d7/SQ5sUcRZ/0qoc8M8/COlCmRvSbmi0zF21U/lE5qubULKDQGRrKdcO0P1rflJTzXPdcsDX4t3CwedTdkUqNcmDsfxs9RVIHomB8C5qUBXTNXv4Ho/JX6HlN+nFR/2/il8z++aMTVu849WvnqV87T/3ayRetqVO2Ka+MPxiXfgHU/5trKWlfRGPUH4xBf2Iu/SZY9SfmUmLfk4RNRjsgbcX1XllYLAEjadSYK8KvNSHxkGf6/LCAX73GoX8fMv+4WyoRGPTl6SZ987rNKcGVh+nG1gW3XkylYchScFfhurvXzzfTgf8BlkjUEw==###7068:XlxV32DM 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eRFnvBGyqXuZOZhI/ysSOK+D87x5grMbB+d1DReg77FAl4gN13hTraBwI9du+WE3ObntB4mkjAJ/Jrxh3f48eC9uInks1m4PWyvOT7xFMjfQSl9EocFak1iaevvnErmOJopzWL8ir9ygUeSAlg56W7qxmEFrN+/ZyLzhMtwEREe/crfhnWmDrbpxiTQsWUnbad515IcBQAuaJd28zHszTfTTvnj6ltyX0+8uha/Ky0CtcRUcrlblgwkp4fmXtX/1mb8K2P6cFBTyOm5e4s2EYlfar3ArPgmRM++rVPO/yrSChp0LVHjpENBQibUSXuZNg2kX7vLew1OACZiXgMkLO8NgHg3iJcCw6we7fQnY0AD47CPguYpg/mT4KqDdBTLFR29lFJ/qf4UbPkIoPtUf4ekSYPj0A34kwI2Xxw346OWI4ZPv8tPD3F0z31NSrWcDeMhL65d3IrkVj1dtFy8/dG99Nhd6wEVrGKyhGPVZ/4QXW+z3Lf/VrrOdBE9rZ/W+0a52eD457JiEdhKGnoCjG5pp6W9WUr2QGtGoR58lCMYxdT4DHPBidLVapaZ4RwF7pDrsdwooYIaPzXZ8gQKKo217PDrDX+0629FwvN8LM13tYPisv4ZbShe59sH8Nde0n/WWYtrPemmvF5Lft852pxBo1Gnnrd36q11nuzNteFvZHyttQhnKs2S1Wd0Pk/CqGefJci80Q+fKzOjlFmdmCKVJXUNd7QmnqB36yw4jHjdEjcQ6OHYwf9Qz1G+Hzg6aufPNgHWwu53hjl/E45jxdky0i3c7+E+8/Ue8MDA9Ch6PEZM83p1RZbyB6Lx4xvhRLFrFhCAak0PX7cAr+mvDI69AfzvWP49dKXwilLIJETdOzOAevkq1LUhkSWi2KqR7wPPl8Cp5ibyKIJZoWnL5tx95fBnvCnnj8Pj61FXy+hmPbzdd++1HHl/Ufxnu6UeZfH7qOu3bh7fJG8azvEOnJ58HTWE/5+WuN+rZg8QksUhsjuNIeBIRRH5tHoSwLP0Lv0+rIMIhlNXJ6mR1sPDcG8SmDzkSWksuL/3xM+SZi3+evSD0N7G41nkbjV9ZrJU6CfMGRQAiEDWMMBHziIDvJVR6xS/39UB86988FQG56InOe2Oq+BATiUyikKgkGomXRCcxSFDgl5mB2GQ5Ep5EIAGg7LGZvet6M//ngsPrewDlRRboAn/30GfsGv/LW8jDYihSRUa/9+KxHx6Ov5U8LJSy3enXLp714+P+8h5eZb+Xv4KsevFOPw2I5T26YIFNKcqjX7l4px/sO7a/nFh/9MwXj/3Mpwpvt2TSbLy2Tr908axfQHWmvJM8rMGa+D9eXM/FO/1g3yIPDljefeyLF+/0U/sSz5zPfq8goeMlHh6ffQUXBCXeQ6fcrlVvv08lLMmUgOczHxLmQaKw44pBaOml434ostqmPCpMx/HkIRLpexcAe/OsXz6OQ5kRgUuexxAgd/FOPwB7wEOcs/8UdTwWXZR3+imwca7rB0nyaMNxAMRefaFjNsx58axfQRKVMvZeDawOoAcn77+zBV9Bn2E/ybnPGeghRxXgLp5bwivsl/vNk2ibxc30Twam3cbTgcvh8S8HUSEigIsA0QWrQBxAVDCe1z+GeRZIud79TJd68XTfmRmOk3iq1E/qedpPvZlHADVLQ3SmfXKnaWlFK3xHEPk3YqxMO11r5NZ4uPyzxt6SyKPcyocskccHPKdRZgNzsKf+Ti2plD7T0iS18m8U/SRDdrw4+9+/s/GmqN399GzQ+MuJNpdETX/v1BP+S+A6n6q+uYEXCwEo5feJsFmoL9vsNzp7Gc53x55PdnHB+6K8qX9G2DNEn3iF4FGWnLPyXOS0rFDOw+nJ98zlyB3n/d55yaeFm42X2XPmI61lSuPTmMg3ppD2npewh/qVVuUSLxxpT6PNfKAT+aAYrwwn5ep1vY3QKU3f5i7UdEyuOlpFxIh8sYQHUEHfSOhvIe6/nz3hLd7xpTdgGHzGOGiBMZHV4kescLAf/GXKmlX8dL35WHB8OeX/AaYL764=###6888:XlxV32DM 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\ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ngm =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ngm b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ngm new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_map.ngm (revision 224) @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6e 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+ + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_ngdbuild.xrpt =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_ngdbuild.xrpt b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_ngdbuild.xrpt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_ngdbuild.xrpt (revision 224) @@ -0,0 +1,127 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.csv =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.csv b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.csv new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.csv (revision 224) @@ -0,0 +1,175 @@ +#Release 14.7 - par P.20131013 (nt64) +#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +#Mon May 23 12:38:47 2016 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: chn5_mem_spi_joint_map.ncd +#OUTPUT FILE: chn5_mem_spi_joint_pad.csv +#PART TYPE: xc6slx9 +#SPEED GRADE: -3 +#PACKAGE: tqg144 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, +P1,addr<6>,IOB,IO_L83N_VREF_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P2,addr<7>,IOB,IO_L83P_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P3,,,GND,,,,,,,,,,,, +P4,,,VCCO_3,,,3,,,,,3.30,,,, +P5,oe_ram_bar,IOB,IO_L52N_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P6,ub_bar,IOB,IO_L52P_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P7,lb_bar,IOB,IO_L51N_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P8,DATA_INOUT<15>,IOB,IO_L51P_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P9,DATA_INOUT<14>,IOB,IO_L50N_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P10,DATA_INOUT<13>,IOB,IO_L50P_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P11,DATA_INOUT<12>,IOB,IO_L49N_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P12,DATA_INOUT<11>,IOB,IO_L49P_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P13,,,GND,,,,,,,,,,,, +P14,DATA_INOUT<10>,IOB,IO_L44N_GCLK20_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P15,DATA_INOUT<9>,IOB,IO_L44P_GCLK21_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P16,DATA_INOUT<8>,IOB,IO_L43N_GCLK22_IRDY2_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P17,addr<18>,IOB,IO_L43P_GCLK23_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P18,,,VCCO_3,,,3,,,,,3.30,,,, +P19,,,VCCINT,,,,,,,,1.2,,,, +P20,,,VCCAUX,,,,,,,,2.5,,,, +P21,addr<8>,IOB,IO_L42N_GCLK24_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P22,addr<9>,IOB,IO_L42P_GCLK25_TRDY2_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P23,addr<10>,IOB,IO_L41N_GCLK26_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P24,addr<11>,IOB,IO_L41P_GCLK27_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P25,,,GND,,,,,,,,,,,, +P26,addr<17>,IOB,IO_L37N_3,OUTPUT,LVCMOS33,3,12,SLOW,,,,LOCATED,NO,NONE, +P27,,IOBM,IO_L37P_3,UNUSED,,3,,,,,,,,, +P28,,,VCCINT,,,,,,,,1.2,,,, +P29,,IOBS,IO_L36N_3,UNUSED,,3,,,,,,,,, +P30,,IOBM,IO_L36P_3,UNUSED,,3,,,,,,,,, +P31,,,VCCO_3,,,3,,,,,3.30,,,, +P32,DATA_INOUT<0>,IOB,IO_L2N_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P33,DATA_INOUT<1>,IOB,IO_L2P_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P34,DATA_INOUT<2>,IOB,IO_L1N_VREF_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P35,DATA_INOUT<3>,IOB,IO_L1P_3,BIDIR,LVCMOS33,3,12,SLOW,,NONE,,LOCATED,NO,NONE, +P36,,,VCCAUX,,,,,,,,2.5,,,, +P37,,,PROGRAM_B_2,,,,,,,,,,,, +P38,DATA_INOUT<4>,IOB,IO_L65N_CSO_B_2,BIDIR,LVCMOS33,2,12,SLOW,,NONE,,LOCATED,NO,NONE, +P39,DATA_INOUT<5>,IOB,IO_L65P_INIT_B_2,BIDIR,LVCMOS33,2,12,SLOW,,NONE,,LOCATED,NO,NONE, +P40,DATA_INOUT<6>,IOB,IO_L64N_D9_2,BIDIR,LVCMOS33,2,12,SLOW,,NONE,,LOCATED,NO,NONE, +P41,DATA_INOUT<7>,IOB,IO_L64P_D8_2,BIDIR,LVCMOS33,2,12,SLOW,,NONE,,LOCATED,NO,NONE, +P42,,,VCCO_2,,,2,,,,,3.30,,,, +P43,we_bar,IOB,IO_L62N_D6_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P44,addr<16>,IOB,IO_L62P_D5_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P45,addr<15>,IOB,IO_L49N_D4_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P46,addr<14>,IOB,IO_L49P_D3_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P47,addr<13>,IOB,IO_L48N_RDWR_B_VREF_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P48,addr<12>,IOB,IO_L48P_D7_2,OUTPUT,LVCMOS33,2,12,SLOW,,,,LOCATED,NO,NONE, +P49,,,GND,,,,,,,,,,,, +P50,,IOBS,IO_L31N_GCLK30_D15_2,UNUSED,,2,,,,,,,,, +P51,clk_main,IOB,IO_L31P_GCLK31_D14_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P52,,,VCCINT,,,,,,,,1.2,,,, +P53,,,VCCAUX,,,,,,,,2.5,,,, +P54,,,GND,,,,,,,,,,,, +P55,,IOBS,IO_L30N_GCLK0_USERCCLK_2,UNUSED,,2,,,,,,,,, +P56,,IOBM,IO_L30P_GCLK1_D13_2,UNUSED,,2,,,,,,,,, +P57,clk_acq_ch5,IOB,IO_L14N_D12_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P58,chn_bits_acq_ch5<0>,IOB,IO_L14P_D11_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P59,chn_bits_acq_ch5<1>,IOB,IO_L13N_D10_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P60,,IOBM,IO_L13P_M1_2,UNUSED,,2,,,,,,,,, +P61,chn_bits_acq_ch5<2>,IOB,IO_L12N_D2_MISO3_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P62,chn_bits_acq_ch5<3>,IOB,IO_L12P_D1_MISO2_2,INPUT,LVCMOS33,2,,,,NONE,,LOCATED,NO,NONE, +P63,,,VCCO_2,,,2,,,,,3.30,,,, +P64,,IOBS,IO_L3N_MOSI_CSI_B_MISO0_2,UNUSED,,2,,,,,,,,, +P65,,IOBM,IO_L3P_D0_DIN_MISO_MISO1_2,UNUSED,,2,,,,,,,,, +P66,,IOBS,IO_L2N_CMPMOSI_2,UNUSED,,2,,,,,,,,, +P67,,IOBM,IO_L2P_CMPCLK_2,UNUSED,,2,,,,,,,,, +P68,,,GND,,,,,,,,,,,, +P69,,IOBS,IO_L1N_M0_CMPMISO_2,UNUSED,,2,,,,,,,,, +P70,,IOBM,IO_L1P_CCLK_2,UNUSED,,2,,,,,,,,, +P71,,,DONE_2,,,,,,,,,,,, +P72,,,CMPCS_B_2,,,,,,,,,,,, +P73,,,SUSPEND,,,,,,,,,,,, +P74,,IOBS,IO_L74N_DOUT_BUSY_1,UNUSED,,1,,,,,,,,, +P75,,IOBM,IO_L74P_AWAKE_1,UNUSED,,1,,,,,,,,, +P76,,,VCCO_1,,,1,,,,,3.30,,,, +P77,,,GND,,,,,,,,,,,, +P78,pps,IOB,IO_L47N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE, +P79,,IOBM,IO_L47P_1,UNUSED,,1,,,,,,,,, +P80,clk_to_acq,IOB,IO_L46N_1,OUTPUT,LVCMOS33,1,12,SLOW,,,,LOCATED,YES,NONE, +P81,,IOBM,IO_L46P_1,UNUSED,,1,,,,,,,,, +P82,lock,IOB,IO_L45N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE, +P83,sda_rpi,IOB,IO_L45P_1,BIDIR,I2C,1,,,,NONE,,LOCATED,NO,NONE, +P84,,IOBS,IO_L43N_GCLK4_1,UNUSED,,1,,,,,,,,, +P85,scl_rpi,IOB,IO_L43P_GCLK5_1,BIDIR,I2C,1,,,,NONE,,LOCATED,NO,NONE, +P86,,,VCCO_1,,,1,,,,,3.30,,,, +P87,,IOBS,IO_L42N_GCLK6_TRDY1_1,UNUSED,,1,,,,,,,,, +P88,,IOBM,IO_L42P_GCLK7_1,UNUSED,,1,,,,,,,,, +P89,,,VCCINT,,,,,,,,1.2,,,, +P90,,,VCCAUX,,,,,,,,2.5,,,, +P91,,,GND,,,,,,,,,,,, +P92,,IOBS,IO_L41N_GCLK8_1,UNUSED,,1,,,,,,,,, +P93,,IOBM,IO_L41P_GCLK9_IRDY1_1,UNUSED,,1,,,,,,,,, +P94,,IOBS,IO_L40N_GCLK10_1,UNUSED,,1,,,,,,,,, +P95,SCK,IOB,IO_L40P_GCLK11_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE, +P96,,,GND,,,,,,,,,,,, +P97,CS,IOB,IO_L34N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE, +P98,MISO,IOB,IO_L34P_1,OUTPUT,LVCMOS33,1,12,SLOW,,,,LOCATED,NO,NONE, +P99,MOSI,IOB,IO_L33N_1,INPUT,LVCMOS33,1,,,,NONE,,LOCATED,NO,NONE, +P100,,IOBM,IO_L33P_1,UNUSED,,1,,,,,,,,, +P101,,IOBS,IO_L32N_1,UNUSED,,1,,,,,,,,, +P102,,IOBM,IO_L32P_1,UNUSED,,1,,,,,,,,, +P103,,,VCCO_1,,,1,,,,,3.30,,,, +P104,,IOBS,IO_L1N_VREF_1,UNUSED,,1,,,,,,,,, +P105,,IOBM,IO_L1P_1,UNUSED,,1,,,,,,,,, +P106,,,TDO,,,,,,,,,,,, +P107,,,TMS,,,,,,,,,,,, +P108,,,GND,,,,,,,,,,,, +P109,,,TCK,,,,,,,,,,,, +P110,,,TDI,,,,,,,,,,,, +P111,clk_acq_ch1,IOB,IO_L66N_SCP0_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P112,chn_bits_acq_ch1<0>,IOB,IO_L66P_SCP1_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P113,,,GND,,,,,,,,,,,, +P114,chn_bits_acq_ch1<1>,IOB,IO_L65N_SCP2_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P115,chn_bits_acq_ch1<2>,IOB,IO_L65P_SCP3_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P116,chn_bits_acq_ch1<3>,IOB,IO_L64N_SCP4_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P117,clk_acq_ch2,IOB,IO_L64P_SCP5_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P118,chn_bits_acq_ch2<0>,IOB,IO_L63N_SCP6_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P119,chn_bits_acq_ch2<1>,IOB,IO_L63P_SCP7_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P120,chn_bits_acq_ch2<2>,IOB,IO_L62N_VREF_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P121,chn_bits_acq_ch2<3>,IOB,IO_L62P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P122,,,VCCO_0,,,0,,,,,3.30,,,, +P123,clk_acq_ch3,IOB,IO_L37N_GCLK12_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P124,chn_bits_acq_ch3<0>,IOB,IO_L37P_GCLK13_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P125,,,VCCO_0,,,0,,,,,3.30,,,, +P126,chn_bits_acq_ch3<1>,IOB,IO_L36N_GCLK14_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P127,chn_bits_acq_ch3<2>,IOB,IO_L36P_GCLK15_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P128,,,VCCINT,,,,,,,,1.2,,,, +P129,,,VCCAUX,,,,,,,,2.5,,,, +P130,,,GND,,,,,,,,,,,, +P131,chn_bits_acq_ch3<3>,IOB,IO_L35N_GCLK16_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P132,clk_acq_ch4,IOB,IO_L35P_GCLK17_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P133,chn_bits_acq_ch4<0>,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P134,chn_bits_acq_ch4<1>,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P135,,,VCCO_0,,,0,,,,,3.30,,,, +P136,,,GND,,,,,,,,,,,, +P137,chn_bits_acq_ch4<2>,IOB,IO_L4N_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P138,chn_bits_acq_ch4<3>,IOB,IO_L4P_0,INPUT,LVCMOS33,0,,,,NONE,,LOCATED,NO,NONE, +P139,addr<4>,IOB,IO_L3N_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, +P140,addr<3>,IOB,IO_L3P_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, +P141,addr<2>,IOB,IO_L2N_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, +P142,addr<1>,IOB,IO_L2P_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, +P143,addr<0>,IOB,IO_L1N_VREF_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, +P144,addr<5>,IOB,IO_L1P_HSWAPEN_0,OUTPUT,LVCMOS33,0,12,SLOW,,,,LOCATED,NO,NONE, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.txt =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.txt b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.txt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_pad.txt (revision 224) @@ -0,0 +1,174 @@ +Release 14.7 - par P.20131013 (nt64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Mon May 23 12:38:47 2016 + + +INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: +1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: chn5_mem_spi_joint_map.ncd +OUTPUT FILE: chn5_mem_spi_joint_pad.txt +PART TYPE: xc6slx9 +SPEED GRADE: -3 +PACKAGE: tqg144 + +Pinout by Pin Number: + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|P1 |addr<6> |IOB |IO_L83N_VREF_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P2 |addr<7> |IOB |IO_L83P_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P3 | | |GND | | | | | | | | | | | | +|P4 | | |VCCO_3 | | |3 | | | | |3.30 | | | | +|P5 |oe_ram_bar |IOB |IO_L52N_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P6 |ub_bar |IOB |IO_L52P_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P7 |lb_bar |IOB |IO_L51N_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P8 |DATA_INOUT<15> |IOB |IO_L51P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P9 |DATA_INOUT<14> |IOB |IO_L50N_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P10 |DATA_INOUT<13> |IOB |IO_L50P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P11 |DATA_INOUT<12> |IOB |IO_L49N_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P12 |DATA_INOUT<11> |IOB |IO_L49P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P13 | | |GND | | | | | | | | | | | | +|P14 |DATA_INOUT<10> |IOB |IO_L44N_GCLK20_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P15 |DATA_INOUT<9> |IOB |IO_L44P_GCLK21_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P16 |DATA_INOUT<8> |IOB |IO_L43N_GCLK22_IRDY2_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P17 |addr<18> |IOB |IO_L43P_GCLK23_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P18 | | |VCCO_3 | | |3 | | | | |3.30 | | | | +|P19 | | |VCCINT | | | | | | | |1.2 | | | | +|P20 | | |VCCAUX | | | | | | | |2.5 | | | | +|P21 |addr<8> |IOB |IO_L42N_GCLK24_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P22 |addr<9> |IOB |IO_L42P_GCLK25_TRDY2_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P23 |addr<10> |IOB |IO_L41N_GCLK26_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P24 |addr<11> |IOB |IO_L41P_GCLK27_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P25 | | |GND | | | | | | | | | | | | +|P26 |addr<17> |IOB |IO_L37N_3 |OUTPUT |LVCMOS33 |3 |12 |SLOW | | | |LOCATED |NO |NONE | +|P27 | |IOBM |IO_L37P_3 |UNUSED | |3 | | | | | | | | | +|P28 | | |VCCINT | | | | | | | |1.2 | | | | +|P29 | |IOBS |IO_L36N_3 |UNUSED | |3 | | | | | | | | | +|P30 | |IOBM |IO_L36P_3 |UNUSED | |3 | | | | | | | | | +|P31 | | |VCCO_3 | | |3 | | | | |3.30 | | | | +|P32 |DATA_INOUT<0> |IOB |IO_L2N_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P33 |DATA_INOUT<1> |IOB |IO_L2P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P34 |DATA_INOUT<2> |IOB |IO_L1N_VREF_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P35 |DATA_INOUT<3> |IOB |IO_L1P_3 |BIDIR |LVCMOS33 |3 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P36 | | |VCCAUX | | | | | | | |2.5 | | | | +|P37 | | |PROGRAM_B_2 | | | | | | | | | | | | +|P38 |DATA_INOUT<4> |IOB |IO_L65N_CSO_B_2 |BIDIR |LVCMOS33 |2 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P39 |DATA_INOUT<5> |IOB |IO_L65P_INIT_B_2 |BIDIR |LVCMOS33 |2 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P40 |DATA_INOUT<6> |IOB |IO_L64N_D9_2 |BIDIR |LVCMOS33 |2 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P41 |DATA_INOUT<7> |IOB |IO_L64P_D8_2 |BIDIR |LVCMOS33 |2 |12 |SLOW | |NONE | |LOCATED |NO |NONE | +|P42 | | |VCCO_2 | | |2 | | | | |3.30 | | | | +|P43 |we_bar |IOB |IO_L62N_D6_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P44 |addr<16> |IOB |IO_L62P_D5_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P45 |addr<15> |IOB |IO_L49N_D4_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P46 |addr<14> |IOB |IO_L49P_D3_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P47 |addr<13> |IOB |IO_L48N_RDWR_B_VREF_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P48 |addr<12> |IOB |IO_L48P_D7_2 |OUTPUT |LVCMOS33 |2 |12 |SLOW | | | |LOCATED |NO |NONE | +|P49 | | |GND | | | | | | | | | | | | +|P50 | |IOBS |IO_L31N_GCLK30_D15_2 |UNUSED | |2 | | | | | | | | | +|P51 |clk_main |IOB |IO_L31P_GCLK31_D14_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P52 | | |VCCINT | | | | | | | |1.2 | | | | +|P53 | | |VCCAUX | | | | | | | |2.5 | | | | +|P54 | | |GND | | | | | | | | | | | | +|P55 | |IOBS |IO_L30N_GCLK0_USERCCLK_2 |UNUSED | |2 | | | | | | | | | +|P56 | |IOBM |IO_L30P_GCLK1_D13_2 |UNUSED | |2 | | | | | | | | | +|P57 |clk_acq_ch5 |IOB |IO_L14N_D12_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P58 |chn_bits_acq_ch5<0>|IOB |IO_L14P_D11_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P59 |chn_bits_acq_ch5<1>|IOB |IO_L13N_D10_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P60 | |IOBM |IO_L13P_M1_2 |UNUSED | |2 | | | | | | | | | +|P61 |chn_bits_acq_ch5<2>|IOB |IO_L12N_D2_MISO3_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P62 |chn_bits_acq_ch5<3>|IOB |IO_L12P_D1_MISO2_2 |INPUT |LVCMOS33 |2 | | | |NONE | |LOCATED |NO |NONE | +|P63 | | |VCCO_2 | | |2 | | | | |3.30 | | | | +|P64 | |IOBS |IO_L3N_MOSI_CSI_B_MISO0_2 |UNUSED | |2 | | | | | | | | | +|P65 | |IOBM |IO_L3P_D0_DIN_MISO_MISO1_2|UNUSED | |2 | | | | | | | | | +|P66 | |IOBS |IO_L2N_CMPMOSI_2 |UNUSED | |2 | | | | | | | | | +|P67 | |IOBM |IO_L2P_CMPCLK_2 |UNUSED | |2 | | | | | | | | | +|P68 | | |GND | | | | | | | | | | | | +|P69 | |IOBS |IO_L1N_M0_CMPMISO_2 |UNUSED | |2 | | | | | | | | | +|P70 | |IOBM |IO_L1P_CCLK_2 |UNUSED | |2 | | | | | | | | | +|P71 | | |DONE_2 | | | | | | | | | | | | +|P72 | | |CMPCS_B_2 | | | | | | | | | | | | +|P73 | | |SUSPEND | | | | | | | | | | | | +|P74 | |IOBS |IO_L74N_DOUT_BUSY_1 |UNUSED | |1 | | | | | | | | | +|P75 | |IOBM |IO_L74P_AWAKE_1 |UNUSED | |1 | | | | | | | | | +|P76 | | |VCCO_1 | | |1 | | | | |3.30 | | | | +|P77 | | |GND | | | | | | | | | | | | +|P78 |pps |IOB |IO_L47N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE | +|P79 | |IOBM |IO_L47P_1 |UNUSED | |1 | | | | | | | | | +|P80 |clk_to_acq |IOB |IO_L46N_1 |OUTPUT |LVCMOS33 |1 |12 |SLOW | | | |LOCATED |YES |NONE | +|P81 | |IOBM |IO_L46P_1 |UNUSED | |1 | | | | | | | | | +|P82 |lock |IOB |IO_L45N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE | +|P83 |sda_rpi |IOB |IO_L45P_1 |BIDIR |I2C |1 | | | |NONE | |LOCATED |NO |NONE | +|P84 | |IOBS |IO_L43N_GCLK4_1 |UNUSED | |1 | | | | | | | | | +|P85 |scl_rpi |IOB |IO_L43P_GCLK5_1 |BIDIR |I2C |1 | | | |NONE | |LOCATED |NO |NONE | +|P86 | | |VCCO_1 | | |1 | | | | |3.30 | | | | +|P87 | |IOBS |IO_L42N_GCLK6_TRDY1_1 |UNUSED | |1 | | | | | | | | | +|P88 | |IOBM |IO_L42P_GCLK7_1 |UNUSED | |1 | | | | | | | | | +|P89 | | |VCCINT | | | | | | | |1.2 | | | | +|P90 | | |VCCAUX | | | | | | | |2.5 | | | | +|P91 | | |GND | | | | | | | | | | | | +|P92 | |IOBS |IO_L41N_GCLK8_1 |UNUSED | |1 | | | | | | | | | +|P93 | |IOBM |IO_L41P_GCLK9_IRDY1_1 |UNUSED | |1 | | | | | | | | | +|P94 | |IOBS |IO_L40N_GCLK10_1 |UNUSED | |1 | | | | | | | | | +|P95 |SCK |IOB |IO_L40P_GCLK11_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE | +|P96 | | |GND | | | | | | | | | | | | +|P97 |CS |IOB |IO_L34N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE | +|P98 |MISO |IOB |IO_L34P_1 |OUTPUT |LVCMOS33 |1 |12 |SLOW | | | |LOCATED |NO |NONE | +|P99 |MOSI |IOB |IO_L33N_1 |INPUT |LVCMOS33 |1 | | | |NONE | |LOCATED |NO |NONE | +|P100 | |IOBM |IO_L33P_1 |UNUSED | |1 | | | | | | | | | +|P101 | |IOBS |IO_L32N_1 |UNUSED | |1 | | | | | | | | | +|P102 | |IOBM |IO_L32P_1 |UNUSED | |1 | | | | | | | | | +|P103 | | |VCCO_1 | | |1 | | | | |3.30 | | | | +|P104 | |IOBS |IO_L1N_VREF_1 |UNUSED | |1 | | | | | | | | | +|P105 | |IOBM |IO_L1P_1 |UNUSED | |1 | | | | | | | | | +|P106 | | |TDO | | | | | | | | | | | | +|P107 | | |TMS | | | | | | | | | | | | +|P108 | | |GND | | | | | | | | | | | | +|P109 | | |TCK | | | | | | | | | | | | +|P110 | | |TDI | | | | | | | | | | | | +|P111 |clk_acq_ch1 |IOB |IO_L66N_SCP0_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P112 |chn_bits_acq_ch1<0>|IOB |IO_L66P_SCP1_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P113 | | |GND | | | | | | | | | | | | +|P114 |chn_bits_acq_ch1<1>|IOB |IO_L65N_SCP2_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P115 |chn_bits_acq_ch1<2>|IOB |IO_L65P_SCP3_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P116 |chn_bits_acq_ch1<3>|IOB |IO_L64N_SCP4_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P117 |clk_acq_ch2 |IOB |IO_L64P_SCP5_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P118 |chn_bits_acq_ch2<0>|IOB |IO_L63N_SCP6_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P119 |chn_bits_acq_ch2<1>|IOB |IO_L63P_SCP7_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P120 |chn_bits_acq_ch2<2>|IOB |IO_L62N_VREF_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P121 |chn_bits_acq_ch2<3>|IOB |IO_L62P_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P122 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|P123 |clk_acq_ch3 |IOB |IO_L37N_GCLK12_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P124 |chn_bits_acq_ch3<0>|IOB |IO_L37P_GCLK13_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P125 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|P126 |chn_bits_acq_ch3<1>|IOB |IO_L36N_GCLK14_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P127 |chn_bits_acq_ch3<2>|IOB |IO_L36P_GCLK15_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P128 | | |VCCINT | | | | | | | |1.2 | | | | +|P129 | | |VCCAUX | | | | | | | |2.5 | | | | +|P130 | | |GND | | | | | | | | | | | | +|P131 |chn_bits_acq_ch3<3>|IOB |IO_L35N_GCLK16_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P132 |clk_acq_ch4 |IOB |IO_L35P_GCLK17_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P133 |chn_bits_acq_ch4<0>|IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P134 |chn_bits_acq_ch4<1>|IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P135 | | |VCCO_0 | | |0 | | | | |3.30 | | | | +|P136 | | |GND | | | | | | | | | | | | +|P137 |chn_bits_acq_ch4<2>|IOB |IO_L4N_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P138 |chn_bits_acq_ch4<3>|IOB |IO_L4P_0 |INPUT |LVCMOS33 |0 | | | |NONE | |LOCATED |NO |NONE | +|P139 |addr<4> |IOB |IO_L3N_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|P140 |addr<3> |IOB |IO_L3P_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|P141 |addr<2> |IOB |IO_L2N_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|P142 |addr<1> |IOB |IO_L2P_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|P143 |addr<0> |IOB |IO_L1N_VREF_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | +|P144 |addr<5> |IOB |IO_L1P_HSWAPEN_0 |OUTPUT |LVCMOS33 |0 |12 |SLOW | | | |LOCATED |NO |NONE | ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_par.xrpt =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_par.xrpt b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_par.xrpt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_par.xrpt (revision 224) @@ -0,0 +1,1677 @@ + + + + + + +
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+ + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.html =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.html b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.html new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.html (revision 224) @@ -0,0 +1,501 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
chn5_mem_spi_joint Project Status (05/20/2016 - 11:13:02)
Project File:chn5_mem_spi_joint.xiseParser Errors: No Errors
Module Name:chn5_mem_spi_jointImplementation State:Programming File Generated
Target Device:xc6slx9-3tqg144
  • Errors:
 +No Errors
Product Version:ISE 14.7
  • Warnings:
No Warnings
Design Goal:Balanced
  • Routing Results:
 +All Signals Completely Routed
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 +All Constraints Met
Environment: + +System Settings +
  • Final Timing Score:
0  (Timing Report)
+ + + + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers56411,4404% 
    Number used as Flip Flops564   
    Number used as Latches0   
    Number used as Latch-thrus0   
    Number used as AND/OR logics0   
Number of Slice LUTs7395,72012% 
    Number used as logic7315,72012% 
        Number using O6 output only536   
        Number using O5 output only34   
        Number using O5 and O6161   
        Number used as ROM0   
    Number used as Memory11,4401% 
        Number used as Dual Port RAM0   
        Number used as Single Port RAM0   
        Number used as Shift Register1   
            Number using O6 output only1   
            Number using O5 output only0   
            Number using O5 and O60   
    Number used exclusively as route-thrus7   
        Number with same-slice register load4   
        Number with same-slice carry load3   
        Number with other load0   
Number of occupied Slices3371,43023% 
Number of MUXCYs used642,8602% 
Number of LUT Flip Flop pairs used850   
    Number with an unused Flip Flop37585044% 
    Number with an unused LUT11185013% 
    Number of fully used LUT-FF pairs36485042% 
    Number of unique control sets28   
    Number of slice register sites lost
        to control set restrictions		5911,4401% 
Number of bonded IOBs7410272% 
    Number of LOCed IOBs7474100% 
    IOB Flip Flops1   
Number of RAMB16BWERs0320% 
Number of RAMB8BWERs0640% 
Number of BUFIO2/BUFIO2_2CLKs2326% 
    Number used as BUFIO2s2   
    Number used as BUFIO2_2CLKs0   
Number of BUFIO2FB/BUFIO2FB_2CLKs2326% 
    Number used as BUFIO2FBs2   
    Number used as BUFIO2FB_2CLKs0   
Number of BUFG/BUFGMUXs41625% 
    Number used as BUFGs4   
    Number used as BUFGMUX0   
Number of DCM/DCM_CLKGENs2450% 
    Number used as DCMs2   
    Number used as DCM_CLKGENs0   
Number of ILOGIC2/ISERDES2s02000% 
Number of IODELAY2/IODRP2/IODRP2_MCBs02000% 
Number of OLOGIC2/OSERDES2s12001% 
    Number used as OLOGIC2s1   
    Number used as OSERDES2s0   
Number of BSCANs040% 
Number of BUFHs01280% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s0160% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs020% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.79   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0, Component Switching Limit: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
+ + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentlun 23. mayo 12:37:47 2016004 Infos (0 new)
Translation ReportCurrentlun 23. mayo 12:37:54 2016002 Infos (0 new)
Map ReportCurrentlun 23. mayo 12:38:17 2016008 Infos (0 new)
Place and Route ReportCurrentlun 23. mayo 12:38:47 2016000
Power Report     
Post-PAR Static Timing ReportCurrentlun 23. mayo 12:38:55 2016003 Infos (0 new)
Bitgen ReportCurrentlun 23. mayo 12:39:05 2016002 Infos (0 new)
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentlun 23. mayo 12:39:06 2016
WebTalk Log FileCurrentlun 23. mayo 12:39:15 2016
+ + +
Date Generated: 05/24/2016 - 08:10:18
+ \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.xml =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.xml b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.xml new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_summary.xml (revision 224) @@ -0,0 +1,10 @@ + + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_usage.xml =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_usage.xml b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_usage.xml new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_usage.xml (revision 224) @@ -0,0 +1,836 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_xst.xrpt =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_xst.xrpt b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_xst.xrpt new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/chn5_mem_spi_joint_xst.xrpt (revision 224) @@ -0,0 +1,241 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + + + + + + + + + + + + + + + +
+
+ + + + + + +
+
+
+
+
+
+
+
+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + +
+
+
+
+
+ + + +
+ + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/data_header_ram.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/data_header_ram.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/data_header_ram.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/data_header_ram.vhd (revision 224) @@ -0,0 +1,59 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:19:27 05/17/2016 +-- Design Name: +-- Module Name: data_header_ram - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity data_header_ram is +GENERIC( + DATA_MUX_SZ: INTEGER := 16 +); +PORT( + --Senhales desde las dos fuentes de datos + data_header_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0); + data_ram_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0); + + --Senhal de seleccion + sel_header_ram: IN std_logic; + + --Senhal hacia el spi controller + data_tospi: OUT std_logic_vector((DATA_MUX_SZ-1) downto 0) +); +end data_header_ram; + +architecture Behavioral of data_header_ram is + +begin + +WITH sel_header_ram SELECT +data_tospi <= data_header_in WHEN '0', + --data_ram_in WHEN '0', + data_ram_in WHEN '1', + (OTHERS => '0') WHEN OTHERS; +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuse.xmsgs =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuse.xmsgs b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuse.xmsgs new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuse.xmsgs (revision 224) @@ -0,0 +1,9 @@ + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuseRelaunch.cmd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuseRelaunch.cmd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuseRelaunch.cmd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/fuseRelaunch.cmd (revision 224) @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "secureip" -o "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/testbench_isim_translate.exe" -prj "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/testbench_translate.prj" "work.testbench" Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_memory.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_memory.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_memory.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_memory.vhd (revision 224) @@ -0,0 +1,153 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:52:36 05/17/2016 +-- Design Name: +-- Module Name: header_memory - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity header_memory is +GENERIC( + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16 +); +PORT( + + --Senhal reloj principal + clk_main: IN std_logic; + + --Dato de salida con datos de cabecera + data_header: OUT std_logic_vector((DATA_HEADER_SZ-1) downto 0); + + --Reset de puntero + rst_ptr: IN std_logic; + + --Senhales de carga y acknowledge de carga + req_header: IN std_logic; + ld_header: OUT std_logic +); +end header_memory; + +architecture Behavioral of header_memory is + +TYPE header_states IS (idle, + pres, + proc, + aum + ); +SIGNAL header_cur_state: header_states := idle; +SIGNAL header_next_state: header_states := idle; + +SIGNAL ptr_mem: std_logic_vector((COUNT_HEADER_SZ-1) downto 0) := (OTHERS => '0'); + +TYPE t_header_mem IS ARRAY (0 TO (HEADER_SZ-1)) OF std_logic_vector ((DATA_HEADER_SZ-1) downto 0); + +CONSTANT a_header_mem: t_header_mem :=( + "0010010001010010", --$R + "0100111101001010", --JO + "0101100101011001", --YY + "0100110101001101", --MM + "0100010001000100", --DD + "0110100001101000", --hh + "0110110101101101", --mm + "0111001101110011" --ss + + --"0000000100000010", + --"0000001100000100", + --"0000010100000110", + --"0000011100001000", + --"0000100100001010", + --"0000101100001100", + --"0000110100001110", + --"0000111100010000" + ); +begin + +--------------------------------------------------- + +data_header <= a_header_mem(to_integer(unsigned(ptr_mem))); + +ptr_mem_process: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_ptr = '1') THEN + ptr_mem <= (OTHERS => '0'); + ELSE + IF (header_cur_state = aum) THEN + ptr_mem <= std_logic_vector(unsigned(ptr_mem)+1); + END IF; + END IF; + END IF; + END PROCESS; + +cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_ptr = '1') THEN + header_cur_state <= idle; + ELSE + header_cur_state <= header_next_state; + END IF; + END IF; + END PROCESS; + +salidas_estados: PROCESS(header_cur_state, req_header) + BEGIN + CASE header_cur_state IS + WHEN idle => + ld_header <= '0'; + header_next_state <= pres; + + WHEN pres => + ld_header <= '0'; + IF (req_header = '1') THEN + header_next_state <= proc; + ELSE + header_next_state <= pres; + END IF; + + WHEN proc => + ld_header <= '1'; + IF (req_header = '0') THEN + header_next_state <= aum; + ELSE + header_next_state <= proc; + END IF; + + WHEN aum => + ld_header <= '0'; + header_next_state <= idle; + + WHEN OTHERS => + ld_header <= '1'; + header_next_state <= idle; + + END CASE; + END PROCESS; + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_spi_interface.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_spi_interface.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_spi_interface.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/header_spi_interface.vhd (revision 224) @@ -0,0 +1,359 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 16:10:43 05/17/2016 +-- Design Name: +-- Module Name: header_spi_interface - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity header_spi_interface is +GENERIC( + + --Tamanho de palabra de datos desde RAM + DATA_MUX_SZ: INTEGER := 16; + + --Constantes de bloque de memoria con datos de cabecera + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16; + + --Constantes del bloque de controlador SPI + WORD_IN_SZ: INTEGER := 16; + WORD_INT_SZ: INTEGER := 16; + WORD_OUT_SZ: INTEGER := 8; + WORD_SPIIN_SZ: INTEGER := 8; + + POS_WORD1: INTEGER := 16; + POS_WORD2: INTEGER := 8; + + --Constantes del bloque spi esclavo + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 + +); +PORT( + + --Senhal de reset general + rst_bar: IN std_logic; + + --Senhal de reloj principal + clk_main: IN std_logic; + + --Senhales interfaz SPI esclavo + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + MISO : OUT std_logic; + + --Senhales del bloque de memoria con el controlador SPI + --Senhal request hacia bloque controlador RAM + req_ram: OUT std_logic; + + --Senhal desde bloque controlador RAM + ld_ram: IN std_logic; + + --Dato desde la RAM + data_ram_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0) + +); +end header_spi_interface; + +architecture Behavioral of header_spi_interface is + +COMPONENT SPI_SLAVE is +GENERIC( + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 +); + +PORT ( + + --Senhal de reset general + rst_bar : IN std_logic; + + --Senhal de reloj principal + clk_main : IN std_logic; + + --Senhales interfaz SPI esclavo + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + MISO : OUT std_logic; + + --Palabras de datos desde hacia SPI esclavo + --Dato hacia el SPI esclavo + data_in : IN std_logic_vector (SPI_DATA_WIDTH-1 downto 0); + --Dato desde el SPI esclavo + data_out : OUT std_logic_vector (SPI_DATA_WIDTH-1 downto 0); + + + --Senhales con el SPI interface + --Senhal indicadora de carga + spi_ready : OUT std_logic; + --Senhal de estado de interfaz + spi_free: OUT std_logic + + +); +end COMPONENT; + +COMPONENT spi_controller is +GENERIC( + + WORD_IN_SZ: INTEGER :=16; + WORD_INT_SZ: INTEGER :=16; + WORD_OUT_SZ: INTEGER :=8; + WORD_SPIIN_SZ: INTEGER :=8; + + POS_WORD1: INTEGER :=16; + POS_WORD2: INTEGER :=8 + +); +PORT( + --Senhal de reset general + rst_bar: IN std_logic; + + --Senhal de reloj principal + clk_main: IN std_logic; + + --Senhal request hacia memoria de cabecera + req_header: OUT std_logic; + + --Senhal request hacia memoria de cabecera + ld_header: IN std_logic; + + --Senhal request hacia bloque controlador RAM + req_ram: OUT std_logic; + + --Senhal desde bloque controlador RAM + ld_ram: IN std_logic; + + --Senhal hacia RAM interna de cabecera y futura fecha-hora + rst_headerdate: OUT std_logic; + + --Senhal de seleccion + sel_headerdate_ram: OUT std_logic; + + --Senhal con splitter de 24(32) a 16 + word_in: IN STD_LOGIC_VECTOR((WORD_IN_SZ-1)downto 0); + + --Senhales con SPI Slave + word_out: OUT STD_LOGIC_VECTOR((WORD_OUT_SZ-1) downto 0); + fromspi_in: IN STD_LOGIC_VECTOR((WORD_SPIIN_SZ-1) downto 0); + rdy_8_in: IN STD_LOGIC; + spi_free: IN STD_LOGIC + +); +end COMPONENT; + +COMPONENT header_memory is +GENERIC( + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16 +); + +PORT( + + --Senhal reloj principal + clk_main: IN std_logic; + + --Dato de salida con datos de cabecera + data_header: OUT std_logic_vector((DATA_HEADER_SZ-1) downto 0); + + --Reset de puntero + rst_ptr: IN std_logic; + + --Senhales de carga y acknowledge de carga + req_header: IN std_logic; + ld_header: OUT std_logic +); +end COMPONENT; + +COMPONENT data_header_ram is +GENERIC( + DATA_MUX_SZ: INTEGER := 16 +); +PORT( + --Senhales desde las dos fuentes de datos + data_header_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0); + data_ram_in: IN std_logic_vector((DATA_MUX_SZ-1) downto 0); + + --Senhal de seleccion + sel_header_ram: IN std_logic; + + --Senhal hacia el spi controller + data_tospi: OUT std_logic_vector((DATA_MUX_SZ-1) downto 0) +); +end COMPONENT; + +--Senhales enlace entre SPI eslcavo y SPI controller +--Senhales de datos +SIGNAL from_spi: std_logic_vector (SPI_DATA_WIDTH-1 downto 0) := (OTHERS => '0'); +SIGNAL to_spi: std_logic_vector (SPI_DATA_WIDTH-1 downto 0) := (OTHERS => '0'); + +--Senhales de control SPI esclavo y SPI controlador +SIGNAL spi_ready: std_logic := '0'; +SIGNAL spi_free: std_logic := '0'; + +--Senhales de control con la memoria cabecera +SIGNAL req_header: std_logic := '0'; +SIGNAL ld_header: std_logic := '0'; + +--Senhal de seleccion del dato proveniente del multiplexor +SIGNAL sel_headerdate_ram: std_logic := '0'; + +--Senhal de reset de la direccion de la memoria de cabecera +SIGNAL rst_headerdate: std_logic := '0'; + +--Dato proveniente sobre multiplexor +SIGNAL data_mux: std_logic_vector((DATA_MUX_SZ-1) downto 0) := (OTHERS => '0'); +SIGNAL data_mux_header: std_logic_vector((DATA_MUX_SZ-1) downto 0) := (OTHERS => '0'); + + +begin + +controlador_spi_esclavo: SPI_SLAVE +GENERIC MAP( + SPI_DATA_WIDTH => SPI_DATA_WIDTH, + SPI_BIT_COUNT_WIDTH => SPI_BIT_COUNT_WIDTH +) +PORT MAP( + --Senhal de reset general + rst_bar => rst_bar, + + --Senhal de reloj principal + clk_main => clk_main, + + --Senhales interfaz SPI esclavo + MOSI => MOSI, + SCK => SCK, + CS => CS, + MISO => MISO, + + --Palabras de datos desde hacia SPI esclavo + --Dato hacia el SPI esclavo + data_in => to_spi, + --Dato desde el SPI esclavo + data_out => from_spi, + + --Senhales con el SPI interface + --Senhal indicadora de carga + spi_ready => spi_ready, + --Senhal de estado de interfaz + spi_free => spi_free + +); + +controlador_spi_principal : spi_controller +GENERIC MAP( + + WORD_IN_SZ => WORD_IN_SZ, + WORD_INT_SZ => WORD_INT_SZ, + WORD_OUT_SZ => WORD_OUT_SZ, + WORD_SPIIN_SZ => WORD_SPIIN_SZ, + + POS_WORD1 => POS_WORD1, + POS_WORD2 => POS_WORD2 + +) +PORT MAP( + --Senhal de reset general + rst_bar => rst_bar, + + --Senhal de reloj principal + clk_main => clk_main, + + --Senhal request hacia memoria de cabecera + req_header => req_header, + + --Senhal request hacia memoria de cabecera + ld_header => ld_header, + + --Senhal request hacia bloque controlador RAM + req_ram => req_ram, + + --Senhal desde bloque controlador RAM + ld_ram => ld_ram, + + --Senhal hacia RAM interna de cabecera y futura fecha-hora + rst_headerdate => rst_headerdate, + + --Senhal de seleccion + sel_headerdate_ram => sel_headerdate_ram, + + --Senhal con splitter de 24(32) a 16 + word_in => data_mux, + + --Senhales con SPI Slave + word_out => to_spi, + fromspi_in => from_spi, + + rdy_8_in => spi_ready, + spi_free => spi_free + +); + +cabecera_memoria : header_memory +GENERIC MAP( + COUNT_HEADER_SZ => COUNT_HEADER_SZ, + HEADER_SZ => HEADER_SZ, + DATA_HEADER_SZ => DATA_HEADER_SZ +) +PORT MAP( + + --Senhal reloj principal + clk_main => clk_main, + + --Dato de salida con datos de cabecera + data_header => data_mux_header, + + --Reset de puntero + rst_ptr => rst_headerdate, + + --Senhales de carga y acknowledge de carga + req_header => req_header, + ld_header => ld_header +); + +multiplexor_ram_header: data_header_ram +GENERIC MAP( + DATA_MUX_SZ => DATA_MUX_SZ +) +PORT MAP( + --Senhales desde las dos fuentes de datos + data_header_in => data_mux_header, + data_ram_in => data_ram_in, + + --Senhal de seleccion + sel_header_ram => sel_headerdate_ram, + + --Senhal hacia el spi controller + data_tospi => data_mux +); + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/i2c_inst.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/i2c_inst.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/i2c_inst.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/i2c_inst.vhd (revision 224) @@ -0,0 +1,102 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 00:26:16 02/17/2016 +-- Design Name: +-- Module Name: i2c_inst - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_STD.ALL; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity i2c_inst is +PORT( + clk_main: IN std_logic; + rst_bar: IN std_logic; + SDA: INOUT std_logic; + SCL: INOUT std_logic +); +end i2c_inst; + +architecture Behavioral of i2c_inst is + +SIGNAL SCLi: std_logic :='0'; +SIGNAL SDAi: std_logic :='0'; +SIGNAL SCLoe: std_logic :='0'; +SIGNAL SDAoe: std_logic :='0'; +SIGNAL bit_counter: std_logic_vector(2 downto 0) :=(OTHERS => '0'); +SIGNAL flanco_SCL: std_logic_vector(1 downto 0) := (OTHERS => '0'); +SIGNAL inc_count: std_logic := '0'; +begin + + SCL <= '0' WHEN (SCLOe ='0') else 'Z'; + SDA <= '0' WHEN (SDAOe ='0') else 'Z'; + + SCLi <= SCL; + SDAi <= SDA; + + +incremento_contador : PROCESS(clk_main) +BEGIN + IF(rising_edge(clk_main))THEN + IF(rst_bar = '0') THEN + bit_counter <= "100"; + + ELSE + IF(inc_count = '1') THEN + IF(bit_counter = "100") THEN + bit_counter <= (OTHERS=>'0'); + IF (SDAi = '0') THEN + SDAOe <= '1'; + ELSE + SDAOe <= '0'; + END IF; + SCLOe <= '1'; + + ELSE + bit_counter <= std_logic_vector(unsigned(bit_counter) + 1); + END IF; + + END IF; + END IF; + END IF; +END PROCESS; + +flancos_scl: PROCESS(clk_main) +BEGIN + IF(rising_edge(clk_main))THEN + IF(rst_bar = '0') THEN + flanco_SCL <= (OTHERS => '0'); + + ELSE + flanco_SCL <= flanco_SCL(0) & SCLi; + + IF (flanco_SCL(1 downto 0) = "01") THEN + inc_count <= '1'; + ELSE + inc_count <= '0'; + END IF; + END IF; + END IF; +END PROCESS; +end Behavioral; Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.projectmgr =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.projectmgr b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.projectmgr new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.projectmgr (revision 224) @@ -0,0 +1,216 @@ + + + + + + + + + 2 + + + controlador_spi_esclavo - SPI_SLAVE - Behavioral (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/SPI_SLAVE.vhd) + + 11 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000244000000020000000000000000000000000200000064ffffffff000000810000000300000002000002440000000100000003000000000000000100000003 + true + controlador_spi_esclavo - SPI_SLAVE - Behavioral (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/SPI_SLAVE.vhd) + + + + 1 + Design Utilities + Implement Design/Place & Route/Back-annotate Pin Locations + Implement Design/Place & Route/Generate IBIS Model + Implement Design/Place & Route/Generate Post-Place & Route Static Timing + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff0000000000000001000000000000000001000000000000000000000000000000000000028e000000040101000100000000000000000000000064ffffffff000000810000000000000004000000ba00000001000000000000009d0000000100000000000000660000000100000000000000d10000000100000000 + false + chn5_mem_spi_joint.ucf + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000 + false + work + + + + 2 + /chn5_mem_spi_joint - Behavioral C:|Users|Francisco|Documents|Francisco_ROJ|ProcessingEngine|Projects|chn5_mem_spi_joint|chn5_mem_spi_joint.vhd + /testbench - behavior C:|Users|Francisco|Documents|Francisco_ROJ|ProcessingEngine|Projects|chn5_mem_spi_joint|tb_ch5_mem_spi_joint.vhd + /testbench - behavior C:|Users|Francisco|Documents|Francisco_ROJ|ProcessingEngine|Projects|chn5_mem_spi_joint|tb_chn5_mem_spi_joint.vhd/uut - chn5_mem_spi_joint - Behavioral + + + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000001b1000000020000000000000000000000000200000064ffffffff000000810000000300000002000001b10000000100000003000000000000000100000003 + false + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + + + 1 + Design Utilities + ISim Simulator + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + + + + + 1 + + + Simulate Behavioral Model + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + Simulate Behavioral Model + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + + + 1 + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + + + + + 1 + Design Utilities/Compile HDL Simulation Libraries + + + Design Utilities + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + Design Utilities + + + + 2 + /testbench - behavior C:|Users|Francisco|Documents|Francisco_ROJ|ProcessingEngine|Projects|chn5_mem_spi_joint|tb_chn5_mem_spi_joint.vhd + + + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000014f0000000100000003000000000000000100000003 + false + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + + + + + 1 + + + Simulate Post-Place & Route Model + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + Simulate Post-Place & Route Model + + + + 2 + /testbench - behavior C:|Users|Francisco|Documents|Francisco_ROJ|ProcessingEngine|Projects|chn5_mem_spi_joint|tb_chn5_mem_spi_joint.vhd + + + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000014f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000014f0000000100000003000000000000000100000003 + false + testbench - behavior (C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd) + + + + 1 + Design Utilities/Compile HDL Simulation Libraries + + + Update All Schematic Files + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + Update All Schematic Files + + + + 1 + + + Simulate Post-Translate Model + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000001d8000000010000000100000000000000000000000064ffffffff000000810000000000000001000001d80000000100000000 + false + Simulate Post-Translate Model + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.xreport =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.xreport b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.xreport new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.xreport (revision 224) @@ -0,0 +1,215 @@ + + +
+ 2016-05-24T08:10:18 + chn5_mem_spi_joint + 2016-05-20T11:13:02 + C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/iseconfig/chn5_mem_spi_joint.xreport + C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint\ + 2016-05-18T09:45:49 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/mux_np.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/mux_np.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/mux_np.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/mux_np.vhd (revision 224) @@ -0,0 +1,123 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 10:04:18 05/16/2016 +-- Design Name: +-- Module Name: mux_np - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity mux_np is +GENERIC( + CHAN_NUM: INTEGER :=5; + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16 + ); +PORT( + --Palabras desde "Nibble/packet channels" + DATA_CH1 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH2 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH3 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH4 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH5 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + + --Selector de dato de canal a presentar + oe_ch_vect : IN std_logic_vector((CHAN_NUM-1) downto 0); + + --Selector de palabra de 16 bits en + hb_lbbar: IN std_logic; + + --Dato a escribir en memoria + DATA_OUT : OUT std_logic_vector((WORD_OUT_MUX_SZ-1) downto 0) +); +end mux_np; + +architecture Behavioral of mux_np is + +CONSTANT cabecera_const: STD_LOGIC_VECTOR((HEADER_CONST_SZ-1)downto 0):= "0110"; +CONSTANT cabecera_ch1: STD_LOGIC_VECTOR((HEADER_CH_SZ-1)downto 0):= "0001"; +CONSTANT cabecera_ch2: STD_LOGIC_VECTOR((HEADER_CH_SZ-1)downto 0):= "0010"; +CONSTANT cabecera_ch3: STD_LOGIC_VECTOR((HEADER_CH_SZ-1)downto 0):= "0011"; +CONSTANT cabecera_ch4: STD_LOGIC_VECTOR((HEADER_CH_SZ-1)downto 0):= "0100"; +CONSTANT cabecera_ch5: STD_LOGIC_VECTOR((HEADER_CH_SZ-1)downto 0):= "0101"; + +SIGNAL word_int: STD_LOGIC_VECTOR((WORD_INT_MUX_SZ-1)downto 0) := (OTHERS=>'0'); + +begin + +selector_wordin: PROCESS(oe_ch_vect,DATA_CH5,DATA_CH4,DATA_CH3,DATA_CH2,DATA_CH1) + BEGIN + CASE oe_ch_vect IS + WHEN "10000" => + word_int <= cabecera_const & cabecera_ch5 & DATA_CH5; + --word_int <= (OTHERS => '0'); + --word_int <= "01100110011001100110011001100110"; + WHEN "01000" => + word_int <= cabecera_const & cabecera_ch4 & DATA_CH4; + --word_int <= (OTHERS => '0'); + --word_int <= "01100110011001100110011001100110"; + --word_int <= "10101010010101011010101001010101"; + WHEN "00100" => + word_int <= cabecera_const & cabecera_ch3 & DATA_CH3; + --word_int <= (OTHERS => '0'); + --word_int <= "10101010010101011010101001010101"; + --word_int <= "01100110011001100110011001100110"; + WHEN "00010" => + word_int <= cabecera_const & cabecera_ch2 & DATA_CH2; --DATA_CH2(23 downto 16) + --word_int <= cabecera_const & cabecera_ch2 & "10000001" & "1010101001010101"; --& DATA_CH2(15 downto 0); + --word_int <= "01100010"&"11111101"&"11111110"&"11111110"; + --word_int <= "01100110011001100110011001100110"; + --word_int <= "10101010010101011010101001010101"; + WHEN "00001" => + word_int <= cabecera_const & cabecera_ch1 & DATA_CH1; + --word_int <= (OTHERS => '0'); + --word_int <= "10101010010101011010101001010101"; + --word_int <= "01100110011001100110011001100110"; + --WHEN "00000" => + --word_int <= (OTHERS => '0'); + --word_int <= "01100110011001100110011001100110"; + --word_int <= "10101010010101011010101001010101"; + WHEN OTHERS => + word_int <= (OTHERS => '0'); + --word_int <= "10101010010101011010101001010101"; + END CASE; + END PROCESS; + +selector_byte: PROCESS(hb_lbbar,word_int) + BEGIN + IF(hb_lbbar = '1') THEN + DATA_OUT <= word_int(31 downto 16); + ELSIF(hb_lbbar = '0') THEN + DATA_OUT <= word_int(15 downto 0); + ELSE + DATA_OUT <= (OTHERS => '0'); + END IF; + END PROCESS; + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/nibble_pack.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/nibble_pack.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/nibble_pack.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/nibble_pack.vhd (revision 224) @@ -0,0 +1,259 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:24:28 05/06/2016 +-- Design Name: +-- Module Name: nibble_pack - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.Numeric_STD.ALL; + +entity nibble_pack is +GENERIC( + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3 + ); + +PORT( + + --Reset del sistema + rst_bar: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos + rdy_mem: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no + +); +end nibble_pack; + +architecture Behavioral of nibble_pack is +SIGNAL clk_acq_r : std_logic_vector (2 downto 0) :=(OTHERS=>'1'); +SIGNAL chn_bits_acq_bit0 : std_logic_vector (1 downto 0) :=(OTHERS=>'0'); +SIGNAL chn_bits_acq_bit1 : std_logic_vector (1 downto 0) :=(OTHERS=>'0'); +SIGNAL chn_bits_acq_bit2 : std_logic_vector (1 downto 0) :=(OTHERS=>'0'); +SIGNAL chn_bits_acq_bit3 : std_logic_vector (1 downto 0) :=(OTHERS=>'0'); + +SIGNAL clk_acq_rise : std_logic :='0'; +SIGNAL clk_acq_fall: std_logic :='0'; +SIGNAL rdy_mem_aux: std_logic :='0'; + +SIGNAL start_count: std_logic :='0'; + +SIGNAL nibble_counter : std_logic_vector (2 downto 0) :=(OTHERS=>'0'); +SIGNAL resul_mem_internal: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0'); +SIGNAL resul_mem_internal_aux: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS=>'0'); +CONSTANT TOP_COUNT: std_logic_vector((SPI_NIBL_COUNT_WIDTH-1) downto 0) :="101"; +CONSTANT BASE_COUNT: std_logic_vector((SPI_NIBL_COUNT_WIDTH-1) downto 0) :=(OTHERS=>'0'); + +TYPE data_states IS (idle, + data_pres, data_proc + ); +SIGNAL data_cur_state: data_states := idle; +SIGNAL data_next_state: data_states := idle; + +begin + +sync_data: PROCESS(clk_main) + BEGIN + IF(rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + chn_bits_acq_bit0 <= (OTHERS=>'0'); + chn_bits_acq_bit1 <= (OTHERS=>'0'); + chn_bits_acq_bit2 <= (OTHERS=>'0'); + chn_bits_acq_bit3 <= (OTHERS=>'0'); + ELSE + chn_bits_acq_bit0 <= chn_bits_acq_bit0(0) & chn_bits_acq(0); + chn_bits_acq_bit1 <= chn_bits_acq_bit1(0) & chn_bits_acq(1); + chn_bits_acq_bit2 <= chn_bits_acq_bit2(0) & chn_bits_acq(2); + chn_bits_acq_bit3 <= chn_bits_acq_bit3(0) & chn_bits_acq(3); + END IF; + END IF; + END PROCESS; + +edge_det: PROCESS(clk_main) + BEGIN + IF(rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + clk_acq_r <=(OTHERS =>'1'); + clk_acq_rise <= '0'; + clk_acq_fall <= '0'; + ELSE + clk_acq_r <= clk_acq_r(1 downto 0) & clk_acq; + IF (clk_acq_r(2 downto 1) = "01") THEN + clk_acq_rise <= '1'; + ELSE + clk_acq_rise <= '0'; + END IF; + + IF (clk_acq_r(2 downto 1) = "10") THEN + clk_acq_fall <= '1'; + ELSE + clk_acq_fall <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + +start_save: PROCESS(clk_main) + BEGIN + IF(rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + --IF(nibble_counter = "000") THEN + start_count <= '0'; + --END IF; + ELSE + IF (clk_acq_fall = '1' AND (nibble_counter = BASE_COUNT)) THEN + start_count <= '1'; + ELSIF(clk_acq_rise = '1' AND(nibble_counter = TOP_COUNT)) THEN + start_count <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + +save_bits: PROCESS(clk_main) + BEGIN + IF(rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + --IF(nibble_counter = "000") THEN + nibble_counter <=(OTHERS => '0') ; + resul_mem_internal <=(OTHERS => '0') ; + --END IF; + ELSE + IF (start_count = '1') THEN + IF(clk_acq_rise = '1') THEN + nibble_counter <=std_logic_vector(unsigned(nibble_counter)+1); + CASE nibble_counter IS + WHEN "000" => + resul_mem_internal(23 downto 20) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(1) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + WHEN "001" => + resul_mem_internal(19 downto 16) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(1) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + WHEN "010" => + resul_mem_internal(15 downto 12) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(1) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + WHEN "011" => + resul_mem_internal(11 downto 8) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(1) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + WHEN "100" => + resul_mem_internal(7 downto 4) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(0) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + WHEN "101" => + resul_mem_internal(3 downto 0) <= chn_bits_acq_bit3(1) & chn_bits_acq_bit2(0) & chn_bits_acq_bit1(1) & chn_bits_acq_bit0(1); + nibble_counter <=(OTHERS => '0'); + WHEN OTHERS => + nibble_counter <=(OTHERS => '0'); + END CASE; + END IF; + END IF; + END IF; + END IF; + END PROCESS; + +guardar_dato: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(data_cur_state = idle) THEN + IF(rdy_mem_aux = '1') THEN + resul_mem_internal_aux((RESUL_NP_SZ-1)downto 0) <=resul_mem_internal; + END IF; + END IF; + END IF; + END PROCESS; + +output_rdy_mem: PROCESS(clk_main) + BEGIN + IF(rising_edge(clk_main)) THEN + IF (rst_bar = '0') THEN + rdy_mem_aux <= '0'; + ELSE + IF((nibble_counter = TOP_COUNT)) THEN + IF((clk_acq_rise = '1')) THEN + rdy_mem_aux <= '1'; + END IF; + ELSE + rdy_mem_aux <= '0'; + END IF; + END IF; + END IF; + END PROCESS; + +--resul_mem <= resul_mem_internal; + + + +cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + data_cur_state <= idle; + ELSE + data_cur_state <= data_next_state; + END IF; + END IF; + END PROCESS; + +salidas_estados: PROCESS(resul_mem_internal_aux,data_cur_state,libre_24,rdy_mem_aux) + BEGIN + CASE data_cur_state IS + WHEN idle => + rdy_mem <= '0'; + resul_mem <= (OTHERS => '0'); + --resul_mem <= "100000000000100001110000"; + IF (rdy_mem_aux = '1') THEN + data_next_state <= data_pres; + ELSE + data_next_state <= idle; + END IF; + + WHEN data_pres => + rdy_mem <= '1'; + resul_mem <= resul_mem_internal_aux; + --resul_mem <= "100000000000100001110000"; --1000 0000 0000 1000 0111 0000 --800870 + --resul_mem <= "111111011111111011111110"; + IF (libre_24 = '1') THEN + data_next_state <= data_proc; + ELSE + data_next_state <= data_pres; + END IF; + + WHEN data_proc => + rdy_mem <= '1'; + resul_mem <= resul_mem_internal_aux; + --resul_mem <= "100000000000100001110000"; + --resul_mem <= "111111011111111011111110"; + IF (libre_24 = '0') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + data_next_state <= idle; + ELSE + data_next_state <= data_proc; + END IF; + + WHEN OTHERS => + rdy_mem <= '0'; + resul_mem <= (OTHERS => '0'); + data_next_state <= idle; + + END CASE; + END PROCESS; + + +end Behavioral; \ No newline at end of file Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pa.fromHdl.tcl =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pa.fromHdl.tcl b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pa.fromHdl.tcl new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pa.fromHdl.tcl (revision 224) @@ -0,0 +1,49 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name chn5_mem_spi_joint -dir "C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/planAhead_run_2" -part xc6slx9tqg144-3 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property target_constrs_file "chn5_mem_spi_joint.ucf" [current_fileset -constrset] +set hdlfile [add_files [list {W_R_RAM_CONTROLLER.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {SPI_SLAVE.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {spi_controller.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {SEL_WRbar.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {nibble_pack.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {mux_np.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {header_memory.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {data_header_ram.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {u_np_mux_memcon_seliobar.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {i2c_inst.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {header_spi_interface.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {DCM_fwd_int.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {chn5_mem_spi_joint.vhd}]] +set_property file_type VHDL $hdlfile +set_property library work $hdlfile +set_property top chn5_mem_spi_joint $srcset +add_files [list {chn5_mem_spi_joint.ucf}] -fileset [get_property constrset [current_run]] +open_rtl_design -part xc6slx9tqg144-3 Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/par_usage_statistics.html =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/par_usage_statistics.html b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/par_usage_statistics.html new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/par_usage_statistics.html (revision 224) @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Par Statistics
Total Non-vccgnd Signals=1102
Total Non-vccgnd Design Pins=4110
Total Non-vccgnd Conns=4110
Total Non-vccgnd Timing Constrained Conns=3847
Phase 1 CPU=5.8 sec
Phase 2 CPU=6.3 sec
Phase 3 CPU=8.7 sec
Phase 4 CPU=9.8 sec
Phase 5 CPU=13.3 sec
Phase 6 CPU=14.2 sec
Phase 7 CPU=26.3 sec
Phase 8 CPU=26.3 sec
Phase 9 CPU=26.3 sec
Phase 10 CPU=26.5 sec
AvgWirelenPerPin Fanout 1=5.0
AvgWirelenPerPin Fanout 2=2.0
AvgWirelenPerPin Fanout 3=1.3
AvgWirelenPerPin Fanout 4=4.0
AvgWirelenPerPin Fanout 10=3.3
AvgWirelenPerPin Fanout 50=2.4
AvgWirelenPerPin Fanout 100=6.9
AvgWirelenPerPin Fanout 500=5.4
AvgWirelenPerPin Fanout 5000=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.6620
Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pepExtractor.prj =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pepExtractor.prj b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pepExtractor.prj new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/pepExtractor.prj (revision 224) @@ -0,0 +1,13 @@ +work "DCM_fwd_int.vhd" +work "SEL_WRbar.vhd" +work "SPI_SLAVE.vhd" +work "W_R_RAM_CONTROLLER.vhd" +work "chn5_mem_spi_joint.vhd" +work "data_header_ram.vhd" +work "header_memory.vhd" +work "header_spi_interface.vhd" +work "i2c_inst.vhd" +work "mux_np.vhd" +work "nibble_pack.vhd" +work "spi_controller.vhd" +work "u_np_mux_memcon_seliobar.vhd" Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid5356.debug =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid5356.debug b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid5356.debug new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid5356.debug (revision 224) @@ -0,0 +1,73 @@ +#------------------------------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 +# Current time: 5/18/16 11:46:27 AM +# Process ID: 5356 +# Platform: Windows +# +# This file is an indication that an internal application error occurred. +# This information is useful for debugging. Please open a case with Xilinx +# Technical Support with this file and a testcase attached. +#------------------------------------------------------------------------------- +5/18/16 11:46:27 AM +ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR + + at ui.h.e.CF(SourceFile:217) + at ui.h.I.CF(SourceFile:702) + at ui.frmwork.HTclEventBroker.a(SourceFile:368) + at ui.frmwork.HTclEventBroker.bb(SourceFile:354) + at ui.project.a.een(SourceFile:759) + at ui.project.a.cleanup(SourceFile:608) + at ui.project.r.cleanup(SourceFile:631) + at ui.PlanAhead.aJj(SourceFile:335) + at ui.PlanAhead.a(SourceFile:1192) + at ui.frmwork.a.i.c(SourceFile:35) + at ui.frmwork.HTclEventBroker.a(SourceFile:233) + at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325) + at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method) + at ui.e.gY(SourceFile:195) + at ui.bl.run(SourceFile:882) + at ui.cd.run(SourceFile:1821) + at ui.views.F.aw.a(SourceFile:341) + at ui.cd.b(SourceFile:1809) + at ui.cd.a(SourceFile:1784) + at ui.PlanAhead.a(SourceFile:778) + at ui.aL.c(SourceFile:885) + at ui.aL.aHs(SourceFile:824) + at ui.bk.windowClosing(SourceFile:503) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.Window.processWindowEvent(Window.java:2051) + at javax.swing.JFrame.processWindowEvent(JFrame.java:296) + at java.awt.Window.processEvent(Window.java:2009) + at ui.aL.processEvent(SourceFile:1214) + at java.awt.Component.dispatchEventImpl(Component.java:4861) + at java.awt.Container.dispatchEventImpl(Container.java:2287) + at java.awt.Window.dispatchEventImpl(Window.java:2719) + at java.awt.Component.dispatchEvent(Component.java:4687) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729) + at java.awt.EventQueue.access$200(EventQueue.java:103) + at java.awt.EventQueue$3.run(EventQueue.java:688) + at java.awt.EventQueue$3.run(EventQueue.java:686) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87) + at java.awt.EventQueue$4.run(EventQueue.java:702) + at java.awt.EventQueue$4.run(EventQueue.java:700) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:699) + at ui.frmwork.a.e.dispatchEvent(SourceFile:73) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:91) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid6960.debug =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid6960.debug b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid6960.debug new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid6960.debug (revision 224) @@ -0,0 +1,72 @@ +#------------------------------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 +# Current time: 5/18/16 4:02:05 PM +# Process ID: 6960 +# Platform: Windows +# +# This file is an indication that an internal application error occurred. +# This information is useful for debugging. Please open a case with Xilinx +# Technical Support with this file and a testcase attached. +#------------------------------------------------------------------------------- +5/18/16 4:02:05 PM +ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR + + at ui.h.e.CF(SourceFile:217) + at ui.h.I.CF(SourceFile:702) + at ui.frmwork.HTclEventBroker.a(SourceFile:368) + at ui.frmwork.HTclEventBroker.bb(SourceFile:354) + at ui.project.a.een(SourceFile:759) + at ui.project.a.cleanup(SourceFile:608) + at ui.project.r.cleanup(SourceFile:631) + at ui.PlanAhead.aJj(SourceFile:335) + at ui.PlanAhead.a(SourceFile:1192) + at ui.frmwork.a.i.c(SourceFile:35) + at ui.frmwork.HTclEventBroker.a(SourceFile:233) + at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325) + at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method) + at ui.e.gY(SourceFile:195) + at ui.bl.run(SourceFile:882) + at ui.cd.run(SourceFile:1821) + at ui.views.F.aw.a(SourceFile:341) + at ui.cd.b(SourceFile:1809) + at ui.cd.a(SourceFile:1784) + at ui.PlanAhead.a(SourceFile:778) + at ui.aL.c(SourceFile:885) + at ui.aL.aHs(SourceFile:824) + at ui.bk.windowClosing(SourceFile:503) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.Window.processWindowEvent(Window.java:2051) + at javax.swing.JFrame.processWindowEvent(JFrame.java:296) + at java.awt.Window.processEvent(Window.java:2009) + at ui.aL.processEvent(SourceFile:1214) + at java.awt.Component.dispatchEventImpl(Component.java:4861) + at java.awt.Container.dispatchEventImpl(Container.java:2287) + at java.awt.Window.dispatchEventImpl(Window.java:2719) + at java.awt.Component.dispatchEvent(Component.java:4687) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729) + at java.awt.EventQueue.access$200(EventQueue.java:103) + at java.awt.EventQueue$3.run(EventQueue.java:688) + at java.awt.EventQueue$3.run(EventQueue.java:686) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87) + at java.awt.EventQueue$4.run(EventQueue.java:702) + at java.awt.EventQueue$4.run(EventQueue.java:700) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:699) + at ui.frmwork.a.e.dispatchEvent(SourceFile:73) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:91) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid7604.debug =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid7604.debug b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid7604.debug new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid7604.debug (revision 224) @@ -0,0 +1,72 @@ +#------------------------------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 +# Current time: 5/18/16 4:00:35 PM +# Process ID: 7604 +# Platform: Windows +# +# This file is an indication that an internal application error occurred. +# This information is useful for debugging. Please open a case with Xilinx +# Technical Support with this file and a testcase attached. +#------------------------------------------------------------------------------- +5/18/16 4:00:35 PM +ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR + + at ui.h.e.CF(SourceFile:217) + at ui.h.I.CF(SourceFile:702) + at ui.frmwork.HTclEventBroker.a(SourceFile:368) + at ui.frmwork.HTclEventBroker.bb(SourceFile:354) + at ui.project.a.een(SourceFile:759) + at ui.project.a.cleanup(SourceFile:608) + at ui.project.r.cleanup(SourceFile:631) + at ui.PlanAhead.aJj(SourceFile:335) + at ui.PlanAhead.a(SourceFile:1192) + at ui.frmwork.a.i.c(SourceFile:35) + at ui.frmwork.HTclEventBroker.a(SourceFile:233) + at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325) + at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method) + at ui.e.gY(SourceFile:195) + at ui.bl.run(SourceFile:882) + at ui.cd.run(SourceFile:1821) + at ui.views.F.aw.a(SourceFile:341) + at ui.cd.b(SourceFile:1809) + at ui.cd.a(SourceFile:1784) + at ui.PlanAhead.a(SourceFile:778) + at ui.aL.c(SourceFile:885) + at ui.aL.aHs(SourceFile:824) + at ui.bk.windowClosing(SourceFile:503) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.Window.processWindowEvent(Window.java:2051) + at javax.swing.JFrame.processWindowEvent(JFrame.java:296) + at java.awt.Window.processEvent(Window.java:2009) + at ui.aL.processEvent(SourceFile:1214) + at java.awt.Component.dispatchEventImpl(Component.java:4861) + at java.awt.Container.dispatchEventImpl(Container.java:2287) + at java.awt.Window.dispatchEventImpl(Window.java:2719) + at java.awt.Component.dispatchEvent(Component.java:4687) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729) + at java.awt.EventQueue.access$200(EventQueue.java:103) + at java.awt.EventQueue$3.run(EventQueue.java:688) + at java.awt.EventQueue$3.run(EventQueue.java:686) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87) + at java.awt.EventQueue$4.run(EventQueue.java:702) + at java.awt.EventQueue$4.run(EventQueue.java:700) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:699) + at ui.frmwork.a.e.dispatchEvent(SourceFile:73) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:91) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid8656.debug =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid8656.debug b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid8656.debug new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/planAhead_pid8656.debug (revision 224) @@ -0,0 +1,72 @@ +#------------------------------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:29:51 MDT 2013 +# Current time: 5/18/16 11:47:10 AM +# Process ID: 8656 +# Platform: Windows +# +# This file is an indication that an internal application error occurred. +# This information is useful for debugging. Please open a case with Xilinx +# Technical Support with this file and a testcase attached. +#------------------------------------------------------------------------------- +5/18/16 11:47:10 AM +ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR + + at ui.h.e.CF(SourceFile:217) + at ui.h.I.CF(SourceFile:702) + at ui.frmwork.HTclEventBroker.a(SourceFile:368) + at ui.frmwork.HTclEventBroker.bb(SourceFile:354) + at ui.project.a.een(SourceFile:759) + at ui.project.a.cleanup(SourceFile:608) + at ui.project.r.cleanup(SourceFile:631) + at ui.PlanAhead.aJj(SourceFile:335) + at ui.PlanAhead.a(SourceFile:1192) + at ui.frmwork.a.i.c(SourceFile:35) + at ui.frmwork.HTclEventBroker.a(SourceFile:233) + at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325) + at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method) + at ui.e.gY(SourceFile:195) + at ui.bl.run(SourceFile:882) + at ui.cd.run(SourceFile:1821) + at ui.views.F.aw.a(SourceFile:341) + at ui.cd.b(SourceFile:1809) + at ui.cd.a(SourceFile:1784) + at ui.PlanAhead.a(SourceFile:778) + at ui.aL.c(SourceFile:885) + at ui.aL.aHs(SourceFile:824) + at ui.bk.windowClosing(SourceFile:503) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.Window.processWindowEvent(Window.java:2051) + at javax.swing.JFrame.processWindowEvent(JFrame.java:296) + at java.awt.Window.processEvent(Window.java:2009) + at ui.aL.processEvent(SourceFile:1214) + at java.awt.Component.dispatchEventImpl(Component.java:4861) + at java.awt.Container.dispatchEventImpl(Container.java:2287) + at java.awt.Window.dispatchEventImpl(Window.java:2719) + at java.awt.Component.dispatchEvent(Component.java:4687) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729) + at java.awt.EventQueue.access$200(EventQueue.java:103) + at java.awt.EventQueue$3.run(EventQueue.java:688) + at java.awt.EventQueue$3.run(EventQueue.java:686) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87) + at java.awt.EventQueue$4.run(EventQueue.java:702) + at java.awt.EventQueue$4.run(EventQueue.java:700) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:699) + at ui.frmwork.a.e.dispatchEvent(SourceFile:73) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:91) + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/spi_controller.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/spi_controller.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/spi_controller.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/spi_controller.vhd (revision 224) @@ -0,0 +1,451 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:57:52 05/16/2016 +-- Design Name: +-- Module Name: spi_controller - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity spi_controller is +GENERIC( + + WORD_IN_SZ: INTEGER :=16; + WORD_INT_SZ: INTEGER :=16; + WORD_OUT_SZ: INTEGER :=8; + WORD_SPIIN_SZ: INTEGER :=8; + + POS_WORD1: INTEGER :=16; + POS_WORD2: INTEGER :=8 + +); +PORT( + --Senhal de reset general + rst_bar: IN std_logic; + + --Senhal de reloj principal + clk_main: IN std_logic; + + --Senhal request hacia memoria de cabecera + req_header: OUT std_logic; + + --Senhal request hacia memoria de cabecera + ld_header: IN std_logic; + + --Senhal request hacia bloque controlador RAM + req_ram: OUT std_logic; + + --Senhal desde bloque controlador RAM + ld_ram: IN std_logic; + + --Senhal hacia RAM interna de cabecera y futura fecha-hora + rst_headerdate: OUT std_logic; + + --Senhal de seleccion + sel_headerdate_ram: OUT std_logic; + + --Senhal con splitter de 24(32) a 16 + word_in: IN STD_LOGIC_VECTOR((WORD_IN_SZ-1)downto 0); + + --Senhales con SPI Slave + word_out: OUT STD_LOGIC_VECTOR((WORD_OUT_SZ-1) downto 0); + fromspi_in: IN STD_LOGIC_VECTOR((WORD_SPIIN_SZ-1) downto 0); + rdy_8_in: IN STD_LOGIC; + --req_8_in: IN STD_LOGIC; + spi_free: IN STD_LOGIC + +); +end spi_controller; + +architecture Behavioral of spi_controller is + +--Estado para control de solicitud de request a memoria ram o header +TYPE spi_contrl_states IS (idle, + pide_dato_header, pide_dato_ram, + w1_pres_header,w1_proc_header,w1_espera_header, + w2_pres_header,w2_proc_header,w2_espera_header, + w1_pres_ram,w1_proc_ram,w1_espera_ram, + w2_pres_ram,w2_proc_ram,w2_espera_ram, + w2_aum_header, w2_aum_ram + ); +SIGNAL spi_contrl_cur_state: spi_contrl_states := idle; +SIGNAL spi_contrl_next_state: spi_contrl_states := idle; + +--Estado segun comando +TYPE cmd_states IS (stop,start); +SIGNAL cmd_cur_state: cmd_states := stop; +SIGNAL cmd_next_state: cmd_states := stop; + +--Palabra interior de tamanho de la ram +SIGNAL word_int: STD_LOGIC_VECTOR((WORD_INT_SZ-1)downto 0) := (OTHERS=>'0'); + +--Palabra leida desde el spi esclavo +SIGNAL word_fromspi_int: STD_LOGIC_VECTOR((WORD_SPIIN_SZ-1)downto 0) := (OTHERS=>'0'); + + +--Constantes de estados +CONSTANT CMD_STR: std_logic_vector (7 downto 0) := "01100011"; +CONSTANT CMD_STP: std_logic_vector (7 downto 0) := "01101100"; + +--Constante de límites de cambio de estados de header a ram +CONSTANT DIR_HEADER: std_logic_vector (11 downto 0) := "000000000111"; --7 +CONSTANT DIR_RAM: std_logic_vector (11 downto 0) := "100111001011"; --2507 + +--Contador de paquetes +SIGNAL count_pac: std_logic_vector (11 downto 0) := (OTHERS => '0'); --"1001110000111"; + +begin + +guardar_dato_16: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + word_int <=(OTHERS=>'0'); + ELSE + IF(spi_contrl_cur_state = pide_dato_header OR spi_contrl_cur_state = pide_dato_ram) THEN + --IF(ld_header = '1' OR ld_ram = '1') THEN + word_int((WORD_INT_SZ-1)downto 0) <=word_in; + --END IF; + END IF; + END IF; + END IF; + END PROCESS; + +guardar_dato_8: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + word_fromspi_int((WORD_SPIIN_SZ-1)downto 0) <= (OTHERS=>'0'); + ELSE + --IF(spi_contrl_cur_state = w1_pres OR spi_contrl_cur_state = w2_pres) THEN + IF(rdy_8_in = '1') THEN + word_fromspi_int((WORD_SPIIN_SZ-1)downto 0) <= fromspi_in; + END IF; + --END IF; + END IF; + END IF; + END PROCESS; + +--Cambio de estado del estado segun comando recibido +cmd_cambio_estado:PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + cmd_cur_state <= stop; + ELSE + cmd_cur_state <= cmd_next_state; + END IF; + END IF; + END PROCESS; + +--Revisar si los estados de set, act y proc se pueden unificar. Al parecer los de set sí. +cmd_salidas_estados: PROCESS(cmd_cur_state,word_fromspi_int) + BEGIN + + CASE cmd_cur_state IS + WHEN stop => + IF (word_fromspi_int = CMD_STR) THEN + cmd_next_state <= start; + ELSE + cmd_next_state <= stop; + END IF; + + WHEN start => + IF (word_fromspi_int = CMD_STP) THEN + cmd_next_state <= stop; + ELSE + cmd_next_state <= start; + END IF; + + WHEN OTHERS => + cmd_next_state <= stop; + + END CASE; + + END PROCESS; + +--word_fromspi_out <= word_fromspi_int; + +--- +count_pac_proc: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + CASE spi_contrl_cur_state IS + WHEN idle => + count_pac <= (OTHERS => '0'); + + WHEN w2_aum_ram | w2_aum_header => + count_pac <= std_logic_vector(unsigned(count_pac)+1); + + WHEN OTHERS => + count_pac <= count_pac; + END CASE; + END IF; + END PROCESS; + +ctrl_cambio_estados: PROCESS(clk_main) + BEGIN + IF (rising_edge(clk_main)) THEN + IF(rst_bar = '0') THEN + spi_contrl_cur_state <= idle; + ELSE + spi_contrl_cur_state <= spi_contrl_next_state; + END IF; + END IF; + END PROCESS; + +ctrl_salidas_estados: PROCESS(ld_header, ld_ram, + word_int, + spi_contrl_cur_state, + cmd_cur_state, count_pac, + --req_8_in, + spi_free) + BEGIN + CASE spi_contrl_cur_state IS + WHEN idle => + req_header <= '0'; + req_ram <= '0'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '1'; + sel_headerdate_ram <= '0'; + IF (cmd_cur_state = START) THEN + spi_contrl_next_state <= pide_dato_header; + ELSIF (cmd_cur_state = STOP) THEN + spi_contrl_next_state <= idle; + ELSE + spi_contrl_next_state <= idle; + END IF; + + WHEN pide_dato_header => + req_header <= '1'; + req_ram <= '1'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (ld_header = '1') THEN + spi_contrl_next_state <= w1_pres_header; + ELSE + spi_contrl_next_state <= pide_dato_header; + END IF; + + WHEN w1_pres_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '1') THEN + spi_contrl_next_state <= w1_espera_header; + ELSE + spi_contrl_next_state <= w1_pres_header; + END IF; + + WHEN w1_espera_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '0') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w1_proc_header; + ELSE + spi_contrl_next_state <= w1_espera_header; + END IF; + + WHEN w1_proc_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '1') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_pres_header; + ELSE + spi_contrl_next_state <= w1_proc_header; + END IF; + + WHEN w2_pres_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD2-1) downto 0); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '1') THEN + spi_contrl_next_state <= w2_espera_header; + ELSE + spi_contrl_next_state <= w2_pres_header; + END IF; + + WHEN w2_espera_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD2-1) downto 0); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '0') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_proc_header; + ELSE + spi_contrl_next_state <= w2_espera_header; + END IF; + + WHEN w2_proc_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= word_int((POS_WORD2-1) downto 0);--word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (spi_free = '1') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_aum_header; + ELSE + spi_contrl_next_state <= w2_proc_header; + END IF; + + WHEN w2_aum_header => + req_header <= '0'; + req_ram <= '1'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '0'; + sel_headerdate_ram <= '0'; + IF (count_pac = DIR_HEADER) THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= pide_dato_ram; + ELSE + spi_contrl_next_state <= pide_dato_header; + END IF; + + WHEN pide_dato_ram => + req_header <= '0'; + req_ram <= '1'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (ld_ram = '1') THEN + spi_contrl_next_state <= w1_pres_ram; + ELSE + spi_contrl_next_state <= pide_dato_ram; + END IF; + + WHEN w1_pres_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD2-1) downto 0); + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '1') THEN + spi_contrl_next_state <= w1_espera_ram; + ELSE + spi_contrl_next_state <= w1_pres_ram; + END IF; + + WHEN w1_espera_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD2-1) downto 0); + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '0') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w1_proc_ram; + ELSE + spi_contrl_next_state <= w1_espera_ram; + END IF; + + + WHEN w1_proc_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD2-1) downto 0); + word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '1') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_pres_ram; + ELSE + spi_contrl_next_state <= w1_proc_ram; + END IF; + + WHEN w2_pres_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + word_out <= word_int((POS_WORD2-1) downto 0); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '1') THEN + spi_contrl_next_state <= w2_espera_ram; + ELSE + spi_contrl_next_state <= w2_pres_ram; + END IF; + + WHEN w2_espera_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + word_out <= word_int((POS_WORD2-1) downto 0); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '0') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_proc_ram; + ELSE + spi_contrl_next_state <= w2_espera_ram; + END IF; + + WHEN w2_proc_ram => + req_header <= '0'; + req_ram <= '0'; + --word_out <= word_int((POS_WORD1-1) downto (POS_WORD2)); + word_out <= word_int((POS_WORD2-1) downto 0);--word_int((POS_WORD1-1) downto (POS_WORD2)); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (spi_free = '1') THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= w2_aum_ram; + ELSE + spi_contrl_next_state <= w2_proc_ram; + END IF; + + WHEN w2_aum_ram => + req_header <= '0'; + req_ram <= '0'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + IF (count_pac = DIR_RAM) THEN --Si ya está ocupado con el dato antes presentado entonces ya puedo ir pidiendo otro dato + spi_contrl_next_state <= idle; + ELSE + spi_contrl_next_state <= pide_dato_ram; + END IF; + + WHEN OTHERS => + req_header <= '0'; + req_ram <= '0'; + word_out <= (OTHERS => '0'); + rst_headerdate <= '0'; + sel_headerdate_ram <= '1'; + spi_contrl_next_state <= idle; + + END CASE; + END PROCESS; +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_ch5_mem_spi_joint.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_ch5_mem_spi_joint.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_ch5_mem_spi_joint.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_ch5_mem_spi_joint.vhd (revision 224) @@ -0,0 +1,46 @@ +-- TestBench Template + + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + + ENTITY testbench IS + END testbench; + + ARCHITECTURE behavior OF testbench IS + + -- Component Declaration + COMPONENT + PORT( + : IN std_logic; + : IN std_logic_vector(3 downto 0); + : OUT std_logic_vector(3 downto 0) + ); + END COMPONENT; + + SIGNAL : std_logic; + SIGNAL : std_logic_vector(3 downto 0); + + + BEGIN + + -- Component Instantiation + uut: PORT MAP( + => , + => + ); + + + -- Test Bench Statements + tb : PROCESS + BEGIN + + wait for 100 ns; -- wait until global set/reset completes + + -- Add user defined stimulus here + + wait; -- will wait forever + END PROCESS tb; + -- End Test Bench + + END; Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/tb_chn5_mem_spi_joint.vhd (revision 224) @@ -0,0 +1,4085 @@ +-- TestBench Template + + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + + ENTITY testbench IS +GENERIC( + --Tamanho de palabras de entradas y resultado hacia el multipllexor + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + RESUL_MUX_SZ: INTEGER :=16; + + --Tamanho de la palabra hacia o desde la RAM + RESUL_RAM_SZ: INTEGER :=16; + CHAN_NUM: INTEGER :=5; + ADDR_LENGTH: INTEGER :=19; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3; + + --Constantes del multiplexor + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16; + + --Constantes hacia el bloque selector de entrada salida + RESUL_IOSEL_SZ: INTEGER := 16; + + --Tamanho de palabra de datos desde RAM + DATA_MUX_SZ: INTEGER := 16; + + --Constantes de bloque de memoria con datos de cabecera + COUNT_HEADER_SZ: INTEGER := 3; + HEADER_SZ: INTEGER :=8; + DATA_HEADER_SZ: INTEGER := 16; + + --Constantes del bloque de controlador SPI + WORD_IN_SZ: INTEGER := 16; + WORD_INT_SZ: INTEGER := 16; + WORD_OUT_SZ: INTEGER := 8; + WORD_SPIIN_SZ: INTEGER := 8; + + POS_WORD1: INTEGER := 16; + POS_WORD2: INTEGER := 8; + + --Constantes del bloque spi esclavo + SPI_DATA_WIDTH: INTEGER :=8; + SPI_BIT_COUNT_WIDTH: INTEGER :=3 +); + END testbench; + + ARCHITECTURE behavior OF testbench IS + +COMPONENT chn5_mem_spi_joint is +--GENERIC( + --Tamanho de palabras de entradas y resultado hacia el multipllexor +-- NIBBLE_SZ: INTEGER :=4; +-- RESUL_NP_SZ: INTEGER :=24; +-- RESUL_MUX_SZ: INTEGER :=16; + + --Tamanho de la palabra hacia o desde la RAM +-- RESUL_RAM_SZ: INTEGER :=16; +-- CHAN_NUM: INTEGER :=5; +-- ADDR_LENGTH: INTEGER :=19; +-- SPI_NIBL_COUNT_WIDTH: INTEGER := 3; + + --Constantes del multiplexor +-- HEADER_CONST_SZ: INTEGER :=4; +-- HEADER_CH_SZ: INTEGER :=4; +-- WORD_INT_MUX_SZ: INTEGER := 32; +-- WORD_OUT_MUX_SZ: INTEGER := 16; + + --Constantes hacia el bloque selector de entrada salida +-- RESUL_IOSEL_SZ: INTEGER := 16; + + --Tamanho de palabra de datos desde RAM +-- DATA_MUX_SZ: INTEGER := 16; + + --Constantes de bloque de memoria con datos de cabecera +-- COUNT_HEADER_SZ: INTEGER := 3; +-- HEADER_SZ: INTEGER :=8; +-- DATA_HEADER_SZ: INTEGER := 16; + + --Constantes del bloque de controlador SPI +-- WORD_IN_SZ: INTEGER := 16; +-- WORD_INT_SZ: INTEGER := 16; +-- WORD_OUT_SZ: INTEGER := 8; +-- WORD_SPIIN_SZ: INTEGER := 8; + +-- POS_WORD1: INTEGER := 16; +-- POS_WORD2: INTEGER := 8; + + --Constantes del bloque spi esclavo +-- SPI_DATA_WIDTH: INTEGER :=8; +-- SPI_BIT_COUNT_WIDTH: INTEGER :=3 + +--); +PORT( + --Reset del sistema + lock: IN STD_LOGIC; + + --Pulso por segundo + pps: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT: INOUT std_logic_vector((RESUL_RAM_SZ-1) downto 0); + + --Senhales interfaz SPI esclavo + MOSI : IN std_logic; + SCK : IN std_logic; + CS : IN std_logic; + MISO : OUT std_logic; + + --Senhal de reloj hacia el bloque de adquisicion + clk_to_acq: OUT std_logic; + + --Pines para siguiente implementacion de I2C + scl_rpi: INOUT std_logic; + sda_rpi: INOUT std_logic + +); +end COMPONENT; + +--Reset del sistema +SIGNAL lock: STD_LOGIC :='0'; + + --Pulso por segundo +SIGNAL pps: STD_LOGIC :='0'; + + --Reloj principal +SIGNAL clk_main: STD_LOGIC :='0'; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador +SIGNAL clk_acq_ch1: STD_LOGIC :='0'; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición +SIGNAL chn_bits_acq_ch1: STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0) := (OTHERS => '0'); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición +SIGNAL clk_acq_ch2: STD_LOGIC :='0'; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición +SIGNAL chn_bits_acq_ch2: STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0) := (OTHERS => '0'); --Nibble de datos provenientes del XMEGA por canal +SIGNAL clk_acq_ch3: STD_LOGIC :='0'; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición +SIGNAL chn_bits_acq_ch3: STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0) := (OTHERS => '0'); --Nibble de datos provenientes del XMEGA por canal +SIGNAL clk_acq_ch4: STD_LOGIC :='0'; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición +SIGNAL chn_bits_acq_ch4: STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0) := (OTHERS => '0'); --Nibble de datos provenientes del XMEGA por canal +SIGNAL clk_acq_ch5: STD_LOGIC :='0'; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición +SIGNAL chn_bits_acq_ch5: STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0) := (OTHERS => '0'); --Nibble de datos provenientes del XMEGA por canal + + --Senhales de control de memoria RAM +SIGNAL we_bar: std_logic; +SIGNAL ub_bar: std_logic; +SIGNAL lb_bar: std_logic; + +SIGNAL oe_ram_bar: std_logic; + + --Direccion de escritura/lectura +SIGNAL addr: std_logic_vector((ADDR_LENGTH-1) downto 0); + + --Dato desde/hacia la memoria RAM externa +SIGNAL DATA_INOUT: std_logic_vector((RESUL_RAM_SZ-1) downto 0); + + --Senhales interfaz SPI esclavo +SIGNAL MOSI : std_logic :='0'; +SIGNAL SCK : std_logic :='0'; +SIGNAL CS : std_logic :='0'; +SIGNAL MISO : std_logic; --output + + --Senhal de reloj hacia el bloque de adquisicion +SIGNAL clk_to_acq: std_logic; + + --Pines para siguiente implementacion de I2C +SIGNAL scl_rpi: std_logic :='0'; +SIGNAL sda_rpi: std_logic :='0'; + +constant clk_main_period : time := 16.667 ns; + + BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: chn5_mem_spi_joint +-- GENERIC MAP( + --Tamanho de palabras de entradas y resultado hacia el multipllexor +-- NIBBLE_SZ => NIBBLE_SZ, +-- RESUL_NP_SZ => RESUL_NP_SZ, +-- RESUL_MUX_SZ => RESUL_MUX_SZ, + + --Tamanho de la palabra hacia o desde la RAM +-- RESUL_RAM_SZ => RESUL_RAM_SZ, +-- CHAN_NUM => CHAN_NUM, +-- ADDR_LENGTH => ADDR_LENGTH, +-- SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH, +-- + --Constantes del multiplexor +-- HEADER_CONST_SZ => HEADER_CONST_SZ, +-- HEADER_CH_SZ => HEADER_CH_SZ, +-- WORD_INT_MUX_SZ => WORD_INT_MUX_SZ, +-- WORD_OUT_MUX_SZ => WORD_OUT_MUX_SZ, + + --Constantes hacia el bloque selector de entrada salida +-- RESUL_IOSEL_SZ => RESUL_IOSEL_SZ, + + --Tamanho de palabra de datos desde RAM +-- DATA_MUX_SZ => DATA_MUX_SZ, + + --Constantes de bloque de memoria con datos de cabecera +-- COUNT_HEADER_SZ => COUNT_HEADER_SZ, +-- HEADER_SZ => HEADER_SZ, +-- DATA_HEADER_SZ => DATA_HEADER_SZ, + + --Constantes del bloque de controlador SPI +-- WORD_IN_SZ => WORD_IN_SZ, +-- WORD_INT_SZ => WORD_INT_SZ, +-- WORD_OUT_SZ => WORD_OUT_SZ, +-- WORD_SPIIN_SZ => WORD_SPIIN_SZ, + +-- POS_WORD1 => POS_WORD1, +-- POS_WORD2 => POS_WORD2, + + --Constantes del bloque spi esclavo +-- SPI_DATA_WIDTH => SPI_DATA_WIDTH, +-- SPI_BIT_COUNT_WIDTH => SPI_BIT_COUNT_WIDTH + +--) +PORT MAP( + --Reset del sistema + lock => lock, + + --Pulso por segundo + pps => pps, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1 => clk_acq_ch1, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1 => chn_bits_acq_ch1,--Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2 => clk_acq_ch2,--Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2 => chn_bits_acq_ch2, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3 => clk_acq_ch3, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3 => chn_bits_acq_ch3, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4 => clk_acq_ch4, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4 => chn_bits_acq_ch4, --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5 => clk_acq_ch5, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5 => chn_bits_acq_ch5, --Nibble de datos provenientes del XMEGA por canal + + --Senhales de control de memoria RAM + we_bar => we_bar, + ub_bar => ub_bar, + lb_bar => lb_bar, + --cs1_bar: OUT std_logic; + --cs2: OUT std_logic; + oe_ram_bar => oe_ram_bar, + + --Direccion de escritura/lectura + addr => addr, + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT => DATA_INOUT, + + --Senhales interfaz SPI esclavo + MOSI => MOSI, + SCK => SCK, + CS => CS, + MISO => MISO, + + --Senhal de reloj hacia el bloque de adquisicion + clk_to_acq => clk_to_acq, + + --Pines para siguiente implementacion de I2C + scl_rpi => scl_rpi, + sda_rpi => sda_rpi + +); + + -- Clock process definitions + clk_main_process :process + begin + clk_main <= '0'; + wait for clk_main_period/2; + clk_main <= '1'; + wait for clk_main_period/2; + end process; + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 50 ns; + + wait for clk_main_period*10; + MOSI <= '1'; + lock <= '0'; + wait for 2 us; + SCK <= '1'; + wait for clk_main_period*10; + --Comportamiento con reset activo y sin seleccionar el chip + CS <= '1'; + lock <= '0'; + wait for clk_main_period*10; + --Comportamiento con reset activo y seleccionando el chip + CS <= '0'; + lock <= '0'; + wait for clk_main_period*10; + --Comportamiento con reset apagado y seleccionando el chip + --pero no tengo entradas MISO ni SCLK + CS <= '1'; + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + wait for clk_main_period*10; + + pps <= '1'; + + wait for clk_main_period*40; + + pps <= '0'; + wait for clk_main_period*40; + wait for 700us; + + pps <= '1'; + + wait for clk_main_period*40; + + pps <= '0'; + wait for clk_main_period*40;--Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + wait for 350 us; + CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + --clk_acq_ch1 <= '1'; + + --wait for clk_main_period*4; + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0111"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1011"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0111"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1011"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + ----------------------------------- + ----------------------------------- + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + + + ------------------------------------ + ------------------------------------ + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + ----------------------------------------------------------- + ----------------------------------------------------------- + + --Caso reloj continuo + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + --clk_acq_ch1 <= '1'; + + --wait for clk_main_period*4; + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0111"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1011"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0110"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0010"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "0111"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + --clk_acq_ch1 <= '0'; + --chn_bits_acq_ch1 <= "1011"; + --wait for clk_main_period*4; + --clk_acq_ch1 <= '1'; + --wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + ----------------------------------- + ----------------------------------- + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + + + ------------------------------------ + ------------------------------------ + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait for clk_main_period*10; + CS <= '0'; + lock <= '1'; + + wait for clk_main_period*10; + + + --Comportamiento con reset apagado y seleccionando el chip + --Genero señal SCLK + + --CS <= '1'; + --data_in <= "10101010"; + SCK <= '1'; + wait for clk_main_period*10; + + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + ------------------------------- + --En este espacio se va cargar el dato + clk_acq_ch1 <= '1'; + + wait for clk_main_period*4; + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0110"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0010"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "0111"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + clk_acq_ch1 <= '0'; + chn_bits_acq_ch1 <= "1011"; + wait for clk_main_period*4; + clk_acq_ch1 <= '1'; + wait for clk_main_period*4; + + wait for clk_main_period*15; + ------------------------------- + --BIT 7 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT6 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT5 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT4 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT3 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT2 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT1 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --BIT0 + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --------------------------- + --BYTE 1: MOSI 10100101 + --------------------------- + --MOSI: + --CS <= '1'; + --data_in <= "01010101"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + wait for clk_main_period*10; + + --BIT 7 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + SCK <= '0'; + MOSI <='1'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + -------------------------------- + --SEGUNDO BYTE DE PRUEBA + --Valor: 01101001 + -------------------------------- + + --CS <= '1'; + --data_in <= "01001000"; + SCK <= '1'; + wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*10; + + --MOSI: BIT 7 + MOSI <='0'; + --data_in <= "01001000"; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + -------------------------------- + --TERCER BYTE DE PRUEBA + --Valor: 10100101 + -------------------------------- + --MOSI: BIT 7 + --CS <= '1'; + --data_in <= "01111110"; + SCK <= '1'; + --wait for clk_main_period*10; + --CS <= '0'; + SCK <= '1'; + wait for clk_main_period*8; + + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 6 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 5 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 4 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 3 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 2 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 1 + MOSI <='0'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + --MOSI: BIT 0 + MOSI <='1'; + SCK <= '0'; + wait for clk_main_period*3; + SCK <= '1'; + wait for clk_main_period*3; + + wait; + end process; + END; Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/u_np_mux_memcon_seliobar.vhd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/u_np_mux_memcon_seliobar.vhd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/u_np_mux_memcon_seliobar.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/u_np_mux_memcon_seliobar.vhd (revision 224) @@ -0,0 +1,464 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 11:08:23 05/16/2016 +-- Design Name: +-- Module Name: u_np_mux_memcon_seliobar - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +library UNISIM; +use UNISIM.VComponents.all; + +entity u_np_mux_memcon_seliobar is +GENERIC( + --Tamanho de palabras de entradas y resultado hacia el multipllexor + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + RESUL_MUX_SZ: INTEGER :=16; + + --Tamanho de la palabra hacia o desde la RAM + RESUL_RAM_SZ: INTEGER :=16; + CHAN_NUM: INTEGER :=5; + ADDR_LENGTH: INTEGER :=19; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3; + + --Constantes del multiplexor + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16; + + --Constantes hacia el bloque selector de entrada salida + RESUL_IOSEL_SZ: INTEGER := 16 + +); +PORT( + --Reset del sistema + rst_bar_int: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq_ch1: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch1: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + clk_acq_ch2: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch2: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch3: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch3: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch4: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch4: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + clk_acq_ch5: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq_ch5: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req: IN std_logic; + --Hacia el SPI_Controller + ld_ram: OUT std_logic; + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + cs1_bar: OUT std_logic; + cs2: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0); + + --Dato desde/hacia la memoria RAM externa + DATA_INOUT: INOUT std_logic_vector((RESUL_RAM_SZ-1) downto 0); + + --Dato leído de la RAM hacia el SPI Controller o cache + DATA_R : OUT std_logic_vector((RESUL_RAM_SZ-1) downto 0) +); + +end u_np_mux_memcon_seliobar; + +architecture Behavioral of u_np_mux_memcon_seliobar is + +COMPONENT nibble_pack is +GENERIC( + NIBBLE_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + SPI_NIBL_COUNT_WIDTH: INTEGER := 3 + ); + +PORT( + + --Reset del sistema + rst_bar: IN STD_LOGIC; + + --Reloj principal + clk_main: IN STD_LOGIC; --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq: IN STD_LOGIC; --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq: IN STD_LOGIC_VECTOR((NIBBLE_SZ-1) downto 0); --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem: OUT STD_LOGIC_VECTOR((RESUL_NP_SZ-1) downto 0); --Salida al espacio de memoria para almacenar datos crudos + rdy_mem: OUT STD_LOGIC; --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24: IN STD_LOGIC --Senhal para indicar que el dato presentado fue leido o no + +); +end COMPONENT; + +COMPONENT W_R_RAM_CONTROLLER IS +GENERIC( + ADDR_LENGTH: INTEGER := 19; + CHAN_NUM: INTEGER := 5 + +); + +PORT( + --Reset general + rst_bar: IN std_logic; + + --Entrada de reloj principal + clk_main: IN std_logic; + + --Entradas para indicar dato preparado por leer + --Desde los nibble to packets + wr_ch_vector: IN std_logic_vector((CHAN_NUM-1) downto 0); + + --Senhal para que indica que termino con una peticion + --Hacia los nibble to packets + ack_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0); + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req: IN std_logic; + --Hacia el SPI_Controller + ld_ram: OUT std_logic; + + --Senhales de control de memoria RAM + we_bar: OUT std_logic; + ub_bar: OUT std_logic; + lb_bar: OUT std_logic; + cs1_bar: OUT std_logic; + cs2: OUT std_logic; + oe_ram_bar: OUT std_logic; + + --Selector de canal de salida hacia RAM + --Hacia el multiplexor + oe_ch_vector: OUT std_logic_vector((CHAN_NUM-1) downto 0); + hb_lbbar: OUT std_logic; + + --Direccion de escritura/lectura + addr: OUT std_logic_vector((ADDR_LENGTH-1) downto 0) + +); +end COMPONENT; + +COMPONENT mux_np is +GENERIC( + CHAN_NUM: INTEGER :=5; + HEADER_CONST_SZ: INTEGER :=4; + HEADER_CH_SZ: INTEGER :=4; + RESUL_NP_SZ: INTEGER :=24; + WORD_INT_MUX_SZ: INTEGER := 32; + WORD_OUT_MUX_SZ: INTEGER := 16 + ); +PORT( + --Palabras desde "Nibble/packet channels" + DATA_CH1 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH2 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH3 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH4 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + DATA_CH5 : IN std_logic_vector((RESUL_NP_SZ-1) downto 0); + + --Selector de dato de canal a presentar + oe_ch_vect : IN std_logic_vector((CHAN_NUM-1) downto 0); + + --Selector de palabra de 16 bits en + hb_lbbar: IN std_logic; + + --Dato a escribir en memoria + DATA_OUT : OUT std_logic_vector((WORD_OUT_MUX_SZ-1) downto 0) +); +end COMPONENT; + +COMPONENT SEL_WRbar is +GENERIC( + RESUL_IOSEL_SZ: INTEGER :=16 + ); + +PORT( + DATA_W : IN std_logic_vector((RESUL_IOSEL_SZ-1) downto 0); + DATA_R : OUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0); + OEbar: IN std_logic; + DATA_INOUT: INOUT std_logic_vector((RESUL_IOSEL_SZ-1) downto 0) +); +end COMPONENT; + +--Senhales desde paquetes de datos del nibble/packet hacia multiplexor +SIGNAL pack_ch1: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS => '0'); +SIGNAL pack_ch2: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS => '0'); +SIGNAL pack_ch3: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS => '0'); +SIGNAL pack_ch4: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS => '0'); +SIGNAL pack_ch5: std_logic_vector((RESUL_NP_SZ-1) downto 0) :=(OTHERS => '0'); + +--Senhales de union entre el controlador de memoria y la multiplexor +SIGNAL oe_ch_vect: std_logic_vector((CHAN_NUM-1) downto 0) :=(OTHERS => '0'); +SIGNAL hb_lbbar: std_logic := '0'; + +--Senhales desde paquetes de datos del nibble/packet con el mem_controller +SIGNAL rdy_ch_vect: std_logic_vector((CHAN_NUM-1) downto 0) :=(OTHERS => '0'); +SIGNAL ack_ch_vector: std_logic_vector((CHAN_NUM-1) downto 0) :=(OTHERS => '0'); + +--Dato desde el multiplexor al selector de entrada salida +SIGNAL data_mux: std_logic_vector((RESUL_MUX_SZ-1) downto 0) :=(OTHERS => '0'); + +--Senhal de habilitacion de salida hacia el selector de IObar +SIGNAL OEbar: std_logic := '1'; + +--Registro para detección de flanco +SIGNAL pps_r: std_logic_vector(1 downto 0) :="00"; +SIGNAL pps_rst: std_logic :='0'; + +--Senhal de reset interna formada de rst_bar y pps_r +--SIGNAL rst_bar_int: std_logic :='0'; + +begin + +nibble_pack_ch1: nibble_pack +GENERIC MAP( + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH + ) + +PORT MAP( + --Reset del sistema + rst_bar => rst_bar_int, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq => clk_acq_ch1, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq => chn_bits_acq_ch1, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem => pack_ch1, --Salida al espacio de memoria para almacenar datos crudos + rdy_mem => rdy_ch_vect(0), --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24 => ack_ch_vector(0) --Senhal para indicar que el dato presentado fue leido o no + +); + +nibble_pack_ch2: nibble_pack +GENERIC MAP( + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH + ) + +PORT MAP( + --Reset del sistema + rst_bar => rst_bar_int, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq => clk_acq_ch2, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq => chn_bits_acq_ch2, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem => pack_ch2, --Salida al espacio de memoria para almacenar datos crudos + rdy_mem => rdy_ch_vect(1), --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24 => ack_ch_vector(1) --Senhal para indicar que el dato presentado fue leido o no + +); + +nibble_pack_ch3: nibble_pack +GENERIC MAP( + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH + ) + +PORT MAP( + --Reset del sistema + rst_bar => rst_bar_int, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq => clk_acq_ch3, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq => chn_bits_acq_ch3, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem => pack_ch3, --Salida al espacio de memoria para almacenar datos crudos + rdy_mem => rdy_ch_vect(2), --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24 => ack_ch_vector(2) --Senhal para indicar que el dato presentado fue leido o no + +); + +nibble_pack_ch4: nibble_pack +GENERIC MAP( + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH + ) + +PORT MAP( + --Reset del sistema + rst_bar => rst_bar_int, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq => clk_acq_ch4, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq => chn_bits_acq_ch4, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem => pack_ch4, --Salida al espacio de memoria para almacenar datos crudos + rdy_mem => rdy_ch_vect(3), --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24 => ack_ch_vector(3) --Senhal para indicar que el dato presentado fue leido o no + +); + +nibble_pack_ch5: nibble_pack +GENERIC MAP( + NIBBLE_SZ => NIBBLE_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + SPI_NIBL_COUNT_WIDTH => SPI_NIBL_COUNT_WIDTH + ) + +PORT MAP( + --Reset del sistema + rst_bar => rst_bar_int, + + --Reloj principal + clk_main => clk_main, --Reloj externo de por lo menos 32MHz proveniente del módulo de sincronización + + --Senhales con el microcontrolador + clk_acq => clk_acq_ch5, --Senhal de "reloj" proveniente del XMEGA por canal del módulo de adquisición + chn_bits_acq => chn_bits_acq_ch5, --Nibble de datos provenientes del XMEGA por canal del módulo de adquisición + + --Senhales hacia el sistema + resul_mem => pack_ch5, --Salida al espacio de memoria para almacenar datos crudos + rdy_mem => rdy_ch_vect(4), --Senhal para indicar que el dato fue obtenido satisfactoriamente y esta listo para ser almacenado en memoria + libre_24 => ack_ch_vector(4) --Senhal para indicar que el dato presentado fue leido o no + +); + + + +ram_control: W_R_RAM_CONTROLLER +GENERIC MAP( + ADDR_LENGTH => ADDR_LENGTH, + CHAN_NUM => CHAN_NUM + +) + +PORT MAP( + --Reset general + rst_bar => rst_bar_int, + + --Entrada de reloj principal + clk_main => clk_main, + + --Entradas para indicar dato preparado por leer + --Desde los nibble to packets + wr_ch_vector => rdy_ch_vect, + + --Senhal para que indica que termino con una peticion + --Hacia los nibble to packets + ack_ch_vector => ack_ch_vector, + + --Senhal de requerimiento de lectura de dato + --Desde el SPI_Controller + rd_req => rd_req, + --Hacia el SPI_Controller + ld_ram => ld_ram, + + --Senhales de control de memoria RAM + we_bar => we_bar, + ub_bar => ub_bar, + lb_bar => lb_bar, + cs1_bar => cs1_bar, + cs2 => cs2, + oe_ram_bar => OEbar, + + --Selector de canal de salida hacia RAM + --Hacia el multiplexor + oe_ch_vector => oe_ch_vect, + hb_lbbar => hb_lbbar, + + --Direccion de escritura/lectura + addr => addr + +); + +oe_ram_bar <= OEbar; + +mux_data: mux_np +GENERIC MAP( + CHAN_NUM => CHAN_NUM, + HEADER_CONST_SZ => HEADER_CONST_SZ, + HEADER_CH_SZ => HEADER_CH_SZ, + RESUL_NP_SZ => RESUL_NP_SZ, + WORD_INT_MUX_SZ => WORD_INT_MUX_SZ, + WORD_OUT_MUX_SZ => WORD_OUT_MUX_SZ + ) +PORT MAP( + --Palabras desde "Nibble/packet channels" + DATA_CH1 => pack_ch1, + DATA_CH2 => pack_ch2, + DATA_CH3 => pack_ch3, + DATA_CH4 => pack_ch4, + DATA_CH5 => pack_ch5, + + --Selector de dato de canal a presentar + oe_ch_vect => oe_ch_vect, + + --Selector de palabra de 16 bits en + hb_lbbar => hb_lbbar, + + --Dato a escribir en memoria + DATA_OUT => data_mux +); + + + +io_sel: SEL_WRbar +GENERIC MAP( + RESUL_IOSEL_SZ => RESUL_IOSEL_SZ + ) + +PORT MAP( + DATA_W => data_mux, + DATA_R => DATA_R, + OEbar => OEbar, + DATA_INOUT => DATA_INOUT +); + +end Behavioral; + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/usage_statistics_webtalk.html =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/usage_statistics_webtalk.html b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/usage_statistics_webtalk.html new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/usage_statistics_webtalk.html (revision 224) @@ -0,0 +1,1322 @@ +Device Usage Statistics Report + +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Version and Target Device
Product Version:ISE:14.7 (WebPack) - P.20131013Target Family:Spartan6
OS Platform:NT64Target Device:xc6slx9
Project ID (random number)5402c7000f65437cb4136d1c7067b320.09E7CA3DCC8644B38A16D7AF4C01A33A.72Target Package:tqg144
Registration ID211109259_0_0_038Target Speed:-3
Date Generated2016-05-23T12:39:06Tool FlowISE
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + +
User Environment
OS NameMicrosoft , 64-bitOS Releasemajor release (build 9200)
CPU NameIntel(R) Core(TM) i5-4210U CPU @ 1.70GHzCPU Speed2394 MHz
OS NameMicrosoft , 64-bitOS Releasemajor release (build 9200)
CPU NameIntel(R) Core(TM) i5-4210U CPU @ 1.70GHzCPU Speed2394 MHz
+ 
+ + + + + + + + + + + + +
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
+Adders/Subtractors=10 +
    +
  • 12-bit adder=2
    • +
  • 19-bit adder=1
    • +
  • 3-bit adder=1
    • +
  • 4-bit adder=1
    • +
  • 9-bit adder=5
    • +
+ +Counters=9 +
    +
  • 12-bit up counter=1
    • +
  • 16-bit up counter=1
    • +
  • 3-bit up counter=7
    • +
+ +FSMs=10 + +Multiplexers=84 +
    +
  • 1-bit 2-to-1 multiplexer=2
    • +
  • 12-bit 2-to-1 multiplexer=2
    • +
  • 16-bit 2-to-1 multiplexer=3
    • +
  • 19-bit 2-to-1 multiplexer=23
    • +
  • 24-bit 2-to-1 multiplexer=30
    • +
  • 3-bit 2-to-1 multiplexer=2
    • +
  • 32-bit 2-to-1 multiplexer=5
    • +
  • 4-bit 2-to-1 multiplexer=4
    • +
  • 8-bit 2-to-1 multiplexer=3
    • +
  • 9-bit 2-to-1 multiplexer=10
    • +
+ +RAMs=1 +
    +
  • 8x16-bit single-port distributed Read Only RAM=1
    • +
+ +Registers=450 +
    +
  • Flip-Flops=450
    • +
+ +		 +MiscellaneousStatistics +
    +
  • AGG_BONDED_IO=74
    • +
  • AGG_IO=74
    • +
  • AGG_LOCED_IO=74
    • +
  • AGG_SLICE=337
    • +
  • NUM_BONDED_IOB=74
    • +
  • NUM_BSFULL=364
    • +
  • NUM_BSLUTONLY=375
    • +
  • NUM_BSREGONLY=111
    • +
  • NUM_BSUSED=850
    • +
  • NUM_BUFG=4
    • +
  • NUM_BUFIO2=2
    • +
  • NUM_BUFIO2FB=2
    • +
  • NUM_DCM=2
    • +
  • NUM_IOB_FF=1
    • +
  • NUM_LOCED_IOB=74
    • +
  • NUM_LOGIC_O5ANDO6=161
    • +
  • NUM_LOGIC_O5ONLY=34
    • +
  • NUM_LOGIC_O6ONLY=536
    • +
  • NUM_LUT_RT_DRIVES_CARRY4=3
    • +
  • NUM_LUT_RT_DRIVES_FLOP=4
    • +
  • NUM_LUT_RT_EXO5=4
    • +
  • NUM_LUT_RT_EXO6=3
    • +
  • NUM_LUT_RT_O5=1
    • +
  • NUM_LUT_RT_O6=34
    • +
  • NUM_OLOGIC2=1
    • +
  • NUM_SLICEL=24
    • +
  • NUM_SLICEM=1
    • +
  • NUM_SLICEX=312
    • +
  • NUM_SLICE_CARRY4=16
    • +
  • NUM_SLICE_CONTROLSET=28
    • +
  • NUM_SLICE_CYINIT=939
    • +
  • NUM_SLICE_F7MUX=8
    • +
  • NUM_SLICE_FF=564
    • +
  • NUM_SLICE_UNUSEDCTRL=111
    • +
  • NUM_SRL_O6ONLY=1
    • +
  • NUM_UNUSABLE_FF_BELS=59
    • +
+ +		 +NetStatistics +
    +
  • NumNets_Active=1176
    • +
  • NumNets_Gnd=1
    • +
  • NumNets_Vcc=1
    • +
  • NumNodesOfType_Active_BOUNCEACROSS=48
    • +
  • NumNodesOfType_Active_BOUNCEIN=178
    • +
  • NumNodesOfType_Active_BUFGOUT=4
    • +
  • NumNodesOfType_Active_BUFHINP2OUT=11
    • +
  • NumNodesOfType_Active_BUFIOINP=4
    • +
  • NumNodesOfType_Active_CLKPIN=228
    • +
  • NumNodesOfType_Active_CLKPINFEED=27
    • +
  • NumNodesOfType_Active_CNTRLPIN=127
    • +
  • NumNodesOfType_Active_DOUBLE=1755
    • +
  • NumNodesOfType_Active_GENERIC=157
    • +
  • NumNodesOfType_Active_GLOBAL=101
    • +
  • NumNodesOfType_Active_INPUT=20
    • +
  • NumNodesOfType_Active_IOBIN2OUT=101
    • +
  • NumNodesOfType_Active_IOBOUTPUT=102
    • +
  • NumNodesOfType_Active_LUTINPUT=3511
    • +
  • NumNodesOfType_Active_OUTBOUND=1137
    • +
  • NumNodesOfType_Active_OUTPUT=1096
    • +
  • NumNodesOfType_Active_PADINPUT=52
    • +
  • NumNodesOfType_Active_PADOUTPUT=49
    • +
  • NumNodesOfType_Active_PINBOUNCE=683
    • +
  • NumNodesOfType_Active_PINFEED=3841
    • +
  • NumNodesOfType_Active_PINFEED1=1
    • +
  • NumNodesOfType_Active_PINFEED2=4
    • +
  • NumNodesOfType_Active_QUAD=1503
    • +
  • NumNodesOfType_Active_REGINPUT=168
    • +
  • NumNodesOfType_Active_SINGLE=2111
    • +
  • NumNodesOfType_Vcc_CLKPIN=2
    • +
  • NumNodesOfType_Vcc_CNTRLPIN=1
    • +
  • NumNodesOfType_Vcc_HVCCOUT=108
    • +
  • NumNodesOfType_Vcc_IOBINPUT=1
    • +
  • NumNodesOfType_Vcc_KVCCOUT=3
    • +
  • NumNodesOfType_Vcc_LUTINPUT=198
    • +
  • NumNodesOfType_Vcc_PINFEED=202
    • +
+ +SiteStatistics +
    +
  • BUFG-BUFGMUX=4
    • +
  • IOB-IOBM=36
    • +
  • IOB-IOBS=38
    • +
  • SLICEL-SLICEM=18
    • +
  • SLICEX-SLICEL=90
    • +
  • SLICEX-SLICEM=73
    • +
+ +		 +SiteSummary +
    +
  • BUFG=4
    • +
  • BUFG_BUFG=4
    • +
  • BUFIO2=2
    • +
  • BUFIO2FB=2
    • +
  • BUFIO2FB_BUFIO2FB=2
    • +
  • BUFIO2_BUFIO2=2
    • +
  • CARRY4=16
    • +
  • DCM=2
    • +
  • DCM_DCM=2
    • +
  • FF_SR=90
    • +
  • HARD0=4
    • +
  • INVERTER=1
    • +
  • IOB=74
    • +
  • IOB_IMUX=49
    • +
  • IOB_INBUF=49
    • +
  • IOB_OUTBUF=43
    • +
  • LUT5=200
    • +
  • LUT6=734
    • +
  • LUT_OR_MEM6=1
    • +
  • OLOGIC2=1
    • +
  • OLOGIC2_OUTFF=1
    • +
  • PAD=74
    • +
  • REG_SR=474
    • +
  • SELMUX2_1=8
    • +
  • SLICEL=24
    • +
  • SLICEM=1
    • +
  • SLICEX=312
    • +
+ +
+ 
+ + + + + + + +
Configuration Data
+BUFIO2FB_BUFIO2FB +
    +
  • DIVIDE_BYPASS=[TRUE:2]
    • +
  • INVERT_INPUTS=[FALSE:2]
    • +
+ +BUFIO2_BUFIO2 +
    +
  • DIVIDE=[1:2]
    • +
  • DIVIDE_BYPASS=[TRUE:2]
    • +
  • I_INVERT=[FALSE:2]
    • +
+ +DCM +
    +
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
    • +
  • PSEN=[PSEN_INV:0] [PSEN:2]
    • +
  • PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
    • +
  • RST=[RST:2] [RST_INV:0]
    • +
+ +DCM_DCM +
    +
  • CLKDV_DIVIDE=[2.0:2]
    • +
  • CLKIN_DIVIDE_BY_2=[FALSE:2]
    • +
  • CLKOUT_PHASE_SHIFT=[NONE:2]
    • +
  • CLK_FEEDBACK=[1X:2]
    • +
  • DESKEW_ADJUST=[5:2]
    • +
  • DFS_FREQUENCY_MODE=[LOW:2]
    • +
  • DLL_FREQUENCY_MODE=[LOW:2]
    • +
  • DSS_MODE=[NONE:2]
    • +
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
    • +
  • PSCLK=[PSCLK_INV:0] [PSCLK:2]
    • +
  • PSEN=[PSEN_INV:0] [PSEN:2]
    • +
  • PSINCDEC=[PSINCDEC:2] [PSINCDEC_INV:0]
    • +
  • RST=[RST:2] [RST_INV:0]
    • +
  • STARTUP_WAIT=[FALSE:2]
    • +
  • VERY_HIGH_FREQUENCY=[FALSE:2]
    • +
+		 + +FF_SR +
    +
  • CK=[CK:90] [CK_INV:0]
    • +
  • SRINIT=[SRINIT0:83] [SRINIT1:7]
    • +
  • SYNC_ATTR=[ASYNC:79] [SYNC:11]
    • +
+ +IOB_OUTBUF +
    +
  • DRIVEATTRBOX=[12:41]
    • +
  • SLEW=[SLOW:41]
    • +
  • SUSPEND=[3STATE:43]
    • +
+ +LUT_OR_MEM5 +
    +
  • LUT_OR_MEM=[LUT:1]
    • +
+ +LUT_OR_MEM6 +
    +
  • CLK=[CLK:1] [CLK_INV:0]
    • +
  • LUT_OR_MEM=[RAM:1]
    • +
  • RAMMODE=[SRL16:1]
    • +
+ +OLOGIC2 +
    +
  • CLK0=[CLK0_INV:0] [CLK0:1]
    • +
  • CLK1=[CLK1:0] [CLK1_INV:1]
    • +
+		 + +OLOGIC2_OUTFF +
    +
  • CK0=[CK0_INV:0] [CK0:1]
    • +
  • CK1=[CK1_INV:1] [CK1:0]
    • +
  • DDR_ALIGNMENT=[NONE:1]
    • +
  • OUTFFTYPE=[DDR:1]
    • +
  • SRINIT_OQ=[0:1]
    • +
  • SRTYPE_OQ=[SYNC:1]
    • +
+ +REG_SR +
    +
  • CK=[CK:474] [CK_INV:0]
    • +
  • LATCH_OR_FF=[FF:474]
    • +
  • SRINIT=[SRINIT0:464] [SRINIT1:10]
    • +
  • SYNC_ATTR=[ASYNC:396] [SYNC:78]
    • +
+ +SLICEL +
    +
  • CLK=[CLK:7] [CLK_INV:0]
    • +
+ +SLICEM +
    +
  • CLK=[CLK:1] [CLK_INV:0]
    • +
+		 + +SLICEX +
    +
  • CLK=[CLK:218] [CLK_INV:0]
    • +
+ +
+ 
+ + + + + + + +
Pin Data
+BUFG +
    +
  • I0=4
    • +
  • O=4
    • +
+ +BUFG_BUFG +
    +
  • I0=4
    • +
  • O=4
    • +
+ +BUFIO2 +
    +
  • DIVCLK=2
    • +
  • I=2
    • +
+ +BUFIO2FB +
    +
  • I=2
    • +
  • O=2
    • +
+ +BUFIO2FB_BUFIO2FB +
    +
  • I=2
    • +
  • O=2
    • +
+ +BUFIO2_BUFIO2 +
    +
  • DIVCLK=2
    • +
  • I=2
    • +
+ +CARRY4 +
    +
  • CIN=11
    • +
  • CO3=11
    • +
  • CYINIT=5
    • +
  • DI0=16
    • +
  • DI1=16
    • +
  • DI2=16
    • +
  • DI3=11
    • +
  • O0=16
    • +
  • O1=16
    • +
  • O2=16
    • +
  • O3=16
    • +
  • S0=16
    • +
  • S1=16
    • +
  • S2=16
    • +
  • S3=16
    • +
+ +DCM +
    +
  • CLK0=2
    • +
  • CLKFB=2
    • +
  • CLKFX=2
    • +
  • CLKIN=2
    • +
  • PSCLK=2
    • +
  • PSEN=2
    • +
  • PSINCDEC=2
    • +
  • RST=2
    • +
+ +DCM_DCM +
    +
  • CLK0=2
    • +
  • CLKFB=2
    • +
  • CLKFX=2
    • +
  • CLKIN=2
    • +
  • PSCLK=2
    • +
  • PSEN=2
    • +
  • PSINCDEC=2
    • +
  • RST=2
    • +
+ +FF_SR +
    +
  • CE=31
    • +
  • CK=90
    • +
  • D=90
    • +
  • Q=90
    • +
  • SR=11
    • +
+ +HARD0 +
    +
  • 0=4
    • +
+ +INVERTER +
    +
  • IN=1
    • +
  • OUT=1
    • +
+ +IOB +
    +
  • I=49
    • +
  • O=43
    • +
  • PAD=74
    • +
  • T=18
    • +
+		 + +IOB_IMUX +
    +
  • I=48
    • +
  • I_B=1
    • +
  • OUT=49
    • +
+ +IOB_INBUF +
    +
  • OUT=49
    • +
  • PAD=49
    • +
+ +IOB_OUTBUF +
    +
  • IN=43
    • +
  • OUT=43
    • +
  • TRI=18
    • +
+ +LUT5 +
    +
  • A1=61
    • +
  • A2=123
    • +
  • A3=139
    • +
  • A4=99
    • +
  • A5=80
    • +
  • O5=200
    • +
+ +LUT6 +
    +
  • A1=286
    • +
  • A2=529
    • +
  • A3=627
    • +
  • A4=691
    • +
  • A5=707
    • +
  • A6=725
    • +
  • O6=734
    • +
+ +LUT_OR_MEM5 +
    +
  • A1=1
    • +
  • A2=1
    • +
  • A3=1
    • +
  • A4=1
    • +
  • A5=1
    • +
  • O5=1
    • +
+ +LUT_OR_MEM6 +
    +
  • A1=1
    • +
  • A2=1
    • +
  • A3=1
    • +
  • A4=1
    • +
  • A5=1
    • +
  • A6=1
    • +
  • CLK=1
    • +
  • DI2=1
    • +
  • O6=1
    • +
  • WE=1
    • +
+ +OLOGIC2 +
    +
  • CLK0=1
    • +
  • CLK1=1
    • +
  • D1=1
    • +
  • D2=1
    • +
  • OCE=1
    • +
  • OQ=1
    • +
  • SR=1
    • +
+ +OLOGIC2_OUTFF +
    +
  • CE=1
    • +
  • CK0=1
    • +
  • CK1=1
    • +
  • D1=1
    • +
  • D2=1
    • +
  • Q=1
    • +
  • SR=1
    • +
+ +PAD +
    +
  • PAD=74
    • +
+		 + +REG_SR +
    +
  • CE=291
    • +
  • CK=474
    • +
  • D=474
    • +
  • Q=474
    • +
  • SR=78
    • +
+ +SELMUX2_1 +
    +
  • 0=8
    • +
  • 1=8
    • +
  • OUT=8
    • +
  • S0=8
    • +
+ +SLICEL +
    +
  • A1=3
    • +
  • A2=3
    • +
  • A3=3
    • +
  • A4=10
    • +
  • A5=12
    • +
  • A6=16
    • +
  • AMUX=12
    • +
  • AQ=7
    • +
  • AX=7
    • +
  • B=1
    • +
  • B1=3
    • +
  • B2=4
    • +
  • B3=4
    • +
  • B4=11
    • +
  • B5=13
    • +
  • B6=17
    • +
  • BMUX=13
    • +
  • BQ=5
    • +
  • BX=3
    • +
  • C1=7
    • +
  • C2=8
    • +
  • C3=10
    • +
  • C4=18
    • +
  • C5=20
    • +
  • C6=24
    • +
  • CE=6
    • +
  • CIN=11
    • +
  • CLK=7
    • +
  • CMUX=20
    • +
  • COUT=11
    • +
  • CQ=5
    • +
  • CX=10
    • +
  • D1=9
    • +
  • D2=10
    • +
  • D3=10
    • +
  • D4=16
    • +
  • D5=17
    • +
  • D6=22
    • +
  • DMUX=12
    • +
  • DQ=5
    • +
  • DX=3
    • +
  • SR=1
    • +
+ +SLICEM +
    +
  • A1=1
    • +
  • A2=1
    • +
  • A3=1
    • +
  • A4=1
    • +
  • A5=1
    • +
  • A6=1
    • +
  • AI=1
    • +
  • AQ=1
    • +
  • CE=1
    • +
  • CLK=1
    • +
+		 + +SLICEX +
    +
  • A=92
    • +
  • A1=90
    • +
  • A2=178
    • +
  • A3=181
    • +
  • A4=193
    • +
  • A5=188
    • +
  • A6=187
    • +
  • AMUX=31
    • +
  • AQ=142
    • +
  • AX=40
    • +
  • B=94
    • +
  • B1=83
    • +
  • B2=123
    • +
  • B3=143
    • +
  • B4=146
    • +
  • B5=154
    • +
  • B6=153
    • +
  • BMUX=31
    • +
  • BQ=97
    • +
  • BX=38
    • +
  • C=56
    • +
  • C1=61
    • +
  • C2=133
    • +
  • C3=134
    • +
  • C4=137
    • +
  • C5=141
    • +
  • C6=140
    • +
  • CE=78
    • +
  • CLK=218
    • +
  • CMUX=40
    • +
  • CQ=118
    • +
  • CX=33
    • +
  • D=107
    • +
  • D1=81
    • +
  • D2=144
    • +
  • D3=155
    • +
  • D4=160
    • +
  • D5=166
    • +
  • D6=166
    • +
  • DMUX=46
    • +
  • DQ=94
    • +
  • DX=34
    • +
  • SR=41
    • +
+ +
+ 
+ + +
Tool Usage
Command Line History
    +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • xst -intstyle ise -ifn <ise_file>
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
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  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • xst -intstyle ise -ifn <ise_file>
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
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  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
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    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
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  • xst -intstyle ise -ifn <ise_file>
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  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-3 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc6slx9-tqg144-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
    • +
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    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact5500000
bitgen24424400000
map37835400000
netgen414100000
ngc2edif6600000
ngdbuild41141100000
par35135100000
trce35535500000
xst93192800000
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Project Statistics
PROP_Enable_Message_Filtering=falsePROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=BalancedPROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=falsePROP_PropSpecInProjFile=Store all values
PROP_SelectedInstanceHierarchicalPath=/testbenchPROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changedPROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=falsePROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2016-05-18T09:44:41PROP_intWbtProjectID=09E7CA3DCC8644B38A16D7AF4C01A33A
PROP_intWbtProjectIteration=72PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=NoPROP_lockPinsUcfFile=changed
PROP_selectedSimRootSourceNode_behav=work.testbenchPROP_selectedSimRootSourceNode_par=work.testbench
PROP_selectedSimRootSourceNode_translate=work.testbenchPROP_selectedSimSourceNode=uut
PROP_xilxBitgStart_IntDone=truePROP_AutoTop=true
PROP_DevFamily=Spartan6PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog)PROP_DevSpeed=-3
PROP_PreferredLanguage=VHDLFILE_UCF=1
FILE_VHDL=14
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Unisim Statistics
XST_UNISIM_SUMMARY
XST_NUM_IBUFG=1XST_NUM_ODDR2=1
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4NGDBUILD_NUM_DCM_SP=2NGDBUILD_NUM_FD=216NGDBUILD_NUM_FDE=259
NGDBUILD_NUM_FDR=26NGDBUILD_NUM_FDRE=63NGDBUILD_NUM_GND=1NGDBUILD_NUM_IBUF=30
NGDBUILD_NUM_IBUFG=1NGDBUILD_NUM_INV=13NGDBUILD_NUM_IOBUF=18NGDBUILD_NUM_LUT1=37
NGDBUILD_NUM_LUT2=57NGDBUILD_NUM_LUT3=161NGDBUILD_NUM_LUT4=108NGDBUILD_NUM_LUT5=235
NGDBUILD_NUM_LUT6=269NGDBUILD_NUM_MUXCY=59NGDBUILD_NUM_MUXF7=8NGDBUILD_NUM_OBUF=25
NGDBUILD_NUM_ODDR2=1NGDBUILD_NUM_SRLC16E=1NGDBUILD_NUM_VCC=1NGDBUILD_NUM_XORCY=63
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=4NGDBUILD_NUM_DCM_SP=2NGDBUILD_NUM_FD=216NGDBUILD_NUM_FDE=259
NGDBUILD_NUM_FDR=26NGDBUILD_NUM_FDRE=63NGDBUILD_NUM_GND=1NGDBUILD_NUM_IBUF=48
NGDBUILD_NUM_IBUFG=1NGDBUILD_NUM_INV=13NGDBUILD_NUM_LUT1=37NGDBUILD_NUM_LUT2=57
NGDBUILD_NUM_LUT3=161NGDBUILD_NUM_LUT4=108NGDBUILD_NUM_LUT5=235NGDBUILD_NUM_LUT6=269
NGDBUILD_NUM_MUXCY=59NGDBUILD_NUM_MUXF7=8NGDBUILD_NUM_OBUF=25NGDBUILD_NUM_OBUFT=18
NGDBUILD_NUM_ODDR2=1NGDBUILD_NUM_SRLC16E=1NGDBUILD_NUM_TS_TIMESPEC=1NGDBUILD_NUM_VCC=1
NGDBUILD_NUM_XORCY=63
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj-ofn=<design_top>-ofmt=NGC-p=xc6slx9-3-tqg144
-top=<design_top>-opt_mode=Speed-opt_level=1-power=NO
-iuc=NO-keep_hierarchy=No-netlist_hierarchy=As_Optimized-rtlview=Yes
-glob_opt=AllClockNets-read_cores=YES-write_timing_constraints=NO-cross_clock_analysis=NO
-bus_delimiter=<>-slice_utilization_ratio=100-bram_utilization_ratio=100-dsp_utilization_ratio=100
-reduce_control_sets=Auto-fsm_extract=YES-fsm_encoding=Auto-safe_implementation=No
-fsm_style=LUT-ram_extract=Yes-ram_style=Auto-rom_extract=Yes
-shreg_extract=YES-rom_style=Auto-auto_bram_packing=NO-resource_sharing=YES
-async_to_sync=NO-use_dsp48=Auto-iobuf=YES-max_fanout=100000
-bufg=16-register_duplication=YES-register_balancing=No-optimize_primitives=NO
-use_clock_enable=Auto-use_sync_set=Auto-use_sync_reset=Auto-iob=Auto
-equivalent_register_removal=YES-slice_utilization_ratio_maxmargin=5
+ 
Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk.log =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk.log b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk.log new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk.log (revision 224) @@ -0,0 +1,16 @@ +Release 14.7 - WebTalk (P.20131013) +Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. + +Project Information +-------------------- +ProjectID=09E7CA3DCC8644B38A16D7AF4C01A33A +ProjectIteration=72 + +WebTalk Summary +---------------- +INFO:WebTalk:1 - WebTalk is enabled because you are using a WebPACK license. + +INFO:WebTalk:8 - WebTalk Install setting is ON. +INFO:WebTalk:6 - WebTalk User setting is ON. + +INFO:WebTalk:5 - C:/Users/Francisco/Documents/Francisco_ROJ/ProcessingEngine/Projects/chn5_mem_spi_joint/usage_statistics_webtalk.html WebTalk report has not been sent to Xilinx. Please check your network and proxy settings. For additional details about this file, please refer to the WebTalk help file at C:/Xilinx/14.7/ISE_DS/ISE/data/reports/webtalk_introduction.html Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk_pn.xml =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk_pn.xml b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk_pn.xml new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/webtalk_pn.xml (revision 224) @@ -0,0 +1,49 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + Index: trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/xlnx_auto_0_xdb/cst.xbcd =================================================================== diff --git a/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/xlnx_auto_0_xdb/cst.xbcd b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/xlnx_auto_0_xdb/cst.xbcd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Processing/chn5_mem_spi_joint/xlnx_auto_0_xdb/cst.xbcd (revision 224) @@ -0,0 +1,110 @@ +XlxV37EB fa00 11d4xÚÅ‹sÛVvÆÓn§w¶ít7uk›Y›³ivážs.®·2E9Üèµ¢œ·N1EŬ)Q!©¬½Fÿâ$À'âu¿dÆŠ8÷|ß½çøáRº÷Þ{ï5F•½açuïÇîÏüŸþïoÞ›ü÷ÿ¯óúF»×ÝkwtÛsÿwл~×¹ú•äx0®´ï:îhtu×ï¿«¼Ëîeåew$yÑ8ø¹ÿ¿Ó³“ÓæÙùK÷xï¨ù/þ­g/ÜýæáÞK÷›½ÃÍößûvÿÈ=yöûfã|öÄëbw]y·ùíéÞñ~s?îX÷¹Û»ç7ÏßúoýÖû­3ßË?ø¯Îšͳæq£¼Ý>yqÖh~0/·=ì¸ß`èù Ücïº{/èÞIûÜWÙ;Ûÿ×yÜy÷íØ= ¯½ÉÐø¸zðtؽê½ý+ÿÝ{ÁàïUƒ1nžW~í]^ÿ[9ßýº2O^ù²røMãè¤ÍüäïýÀ¨oÁë(ÞÉ1AÛ/”ó´º­mFNV×G1ù]ÖÒºœ.8³S8³ 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1000 //ARRAY_RAWRX/CH_N +#define CH_N 5 +#define SAMP_N 200 +#define BYTES_TX_N 5 //Numero de bytes por paquete de transmision + +static const char *device = "/dev/spidev0.0"; +static uint8_t mode = 3; +static uint8_t bits = 8; +static uint32_t speed = 16000000; +static uint16_t delay; + +volatile uint8_t tx[ARRAY_SIZE]; +volatile uint8_t rx[ARRAY_SIZE] = {0, }; + +volatile int cont_seg=0, cont_min=0; +static int timeset_min = 2; + +static int inicializa_spi(int *fd); +static void transfer(int *fd); +static void pabort(const char *s); + +char station[]="JICAMARCA"; +char magnetometer[]="MAG_VIRT"; +char IAGA[]="JIC"; + +static double ScaleH=2.5; +static double ScaleD=2.5; +static double ScaleZ=2.5; +static double OffsetH=0.0; +static double OffsetD=0.0; +static double OffsetZ=0.0; +static double OffsetTs=0.0; +static double OffsetTc=0.0; +static double LBaseH=25750; +static double LBaseD=-1.4; +static double LBaseZ=350; +static double Hmean=25500; +static double Dmean=-1.4; +static double Zmean=365; +static char pathserver[75] = "test_cwd"; +static char filesminm[255]; +static char filessec[255]; + +static FILE *fp=NULL; +static FILE *fp_mv=NULL; +static FILE *fp_mm=NULL; +static FILE *fzip=NULL; + +double mvX,mvY,mvZ; + +void crear_archivo_sec(FILE** fp,long promedios[CH_N]); +void crear_archivo_minv(FILE** fp,long promedios[CH_N]); +void crear_archivo_minm(FILE** fp); + +void format_time(char *output); +int obtiene_minuto(void); +int obtiene_segundo(void); + + +int open_serial(int *serial_stram); +void* read_uart(void *argv); +int encuentra_fincadena(char *cadena); + +void encuentra_promedios(uint8_t ARRAY[ARRAY_RAWRX_N], long prom[CH_N], int num_ch); + +struct ROJ_GPRMC { + char header[4]; + char gps_time[6]; + char gps_valid; + char gps_lat[9]; + char gps_lathem; + char gps_long[10]; + char gps_longhem; + char gps_spd_grd[5]; + char gps_cour_grd[5]; + char gps_date[6]; + char gps_magvar[5]; + char gps_maghem; +}; + +void encontrar_hora(char *cad_original, struct ROJ_GPRMC *estructura); +void encontrar_fecha(char *cad_original, struct ROJ_GPRMC *estructura); +void encontrar_campo(char *cad_original, char *campo, int pos_campo, int lon_campo); + +void parse_date(char *hora, char *fecha,char *comando); +void parse_anho(char *p_anho, char *fecha); +void parse_mes(char *p_mes, char *fecha); +void parse_hora(char *p_hora, char *hora); + +int main(int argc, char ** argv) { + + pthread_t thread; + int ret, status,i; + errno = 0; + + sleep(1); + + ret = pthread_create(&thread, NULL, read_uart,&i); + + if(ret){ + printf("\npthread_create() failed with errir [%s]\n", strerror(errno)); + return -1; + } + + char c = getchar(); + status = pthread_cancel(thread); + + if (status){ + printf("\npthread_cancel() failed with error [%s]\n", strerror(errno)); + return -1; + } + //----- CLOSE THE UART ----- + return 0; +} + +int open_serial(int *serial_stream){ + int status=0; + + *serial_stream = open("/dev/ttyAMA0", O_RDWR | O_NOCTTY | O_NONBLOCK | O_NDELAY); //Open in non blocking read/write mode + if (*serial_stream == -1){ + printf("Error - Unable to open UART. Ensure it is not in use by another application\n"); + } + + struct termios options; + fcntl(*serial_stream,F_SETFL, O_RDWR); + if(tcgetattr(*serial_stream, &options)<0){ + perror("Getting configuration.\n"); + return -1; + } + printf("Valor de options al leer el valor por defecto:%d\n",(int)options.c_cflag); + cfmakeraw (&options) ; + cfsetispeed(&options, B9600); + cfsetospeed(&options, B9600); + options.c_oflag &= ~OPOST; + options.c_lflag &= ~(ICANON | ECHO | ECHOE | ISIG); + + options.c_cc[VMIN] = 100; //Timeout en décimas de segundo + options.c_cc[VTIME] = 70; // Número de caracteres recibidos + + options.c_cflag &= ~PARENB; + options.c_cflag &= ~CSTOPB; + options.c_cflag &= ~CSIZE; + options.c_cflag |= CS8; + options.c_cflag |= (CLOCAL | CREAD); + + printf("Valor de CS8: %d\n",CS8); + printf("Valor de options: %d.\n",(int)(options.c_cflag)); + + tcflush(*serial_stream, TCIFLUSH); + if(tcsetattr(*serial_stream, TCSANOW | TCSAFLUSH, &options) < 0){ + printf("Error al escribir el uart0_filestream.\n"); + return -1; + } + + ioctl (*serial_stream, TIOCMGET, &status); + + status |= TIOCM_DTR ; + status |= TIOCM_RTS ; + + ioctl (*serial_stream, TIOCMSET, &status); + + usleep (10000) ; // 10mS + + return 0; +} + +void* read_uart(void *argv){ + int length; + int uart0_filestream; + + struct ROJ_GPRMC estr_roj_gprmc_01; + int fd; + if(inicializa_spi(&fd) !=0){ + + printf("Problemas al abrir el archivo de lecctura/escritura SPI.\n"); + }; + + errno = 0; + pthread_setcancelstate(PTHREAD_CANCEL_ENABLE, NULL); + ///////////////////////////////////////// + + if (open_serial(&uart0_filestream) != 0) + { + printf("Problemas al abrir el archivo de lecctura/escritura serial.\n"); + return; + } + + char rx_buffer[4096]; + char arma_buffer[80]; + + char comando_3[42]; + strcpy(comando_3,"sudo date -s "); + + int cont_fin = 0; + for(cont_fin=0; cont_fin<80;cont_fin++){ + arma_buffer[cont_fin]='\0'; + } + + int rx_length_2 = 0; + int rx_length_1 = 0; + int sincronizado = 0; + /////////////////////////////////////////// + + while(1){ + pthread_testcancel(); + + //----- CHECK FOR ANY RX BYTES ----- + if ((uart0_filestream) != -1) + { + + ioctl ((uart0_filestream), FIONREAD, &rx_length_2); + //printf("Datos disponibles a leer por iotctl: %d\n", rx_length_2); + rx_length_1 = read((uart0_filestream), (void *)(rx_buffer),70); //Filestream, buffer to store in, number of bytes to read (max) + //printf("Datos disponibles a leer por read: %d\n", rx_length_1); + + + + + if (rx_length_1 < 0) + { + printf("No data o menor a 0.\n"); + close((uart0_filestream)); + if (open_serial(&uart0_filestream) != 0) + { + printf("Problemas al abrir el archivo de lecctura/escritura serial.\n"); + } + + } + else if (rx_length_1 == 0) + { + printf("No data.\n"); + close((uart0_filestream)); + if (open_serial(&uart0_filestream) != 0) + { + printf("Problemas al abrir el archivo de lectura/escritura serial.\n"); + } + + } + else + { + + //Bytes received + rx_buffer[rx_length_1] = '\0'; + + if(sincronizado == 0) + { + + if(rx_buffer[0] != '$') + { + close((uart0_filestream)); + if (open_serial(&uart0_filestream) != 0) + { + printf("Problemas al abrir el archivo de lectura/escritura serial.\n"); + return; + //return -1; + } + printf("No se recibio el caracter inicial.\n"); + tcflush((uart0_filestream), TCIFLUSH); + usleep (10000) ; // 10mS + continue; + } + printf("Sincronizacion de recepcion OK.\n"); + sincronizado = 1; + + } + + + //printf("%i bytes read : %s\n", rx_length_1, rx_buffer); + if(encuentra_fincadena(rx_buffer)==0){ + //printf("Check state.\n"); + //printf("Check state strlen_1: %d.\n", strlen(arma_buffer)); + arma_buffer[strlen(arma_buffer)] = '\0'; + //printf("Check state 2.\n"); + //printf("Check state strlen_2: %d.\n", strlen(arma_buffer)); + + strcpy((arma_buffer+strlen(arma_buffer)),rx_buffer); + arma_buffer[strlen(arma_buffer)] = '\0'; + + //printf("Cadena recibida final: %s.\n",arma_buffer); + arma_buffer[0] = '\0'; + //printf("************************\n"); + + //printf("%i bytes read : %s\n", rx_length_1, rx_buffer); + //printf("************************\n"); + + //Actualización de hora cada segundo + encontrar_hora(rx_buffer, &estr_roj_gprmc_01); + encontrar_fecha(rx_buffer, &estr_roj_gprmc_01); + //char comando_3[41]; + parse_date(((&estr_roj_gprmc_01)->gps_time), ((&estr_roj_gprmc_01)->gps_date),comando_3); + //printf("***************************\n"); + //printf("Comando_3 generado: %s.\n",comando_3); + //printf("***************************\n"); + system(comando_3); //La marca de hora estará dado por la hora en este punto + transfer(&fd); + } + else{ + strcpy(arma_buffer,rx_buffer); + arma_buffer[strlen(arma_buffer)] = '\0'; + printf("Cadena recibida hasta el momento: %s.\n",arma_buffer); + //printf("Bytes recibidos todavia sin fin de cadena.\n"); + } + //printf("Check state strlen_fin_main: %d.\n", strlen(arma_buffer)); + printf("Hola Luis este es el fin de la iteracion en el programa.\n"); + + + + if(rx_length_1 >= 70) + { + sincronizado = 0; + } + } + } + } + printf("\r\n"); + close(uart0_filestream); + close(fd); +} + +int encuentra_fincadena(char *cadena){ + int i_fin=0, longitud_cadena=0; + longitud_cadena = strlen(cadena); + //printf("\n**************************"); + //printf("\nTamanho de cadena: %d\n", longitud_cadena); + while((i_fin++=longitud_cadena) + { + //printf("No se encuentra el caracter fin de cadena.\n"); + //printf("**************************\n"); + return 1; + }else + { + //printf("Posicion encontrada del fin de cadena = %d\n", (i_fin+1)); + } + //printf("**************************\n"); + + return 0; +} + +void parse_date(char *hora, char *fecha,char *comando){ + char p_dia[3]; + char p_mes[3]; + char p_anho[5]; + char p_hora[9]; + int i=0; + + p_anho[0] = '2'; + p_anho[1] = '0'; + p_anho[4] = '\0'; + + p_dia[2] = '\0'; + p_dia[1] = fecha[1]; + p_dia[0] = fecha[0]; + + p_hora[8] = '\0'; + + parse_anho(p_anho, fecha); + parse_mes(p_mes, fecha); + + parse_hora(p_hora, hora); + + //printf("Dia parseado: %s\n", p_dia); + //printf("Mes parseado: %s\n", p_mes); + //printf("Anho parseado: %s\n", p_anho); + //printf("Hora parseado: %s\n", p_hora); + + comando[0+13] = '"'; + comando[1+13] = p_mes[0]; + comando[2+13] = p_mes[1]; + comando[3+13] = p_mes[2]; + comando[4+13] = ' '; + + comando[5+13] = p_dia[0]; + comando[6+13] = p_dia[1]; + comando[7+13] = ' '; + + for(i=0;igps_time), 2,6); + //printf("Cadena de hora: %s.\n", (estructura->gps_time)); +} + +void encontrar_fecha(char *cad_original, struct ROJ_GPRMC *estructura){ + // + encontrar_campo(cad_original, (estructura->gps_date), 10,6); + //printf("Cadena de tiempo: %s.\n", (estructura->gps_date)); +} + +void encontrar_campo(char *cad_original, char *campo, int pos_campo, int lon_campo){ + int i,i_comas=0,coma_1=0, coma_2=0; + //printf("Cadena detectada: %s", cad_original); + while(i_comas<(pos_campo-1)){ + while(cad_original[coma_1++] !=','){ + }; + i_comas++; + }; + coma_1--; + while(cad_original[coma_1+coma_2+1] !=','){ + coma_2++; + }; + coma_2 +=coma_1; + + //printf("Posicion coma_1: %d\tPosicion coma 2:%d\n",coma_1,coma_2); + if((coma_2-coma_1)>1){ + for(i=0;itm_sec) == 59){ + for(i=0;itm_sec) == 5){ + //Envio archivo min_m: + strcpy(comando_bash,"python /home/pi/Desktop/Scripts/src_c/uart_files_sockets_fus/src_dev/py_aux/SendfileFTP.py "); + strcat(comando_bash,pathserver); + strcat(comando_bash," "); + strcat(comando_bash,filesminm); + strcat(comando_bash," &"); + printf("CMD:%s\n",comando_bash); + fzip = popen(comando_bash,"r"); + while (fgets( buffer_zip, sizeof(buffer_zip), fzip)){ + } + pclose(fzip); + cont_min = 0; + } + } + + int len; + char outzip[255]; + + if((timeinfo->tm_min) == 03){ + if((timeinfo->tm_sec) == 30){ + strcpy(outzip,filessec); + len = strlen(outzip); + outzip[len] = 'z'; + outzip[len+1] = 'i'; + outzip[len+2] = 'p'; + outzip[len+3] = '\0'; + + strcpy(comando_bash,"gzip -c "); + strcat(comando_bash,filessec); + strcat(comando_bash," > "); + strcat(comando_bash,outzip); + strcat(comando_bash," &"); + printf("CMD:%s\n",comando_bash); + fzip = popen(comando_bash,"r"); + while (fgets( buffer_zip, sizeof(buffer_zip), fzip)){ + } + pclose(fzip); + } + + if((timeinfo->tm_sec) == 50){ + //Envio archivo comprimido + strcpy(comando_bash,"python /home/pi/Desktop/Scripts/src_c/uart_files_sockets_fus/src_dev/py_aux/SendfileFTP.py "); + strcat(comando_bash,pathserver); + strcat(comando_bash," "); + strcat(comando_bash,outzip); + strcat(comando_bash," &"); + printf("CMD:%s\n",comando_bash); + fzip = popen(comando_bash,"r"); + while (fgets( buffer_zip, sizeof(buffer_zip), fzip)){ + } + pclose(fzip); + + strcpy(outzip,filessec); + len = strlen(outzip); + outzip[len] = 'z'; + outzip[len+1] = 'i'; + outzip[len+2] = 'p'; + outzip[len+3] = '\0'; + + } + + } + + fflush(stdout); + puts(""); +} + +void encuentra_promedios(uint8_t ARRAY[ARRAY_RAWRX_N], long prom[CH_N], int num_ch){ + char dato_cadena[7]; + memset(dato_cadena,'\0',7); + + int i=0, j=0; + long result=0; + for(j=0; j32767)?(-65536):0); + } + result = result/SAMP_N; + prom[j] = result; + result = 0; + } +} + +void pabort(const char *s){ + perror(s); + abort(); +} + +void format_time(char *output){ + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + sprintf(output, "[%s%03d%02d.%02ds]",IAGA,timeinfo->tm_yday, timeinfo->tm_hour,timeinfo->tm_year-100); +} + +void format_time_minv(char *output){ + time_t rawtime; + struct tm * timeinfo; + //int i= 0; + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + char buffer[5]; + strftime (buffer,5,"%b",timeinfo); + //for(i=0;buffer[i];i++){ + //buffer[0] = tolower(buffer[0]); + buffer[0] = 32+buffer[0]; + sprintf(output, "[%s%02d%s.%02dv]",IAGA,timeinfo->tm_mday, buffer,timeinfo->tm_year-100); +} + +void format_time_minm(char *output){ + time_t rawtime; + struct tm * timeinfo; + //int i=0; + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + char buffer[5]; + strftime (buffer,5,"%b",timeinfo); + //for(i=0;buffer[i];i++){ + //buffer[0] = tolower(buffer[0]); + buffer[0] = 32+buffer[0]; + sprintf(output, "[%s%02d%s.%02dm]",IAGA,timeinfo->tm_mday, buffer,timeinfo->tm_year-100); +} + +int obtiene_segundo(void){ + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + return timeinfo->tm_sec; +} + +int obtiene_minuto(void){ + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + return timeinfo->tm_min; +} + +void crear_archivo_sec(FILE** fp,long promedios[CH_N]){ + char cadena_hora[256]; + //static char cadena_hora_2[256]=""; + + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + format_time(cadena_hora); + strcpy(filessec,cadena_hora); + + fflush(stdout); + + *((FILE**)fp) = fopen( cadena_hora,"a"); + /* + if(strcmp(cadena_hora, cadena_hora_2)!=0){ + if(*((FILE**)fp) != NULL) + fclose(*((FILE**)fp)); + strcpy(cadena_hora_2, cadena_hora); + *((FILE**)fp) = fopen( cadena_hora,"a"); + } + */ + fseek(*((FILE**)fp), 0, SEEK_END); + if((ftell(*((FILE**)fp)))==0){ + fprintf(*((FILE**)fp),"%s %s <%d> 1 Sec. Raw data\n\n",station,magnetometer,timeinfo->tm_yday); + fprintf(*((FILE**)fp),"HH MM SS channel(H) channel(D) channel(D) channel(Ts) channel(Tc)\n\n"); + fflush(stdout); + } + + fprintf(*((FILE**)fp),"%02d %02d %02d ",timeinfo->tm_hour,timeinfo->tm_min,timeinfo->tm_sec); + fprintf(*((FILE**)fp),"%+08li %+08li %+08li %+08li %+08li\n",(promedios[0]/16),(promedios[1]/16),(promedios[2]/16),(promedios[3]/16),(promedios[4]/16)); + fflush(stdout); + fclose(*((FILE**)fp)); +} + +void crear_archivo_minv(FILE** fp,long datos[CH_N]){ + char cadena_hora[256]; + //static char cadena_hora_2[256]=""; + double mvT1, mvT2; + + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + format_time_minv(cadena_hora); + fflush(stdout); + + *((FILE**)fp) = fopen( cadena_hora,"a"); + + /* + if(strcmp(cadena_hora, cadena_hora_2)!=0){ + if(*((FILE**)fp) != NULL) + fclose(*((FILE**)fp)); + strcpy(cadena_hora_2, cadena_hora); + *((FILE**)fp) = fopen( cadena_hora,"a"); + } + */ + fseek(*((FILE**)fp), 0, SEEK_END); + + + + if((ftell(*((FILE**)fp)))==0){ + printf("%s\n",cadena_hora); + fflush(stdout); + fprintf(*((FILE**)fp),"%s %s <%03d> 1 Min. Reported data\n\n",station,magnetometer,timeinfo->tm_yday); + fprintf(*((FILE**)fp)," DD MM YYYY HH MM H(mv) D(mv) Z(mv) Ts(mv) Tc(mv)\n\n"); + fflush(stdout); + } + + mvX = (datos[0]/8388607.0)*2500.0 - OffsetH; + mvY = (datos[1]/8388607.0)*2500.0 - OffsetD; + mvZ = (datos[2]/8388607.0)*2500.0 - OffsetZ; + mvT1 = (datos[3]/8388607.0)*2500.0 - OffsetTs; + mvT2 = (datos[4]/8388607.0)*2500.0 - OffsetTc; + + fprintf(*((FILE**)fp),"%02d %02d %04d %02d %02d ",timeinfo->tm_mday, timeinfo->tm_mon + 1, timeinfo->tm_year + 1900,timeinfo->tm_hour,timeinfo->tm_min); + fprintf(*((FILE**)fp),"%+09.3f %+09.3f %+09.3f %+09.3f %+09.3f\n",mvX,mvY,mvZ,mvT1,mvT2); + + fflush(stdout); + fclose(*((FILE**)fp)); +} + +void crear_archivo_minm(FILE** fp){ + char cadena_hora[256]; + //static char cadena_hora_2[256]=""; + double datachannelX,datachannelY,datachannelZ,datachannelI,datachannelF; + + time_t rawtime; + struct tm * timeinfo; + + time ( &rawtime ); + timeinfo = localtime ( &rawtime ); + + format_time_minm(cadena_hora); + strcpy(filesminm,cadena_hora); + + fflush(stdout); + + *((FILE**)fp) = fopen( cadena_hora,"a"); + /* + if(strcmp(cadena_hora, cadena_hora_2)!=0){ + if(*((FILE**)fp) != NULL) + fclose(*((FILE**)fp)); + strcpy(cadena_hora_2, cadena_hora); + *((FILE**)fp) = fopen( cadena_hora,"a"); + } + */ + fseek(*((FILE**)fp), 0, SEEK_END); + if((ftell(*((FILE**)fp)))==0){ + fprintf(*((FILE**)fp),"%s %s <%03d> 1 Min. Reported data\n\n",station,magnetometer,timeinfo->tm_yday); + fprintf(*((FILE**)fp)," DD MM YYYY HH MM D(Deg) H(nt) Z(nt) I(Deg) F(nt)\n\n"); + fflush(stdout); + } + + datachannelX = LBaseH + mvX/ScaleH; + datachannelY = LBaseD + (mvY/ScaleD)*(3438/(Hmean*60)); + datachannelZ = LBaseZ + mvZ/ScaleZ; + datachannelI = atan2(datachannelZ,datachannelX)*((double)1/3.1416); + datachannelF = sqrt(pow(datachannelX,(double)2) + pow(datachannelZ,(double)2)); + + fprintf(*((FILE**)fp),"%02d %02d %04d %02d %02d ",timeinfo->tm_mday, timeinfo->tm_mon + 1, timeinfo->tm_year + 1900,timeinfo->tm_hour,timeinfo->tm_min); + fprintf(*((FILE**)fp),"%+08.4f %+08.1f %+08.1f %+08.4f %+08.1f\n",datachannelY,datachannelX,datachannelZ,datachannelI,datachannelF); + fflush(stdout); + fclose(*((FILE**)fp)); +} + +/* +void crea_archivo(FILE** fp, int dato){ + char cadena_hora[256]; + static char cadena_hora_2[256]=""; + format_time(cadena_hora); + //fflush(stdout); + + if(strcmp(cadena_hora, cadena_hora_2)!=0){ + if(*((FILE**)fp) != NULL) + fclose(*((FILE**)fp)); + strcpy(cadena_hora_2, cadena_hora); + *((FILE**)fp) = fopen( cadena_hora,"a"); + fprintf(*((FILE**)fp), "This is testing for fprintf %s Dato: %02x...\n", cadena_hora,dato); + fflush(stdout); + } + else{ + fprintf((*((FILE**)fp)), "This is testing for fprintf %s Dato: %02x...\n", cadena_hora,dato); + fflush(stdout); + } +} +*/ Index: trunk/firmware/sources/Integration/Storage&Communication/ForTestRX/spidev_test_deterr_v03.c =================================================================== diff --git a/trunk/firmware/sources/Integration/Storage&Communication/ForTestRX/spidev_test_deterr_v03.c b/trunk/firmware/sources/Integration/Storage&Communication/ForTestRX/spidev_test_deterr_v03.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/Storage&Communication/ForTestRX/spidev_test_deterr_v03.c (revision 224) @@ -0,0 +1,294 @@ +/* + * SPI testing utility (using spidev driver) + * + * Copyright (c) 2007 MontaVista Software, Inc. + * Copyright (c) 2007 Anton Vorontsov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License. + * + * Cross-compile with cross-gcc -I/path/to/cross-kernel/include + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +static void pabort(const char *s) +{ + perror(s); + abort(); +} + +static const char *device = "/dev/spidev0.0"; +static uint8_t mode = 3; +static uint8_t bits = 8; +static uint32_t speed = 8000000; +static uint16_t delay; + +static void transfer(int fd) +{ + int ret; + int i; + uint8_t tx[2500]; + uint8_t rx[ARRAY_SIZE(tx)] = {0, }; + struct spi_ioc_transfer tr = { + .tx_buf = (unsigned long)tx, + .rx_buf = (unsigned long)rx, + .len = ARRAY_SIZE(tx), + .delay_usecs = delay, + .speed_hz = speed, + .bits_per_word = bits, + }; + for ( i=0; i < 2500; i++) { + tx[i] = 0x63; + } + int j=0; + long long cont3=0; + long long cont3total=0; + clock_t t1 = clock(); + long long conterrores=0; + for ( i=0; i < 2; ) { + cont3=0; + ret = ioctl(fd, SPI_IOC_MESSAGE(1), &tr); + for(j=0;j<2500;j++){ + if(rx[j]==98){ + if(rx[j+1]!=156){ + printf("%02X\n",rx[j]); + printf("%02X\n",rx[j+1]); + printf("%02X\n",rx[j+2]); + printf("%02X\n",rx[j+3]); + while(1){ + printf("ERROR."); + while(1){ + sleep(1); + } + } + cont3++;} + } + cont3total++; + //if(rx[j]==98||rx[j]==129||rx[j]==130||rx[j]==131||rx[j]==132) printf("%02X\n",rx[j]); + //if(rx[j]==98){ + // if(rx[j+1]!=129){ + // if(rx[j+1]!=127){ + // conterrores++; + // printf("%02X\n",rx[j+1]); + // } + // cont3++; + // } + // + //} + + //if(rx[j]==98||rx[j]==36||rx[j]=='M'||rx[j]=='m'||rx[j]=='Y'||rx[j]=='h'){ + // if(cont3>4){ + // printf("Error en la TX.\n"); + // printf("%02X\n",rx[j-4]); + // printf("%02X\n",rx[j-3]); + // printf("%02X\n",rx[j-2]); + // printf("%02X\n",rx[j-1]); + // } + + // cont3=0; + //cont3total++; + //printf("%02X\n",rx[j]); + + //} + //if(rx[j]!=0){ + // cont3++; + //} + + //if(cont3==5){ + // if(rx[j]!=98){ + // //if(rx[j]==18){ + // printf("Error de TX:\n"); + // printf("%02X\n",rx[j-1]); + // printf("%02X\n",rx[j]); + // conterrores++; + + + // } + + //} + //else{ + // if(cont3>5 && rx[j]!=0) + // printf("%02X\n",rx[j]); + //} + + //else{ + // if(cont3>4) + // printf("Error de envio.\n"); + // cont3=0; + //} + + } + if (cont3!=0) + printf("Numero de paquetes: %lld\n",cont3); + sleep(1); + printf("Fin de espera\n"); + } + + clock_t t2 = clock(); + printf("The time taken is..t1=%G...t2=%G... (t2-t1)=%G...(t2-t1)/CLOCKS_PER_SEC=%G...CLOCKS_PER_SEC=%G...Per byte(us) = %G", (double)(t1), (double)(t2),(double)(t2-t1),(double)(t2-t1)/CLOCKS_PER_SEC,(double)CLOCKS_PER_SEC,(double)(t2-t1)*1000000/(CLOCKS_PER_SEC*(double)(4096*768))); + printf("\ncontador cont3total= %lld",cont3total); + printf("\ncontador de bytes con valores distintos de cero=%lld",cont3); + printf("\nContador errores= %lld",conterrores); + if (ret < 1) + pabort("can't send spi message"); + + //for (ret = 0; ret < ARRAY_SIZE(tx); ret++) { + // if (!(ret % 6)) + // puts(""); + // printf("%.2X ", rx[ret]); + //} + puts(""); +} + +static void print_usage(const char *prog) +{ + printf("Usage: %s [-DsbdlHOLC3]\n", prog); + puts(" -D --device device to use (default /dev/spidev1.1)\n" + " -s --speed max speed (Hz)\n" + " -d --delay delay (usec)\n" + " -b --bpw bits per word \n" + " -l --loop loopback\n" + " -H --cpha clock phase\n" + " -O --cpol clock polarity\n" + " -L --lsb least significant bit first\n" + " -C --cs-high chip select active high\n" + " -3 --3wire SI/SO signals shared\n"); + exit(1); +} + +static void parse_opts(int argc, char *argv[]) +{ + while (1) { + static const struct option lopts[] = { + { "device", 1, 0, 'D' }, + { "speed", 1, 0, 's' }, + { "delay", 1, 0, 'd' }, + { "bpw", 1, 0, 'b' }, + { "loop", 0, 0, 'l' }, + { "cpha", 0, 0, 'H' }, + { "cpol", 0, 0, 'O' }, + { "lsb", 0, 0, 'L' }, + { "cs-high", 0, 0, 'C' }, + { "3wire", 0, 0, '3' }, + { "no-cs", 0, 0, 'N' }, + { "ready", 0, 0, 'R' }, + { NULL, 0, 0, 0 }, + }; + int c; + + c = getopt_long(argc, argv, "D:s:d:b:lHOLC3NR", lopts, NULL); + + if (c == -1) + break; + + switch (c) { + case 'D': + device = optarg; + break; + case 's': + speed = atoi(optarg); + break; + case 'd': + delay = atoi(optarg); + break; + case 'b': + bits = atoi(optarg); + break; + case 'l': + mode |= SPI_LOOP; + break; + case 'H': + mode |= SPI_CPHA; + break; + case 'O': + mode |= SPI_CPOL; + break; + case 'L': + mode |= SPI_LSB_FIRST; + break; + case 'C': + mode |= SPI_CS_HIGH; + break; + case '3': + mode |= SPI_3WIRE; + break; + case 'N': + mode |= SPI_NO_CS; + break; + case 'R': + mode |= SPI_READY; + break; + default: + print_usage(argv[0]); + break; + } + } +} + +int main(int argc, char *argv[]) +{ + int ret = 0; + int fd; + + parse_opts(argc, argv); + + fd = open(device, O_RDWR); + if (fd < 0) + pabort("can't open device"); + + /* + * spi mode + */ + ret = ioctl(fd, SPI_IOC_WR_MODE, &mode); + if (ret == -1) + pabort("can't set spi mode"); + + ret = ioctl(fd, SPI_IOC_RD_MODE, &mode); + if (ret == -1) + pabort("can't get spi mode"); + + /* + * bits per word + */ + ret = ioctl(fd, SPI_IOC_WR_BITS_PER_WORD, &bits); + if (ret == -1) + pabort("can't set bits per word"); + + ret = ioctl(fd, SPI_IOC_RD_BITS_PER_WORD, &bits); + if (ret == -1) + pabort("can't get bits per word"); + + /* + * max speed hz + */ + ret = ioctl(fd, SPI_IOC_WR_MAX_SPEED_HZ, &speed); + if (ret == -1) + pabort("can't set max speed hz"); + + ret = ioctl(fd, SPI_IOC_RD_MAX_SPEED_HZ, &speed); + if (ret == -1) + pabort("can't get max speed hz"); + + printf("spi mode: %d\n", mode); + printf("bits per word: %d\n", bits); + printf("max speed: %d Hz (%d KHz)\n", speed, speed/1000); + + transfer(fd); + + close(fd); + + return ret; +} Index: trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsln =================================================================== diff --git a/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsln b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsln new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsln (revision 224) @@ -0,0 +1,20 @@ + +Microsoft Visual Studio Solution File, Format Version 11.00 +# Atmel Studio Solution File, Format Version 11.00 +Project("{18226A42-8477-4023-8AD2-40C49DA407C9}") = "time_engine_asm", "time_engine_asm\time_engine_asm.asmproj", "{594A91A5-03DC-4F7D-A86A-7F24849F6869}" +EndProject +Global + GlobalSection(SolutionConfigurationPlatforms) = preSolution + Debug|AVR = Debug|AVR + Release|AVR = Release|AVR + EndGlobalSection + GlobalSection(ProjectConfigurationPlatforms) = postSolution + {594A91A5-03DC-4F7D-A86A-7F24849F6869}.Debug|AVR.ActiveCfg = Debug|AVR + {594A91A5-03DC-4F7D-A86A-7F24849F6869}.Debug|AVR.Build.0 = Debug|AVR + {594A91A5-03DC-4F7D-A86A-7F24849F6869}.Release|AVR.ActiveCfg = Release|AVR + {594A91A5-03DC-4F7D-A86A-7F24849F6869}.Release|AVR.Build.0 = Release|AVR + EndGlobalSection + GlobalSection(SolutionProperties) = preSolution + HideSolutionNode = FALSE + EndGlobalSection +EndGlobal =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsuo =================================================================== diff --git a/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsuo b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsuo new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm.atsuo (revision 224) Index: trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.hex =================================================================== diff --git a/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.hex b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.hex new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.hex (revision 224) @@ -0,0 +1,61 @@ +:020000020000FC +:040000000C94AE00AE +:100064000C94C0001FEF0FEF12B901B9000005EFA7 +:1000740010E715B904B900000FEF10E007B918B97B +:1000840000000CEF1CEF1BB90AB900000EEC18ECD1 +:100094001EB90DB900001FEF0FEF11BB00BB00002C +:1000A4001FEF0FEF14BB03BB00001CEF0EEF109308 +:1000B40002010093010100001FEF0FEF10930501EF +:1000C4000093040100001FEF0FEF10930B01009346 +:1000D4000A0100001FEF0FEF1093080100930701BE +:1000E40000001CEF0EEF10930201009301010000C9 +:1000F400089507E610E00093C4001093C50008E1DA +:100104000093C00008E90093C10006E00093C20018 +:10011400089503E310E00093D4001093D50008E1A0 +:100124000093D00008E10093D10006E00093D200D0 +:100134000895AAE4B2E004E20D9307E40D9300E508 +:100144000D9302E50D930DE40D9303E40D930CE27E +:100154000D930DE20D9308950FEF0DBF01E20EBF55 +:1001640081DFC7DFD6DFE5DF0FEF08B9AAE4B2E02D +:10017400C0E0D2E069D07894A895FECF0091C60083 +:100184001D911D3299F0011729F0AAE4B2E0C0E0F4 +:10019400D2E018950C3209F0189508B10F3F19F404 +:1001A400002708B918950FEF08B918951197099306 +:1001B4000D3009F01895AAE4B2E0C0E0D2E001D015 +:1001C40018950ED0C7E0D2E00881013429F408D094 +:1001D4000FEF00930B0108950EEF00930B010895A8 +:1001E40004E20AD002E508D00FE406D00AE404D001 +:1001F4000CE202D008D008951091D00015FFFCCF76 +:100204000093D6000895C0E0D2E009910D3011F0BA +:10021400F3DFFBCF01D00895E0E4F2E0FD1739F4F9 +:10022400EC1729F40DE0E8DF0AE0E6DF08950FE5B6 +:10023400E3DF2196F3CF0FEF1FEF1A9509F0FDCFFF +:100244000A9509F0F9CF0895A89500916000086116 +:10025400009360000EE000936000089508E4CCDF92 +:100264000FE6CADF0CE6C8DF01E6C6DF00E2C4DF42 +:100274000DE4C2DF05E7C0DF0EE6BEDF04E6BCDF47 +:100284000FE6BADF0DE0B8DF0AE0B6DF08E4B4DF5A +:100294000FE6B2DF0CE6B0DF01E6AEDF00E2ACDF72 +:1002A4000DE4AADF05E7A8DF0EE6A6DF04E6A4DF77 +:1002B4000FE6A2DF00E2A0DF0DE09EDF0AE09CDF94 +:1002C40008E49ADF0FE698DF0CE696DF01E694DF98 +:1002D40000E292DF0DE490DF05E78EDF0EE68CDFAF +:1002E40004E68ADF0FE688DF00E286DF0DE084DFC4 +:1002F4000AE082DF08E480DF0FE67EDF0CE67CDFC5 +:1003040001E67ADF00E278DF0DE476DF05E774DFEB +:100314000EE672DF04E670DF0FE66EDF00E26CDFEC +:100324000DE06ADF0AE068DF08E466DF0FE664DFF9 +:100334000CE662DF01E660DF00E25EDF0DE45CDF15 +:1003440005E75ADF0EE658DF04E656DF0FE654DF12 +:1003540000E252DF0DE050DF0AE04EDF08E44CDF3C +:100364000FE64ADF0CE648DF01E646DF00E244DF41 +:100374000DE442DF05E740DF0EE63EDF04E63CDF46 +:100384000FE63ADF00E238DF0DE036DF0AE034DF63 +:1003940008E432DF0FE630DF0CE62EDF01E62CDF67 +:1003A40000E22ADF0DE428DF05E726DF0EE624DF7E +:1003B40004E622DF0FE620DF0DE01EDF0AE01CDF8B +:1003C40008E41ADF0FE618DF0CE616DF01E614DF97 +:1003D40000E212DF0DE410DF05E70EDF0EE60CDFAE +:1003E40004E60ADF0FE608DF0DE006DF0AE004DFBB +:1003F40003E202DF0DE000DF0AE0FEDE1CDF089509 +:00000001FF Index: trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.lss =================================================================== diff --git a/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.lss b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.lss new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/Debug/time_engine_asm.lss (revision 224) @@ -0,0 +1,2654 @@ + +AVRASM ver. 2.1.57 C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm Tue May 24 14:25:38 2016 + +[builtin](2): Including file 'C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR Assembler\Native\2.1.1175\avrassembler\Include\m2560def.inc' + + /* + + ;***** Created: 2011-02-09 12:03 ******* Source: ATmega2560.xml ********** + ;************************************************************************* + ;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y + ;* + ;* Number : AVR000 + ;* File Name : "m2560def.inc" + ;* Title : Register/Bit Definitions for the ATmega2560 + ;* Date : 2011-02-09 + ;* Version : 2.35 + ;* Support E-mail : avr@atmel.com + ;* Target MCU : ATmega2560 + ;* + ;* DESCRIPTION + ;* When including this file in the assembly program file, all I/O register + ;* names and I/O register bit names appearing in the data book can be used. + ;* In addition, the six registers forming the three data pointers X, Y and + ;* Z have been assigned names XL - ZH. Highest RAM address for Internal + ;* SRAM is also defined + ;* + ;* The Register names are represented by their hexadecimal address. + ;* + ;* The Register Bit names are represented by their bit number (0-7). + ;* + ;* Please observe the difference in using the bit names with instructions + ;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc" + ;* (skip if bit in register set/cleared). The following example illustrates + ;* this: + ;* + ;* in r16,PORTB ;read PORTB latch + ;* sbr r16,(1< +0000db f009 breq fin_gprmc +0000dc 9518 reti + + fin_gprmc: +0000dd e4aa ldi XL, low(header_rmc) +0000de e0b2 ldi XH, high(header_rmc) +0000df e0c0 ldi YL, low(sgprmc) +0000e0 e0d2 ldi YH, high(sgprmc) +0000e1 d001 rcall eval_lock +0000e2 9518 reti + + eval_lock: +0000e3 d00e rcall envio_uart02 +0000e4 e0c7 ldi YL, low(sgprmc+7) //Posicion 7(LSB0) del dato válido o inválido en la trama GPRMC +0000e5 e0d2 ldi YH, high(sgprmc+7) +0000e6 8108 ld temp_1, Y +0000e7 3401 cpi temp_1, 0x41 //Comparacion A +0000e8 f429 brne deslock +0000e9 d008 rcall envio_uart02 +0000ea ef0f ldi temp_1, 0xFF //Enciende lock +0000eb 9300 010b sts PORTL, temp_1 +0000ed 9508 ret + deslock: +0000ee ef0e ldi temp_1, 0xFE //Apaga lock +0000ef 9300 010b sts PORTL, temp_1 +0000f1 9508 ret + + envio_uart02: + //Envio Cabecera $ROJ +0000f2 e204 ldi temp_1,0x24 //$ +0000f3 d00a rcall wr_uart2 +0000f4 e502 ldi temp_1,0x52 //R +0000f5 d008 rcall wr_uart2 +0000f6 e40f ldi temp_1,0x4F //O +0000f7 d006 rcall wr_uart2 +0000f8 e40a ldi temp_1,0x4A //J +0000f9 d004 rcall wr_uart2 +0000fa e20c ldi temp_1,',' //J +0000fb d002 rcall wr_uart2 +0000fc d008 rcall envio_tabla_gprmc +0000fd 9508 ret + + wr_uart2: +0000fe 9110 00d0 lds temp_2, UCSR2A +000100 ff15 sbrs temp_2, UDRE2 +000101 cffc rjmp wr_uart2 +000102 9300 00d6 sts UDR2, temp_1 +000104 9508 ret + + envio_tabla_gprmc: +000105 e0c0 ldi YL, low(sgprmc) //Posicion 7(LSB0) del dato válido o inválido en la trama GPRMC +000106 e0d2 ldi YH, high(sgprmc) + cont_uart2: +000107 9109 ld temp_1,Y+ +000108 300d cpi temp_1, 0x0D // +000109 f011 breq fin_tabla_gprmc +00010a dff3 rcall wr_uart2 +00010b cffb rjmp cont_uart2 + fin_tabla_gprmc: +00010c d001 rcall completa_uart2 +00010d 9508 ret + + completa_uart2: +00010e e4e0 ldi ZL,low(sgprmc+64) +00010f e0f2 ldi ZH,high(sgprmc+64) + eval_uart2: +000110 17fd cp ZH, YH +000111 f439 brne envia_rell_uart2 +000112 17ec cp ZL, YL +000113 f429 brne envia_rell_uart2 +000114 e00d ldi temp_1,0x0D +000115 dfe8 rcall wr_uart2 +000116 e00a ldi temp_1,0x0A +000117 dfe6 rcall wr_uart2 +000118 9508 ret + envia_rell_uart2: +000119 e50f ldi temp_1, '_' +00011a dfe3 rcall wr_uart2 +00011b 9621 adiw YL,1 +00011c cff3 rjmp eval_uart2 + + delay_intwr: +00011d ef0f ldi temp_1, 255 + recarga_temp_2: +00011e ef1f ldi temp_2, 255 + dec_temp_2: +00011f 951a dec temp_2 +000120 f009 breq dec_temp_1 +000121 cffd rjmp dec_temp_2 + dec_temp_1: +000122 950a dec temp_1 +000123 f009 breq fin_delay_intwr +000124 cff9 rjmp recarga_temp_2 + fin_delay_intwr: +000125 9508 ret + + wdt_ini: +000126 95a8 wdr +000127 9100 0060 lds temp_1, WDTCSR +000129 6108 ori temp_1, (1< + 2.1.57 + "ATmega2560" + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\Debug + + C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR Assembler\Native\2.1.1175\avrassembler\Include + C:\Program Files (x86)\Atmel\AVR Tools\AvrAssembler2\Appnotes + + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm + + C:\Program Files (x86)\Atmel\Atmel Toolchain\AVR Assembler\Native\2.1.1175\avrassembler\Include\m2560def.inc + + + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\Debug/time_engine_asm.obj + + + time_engine_asm.hex + + + time_engine_asm.map + time_engine_asm.lss + + + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm14 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm15 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm186 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm212 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm29 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm119 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm134 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm158 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm349 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm203 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm249 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm226 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm231 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm244 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm256 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm264 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm280 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm275 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm295 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm302 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm305 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm311 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm315 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm318 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm328 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm334 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm336 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm338 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm342 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm346 + C:\Users\Francisco\Documents\Atmel Studio\6.2\MEGA2569_UART\time_engine_asm\time_engine_asm\time_engine_asm.asm357 + + Index: trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/time_engine_asm.asm =================================================================== diff --git a/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/time_engine_asm.asm b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/time_engine_asm.asm new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Integration/TimeEngine/MEGA2569_UART/time_engine_asm/time_engine_asm/time_engine_asm.asm (revision 224) @@ -0,0 +1,758 @@ +/* + * time_engine_asm.asm + * + * Created: 15/03/16 10:13:18 + * Author: Francisco + */ + +.equ f_cpu = 8000000 +.def temp_1 = R16 +.def temp_2 = R17 + +.dseg +.equ size_of_gprmc = 74 +sgprmc: .byte size_of_gprmc +header_rmc: .byte 8 + ;.db 0x24 ;$ + ;.db 0x47 ;G + ;.db 0x50 ;P + ;.db 0x52 ;R + ;.db 0x4D ;M + ;.db 0x43 ;C + ;.db 0x2C ;, + ;.db 0x2D ;- +.cseg +.org 0x0000 + jmp start +.org 0x0032 + jmp rx_subint +pin_conf_1: + + //Salidas al aire Puerto A + ldi temp_2, 0xFF + ldi temp_1, 0xFF + OUT PORTA, temp_2 + OUT DDRA, temp_1 + nop + + //Salidas al aire Puerto B + ldi temp_1, 0b11110101 + ldi temp_2, 0b01110000 + OUT PORTB, temp_2 + OUT DDRB, temp_1 + nop + + //Salidas AUX Puerto C + ldi temp_1, 0xFF + ldi temp_2, 0x00 + OUT DDRC, temp_1 + OUT PORTC,temp_2 + nop + + //Salidas PD1:SDA PD0:SCL Puerto D + ldi temp_1, 0b11111100 + ldi temp_2, 0b11111100 + OUT PORTD, temp_2 + OUT DDRD, temp_1 + nop + + //P7,P6,P3: Al aire -- PE5: bar_INVALID--PE4: PPS_IN--PE2: bar_EN_RS232--PE1:TX_RS232--PE0:RX_RS232 + ldi temp_1, 0b11001110 + ldi temp_2, 0b11001000 + OUT PORTE, temp_2 + OUT DDRE, temp_1 + nop + + //Salidas al aire Puerto F + ldi temp_2, 0xFF + ldi temp_1, 0xFF + OUT PORTF, temp_2 + OUT DDRF, temp_1 + nop + + //Salidas al aire Puerto G + ldi temp_2, 0xFF + ldi temp_1, 0xFF + OUT PORTG, temp_2 + OUT DDRG, temp_1 + nop + + + //Puertos al aire PORTH excepto PH1 Salida-UART2_TX y PH0 Entrada UART2_RX + ldi temp_2, 0b11111100 + ldi temp_1, 0b11111110 + STS PORTH, temp_2 + STS DDRH, temp_1 + nop + + //Salidas al aire Puerto J + ldi temp_2, 0xFF + ldi temp_1, 0xFF + STS PORTJ, temp_2 + STS DDRJ, temp_1 + nop + + //Salidas al aire Puerto L excepto PL7 + ldi temp_2, 0xFF + ldi temp_1, 0xFF + STS PORTL, temp_2 + STS DDRL, temp_1 + nop + + //Salidas Puerto K al GPS ENABLE que irá en tarjeta separada + //Salidas al PLL que está deshabilitado + ldi temp_2, 0xFF + ldi temp_1, 0xFF + STS PORTK, temp_2 + STS DDRK, temp_1 + nop + + //Puertos al aire PORTH excepto PH1 Salida-UART2_TX y PH0 Entrada UART2_RX + ldi temp_2, 0b11111100 + ldi temp_1, 0b11111110 + STS PORTH, temp_2 + STS DDRH, temp_1 + nop + + + ret +uart0_conf: + ldi temp_1,103 + ldi temp_2,0 + sts UBRR0L,temp_1 + sts UBRR0H,temp_2 + ldi temp_1,(0< + breq fin_gprmc + reti + +fin_gprmc: + ldi XL, low(header_rmc) + ldi XH, high(header_rmc) + ldi YL, low(sgprmc) + ldi YH, high(sgprmc) + rcall eval_lock + reti + +eval_lock: + rcall envio_uart02 + ldi YL, low(sgprmc+7) //Posicion 7(LSB0) del dato válido o inválido en la trama GPRMC + ldi YH, high(sgprmc+7) + ld temp_1, Y + cpi temp_1, 0x41 //Comparacion A + brne deslock + rcall envio_uart02 + ldi temp_1, 0xFF //Enciende lock + sts PORTL, temp_1 + ret +deslock: + ldi temp_1, 0xFE //Apaga lock + sts PORTL, temp_1 + ret + +envio_uart02: + //Envio Cabecera $ROJ + ldi temp_1,0x24 //$ + rcall wr_uart2 + ldi temp_1,0x52 //R + rcall wr_uart2 + ldi temp_1,0x4F //O + rcall wr_uart2 + ldi temp_1,0x4A //J + rcall wr_uart2 + ldi temp_1,',' //J + rcall wr_uart2 + rcall envio_tabla_gprmc + ret + +wr_uart2: + lds temp_2, UCSR2A + sbrs temp_2, UDRE2 + rjmp wr_uart2 + sts UDR2, temp_1 + ret + +envio_tabla_gprmc: + ldi YL, low(sgprmc) //Posicion 7(LSB0) del dato válido o inválido en la trama GPRMC + ldi YH, high(sgprmc) +cont_uart2: + ld temp_1,Y+ + cpi temp_1, 0x0D // + breq fin_tabla_gprmc + rcall wr_uart2 + rjmp cont_uart2 +fin_tabla_gprmc: + rcall completa_uart2 + ret + +completa_uart2: + ldi ZL,low(sgprmc+64) + ldi ZH,high(sgprmc+64) +eval_uart2: + cp ZH, YH + brne envia_rell_uart2 + cp ZL, YL + brne envia_rell_uart2 + ldi temp_1,0x0D + rcall wr_uart2 + ldi temp_1,0x0A + rcall wr_uart2 + ret +envia_rell_uart2: + ldi temp_1, '_' + rcall wr_uart2 + adiw YL,1 + rjmp eval_uart2 + +delay_intwr: + ldi temp_1, 255 +recarga_temp_2: + ldi temp_2, 255 +dec_temp_2: + dec temp_2 + breq dec_temp_1 + rjmp dec_temp_2 +dec_temp_1: + dec temp_1 + breq fin_delay_intwr + rjmp recarga_temp_2 +fin_delay_intwr: + ret + +wdt_ini: + wdr + lds temp_1, WDTCSR + ori temp_1, (1< + + + 2.0 + 6.2 + com.Atmel.AVRAssembler + {594a91a5-03dc-4f7d-a86a-7f24849f6869} + none + ATmega2560 + $(MSBuildProjectName) + .obj + $(MSBuildProjectDirectory)\$(Configuration) + ASSEMBLY + time_engine_asm + time_engine_asm + time_engine_asm + $(MSBuildProjectDirectory)\time_engine_asm.asm + Native + true + false + true + true + 0x20000000 + + true + exception_table + 2 + 0 + + + + + + + + + + + + + com.atmel.avrdbg.tool.atmelice + + + + 8000 + 200000 + + ISP + + com.atmel.avrdbg.tool.atmelice + J41800030896 + Atmel-ICE + + ISP + + + + + (%24IncludeFile) + + + Executable + + + + + (%24IncludeFile) + + + + + + Code + + + + \ No newline at end of file Index: trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.c =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.c b/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.c (revision 224) @@ -0,0 +1,78 @@ +// Code adapted from example by Gert van Loo & Dom +// Example code from: http://elinux.org/Rpi_Low-level_peripherals#C_2 + +// flashes (blinks) LED on Raspberry PI GPIO7 + +#define BCM2708_PERI_BASE 0x20000000 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */ + + +#include +#include +#include +#include +#include + +#define BLOCK_SIZE (4*1024) + +int mem_fd; +void *gpio_map; + +// I/O access +volatile unsigned *gpio; + + +// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y) +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) +#define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3)) +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) + +#define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0 +#define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0 +#define GET_GPIO(g) (*(gpio+13)&(1< bit is 1 <- port is HIGH=3.3V + { printf("Button pressed!\n"); + return 0; + } + else // port is LOW=0V + { printf("Button released!\n"); + return 1; + } +} + +// +// Set up a memory regions to access GPIO +// +void setup_io() +{ + /* open /dev/mem */ + printf("Inicio Setup.\n"); + if ((mem_fd = open("/dev/mem", O_RDWR|O_SYNC) ) < 0) { + printf("can't open /dev/mem \n"); + exit(-1); + } + + /* mmap GPIO */ + gpio_map = mmap( + NULL, //Any adddress in our space will do + BLOCK_SIZE, //Map length + PROT_READ|PROT_WRITE, // Enable reading & writting to mapped memory + MAP_SHARED, //Shared with other processes + mem_fd, //File to map + GPIO_BASE //Offset to GPIO peripheral + ); + + close(mem_fd); //No need to keep mem_fd open after mmap + + if (gpio_map == MAP_FAILED) { + printf("mmap error %d\n", (int)gpio_map); //errno also set! + exit(-1); + } + + // Always use volatile pointer! + gpio = (volatile unsigned *)gpio_map; +} // setup_io() + Index: trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.h =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.h b/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/gpio2_test.h (revision 224) @@ -0,0 +1,30 @@ + +#define BCM2708_PERI_BASE 0x20000000 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO controller */ + + +#include +#include +#include +#include +#include + +#define BLOCK_SIZE (4*1024) + +int mem_fd; +void *gpio_map; + +// I/O access +volatile unsigned *gpio; + + +// GPIO setup macros. Always use INP_GPIO(x) before using OUT_GPIO(x) or SET_GPIO_ALT(x,y) +#define INP_GPIO(g) *(gpio+((g)/10)) &= ~(7<<(((g)%10)*3)) +#define OUT_GPIO(g) *(gpio+((g)/10)) |= (1<<(((g)%10)*3)) +#define SET_GPIO_ALT(g,a) *(gpio+(((g)/10))) |= (((a)<=3?(a)+4:(a)==4?3:2)<<(((g)%10)*3)) + +#define GPIO_SET *(gpio+7) // sets bits which are 1 ignores bits which are 0 +#define GPIO_CLR *(gpio+10) // clears bits which are 1 ignores bits which are 0 +#define GET_GPIO(g) (*(gpio+13)&(1< +#include +#include +#include "./sr_clinit.h" +#include "./gpio2_test.h" + +#define False 1 +#define True 0 +#define pin 17 //GPIO[17] GPIOGEN(0) PIN11 P1 + +int main(int argc, char *argv[]) +{ + int pin_value = False; + time_t current_time; + int count = 0; + + setup_io(); + + if (argc != 4) + { + printf("Usage : %s \n", argv[0]); + return 1; + } + + // init GPIO[17] to be INPUT port + INP_GPIO(pin); + + while (1) + { + current_time = time(NULL); + pin_value = printButton(pin); + count ++; + printf("\n\n%s\n", ctime(¤t_time)); + printf("Work station call help [%d] time\n", count); + if (True == pin_value) + { + if (0 != socket_clinit_main(argc,argv)) + { + printf("cannot call help 1\n"); + return 1; + } + + } + else + { + if (0 != socket_clinit_main_2(argc,argv)) + { + printf("cannot call help 2\n"); + return 1; + } + } + sleep(5); + } +} Index: trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.c =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.c b/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.c new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.c (revision 224) @@ -0,0 +1,136 @@ +/* +Function : Socket code for clinit +Arthur : SheldonRush Peng +Date : 2013/7/26 +*/ + +#include +#include +#include +#include +#include +#include "sr_clinit.h" + +//char recvbuf_1[1024]; +//char recvbuf_2[1024]; + +int socket_clinit_main(int argc, char *argv[]) +{ + int sockfd = 0, n = 0; + char sendBuff[1024]; + + struct sockaddr_in serv_addr; + + if (argc != 4) + { + printf("Usage : %s \n", argv[0]); + return 1; + } + + if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + printf("Error : cannot create a socket\n"); + return 1; + } + memset(sendBuff, '\0', sizeof(sendBuff)); + + serv_addr.sin_family = AF_INET; + serv_addr.sin_port = htons(atoi(argv[2])); + + int test_inet = inet_pton(AF_INET, argv[1], &serv_addr.sin_addr); + if ( test_inet <= 0 ) + { + printf("Error inet: %d\n",test_inet); + printf("%s \n" , " Error : cannot convert text to ip binary"); + return 1; + } + //printf("%s",serv_addr.sin_addr); + + int test_connect = connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)); + if ( test_connect < 0 ) + { + printf("Error connect: %d\n",test_connect); + printf("Error : cannot connect server 1\n"); + return 1; + } + + printf("Clinit: Send data to server, station id = %d\n", atoi(argv[3])); + snprintf(sendBuff, sizeof(sendBuff), "Hola Luis. Soy la estacion [%d] y PIN11_GPIO=0 CERRADO \n", atoi(argv[3])); + printf("Clint: data is { %s }\n", sendBuff); + + write(sockfd, sendBuff, strlen(sendBuff)); + + //int iResult = recv(sockfd, recvbuf_1, sizeof(recvbuf_1)-1, 0); + + //if ( iResult > 0 ) + // printf("Bytes received: %d\n", iResult); + //else if ( iResult == 0 ) + // printf("Connection closed\n"); + //else + // printf("recv failed with error\n"); + + close(sockfd); + + return 0; +} + +int socket_clinit_main_2(int argc, char *argv[]) +{ + int sockfd = 0, n = 0; + char sendBuff[1024]; + + struct sockaddr_in serv_addr; + + if (argc != 4) + { + printf("Usage : %s \n", argv[0]); + return 1; + } + + if ((sockfd = socket(AF_INET, SOCK_STREAM, 0)) < 0) + { + printf("Error : cannot create a socket.\n"); + return 1; + } + + printf("Creation of socket was succesfull\n"); + + memset(sendBuff, '\0', sizeof(sendBuff)); + + serv_addr.sin_family = AF_INET; + serv_addr.sin_port = htons(atoi(argv[2])); + + int test_inet = inet_pton(AF_INET, argv[1], &serv_addr.sin_addr); + if ( test_inet <= 0 ) + { + printf("Error inet: %d\n",test_inet); + printf("%s \n" , " Error : cannot convert text to ip binary"); + return 1; + } + //printf("%s",serv_addr.sin_addr); + + int test_connect = connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)); + if ( test_connect < 0 ) + { + printf("Error connect: %d\n",test_connect); + printf("Error : cannot connect server 1\n"); + return 1; + } + + printf("Clinit: Send data to server, station id = %d\n", atoi(argv[3])); + snprintf(sendBuff, sizeof(sendBuff), "Hola Luis. Soy la estacion [%d] y PIN11_GPIO=0 ABIERTO \n", atoi(argv[3])); + printf("Clint: data is { %s }\n", sendBuff); + write(sockfd, sendBuff, strlen(sendBuff)); + + //int iResult = recv(sockfd, recvbuf_2, sizeof(recvbuf_2)-1, 0); + // if ( iResult > 0 ) + // printf("Bytes received: %d\n", iResult); + // else if ( iResult == 0 ) + // printf("Connection closed\n"); + // else + // printf("recv failed with error\n"); + + close(sockfd); + + return 0; +} Index: trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.h =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.h b/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.h new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/sr_clinit.h (revision 224) @@ -0,0 +1,3 @@ + + +extern int socket_clinit_main(int argc, char *argv[]); =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Storage_Sockets/test_tx/test_sock_tx =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/test_sock_tx b/trunk/firmware/sources/Storage_Sockets/test_tx/test_sock_tx new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/test_sock_tx (revision 224) =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/Storage_Sockets/test_tx/tx_sock_gpio_test =================================================================== diff --git a/trunk/firmware/sources/Storage_Sockets/test_tx/tx_sock_gpio_test b/trunk/firmware/sources/Storage_Sockets/test_tx/tx_sock_gpio_test new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/Storage_Sockets/test_tx/tx_sock_gpio_test (revision 224)