Index: trunk/firmware/sources/processingEngine/.directory =================================================================== diff --git a/trunk/firmware/sources/processingEngine/.directory b/trunk/firmware/sources/processingEngine/.directory new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/.directory (revision 215) @@ -0,0 +1,4 @@ +[Dolphin] +Timestamp=2015,3,11,23,23,3 +Version=3 +ViewMode=1 Index: trunk/firmware/sources/processingEngine/.sigasi.lic =================================================================== diff --git a/trunk/firmware/sources/processingEngine/.sigasi.lic b/trunk/firmware/sources/processingEngine/.sigasi.lic new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/.sigasi.lic (revision 215) @@ -0,0 +1,6 @@ +INCREMENT com.sigasi.hdt sigasi 2.0 08-sep-2015 uncounted \ +VENDOR_STRING=company:pucp.edu.pe;id:16476;mac:d067e531aa88;name:a20032304;type:edu \ +HOSTID=ANY ISSUER=Sigasi ISSUED=08-Mar-2015 START=08-Mar-2015 \ +SIGN="1670 17B2 977C C947 45CA 966A C2BD 73B1 BD74 9AA7 F37F \ +7ED5 C530 86CD D95C 11D8 112A FB74 6A16 4707 7ECB 1FBC 5B19 \ +9570 1D03 9A3D AA88 4F2E EE58 6B44" \ No newline at end of file Index: trunk/firmware/sources/processingEngine/Hr.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/Hr.vhd b/trunk/firmware/sources/processingEngine/Hr.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/Hr.vhd (revision 215) @@ -0,0 +1,146 @@ +--------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +use work.cic_utils.all; + +--********************************************************************************** + +entity Hr is + Port ( clk : in std_logic; + reset: in std_logic; + N : in integer range 1 to MAX_M2_DEC; + input : in std_logic_vector(FIXWIDTH-1 downto 0); + output : out std_logic_vector(FIXWIDTH-1 downto 0) + ); +end Hr; + +--********************************************************************************** + +architecture filter of Hr is + + ------------------------------------------------------------- + component hr_block + Port ( clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(FIXWIDTH-1 downto 0); + output : out std_logic_vector(FIXWIDTH-1 downto 0); + ka : in std_logic_vector(4 downto 0); + kb : in std_logic_vector(4 downto 0); + enb : in std_logic); + end component hr_block; + ------------------------------------------------------------- + component clk_div + Port ( clkin : in STD_LOGIC; + clkout: out STD_LOGIC; + reset : in std_logic; + N : in integer range 1 to 19); + end component clk_div; + ------------------------------------------------------------- + type conn is array (0 to MAX_M2_DEC-1) of std_logic_vector(FIXWIDTH-1 downto 0); + signal s1,s2,s3: conn; + signal s4:std_logic_vector(FIXWIDTH-1 downto 0); + signal clkd: std_logic; + type enab is array (0 to MAX_M2_DEC-1) of std_logic; + signal enb: enab; + type k is array (0 to MAX_M2_DEC-1) of std_logic_vector(4 downto 0); + constant ka:k := ("00000","00001","00010","00011", + "00100","00101","00110","00111", + "01000","01001","01010","01011", + "01100","01101","01110","01111", + "10000","10001","10010"); + signal kb:k; + +begin + s1(0) <= input; + output <= s4; + + clkdiv: clk_div port map( + clkin => clk, + clkout => clkd, + reset => reset, + N => N + ); + + --///////////////////////////////////////////////////////////////////////////////// + hr_filter: for i in 0 to MAX_M2_DEC-1 generate + begin + ------------------------------------------------------------- + + Gk: component hr_block + -- (clk,reset,input,output,ka,kb,encb) + port map (clkd,reset,s2(i),s3(i),ka(i),kb(i),enb(i)); + ------------------------------------------------------------- + end generate hr_filter; + --///////////////////////////////////////////////////////////////////////////////// + + + -- shift registers -- + process(clk,reset) + begin + if reset='1' then + for i in 1 to MAX_M2_DEC-1 loop + s1(i) <= (others=>'0'); + end loop; + elsif clk'event and clk='1' then + for i in MAX_M2_DEC-1 downto 1 loop + s1(i) <= s1(i-1); + end loop; + end if; + end process; + + + + -- implementa a los decimadores, cada vez que haya un flanco de subida + -- en el clock clkd (clkd = clk / N), pasa una muestra al lado de baja + -- frecuencia del filtro. + -- la salida final del filtro es la suma de las salidas de los bloques. + process(clkd,reset) + begin + if reset='1' then + for i in 0 to MAX_M2_DEC-1 loop + s2(i) <= (others=>'0'); + end loop; + elsif clkd'event and clkd='1' then + for i in 0 to MAX_M2_DEC-1 loop + s2(i) <= s1(i); + end loop; + end if; + end process; + + +-- process(s3) +-- variable acum : std_logic_vector(FIXWIDTH-1 downto 0); +-- begin +-- acum := s3(0); +-- for i in 1 to MAX_M2_DEC-1 loop +-- acum := acum+s3(i); +-- end loop; +-- s4 <= acum; +-- end process; + + s4 <= s3(0)+s3(1)+s3(2)+s3(3)+s3(4)+s3(5)+ + s3(6)+s3(7)+s3(8)+s3(9)+s3(10)+s3(11)+ + s3(12)+s3(13)+s3(14)+s3(15)+s3(16)+s3(17)+s3(18); + + process(N) + begin + for i in 0 to MAX_M2_DEC-1 loop + if N-1 > i then + kb(i) <= std_logic_vector(to_unsigned(N-i-2,kb(i)'length)); + else + kb(i) <= std_logic_vector(to_unsigned(19,kb(i)'length)); + end if; + + if N-1 >= i then + enb(i) <= '1'; + else + enb(i) <= '0'; + end if; + end loop; + end process; + +end filter; + +--********************************************************************************** \ No newline at end of file Index: trunk/firmware/sources/processingEngine/Hr_block.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/Hr_block.vhd b/trunk/firmware/sources/processingEngine/Hr_block.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/Hr_block.vhd (revision 215) @@ -0,0 +1,68 @@ +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; + +use work.cic_utils.all; + +-- Este modulo implementa el bloque Gk del filtro Hr + +entity hr_block is + Port ( clk : in std_logic; + reset : in std_logic; + input : in std_logic_vector(FIXWIDTH-1 downto 0); + output : out std_logic_vector(FIXWIDTH-1 downto 0); + ka : in std_logic_vector(4 downto 0); + kb : in std_logic_vector(4 downto 0); + enb : in std_logic); +end hr_block; + + + +architecture simple_block of Hr_block is + signal s1,s2,s3 : std_logic_vector(FIXWIDTH-1 downto 0); + signal Ca,Cb : std_logic_vector(FIXWIDTH-1 downto 0); + type ROM is array (0 to 19) of std_logic_vector(FIXWIDTH-1 downto 0); + constant coeffs : ROM:= ( to_fix(2**MANTISSA_BITS), + to_fix((196875 *(2**MANTISSA_BITS))/100000), + to_fix((284375 *(2**MANTISSA_BITS))/100000), + to_fix((362500 *(2**MANTISSA_BITS))/100000), + to_fix((425000 *(2**MANTISSA_BITS))/100000), + to_fix((475000 *(2**MANTISSA_BITS))/100000), + to_fix((503125 *(2**MANTISSA_BITS))/100000), + to_fix((512500 *(2**MANTISSA_BITS))/100000), + to_fix((503125 *(2**MANTISSA_BITS))/100000), + to_fix((475000 *(2**MANTISSA_BITS))/100000), + to_fix((425000 *(2**MANTISSA_BITS))/100000), + to_fix((362500 *(2**MANTISSA_BITS))/100000), + to_fix((284375 *(2**MANTISSA_BITS))/100000), + to_fix((196875 *(2**MANTISSA_BITS))/100000), + to_fix(2**MANTISSA_BITS), + to_fix(0), + to_fix((-100000 *(2**MANTISSA_BITS))/100000), + to_fix((-196875 *(2**MANTISSA_BITS))/100000), + to_fix((-284375 *(2**MANTISSA_BITS))/100000), + to_fix(0));-- el coeficieente 19 no existe, solo es para anular un tap + + +begin + Ca <= coeffs(to_integer(unsigned(ka))); + Cb <= coeffs(to_integer(unsigned(kb))); + + process (clk,enb,reset) + begin + if (enb = '0') or (reset='1') then + s2 <= (others =>'0'); + elsif clk'event and clk='1' then + s2 <= s1; + end if; + + end process; + s1 <= input*Cb; + with enb select + s3 <= input*Ca when '1', + (others=>'0') when others; + + output <= s2+s3; + +end simple_block; \ No newline at end of file Index: trunk/firmware/sources/processingEngine/cic.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/cic.vhd b/trunk/firmware/sources/processingEngine/cic.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/cic.vhd (revision 215) @@ -0,0 +1,65 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 15:48:08 03/12/2015 +-- Design Name: +-- Module Name: cic - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; +use work.cic_utils.all; + + +entity cic is + Port ( clk : in STD_LOGIC; + M1 : in integer(8 downto 0); -- factor de decimacion + M2 : in integer(8 downto 0); + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); +end cic; + + +architecture Behavioral of cic is + -- componentes del cic + COMPONENT integrator + PORT( + clk : IN std_logic; + input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS) + ); + END COMPONENT; + + COMPONENT comb + PORT( + clk : in std_logic; + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS) + ); + END COMPONENT; + + constant K: integer := 3;-- numero de etapas del filtro CIC + type conn is array (2*(K+1)-1 downto 0) of sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal connector : conn; +begin + cic_arc: for i in 0 to (K-1) generate + int: integrator port map(clk=>clk, input=>connector(i), output=>connector(i+1) ); + cmb: comb port map(clk=>clk, input=>connector(i+K), output=>connector(i+K+1) ); + end generate cic_arc; + + +end Behavioral; + Index: trunk/firmware/sources/processingEngine/cic_utils.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/cic_utils.vhd b/trunk/firmware/sources/processingEngine/cic_utils.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/cic_utils.vhd (revision 215) @@ -0,0 +1,79 @@ + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.numeric_std.all; + +package cic_utils is + -- parametros de diseño del filtro CIC ---------------------------------------- + constant MANTISSA_BITS : integer := 24; + constant NUMBER_BITS : integer := 32; -- incluye bit de signo + constant FIXWIDTH : integer := NUMBER_BITS + MANTISSA_BITS; + constant STAGES : integer := 5; -- orden del filtro CIC (numero de etapas) + + -- no modificar --------------------------------------------------------------- + subtype fixpoint is std_logic_vector(FIXWIDTH-1 downto 0); + function "*"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; + function "/"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; + function "+"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; + function "-"(a: std_logic_vector ; b: std_logic_vector) return std_logic_vector; + function to_fix(a: integer) return std_logic_vector; + constant MAX_M2_DEC : integer := 19; + constant ONE: integer := 2**MANTISSA_BITS; + +end cic_utils; + + + + +package body cic_utils is +-- operaciones aritmeticas de punto fijo + function "*" ( a: std_logic_vector ; b: std_logic_vector) + return std_logic_vector is + variable ret : std_logic_vector(2*FIXWIDTH-1 downto 0); + begin + ret := std_logic_vector(signed(a)*signed(b)); + return ret(a'length+MANTISSA_BITS-1 downto MANTISSA_BITS); + end "*"; + + + function "/" (a: std_logic_vector ; b: std_logic_vector) + return std_logic_vector is + variable ret : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0); + variable tmp : std_logic_vector(a'length+MANTISSA_BITS-1 downto 0):=(others=>'0'); + begin + for i in 0 to a'length-1 loop + tmp(i+MANTISSA_BITS ) := a(i); + end loop; + ret := std_logic_vector(signed(tmp)/signed(b)); + return ret(a'length-1 downto 0); + end "/"; + + + function "+" (a: std_logic_vector ; b: std_logic_vector) + return std_logic_vector is + variable ret : std_logic_vector(a'length-1 downto 0); + begin + ret := std_logic_vector(signed(a)+signed(b)); + return ret; + end "+"; + + + function "-" (a: std_logic_vector ; b: std_logic_vector) + return std_logic_vector is + variable ret : std_logic_vector(a'length-1 downto 0); + begin + ret := std_logic_vector(signed(a)-signed(b)); + return ret; + end "-"; + +-- + + function to_fix(a: integer) + return std_logic_vector is + variable ret : std_logic_vector(FIXWIDTH-1 downto 0); + begin + ret := std_logic_vector(to_signed(a,FIXWIDTH)); + return ret; + end to_fix; + +end cic_utils; Index: trunk/firmware/sources/processingEngine/clk_div.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/clk_div.vhd b/trunk/firmware/sources/processingEngine/clk_div.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/clk_div.vhd (revision 215) @@ -0,0 +1,41 @@ +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; +use work.cic_utils.all; + + + +entity clk_div is + Port ( clkin : in STD_LOGIC; + clkout: out STD_LOGIC; + reset : in std_logic; + N : in integer range 0 to 19); +end clk_div; + + +architecture Behavioral of clk_div is + signal clktmp: STD_LOGIC := '0'; + signal cnt1: integer range 0 to 19 := 0; +begin + process(clkin,reset) + begin + if reset = '1' then + cnt1 <= 0; + clktmp <= '0'; + elsif clkin'event and clkin = '1' then + if cnt1 < N then + if cnt1 >= N/2 then + clktmp <= '0'; + end if; + cnt1 <= cnt1 +1; + else + clktmp <= '1'; + cnt1 <= 0; + end if; + end if; + end process; + + clkout <= clktmp; +end Behavioral; + =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: trunk/firmware/sources/processingEngine/coeffs.ods =================================================================== diff --git a/trunk/firmware/sources/processingEngine/coeffs.ods b/trunk/firmware/sources/processingEngine/coeffs.ods new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/coeffs.ods (revision 215) Index: trunk/firmware/sources/processingEngine/comb.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/comb.vhd b/trunk/firmware/sources/processingEngine/comb.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/comb.vhd (revision 215) @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: company +-- Engineer: shinobi +-- +-- Create Date: Mar 9, 2015 - 5:10:57 PM +-- Design Name: modulename +-- Module Name: comb +-- Project Name: projectname +-- Description: +-- +-- +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; + +use work.cic_utils.all; + +-- entity declaration -------------------------------- +entity comb is + port ( + clk : in std_logic; + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS) + ); +end entity comb; + + +-- architecture declaration------------------------ +architecture simple of comb is + signal s_in_1 : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal s_in : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); +begin + process(clk) + begin + if clk'event and clk = '1' then + s_in_1 <= s_in; + end if; + end process; + output <= sust(input ,s_in_1); + s_in <= input; + + +end architecture simple; Index: trunk/firmware/sources/processingEngine/decimator.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/decimator.vhd b/trunk/firmware/sources/processingEngine/decimator.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/decimator.vhd (revision 215) @@ -0,0 +1,52 @@ +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.all; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; +use work.cic_utils.all; + + + +entity decimator is + Port ( clkin : in STD_LOGIC; + clkout: out STD_LOGIC; + reset : in std_logic; + N : in integer range 0 to 19; + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)); +end decimator; + + +architecture Behavioral of decimator is + signal clktmp: STD_LOGIC := '0'; + signal cnt1: integer range 0 to 19 := 0; + signal tmp: sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); +begin + + +process(clkin,reset) +begin + if reset = '1' then + cnt1 <= 0; + clktmp <= '0'; + elsif clkin'event and clkin = '1' then + if cnt1 < N then + if cnt1 >= N/2 then + clktmp <= '0'; + end if; + cnt1 <= cnt1 +1; + else + clktmp <= '1'; + cnt1 <= 0; + tmp <= input; + end if; + end if; +end process; + + +clkout <= clktmp; +output <= tmp; + +end Behavioral; + Index: trunk/firmware/sources/processingEngine/integrator.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/integrator.vhd b/trunk/firmware/sources/processingEngine/integrator.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/integrator.vhd (revision 215) @@ -0,0 +1,47 @@ +---------------------------------------------------------------------------------- +-- Company: company +-- Engineer: shinobi +-- +-- Create Date: Mar 9, 2015 - 5:10:57 PM +-- Design Name: modulename +-- Module Name: integrator +-- Project Name: projectname +-- Description: +-- +-- +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.numeric_std.all; + +use work.cic_utils.all; + +-- entity declaration -------------------------------- +entity integrator is + port ( + clk : in std_logic; + input : in std_logic_vector(FIXWIDTH-1 downto 0); + output : out std_logic_vector(FIXWIDTH-1 downto 0) + ); +end entity integrator; + + +-- architecture declaration------------------------ +architecture simple of integrator is + +signal s_out : std_logic_vector(FIXWIDTH-1 downto 0); +signal s_out_1: std_logic_vector(FIXWIDTH-1 downto 0); + +begin + process(clk) + begin + if clk'event and clk = '1' then + s_out_1 <= s_out; + end if; + end process; + output <= s_out; + s_out <= input+s_out_1; + + +end architecture simple; Index: trunk/firmware/sources/processingEngine/tb_comb.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/tb_comb.vhd b/trunk/firmware/sources/processingEngine/tb_comb.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/tb_comb.vhd (revision 215) @@ -0,0 +1,81 @@ +-- test_comb Template + + LIBRARY ieee; + USE ieee.std_logic_1164.ALL; + USE ieee.numeric_std.ALL; + library IEEE_proposed; + use IEEE_proposed.fixed_pkg.all; + + use work.cic_utils.all; + + + ENTITY test_comb IS + END test_comb; + + ARCHITECTURE behavior OF test_comb IS + + -- Component Declaration + COMPONENT comb + PORT( + clk : in std_logic; + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS) + ); + END COMPONENT; + + --Inputs + signal clk : std_logic := '0'; + signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0'); + + --Outputs + signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + + -- Clock period definitions + constant clk_period : time := 1 ms; + BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: comb PORT MAP( + clk => clk, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 1 ms. + wait for 1 ms; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(2,input); + wait for clk_period; + input <= to_sfixed(3,input); + wait for clk_period; + input <= to_sfixed(5,input); + wait for clk_period; + input <= to_sfixed(8,input); + wait for clk_period; + input <= to_sfixed(13,input); + wait for clk_period; + input <= to_sfixed(21,input); + wait for clk_period; + input <= to_sfixed(34,input); + wait for clk_period; + input <= to_sfixed(55,input); + wait for clk_period; + input <= to_sfixed(89,input); + wait; + end process; + + + END; Index: trunk/firmware/sources/processingEngine/tb_int.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/tb_int.vhd b/trunk/firmware/sources/processingEngine/tb_int.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/tb_int.vhd (revision 215) @@ -0,0 +1,111 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 14:55:16 03/12/2015 +-- Design Name: +-- Module Name: /home/shinobi/workspaces/roj/trunk/firmware/sources/processingEngine/cic/tb_int.vhd +-- Project Name: cic +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: integrator +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; + +use work.fix_arith.all; +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY tb_int IS +END tb_int; + +ARCHITECTURE behavior OF tb_int IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT integrator + PORT( + clk : IN std_logic; + input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS) + ); + END COMPONENT; + + + --Inputs + signal clk : std_logic := '0'; + signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0'); + + --Outputs + signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + + -- Clock period definitions + constant clk_period : time := 1 ms; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: integrator PORT MAP ( + clk => clk, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process; + + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 100 ns. + wait for 1 ms; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(1,input); + wait; + end process; + +END; Index: trunk/firmware/sources/processingEngine/test_decim.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/test_decim.vhd b/trunk/firmware/sources/processingEngine/test_decim.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/test_decim.vhd (revision 215) @@ -0,0 +1,106 @@ +-- test_comb Template + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; +use work.cic_utils.all; + + + ENTITY test_decim IS + END test_decim; + + ARCHITECTURE behavior OF test_decim IS + + -- Component Declaration + COMPONENT decimator + Port ( clkin : in STD_LOGIC; + clkout: out STD_LOGIC; + reset : in std_logic; + N : in integer range 0 to 19; + input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)); + END COMPONENT; + + --Inputs + signal clkin : std_logic := '0'; + signal reset : std_logic := '0'; + signal N : integer range 0 to 19:= 11; + signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0'); + + --Outputs + signal clkout : std_logic := '0'; + signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + + -- Clock period definitions + constant clk_period : time := 1 ms; + BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: decimator PORT MAP( + clkin => clkin, + clkout => clkout, + reset => reset, + N => N, + input => input, + output => output + ); + + -- Clock process definitions + clk_process :process + begin + clkin <= '1'; + wait for clk_period/2; + clkin <= '0'; + wait for clk_period/2; + end process; + + -- Stimulus process + stim_proc: process + begin + -- hold reset state for 1 ms. + wait for clk_period; + input <= to_sfixed(1,input); + wait for clk_period; + input <= to_sfixed(2,input); + wait for clk_period; + input <= to_sfixed(3,input); + wait for clk_period; + input <= to_sfixed(4,input); + wait for clk_period; + input <= to_sfixed(5,input); + wait for clk_period; + input <= to_sfixed(6,input); + wait for clk_period; + input <= to_sfixed(7,input); + wait for clk_period; + input <= to_sfixed(8,input); + wait for clk_period; + input <= to_sfixed(9,input); + wait for clk_period; + input <= to_sfixed(10,input); + wait for clk_period; + input <= to_sfixed(11,input); + wait for clk_period; + input <= to_sfixed(12,input); + wait for clk_period; + input <= to_sfixed(13,input); + wait for clk_period; + input <= to_sfixed(14,input); + wait for clk_period; + input <= to_sfixed(15,input); + wait for clk_period; + input <= to_sfixed(16,input); + wait for clk_period; + input <= to_sfixed(17,input); + wait for clk_period; + input <= to_sfixed(18,input); + wait for clk_period; + input <= to_sfixed(19,input); + wait for clk_period; + input <= to_sfixed(20,input); + end process; + + + END; Index: trunk/firmware/sources/processingEngine/test_hr.vhd =================================================================== diff --git a/trunk/firmware/sources/processingEngine/test_hr.vhd b/trunk/firmware/sources/processingEngine/test_hr.vhd new file mode 10644 --- /dev/null (revision 0) +++ b/trunk/firmware/sources/processingEngine/test_hr.vhd (revision 215) @@ -0,0 +1,82 @@ +-- test_hr Template + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +USE ieee.numeric_std.ALL; +library IEEE_proposed; +use IEEE_proposed.fixed_pkg.all; +use work.cic_utils.all; + + + ENTITY test_hr IS + END test_hr; + + ARCHITECTURE behavior OF test_hr IS + + -- Component Declaration + COMPONENT Hr_block + Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + Cb : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + Ca : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + acum : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + clk : in std_logic; + last : in std_logic); + END COMPONENT; + + signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal Cb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal Ca : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal acum : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS); + signal clk : std_logic; + signal last : std_logic; + + -- Clock period definitions + constant clk_period : time := 1 ms; + + BEGIN + + -- Component Instantiation + uut: Hr_block PORT MAP( + input => input, + output => output, + Cb => Cb, + Ca => Ca, + acum => acum, + clk => clk, + last => last + ); + + Cb <= to_sfixed(2,Cb); + Ca <= to_sfixed(3,Ca); + acum <= to_sfixed(10,Ca); + + + -- Clock process definitions + clk_process :process + begin + clk <= '1'; + wait for clk_period/2; + clk <= '0'; + wait for clk_period/2; + end process; + + + -- Test Bench Statements + tb : PROCESS + BEGIN + + -- hold reset state for 1 ms. + last <= '1'; + input <= to_sfixed(100,input); + wait for clk_period; + last <= '0'; + input <= to_sfixed(100,input); + wait for clk_period; + + wait; + END PROCESS tb; + -- End Test Bench + + END;