##// END OF EJS Templates
jro_hard » gen_acq
RSS
aaguilar - - Load All Authors

File last commit:

r214:215
r221:222
Show More
test_hr.vhd
82 lines | 1.9 KiB | text/x-vhdl | VhdlLexer
/ trunk / firmware / sources / processingEngine / test_hr.vhd
History | Source | Raw |Copy content |Copy permalink
aaguilar
r214 -- test_hr Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;
use work.cic_utils.all;
ENTITY test_hr IS
END test_hr;
ARCHITECTURE behavior OF test_hr IS
-- Component Declaration
COMPONENT Hr_block
Port ( input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
Cb : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
Ca : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
acum : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
clk : in std_logic;
last : in std_logic);
END COMPONENT;
signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal Cb : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal Ca : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal acum : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal clk : std_logic;
signal last : std_logic;
-- Clock period definitions
constant clk_period : time := 1 ms;
BEGIN
-- Component Instantiation
uut: Hr_block PORT MAP(
input => input,
output => output,
Cb => Cb,
Ca => Ca,
acum => acum,
clk => clk,
last => last
);
Cb <= to_sfixed(2,Cb);
Ca <= to_sfixed(3,Ca);
acum <= to_sfixed(10,Ca);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Test Bench Statements
tb : PROCESS
BEGIN
-- hold reset state for 1 ms.
last <= '1';
input <= to_sfixed(100,input);
wait for clk_period;
last <= '0';
input <= to_sfixed(100,input);
wait for clk_period;
wait;
END PROCESS tb;
-- End Test Bench
END;