##// END OF EJS Templates
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tb_comb.vhd
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r214 -- test_comb Template
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;
use work.cic_utils.all;
ENTITY test_comb IS
END test_comb;
ARCHITECTURE behavior OF test_comb IS
-- Component Declaration
COMPONENT comb
PORT(
clk : in std_logic;
input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal input : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS):= (others => '0');
--Outputs
signal output : sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
-- Clock period definitions
constant clk_period : time := 1 ms;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: comb PORT MAP(
clk => clk,
input => input,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 1 ms.
wait for 1 ms;
input <= to_sfixed(1,input);
wait for clk_period;
input <= to_sfixed(2,input);
wait for clk_period;
input <= to_sfixed(3,input);
wait for clk_period;
input <= to_sfixed(5,input);
wait for clk_period;
input <= to_sfixed(8,input);
wait for clk_period;
input <= to_sfixed(13,input);
wait for clk_period;
input <= to_sfixed(21,input);
wait for clk_period;
input <= to_sfixed(34,input);
wait for clk_period;
input <= to_sfixed(55,input);
wait for clk_period;
input <= to_sfixed(89,input);
wait;
end process;
END;