jro_hard/gen_acq Files · trunk/firmware/sources/processingEngine/integrator.vhd

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        aaguilar
    
              r214
            
      ----------------------------------------------------------------------------------

      -- Company: company

      -- Engineer: shinobi

      -- 

      -- Create Date:    Mar 9, 2015  -   5:10:57 PM

      -- Design Name:  modulename

      -- Module Name:  integrator

      -- Project Name:  projectname

      -- Description: 

      --

      --

      --

      ----------------------------------------------------------------------------------

      library IEEE;

      use IEEE.std_logic_1164.all;

      use IEEE.numeric_std.all;

      use work.cic_utils.all;

      -- entity declaration --------------------------------

      entity integrator is

      	port (

      		clk : in std_logic;

      		input : in std_logic_vector(FIXWIDTH-1 downto 0);

      		output : out std_logic_vector(FIXWIDTH-1 downto 0)

      	);

      end entity integrator;

      -- architecture declaration------------------------

      architecture simple of integrator is

      signal s_out : std_logic_vector(FIXWIDTH-1 downto 0);

      signal s_out_1: std_logic_vector(FIXWIDTH-1 downto 0);

      begin

      	process(clk)

      	begin

      		if clk'event and clk = '1' then  

      	      	s_out_1 <= s_out;

      	   	end if;

      	end process;

      	output <= s_out;

      	s_out <= input+s_out_1;

      end architecture simple;

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aaguilar	r214	----------------------------------------------------------------------------------
		-- Company: company
		-- Engineer: shinobi
		--
		-- Create Date: Mar 9, 2015 - 5:10:57 PM
		-- Design Name: modulename
		-- Module Name: integrator
		-- Project Name: projectname
		-- Description:
		--
		--
		--
		----------------------------------------------------------------------------------
		library IEEE;
		use IEEE.std_logic_1164.all;
		use IEEE.numeric_std.all;

		use work.cic_utils.all;

		-- entity declaration --------------------------------
		entity integrator is
		port (
		clk : in std_logic;
		input : in std_logic_vector(FIXWIDTH-1 downto 0);
		output : out std_logic_vector(FIXWIDTH-1 downto 0)
		);
		end entity integrator;


		-- architecture declaration------------------------
		architecture simple of integrator is

		signal s_out : std_logic_vector(FIXWIDTH-1 downto 0);
		signal s_out_1: std_logic_vector(FIXWIDTH-1 downto 0);

		begin
		process(clk)
		begin
		if clk'event and clk = '1' then
		s_out_1 <= s_out;
		end if;
		end process;
		output <= s_out;
		s_out <= input+s_out_1;


		end architecture simple;