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cic.vhd
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r214 ----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:48:08 03/12/2015
-- Design Name:
-- Module Name: cic - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library IEEE_proposed;
use IEEE_proposed.fixed_pkg.all;
use work.cic_utils.all;
entity cic is
Port ( clk : in STD_LOGIC;
M1 : in integer(8 downto 0); -- factor de decimacion
M2 : in integer(8 downto 0);
input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
end cic;
architecture Behavioral of cic is
-- componentes del cic
COMPONENT integrator
PORT(
clk : IN std_logic;
input : IN sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
output : OUT sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
);
END COMPONENT;
COMPONENT comb
PORT(
clk : in std_logic;
input : in sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
output : out sfixed(NUMBER_BITS-1 downto MANTISSA_BITS)
);
END COMPONENT;
constant K: integer := 3;-- numero de etapas del filtro CIC
type conn is array (2*(K+1)-1 downto 0) of sfixed(NUMBER_BITS-1 downto MANTISSA_BITS);
signal connector : conn;
begin
cic_arc: for i in 0 to (K-1) generate
int: integrator port map(clk=>clk, input=>connector(i), output=>connector(i+1) );
cmb: comb port map(clk=>clk, input=>connector(i+K), output=>connector(i+K+1) );
end generate cic_arc;
end Behavioral;