From 028e278dc82090c1a0134a15fe54e5fc734d1453 2020-05-02 01:24:40
From: jrojas <john.rojas@jro.igp.gob.pe>
Date: 2020-05-02 01:24:40
Subject: [PATCH] Quartus project files for the CPLD_CTRL

---

diff --git a/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bdf b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bdf
new file mode 100644
index 0000000..0a610f5
--- /dev/null
+++ b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bdf
@@ -0,0 +1,434 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2013 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.4"))
+(properties
+	(page_setup "header_footer\nDate: %D\n%f\nProject: %j\n\nPage %p of %P\nRevision: %a\nmargin\n1\n1\n1\n1\norientation\n2\npaper_size\n9\npaper_source\n15\nfit_page_wide\n1\nfit_page_tall\n1\n")
+)
+(pin
+	(input)
+	(rect -440 240 -272 256)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "DATA_CMD_IN[10..0]" (rect 9 0 117 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+)
+(pin
+	(input)
+	(rect -400 144 -232 160)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "GCLK" (rect 9 0 38 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -496 80 -448 96))
+)
+(pin
+	(input)
+	(rect -400 176 -232 192)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CMD_CLK_PC" (rect 9 0 82 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -552 192 -496 208))
+)
+(pin
+	(input)
+	(rect -400 192 -232 208)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "CMD_DATA_PC" (rect 9 0 89 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -600 296 -544 312))
+)
+(pin
+	(input)
+	(rect -400 160 -232 176)
+	(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
+	(text "RST_GENERAL" (rect 9 0 88 12)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -536 144 -488 160))
+)
+(pin
+	(output)
+	(rect 120 224 296 240)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DATA_CMD_Y[10..0]" (rect 90 0 195 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 296 240 344 400))
+)
+(pin
+	(output)
+	(rect 120 176 296 192)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "DATA_RDY_Y" (rect 90 0 163 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 296 192 344 208))
+)
+(pin
+	(output)
+	(rect 552 128 728 144)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "Reset" (rect 90 0 119 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 552 144 728 160)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "Enable" (rect 90 0 123 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 552 160 728 176)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "OE" (rect 90 0 105 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+)
+(pin
+	(output)
+	(rect 120 192 296 208)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "LED1" (rect 90 0 117 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 296 208 344 224))
+)
+(pin
+	(output)
+	(rect 120 208 296 224)
+	(text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6)))
+	(text "LED2" (rect 90 0 117 12)(font "Arial" ))
+	(pt 0 8)
+	(drawing
+		(line (pt 0 8)(pt 52 8))
+		(line (pt 52 4)(pt 78 4))
+		(line (pt 52 12)(pt 78 12))
+		(line (pt 52 12)(pt 52 4))
+		(line (pt 78 4)(pt 82 8))
+		(line (pt 82 8)(pt 78 12))
+		(line (pt 78 12)(pt 82 8))
+	)
+	(annotation_block (location)(rect 296 224 344 240))
+)
+(symbol
+	(rect 344 104 536 200)
+	(text "CMD_CPLD_CTRL" (rect 5 0 99 12)(font "Arial" ))
+	(text "inst1" (rect 8 80 31 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "GCLK" (rect 0 0 29 12)(font "Arial" ))
+		(text "GCLK" (rect 21 27 50 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "DATA_CMD_X[10..0]" (rect 0 0 102 12)(font "Arial" ))
+		(text "DATA_CMD_X[10..0]" (rect 21 43 123 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "DATA_RDY_X" (rect 0 0 70 12)(font "Arial" ))
+		(text "DATA_RDY_X" (rect 21 59 91 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 192 32)
+		(output)
+		(text "Reset" (rect 0 0 29 12)(font "Arial" ))
+		(text "Reset" (rect 142 27 171 39)(font "Arial" ))
+		(line (pt 192 32)(pt 176 32))
+	)
+	(port
+		(pt 192 48)
+		(output)
+		(text "Enable" (rect 0 0 33 12)(font "Arial" ))
+		(text "Enable" (rect 138 43 171 55)(font "Arial" ))
+		(line (pt 192 48)(pt 176 48))
+	)
+	(port
+		(pt 192 64)
+		(output)
+		(text "OE" (rect 0 0 15 12)(font "Arial" ))
+		(text "OE" (rect 156 59 171 71)(font "Arial" ))
+		(line (pt 192 64)(pt 176 64))
+	)
+	(drawing
+		(rectangle (rect 16 16 176 80))
+	)
+)
+(symbol
+	(rect -176 120 88 280)
+	(text "CMD_Interprete_Sync" (rect 5 0 114 12)(font "Arial" ))
+	(text "inst3" (rect 8 144 31 156)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "GCLK" (rect 0 0 29 12)(font "Arial" ))
+		(text "GCLK" (rect 21 27 50 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "RST_gral" (rect 0 0 44 12)(font "Arial" ))
+		(text "RST_gral" (rect 21 43 65 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "CMD_CLK_PC" (rect 0 0 73 12)(font "Arial" ))
+		(text "CMD_CLK_PC" (rect 21 59 94 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "CMD_DATA_PC" (rect 0 0 80 12)(font "Arial" ))
+		(text "CMD_DATA_PC" (rect 21 75 101 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "DATA_CMD_IN[10..0]" (rect 0 0 108 12)(font "Arial" ))
+		(text "DATA_CMD_IN[10..0]" (rect 21 91 129 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 264 32)
+		(output)
+		(text "DATA_CMD_X[10..0]" (rect 0 0 102 12)(font "Arial" ))
+		(text "DATA_CMD_X[10..0]" (rect 141 27 243 39)(font "Arial" ))
+		(line (pt 264 32)(pt 248 32)(line_width 3))
+	)
+	(port
+		(pt 264 48)
+		(output)
+		(text "DATA_RDY_X" (rect 0 0 70 12)(font "Arial" ))
+		(text "DATA_RDY_X" (rect 173 43 243 55)(font "Arial" ))
+		(line (pt 264 48)(pt 248 48))
+	)
+	(port
+		(pt 264 64)
+		(output)
+		(text "DATA_RDY_Y" (rect 0 0 73 12)(font "Arial" ))
+		(text "DATA_RDY_Y" (rect 170 59 243 71)(font "Arial" ))
+		(line (pt 264 64)(pt 248 64))
+	)
+	(port
+		(pt 264 80)
+		(output)
+		(text "LED_1" (rect 0 0 33 12)(font "Arial" ))
+		(text "LED_1" (rect 210 75 243 87)(font "Arial" ))
+		(line (pt 264 80)(pt 248 80))
+	)
+	(port
+		(pt 264 96)
+		(output)
+		(text "LED_2" (rect 0 0 33 12)(font "Arial" ))
+		(text "LED_2" (rect 210 91 243 103)(font "Arial" ))
+		(line (pt 264 96)(pt 248 96))
+	)
+	(port
+		(pt 264 112)
+		(output)
+		(text "DATA_CMD_Y[10..0]" (rect 0 0 105 12)(font "Arial" ))
+		(text "DATA_CMD_Y[10..0]" (rect 138 107 243 119)(font "Arial" ))
+		(line (pt 264 112)(pt 248 112)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 248 144))
+	)
+)
+(connector
+	(pt 88 168)
+	(pt 344 168)
+)
+(connector
+	(pt -232 152)
+	(pt -176 152)
+)
+(connector
+	(pt 536 136)
+	(pt 552 136)
+)
+(connector
+	(pt 536 152)
+	(pt 552 152)
+)
+(connector
+	(pt 536 168)
+	(pt 552 168)
+)
+(connector
+	(pt -176 200)
+	(pt -232 200)
+)
+(connector
+	(pt -176 184)
+	(pt -232 184)
+)
+(connector
+	(pt -176 168)
+	(pt -232 168)
+)
+(connector
+	(pt 120 184)
+	(pt 88 184)
+)
+(connector
+	(pt 88 200)
+	(pt 120 200)
+)
+(connector
+	(pt 120 232)
+	(pt 88 232)
+	(bus)
+)
+(connector
+	(pt 88 216)
+	(pt 120 216)
+)
+(connector
+	(text "GCLK" (rect 274 120 303 132)(font "Arial" ))
+	(pt 264 136)
+	(pt 344 136)
+)
+(connector
+	(pt 88 152)
+	(pt 344 152)
+	(bus)
+)
+(connector
+	(pt -176 216)
+	(pt -224 216)
+	(bus)
+)
+(connector
+	(pt -224 216)
+	(pt -224 248)
+	(bus)
+)
+(connector
+	(pt -224 248)
+	(pt -272 248)
+	(bus)
+)
diff --git a/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bsf b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bsf
new file mode 100644
index 0000000..341b55e
--- /dev/null
+++ b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.bsf
@@ -0,0 +1,113 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 312 176)
+	(text "Archit_Comandos_CPLD_CTRL" (rect 5 0 182 14)(font "Arial" (font_size 8)))
+	(text "inst" (rect 8 144 25 156)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "GCLK" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+		(text "GCLK" (rect 21 27 54 41)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "RST_GENERAL" (rect 0 0 87 14)(font "Arial" (font_size 8)))
+		(text "RST_GENERAL" (rect 21 43 108 57)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "CMD_CLK_PC" (rect 0 0 79 14)(font "Arial" (font_size 8)))
+		(text "CMD_CLK_PC" (rect 21 59 100 73)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "CMD_DATA_PC" (rect 0 0 89 14)(font "Arial" (font_size 8)))
+		(text "CMD_DATA_PC" (rect 21 75 110 89)(font "Arial" (font_size 8)))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "DATA_CMD_IN[10..0]" (rect 0 0 120 14)(font "Arial" (font_size 8)))
+		(text "DATA_CMD_IN[10..0]" (rect 21 91 141 105)(font "Arial" (font_size 8)))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 296 32)
+		(output)
+		(text "Reset" (rect 0 0 33 14)(font "Arial" (font_size 8)))
+		(text "Reset" (rect 242 27 275 41)(font "Arial" (font_size 8)))
+		(line (pt 296 32)(pt 280 32)(line_width 1))
+	)
+	(port
+		(pt 296 48)
+		(output)
+		(text "Enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
+		(text "Enable" (rect 238 43 275 57)(font "Arial" (font_size 8)))
+		(line (pt 296 48)(pt 280 48)(line_width 1))
+	)
+	(port
+		(pt 296 64)
+		(output)
+		(text "OE" (rect 0 0 16 14)(font "Arial" (font_size 8)))
+		(text "OE" (rect 259 59 275 73)(font "Arial" (font_size 8)))
+		(line (pt 296 64)(pt 280 64)(line_width 1))
+	)
+	(port
+		(pt 296 80)
+		(output)
+		(text "DATA_RDY_Y" (rect 0 0 83 14)(font "Arial" (font_size 8)))
+		(text "DATA_RDY_Y" (rect 192 75 275 89)(font "Arial" (font_size 8)))
+		(line (pt 296 80)(pt 280 80)(line_width 1))
+	)
+	(port
+		(pt 296 96)
+		(output)
+		(text "LED1" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "LED1" (rect 246 91 275 105)(font "Arial" (font_size 8)))
+		(line (pt 296 96)(pt 280 96)(line_width 1))
+	)
+	(port
+		(pt 296 112)
+		(output)
+		(text "LED2" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "LED2" (rect 246 107 275 121)(font "Arial" (font_size 8)))
+		(line (pt 296 112)(pt 280 112)(line_width 1))
+	)
+	(port
+		(pt 296 128)
+		(output)
+		(text "DATA_CMD_Y[10..0]" (rect 0 0 119 14)(font "Arial" (font_size 8)))
+		(text "DATA_CMD_Y[10..0]" (rect 156 123 275 137)(font "Arial" (font_size 8)))
+		(line (pt 296 128)(pt 280 128)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 280 144)(line_width 1))
+	)
+)
diff --git a/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.vhd b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.vhd
new file mode 100644
index 0000000..c242610
--- /dev/null
+++ b/CPLD_CTRL/Archit_Comandos_CPLD_CTRL.vhd
@@ -0,0 +1,101 @@
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, the Altera Quartus Prime License Agreement,
+-- the Altera MegaCore Function License Agreement, or other 
+-- applicable license agreement, including, without limitation, 
+-- that your use is for the sole purpose of programming logic 
+-- devices manufactured by Altera and sold by Altera or its 
+-- authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+-- PROGRAM		"Quartus Prime"
+-- VERSION		"Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
+-- CREATED		"Sat Nov 04 12:08:17 2017"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY Archit_Comandos_CPLD_CTRL IS 
+	PORT
+	(
+		GCLK :  IN  STD_LOGIC;
+		CMD_CLK_PC :  IN  STD_LOGIC;
+		CMD_DATA_PC :  IN  STD_LOGIC;
+		RST_GENERAL :  IN  STD_LOGIC;
+		DATA_CMD_IN :  IN  STD_LOGIC_VECTOR(10 DOWNTO 0);
+		DATA_RDY_Y :  OUT  STD_LOGIC;
+		Reset :  OUT  STD_LOGIC;
+		Enable :  OUT  STD_LOGIC;
+		OE :  OUT  STD_LOGIC;
+		LED1 :  OUT  STD_LOGIC;
+		LED2 :  OUT  STD_LOGIC;
+		DATA_CMD_Y :  OUT  STD_LOGIC_VECTOR(10 DOWNTO 0)
+	);
+END Archit_Comandos_CPLD_CTRL;
+
+ARCHITECTURE bdf_type OF Archit_Comandos_CPLD_CTRL IS 
+
+COMPONENT cmd_cpld_ctrl
+	PORT(GCLK : IN STD_LOGIC;
+		 DATA_RDY_X : IN STD_LOGIC;
+		 DATA_CMD_X : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+		 Reset : OUT STD_LOGIC;
+		 Enable : OUT STD_LOGIC;
+		 OE : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT cmd_interprete_sync
+	PORT(GCLK : IN STD_LOGIC;
+		 RST_gral : IN STD_LOGIC;
+		 CMD_CLK_PC : IN STD_LOGIC;
+		 CMD_DATA_PC : IN STD_LOGIC;
+		 DATA_CMD_IN : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+		 DATA_RDY_X : OUT STD_LOGIC;
+		 DATA_RDY_Y : OUT STD_LOGIC;
+		 LED_1 : OUT STD_LOGIC;
+		 LED_2 : OUT STD_LOGIC;
+		 DATA_CMD_X : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+		 DATA_CMD_Y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
+	);
+END COMPONENT;
+
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(10 DOWNTO 0);
+
+
+BEGIN 
+
+
+
+b2v_inst1 : cmd_cpld_ctrl
+PORT MAP(GCLK => GCLK,
+		 DATA_RDY_X => SYNTHESIZED_WIRE_0,
+		 DATA_CMD_X => SYNTHESIZED_WIRE_1,
+		 Reset => Reset,
+		 Enable => Enable,
+		 OE => OE);
+
+
+b2v_inst3 : cmd_interprete_sync
+PORT MAP(GCLK => GCLK,
+		 RST_gral => RST_GENERAL,
+		 CMD_CLK_PC => CMD_CLK_PC,
+		 CMD_DATA_PC => CMD_DATA_PC,
+		 DATA_CMD_IN => DATA_CMD_IN,
+		 DATA_RDY_X => SYNTHESIZED_WIRE_0,
+		 DATA_RDY_Y => DATA_RDY_Y,
+		 LED_1 => LED1,
+		 LED_2 => LED2,
+		 DATA_CMD_X => SYNTHESIZED_WIRE_1,
+		 DATA_CMD_Y => DATA_CMD_Y);
+
+
+END bdf_type;
\ No newline at end of file
diff --git a/CPLD_CTRL/Buffer_Bidireccional.bsf b/CPLD_CTRL/Buffer_Bidireccional.bsf
new file mode 100644
index 0000000..3493cff
--- /dev/null
+++ b/CPLD_CTRL/Buffer_Bidireccional.bsf
@@ -0,0 +1,63 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 264 112)
+	(text "Buffer_Bidireccional" (rect 5 0 104 12)(font "Arial" ))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "Data_Adq[width..0]" (rect 0 0 93 12)(font "Arial" ))
+		(text "Data_Adq[width..0]" (rect 21 27 114 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "OE" (rect 0 0 15 12)(font "Arial" ))
+		(text "OE" (rect 21 43 36 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 248 32)
+		(output)
+		(text "Data_Cmd[width..0]" (rect 0 0 97 12)(font "Arial" ))
+		(text "Data_Cmd[width..0]" (rect 130 27 227 39)(font "Arial" ))
+		(line (pt 248 32)(pt 232 32)(line_width 3))
+	)
+	(port
+		(pt 248 48)
+		(bidir)
+		(text "Data_ni[width..0]" (rect 0 0 82 12)(font "Arial" ))
+		(text "Data_ni[width..0]" (rect 145 43 227 55)(font "Arial" ))
+		(line (pt 248 48)(pt 232 48)(line_width 3))
+	)
+	(parameter
+		"width"
+		"31"
+		""
+	)
+	(drawing
+		(rectangle (rect 16 16 232 80)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 264 -64 364 16))
+)
diff --git a/CPLD_CTRL/Buffer_Bidireccional.vhd b/CPLD_CTRL/Buffer_Bidireccional.vhd
new file mode 100644
index 0000000..cf660fe
--- /dev/null
+++ b/CPLD_CTRL/Buffer_Bidireccional.vhd
@@ -0,0 +1,24 @@
+----buffer bidireccional,  
+----02 de noviembre 2009
+----Autor: Rita Abad
+--------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+entity Buffer_Bidireccional is
+  generic (width : natural := 31);      -- Width of buffer
+  port (Data_Adq :in    std_logic_vector ( width downto 0 );  -- input data
+        Data_Cmd :out   std_logic_vector ( width downto 0 );  -- Output data
+        Data_ni  :inout std_logic_vector ( width downto 0 ):=(others=>'0');  -- Bidirectional pin
+        OE       :in    std_ulogic);   -- Output Enable
+end Buffer_Bidireccional;
+
+architecture RTL of Buffer_Bidireccional is
+
+begin  -- RTL
+  Data_ni <= Data_Adq when ( OE = '1' ) else
+          ( others => 'Z' ); 
+  Data_Cmd <= Data_ni;
+end RTL;
diff --git a/CPLD_CTRL/CMD_CPLD_CTRL.bsf b/CPLD_CTRL/CMD_CPLD_CTRL.bsf
new file mode 100644
index 0000000..862d08d
--- /dev/null
+++ b/CPLD_CTRL/CMD_CPLD_CTRL.bsf
@@ -0,0 +1,71 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2007 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 208 112)
+	(text "CMD_CPLD_CTRL" (rect 5 0 99 12)(font "Arial" ))
+	(text "inst" (rect 8 80 25 92)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "GCLK" (rect 0 0 29 12)(font "Arial" ))
+		(text "GCLK" (rect 21 27 50 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "DATA_CMD_X[10..0]" (rect 0 0 102 12)(font "Arial" ))
+		(text "DATA_CMD_X[10..0]" (rect 21 43 123 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "DATA_RDY_X" (rect 0 0 70 12)(font "Arial" ))
+		(text "DATA_RDY_X" (rect 21 59 91 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 192 32)
+		(output)
+		(text "Reset" (rect 0 0 29 12)(font "Arial" ))
+		(text "Reset" (rect 142 27 171 39)(font "Arial" ))
+		(line (pt 192 32)(pt 176 32)(line_width 1))
+	)
+	(port
+		(pt 192 48)
+		(output)
+		(text "Enable" (rect 0 0 33 12)(font "Arial" ))
+		(text "Enable" (rect 138 43 171 55)(font "Arial" ))
+		(line (pt 192 48)(pt 176 48)(line_width 1))
+	)
+	(port
+		(pt 192 64)
+		(output)
+		(text "OE" (rect 0 0 15 12)(font "Arial" ))
+		(text "OE" (rect 156 59 171 71)(font "Arial" ))
+		(line (pt 192 64)(pt 176 64)(line_width 1))
+	)
+	(drawing
+		(rectangle (rect 16 16 176 80)(line_width 1))
+	)
+)
diff --git a/CPLD_CTRL/CMD_CPLD_CTRL.vhd b/CPLD_CTRL/CMD_CPLD_CTRL.vhd
new file mode 100644
index 0000000..aa898fe
--- /dev/null
+++ b/CPLD_CTRL/CMD_CPLD_CTRL.vhd
@@ -0,0 +1,95 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+	
+entity CMD_CPLD_CTRL is
+port(
+	--input de la NIDAQ
+		GCLK:in			std_logic;
+		DATA_CMD_X:in	std_logic_vector(10 downto 0);
+		DATA_RDY_X:in 	std_logic;
+	--output al bloque FIFODCLK		
+		Reset:out std_logic:='1';	
+		Enable:out	std_logic:='0';
+		OE:out			std_logic:='0'--si esta en '0' cuando programa, '1' cuando transfiere datos.
+);
+end CMD_CPLD_CTRL;
+
+architecture ROJ of CMD_CPLD_CTRL is
+type State is (Init1_CMD,Init2_CMD,Wait1_Init_CMD,Wait2_Init_CMD,Reset_S,Enable_S,Disable_S);
+signal MyState:State;
+signal DATA_CMD_CTRL: std_logic_vector(6 downto 0);
+signal DATA_SIZE_CTRL: std_logic_vector(10 downto 0);
+signal i: std_logic_vector(10 downto 0):="00000000000";
+begin
+
+PROCESO_CMD_CTRL:
+process(gclk)
+begin
+	if rising_edge(GCLK) then
+		case MyState is
+			when Init1_CMD=>
+				if  DATA_RDY_X='1' then					
+					DATA_CMD_CTRL<=	DATA_CMD_X(10 downto 4);			
+					MyState<=Init2_CMD;
+					i<="00000000000";
+					OE<='0';
+				end if;
+			when Init2_CMD=>
+				if  DATA_RDY_X='1' then					
+					DATA_SIZE_CTRL<=DATA_CMD_X(10 downto 0);		--Nota de Pedro:Aparentemente, el registro DATA_CMD_X es una se�al interna de 	
+					MyState<=Wait1_Init_CMD;						--ayuda de comunicacion que puede tener dos naturalezas. En el estado "Init1_CMD"
+					OE<='0';										--me pasa la informacion del comando que se se ha recibido. En el estado "Init2_CMD"
+				end if;												--sirve para poder pasar el tama�o de la cantidad de palabras de 11 bits que se enviaran									
+			when Wait1_Init_CMD=>									--por el puerto de datos del NIDAQ. Notar como cambia de un momento a otro.
+				if (DATA_CMD_CTRL(4 downto 1)="0101") then
+					MyState<=Reset_S;
+					Enable<='0';
+					Reset<='1';
+					OE<='0';		
+				elsif (DATA_CMD_CTRL(4 downto 1)="1010") then
+					MyState<=Enable_S;
+					Enable<='1';
+					Reset<='0';
+					OE<='1';		
+				elsif (DATA_CMD_CTRL(4 downto 1)="1011") then
+					MyState<=Disable_S;
+					Enable<='0';
+					Reset<='1';	--Nota PEdro: OE?????????
+					OE<='0';							
+				else
+					MyState<=Init1_CMD;				
+				end if;
+			when Reset_S=>
+				if (DATA_CMD_CTRL(0)='0' or DATA_SIZE_CTRL="00000000000") then
+					MyState<=Init1_CMD;
+				else
+					MyState<=Wait2_Init_CMD;				
+				end if;
+			when Enable_S=>
+				if (DATA_CMD_CTRL(0)='0' or DATA_SIZE_CTRL="00000000000") then
+					MyState<=Init1_CMD;
+				else
+					MyState<=Wait2_Init_CMD;				
+				end if;
+			when Disable_S=>
+				if (DATA_CMD_CTRL(0)='0' or DATA_SIZE_CTRL="00000000000") then
+					MyState<=Init1_CMD;
+				else
+					MyState<=Wait2_Init_CMD;				
+				end if;					
+			when Wait2_Init_CMD=>									
+				if  (i>=DATA_SIZE_CTRL) then				
+					i<="00000000000";
+					MyState<=Init1_CMD;	
+				else
+					MyState<=Wait2_Init_CMD;
+						if DATA_RDY_X='1' then	
+							i<=i+1;						
+						end if;
+				end if;				
+		end case;
+	end if;
+end process PROCESO_CMD_CTRL;
+
+end ROJ;
\ No newline at end of file
diff --git a/CPLD_CTRL/CMD_Interprete_Sync.bsf b/CPLD_CTRL/CMD_Interprete_Sync.bsf
new file mode 100644
index 0000000..8918fd9
--- /dev/null
+++ b/CPLD_CTRL/CMD_Interprete_Sync.bsf
@@ -0,0 +1,106 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 280 176)
+	(text "CMD_Interprete_Sync" (rect 5 0 114 12)(font "Arial" ))
+	(text "inst" (rect 8 144 25 156)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "GCLK" (rect 0 0 29 12)(font "Arial" ))
+		(text "GCLK" (rect 21 27 50 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "RST_gral" (rect 0 0 44 12)(font "Arial" ))
+		(text "RST_gral" (rect 21 43 65 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "CMD_CLK_PC" (rect 0 0 73 12)(font "Arial" ))
+		(text "CMD_CLK_PC" (rect 21 59 94 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "CMD_DATA_PC" (rect 0 0 80 12)(font "Arial" ))
+		(text "CMD_DATA_PC" (rect 21 75 101 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "DATA_CMD_IN[10..0]" (rect 0 0 108 12)(font "Arial" ))
+		(text "DATA_CMD_IN[10..0]" (rect 21 91 129 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 264 32)
+		(output)
+		(text "DATA_CMD_X[10..0]" (rect 0 0 102 12)(font "Arial" ))
+		(text "DATA_CMD_X[10..0]" (rect 141 27 243 39)(font "Arial" ))
+		(line (pt 264 32)(pt 248 32)(line_width 3))
+	)
+	(port
+		(pt 264 48)
+		(output)
+		(text "DATA_RDY_X" (rect 0 0 70 12)(font "Arial" ))
+		(text "DATA_RDY_X" (rect 173 43 243 55)(font "Arial" ))
+		(line (pt 264 48)(pt 248 48)(line_width 1))
+	)
+	(port
+		(pt 264 64)
+		(output)
+		(text "DATA_RDY_Y" (rect 0 0 73 12)(font "Arial" ))
+		(text "DATA_RDY_Y" (rect 170 59 243 71)(font "Arial" ))
+		(line (pt 264 64)(pt 248 64)(line_width 1))
+	)
+	(port
+		(pt 264 80)
+		(output)
+		(text "LED_1" (rect 0 0 33 12)(font "Arial" ))
+		(text "LED_1" (rect 210 75 243 87)(font "Arial" ))
+		(line (pt 264 80)(pt 248 80)(line_width 1))
+	)
+	(port
+		(pt 264 96)
+		(output)
+		(text "LED_2" (rect 0 0 33 12)(font "Arial" ))
+		(text "LED_2" (rect 210 91 243 103)(font "Arial" ))
+		(line (pt 264 96)(pt 248 96)(line_width 1))
+	)
+	(port
+		(pt 264 112)
+		(output)
+		(text "DATA_CMD_Y[10..0]" (rect 0 0 105 12)(font "Arial" ))
+		(text "DATA_CMD_Y[10..0]" (rect 138 107 243 119)(font "Arial" ))
+		(line (pt 264 112)(pt 248 112)(line_width 3))
+	)
+	(drawing
+		(rectangle (rect 16 16 248 144)(line_width 1))
+	)
+)
diff --git a/CPLD_CTRL/CMD_Interprete_Sync.vhd b/CPLD_CTRL/CMD_Interprete_Sync.vhd
new file mode 100644
index 0000000..e1b5d1b
--- /dev/null
+++ b/CPLD_CTRL/CMD_Interprete_Sync.vhd
@@ -0,0 +1,237 @@
+--Descripci�n de la l�gica de interpretaci�n de los comandos provenientes
+--de la PC, 
+--Indica si la trama enviada es v�lida para leer informaci�n
+--pues detecta la se�al synchro que envia la PC
+--son de 22 bits el tama�o de la linea de comandos
+-------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity CMD_Interprete_Sync is
+port(
+	--Input 
+	GCLK:in			std_logic;--clock de 60 MHZ que que envia el Controlador de Radar
+	RST_gral:in 	std_logic;--RST general fisico para empezar todo el proceso
+	CMD_CLK_PC:in	std_logic;--Hablitador que indica en '1' que la PC esta enviando data v�lida para capturar
+	CMD_DATA_PC:in	std_logic;--comandos que van hacer enviados de manera serial 
+	DATA_CMD_IN:in	std_logic_vector(10 downto 0);--data q ingresa por el bus de datos de la NIDAQ
+	--Ouput
+	DATA_CMD_X:out	std_logic_vector(10 downto 0):=(others=>'0');--comandos de 11 bits que son enviados al CPLD De control
+	DATA_RDY_X:out	std_logic:='0';--RDY de la data de comandos que son enviados al CPLD de Control
+	DATA_RDY_Y:out	std_logic:='0';--comandos de 11 bits que son enviados al CPLD Hijo y Papi
+	LED_1:out 		std_logic:='0';--led para indicar que se ha iniciado la comunicaci�n
+	LED_2:out 		std_logic:='0';--led para indicar que se ha iniciado la comunicaci�n	
+	DATA_CMD_Y:out	std_logic_vector(10 downto 0):=(others=>'0')--RDY de la data de comandos que son enviados CPLD Hijo y Papi
+		
+);
+end CMD_Interprete_Sync;
+
+architecture ROJ of CMD_Interprete_Sync is
+signal CMD_CLK_PC_aux	: std_logic;
+signal EN				: std_logic;
+signal EN_aux			: std_logic;
+
+signal CMD_CPLDS		: std_logic_vector(17 downto 0);---vector que guarda los comandos que llegan de manera serial,
+														---ya no se guarda el synchro de 4 bits, por eso vemos un vector
+														---de 18 bits y no de 22 bits
+signal DATA_CMD			: std_logic_vector(10 downto 0):=(others =>'0');---la data de 18 bits se va a segmentar en 11 bits, por ahi va ser0
+														---enviada, tb se sa para enviar los par�metros del filtro
+signal DATA_RDY			: std_logic:='0';--se�al  de un ciclo de reloj que indica cuando 
+									--DATA_CMD es v�lida
+signal Reset_Synchro	: std_logic;
+
+signal s				: std_logic_vector(21 downto 0);--se�al de 22 bits, donde se guarda en forma paralela la data de 
+													--comandos en modo serial 
+signal synchro			: std_logic_vector(3 downto 0);---se�al que guarada la se�al "0101" enviada desde la PC en forma
+												   ---serial
+signal i				: std_logic_vector(10 downto 0):="00000000000";--contador que se va encargar de comparar
+
+
+signal CMD_CLK_PC_reg : std_logic;--Hablitador que indica en '1' que la PC esta enviando data v�lida para capturar
+signal CMD_DATA_PC_reg : std_logic;--comandos que van hacer enviados de manera serial 
+signal DATA_CMD_IN_reg : std_logic_vector(10 downto 0);--data q ingresa por el bus de datos de la NIDAQ
+--------------------------------------------------------------------------------------
+type state is (Init,Select_Port,Wait_Store_Data_CMD,Wait_By_Port,By_Port,Wait_EN,
+				Store_Data_CMD,Store_Data_SIZE,Store_Data,By_Data_1);
+signal MyState:state;
+
+begin
+
+process(GCLK)
+begin
+	if rising_edge(GCLK) then
+		CMD_CLK_PC_reg <= CMD_CLK_PC;
+		CMD_DATA_PC_reg <= CMD_DATA_PC;
+		DATA_CMD_IN_reg <= DATA_CMD_IN;
+	end if;
+end process;
+
+process(GCLK)
+begin
+	if rising_edge(GCLK) then
+		if (RST_gral='1') then		
+			CMD_CLK_PC_aux<=CMD_CLK_PC_reg;
+			EN_aux<=not CMD_CLK_PC_aux;
+		end if;
+	end if;
+end process;
+
+EN<=EN_aux and CMD_CLK_PC_aux;
+
+-------------------------------------------------------------------------------------
+--Check de la salida de EN, pulso genera por el reloj de comando enviado desde la PC
+--solo dura un ciclo de reloj de 60 MHz. 
+-------------------------------------------------------------------------------------
+--Para el control del puerto de comandos, siempre que se va utilizar
+--va requerir del synchro ya definido
+--solo puerto serial
+-------------------------------------------------------------------------------------
+
+process(GCLK)
+begin
+	if rising_edge(GCLK) then
+		if (RST_gral='1') then		
+			if Reset_Synchro='0' then
+				if (EN = '1') then
+				s<= s(20 downto 0)& CMD_DATA_PC_reg;
+				end if;
+			else
+				s<=(others=>'0');
+			end if;				
+		end if;
+	end if;
+end process;
+
+-----------------------------------------------------------------------------------
+--Aqui abajo se define la posicion de como se van guardando la l�nea de comandos
+--de forma serial a paralela 
+synchro<=s(21 downto 18);
+--chip<=s(17 downto 16);
+--cmd<=s(15 downto 12);
+--flag<=s(11);
+--size<=s(10 downto 0);				
+------------------------------------------------------------------------------------
+
+PROCESO_INTERPRETE:
+process(GCLK)
+begin
+if rising_edge(GCLK)then
+	if(RST_gral='1') then
+		case MyState is
+			when Init=>
+				if synchro="0101" then
+					MyState<=Select_Port;	
+					Reset_Synchro<='1';
+					CMD_CPLDS<=s(17 downto 0);--signal interna q guarda los datos;			
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';	
+					LED_1<='1';
+				else
+					MyState<=Init;	
+					Reset_Synchro<='0';		
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';			
+					LED_1<='0';
+				end if;	
+			when Select_Port=>
+					MyState<=Wait_Store_Data_CMD;				
+					Reset_Synchro<='1';								
+					DATA_CMD<=CMD_CPLDS(17 downto 7);
+					Data_RDY<='1';	
+			when Wait_Store_Data_CMD=>
+					MyState<=Store_Data_CMD;				
+					Reset_Synchro<='1';												
+					Data_RDY<='0';		
+			when Store_Data_CMD=>			
+					MyState<=Wait_By_Port;				
+					Reset_Synchro<='1';								
+					DATA_CMD<=CMD_CPLDS(10 downto 0);
+					Data_RDY<='1';
+			when Wait_By_Port=>				
+					MyState<=By_Port;				
+					Reset_Synchro<='1';												
+					Data_RDY<='0';
+			when By_Port=>
+				if ((CMD_CPLDS(11)='1') and (CMD_CPLDS(10 downto 0)/= "00000000000"))  then
+					MyState<=Store_Data_SIZE;
+					Reset_Synchro<='1';					
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';		
+				else
+					MyState<=Init;	
+					Reset_Synchro<='0';		
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';						
+				end if;		
+			when Store_Data_SIZE=>
+				if EN='1' then
+					MyState<=Store_Data;				
+					Reset_Synchro<='1';		
+					i<=i+1;
+					DATA_CMD<=DATA_CMD_IN_reg;
+					Data_RDY<='1';	
+				else
+					Data_RDY<='0';														
+				end if;			
+			when Store_Data=>
+					MyState<=Wait_EN;
+					Reset_Synchro<='1';			
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';									
+			when Wait_EN=>
+				if (i<CMD_CPLDS(10 downto 0)) then
+					if EN='0' then				
+						MyState<=By_Data_1;
+					else				
+						MyState<=Wait_EN;
+					end if;							
+				else
+					MyState<=Init;
+					i<=(others=>'0');
+					Reset_Synchro<='0';			
+					DATA_CMD<=(others=>'0');
+					Data_RDY<='0';					
+				end if;		
+			when By_Data_1=>
+				if EN='1' then
+					MyState<=Store_Data;
+					i<=i+1;				
+					Reset_Synchro<='1';	
+					DATA_CMD<=DATA_CMD_IN_reg;
+					Data_RDY<='1';	
+					LED_2<='1';
+				else
+					Data_RDY<='0';														
+					LED_2<='0';
+				end if;
+		end case;
+	end if;
+end if;
+end process PROCESO_INTERPRETE;
+
+process(GCLK)
+begin
+if rising_edge(GCLK) then
+	if (RST_gral='1') then
+		if (CMD_CPLDS(17 downto 16)="00") then
+				DATA_CMD_Y<=DATA_CMD;
+				Data_RDY_Y<=Data_RDY;
+				DATA_CMD_X<=DATA_CMD;
+				Data_RDY_X<=Data_RDY;
+		elsif (CMD_CPLDS(17 downto 16)="01") then
+				DATA_CMD_X<=DATA_CMD;
+				Data_RDY_X<=Data_RDY;	
+				DATA_CMD_Y<=(others=>'0');
+				Data_RDY_Y<='0';	
+		else
+				DATA_CMD_X<=(others=>'0');
+				Data_RDY_X<='0';		
+				DATA_CMD_Y<=DATA_CMD;
+				Data_RDY_Y<=Data_RDY;
+		end if;
+	end if;
+end if;
+end process;
+
+end ROJ;
diff --git a/CPLD_CTRL/CPLD_CTRL.bdf b/CPLD_CTRL/CPLD_CTRL.bdf
new file mode 100644
index 0000000..60fe4e3
--- /dev/null
+++ b/CPLD_CTRL/CPLD_CTRL.bdf
@@ -0,0 +1,656 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, the Altera Quartus Prime License Agreement,
+the Altera MegaCore Function License Agreement, or other 
+applicable license agreement, including, without limitation, 
+that your use is for the sole purpose of programming logic 
+devices manufactured by Altera and sold by Altera or its 
+authorized distributors.  Please refer to the applicable 
+agreement for further details.
+*/
+//#pragma file_not_in_maxplusii_format
+(header "graphic" (version "1.4"))
+(pin
+	(input)
+	(rect 40 48 208 64)
+	(text "INPUT" (rect 133 0 174 11)(font "Arial" (font_size 6)))
+	(text "GCLK" (rect 9 0 42 14)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
+		(line (pt 121 8)(pt 168 8))
+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 160 18)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -72 32 -24 48))
+)
+(pin
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+	(text "INPUT" (rect 133 0 174 11)(font "Arial" (font_size 6)))
+	(text "CMD_CLK_PC" (rect 9 0 91 14)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
+		(line (pt 92 4)(pt 117 4))
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+		(line (pt 92 12)(pt 92 4))
+		(line (pt 117 4)(pt 121 8))
+		(line (pt 117 12)(pt 121 8))
+	)
+	(text "VCC" (rect 136 7 160 18)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -88 88 8 104))
+)
+(pin
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+	(text "INPUT" (rect 133 0 174 11)(font "Arial" (font_size 6)))
+	(text "CMD_DATA_PC" (rect 9 0 99 14)(font "Arial" ))
+	(pt 168 8)
+	(drawing
+		(line (pt 92 12)(pt 117 12))
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+	)
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+	(annotation_block (location)(rect -96 112 0 128))
+)
+(pin
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+	(text "PCLK1" (rect 9 0 50 14)(font "Arial" ))
+	(pt 168 8)
+	(drawing
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+	)
+	(text "VCC" (rect 136 7 160 18)(font "Arial" (font_size 6)))
+	(annotation_block (location)(rect -64 464 -16 480))
+)
+(pin
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+	(text "DataIn[31..0]" (rect 9 0 116 14)(font "Arial" ))
+	(pt 168 8)
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+)
+(pin
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+	(text "REQ2" (rect 9 0 42 14)(font "Arial" ))
+	(pt 168 8)
+	(drawing
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+)
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+	(text "ACK1" (rect 9 0 42 14)(font "Arial" ))
+	(pt 168 8)
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+	(text "VCC" (rect 136 7 160 18)(font "Arial" (font_size 6)))
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+	(text "RST_GENERAL" (rect 9 0 99 14)(font "Arial" ))
+	(pt 168 8)
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+	(text "RDY_WR_CTRL[1..0]" (rect 9 0 149 14)(font "Arial" ))
+	(pt 168 8)
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+	)
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+		(text "GCLK" (rect 21 43 54 57)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Reset" (rect 0 0 41 14)(font "Arial" ))
+		(text "Reset" (rect 21 59 62 73)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "Enable" (rect 0 0 49 14)(font "Arial" ))
+		(text "Enable" (rect 21 75 70 89)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "DataRDY[1..0]" (rect 0 0 107 14)(font "Arial" ))
+		(text "DataRDY[1..0]" (rect 21 91 128 105)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "DataIn[bits-1..0]" (rect 0 0 140 14)(font "Arial" ))
+		(text "DataIn[bits-1..0]" (rect 21 107 161 121)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 224 32)
+		(output)
+		(text "REQ" (rect 0 0 24 14)(font "Arial" ))
+		(text "REQ" (rect 180 27 204 41)(font "Arial" ))
+		(line (pt 224 32)(pt 208 32))
+	)
+	(port
+		(pt 224 48)
+		(output)
+		(text "DataOut[bits-1..0]" (rect 0 0 148 14)(font "Arial" ))
+		(text "DataOut[bits-1..0]" (rect 115 43 263 57)(font "Arial" ))
+		(line (pt 224 48)(pt 208 48)(line_width 3))
+	)
+	(parameter
+		"BITS"
+		"32"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"WORDS"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 208 144))
+	)
+	(annotation_block (parameter)(rect 456 416 748 479))
+)
+(connector
+	(pt 224 56)
+	(pt 208 56)
+)
+(connector
+	(text "Data_Adq[31..0]" (rect 130 288 253 302)(font "Arial" ))
+	(pt 128 304)
+	(pt 224 304)
+	(bus)
+)
+(connector
+	(text "OE" (rect 154 304 170 318)(font "Arial" ))
+	(pt 144 320)
+	(pt 224 320)
+)
+(connector
+	(text "Reset" (rect 530 40 571 54)(font "Arial" ))
+	(pt 520 56)
+	(pt 584 56)
+)
+(connector
+	(text "Enable" (rect 530 56 579 70)(font "Arial" ))
+	(pt 520 72)
+	(pt 584 72)
+)
+(connector
+	(text "OE" (rect 530 72 546 86)(font "Arial" ))
+	(pt 520 88)
+	(pt 600 88)
+)
+(connector
+	(pt 520 104)
+	(pt 568 104)
+)
+(connector
+	(text "Data_Comandos[31..0]" (rect 472 288 637 302)(font "Arial" ))
+	(pt 472 304)
+	(pt 536 304)
+	(bus)
+)
+(connector
+	(pt 472 320)
+	(pt 552 320)
+	(bus)
+)
+(connector
+	(pt 224 88)
+	(pt 208 88)
+)
+(connector
+	(pt 224 104)
+	(pt 208 104)
+)
+(connector
+	(text "Data_Comandos[10..0]" (rect 98 128 263 142)(font "Arial" ))
+	(pt 88 120)
+	(pt 224 120)
+	(bus)
+)
+(connector
+	(pt 224 72)
+	(pt 208 72)
+)
+(connector
+	(pt 520 152)
+	(pt 568 152)
+	(bus)
+)
+(connector
+	(pt 568 120)
+	(pt 520 120)
+)
+(connector
+	(pt 520 136)
+	(pt 568 136)
+)
+(connector
+	(pt 448 504)
+	(pt 448 496)
+)
+(connector
+	(pt 456 504)
+	(pt 448 504)
+)
+(connector
+	(pt 448 496)
+	(pt 456 496)
+)
+(connector
+	(text "GCLK" (rect 186 496 219 510)(font "Arial" ))
+	(pt 176 512)
+	(pt 232 512)
+)
+(connector
+	(text "Reset" (rect 170 512 211 526)(font "Arial" ))
+	(pt 160 528)
+	(pt 232 528)
+)
+(connector
+	(text "Enable" (rect 170 528 219 542)(font "Arial" ))
+	(pt 160 544)
+	(pt 232 544)
+)
+(connector
+	(text "Data_Adq[31..0]" (rect 474 520 597 534)(font "Arial" ))
+	(pt 456 512)
+	(pt 560 512)
+	(bus)
+)
+(connector
+	(pt 168 504)
+	(pt 168 496)
+)
+(connector
+	(pt 160 504)
+	(pt 168 504)
+)
+(connector
+	(pt 168 496)
+	(pt 232 496)
+)
+(connector
+	(pt 176 568)
+	(pt 176 560)
+	(bus)
+)
+(connector
+	(pt 168 568)
+	(pt 176 568)
+	(bus)
+)
+(connector
+	(pt 176 560)
+	(pt 232 560)
+	(bus)
+)
+(connector
+	(pt 184 584)
+	(pt 184 576)
+	(bus)
+)
+(connector
+	(pt 160 584)
+	(pt 184 584)
+	(bus)
+)
+(connector
+	(pt 184 576)
+	(pt 232 576)
+	(bus)
+)
diff --git a/CPLD_CTRL/CPLD_CTRL.pof b/CPLD_CTRL/CPLD_CTRL.pof
new file mode 100644
index 0000000000000000000000000000000000000000..cd893990289e39f505ee59a2f5f10ed0fd6e839f
GIT binary patch
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z{cN;nM+;5Hzekss!TBLQ4|u<es7C*JPAyLXKl8@jAIl%~&sH-&5IahU#$n+n9h005
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t_WyGIm+SuruIGg6POknRVdmohpGN)V^Ow(GKL6i-PSO9bsBixEe*<fS(vJWD

literal 0
Hc$@<O00001

diff --git a/CPLD_CTRL/CPLD_CTRL.qpf b/CPLD_CTRL/CPLD_CTRL.qpf
new file mode 100644
index 0000000..3625a55
--- /dev/null
+++ b/CPLD_CTRL/CPLD_CTRL.qpf
@@ -0,0 +1,23 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+QUARTUS_VERSION = "7.2"
+DATE = "09:07:41  May 06, 2010"
+
+
+# Revisions
+
+PROJECT_REVISION = "CPLD_CTRL"
diff --git a/CPLD_CTRL/CPLD_CTRL.qsf b/CPLD_CTRL/CPLD_CTRL.qsf
new file mode 100644
index 0000000..8b6fcbc
--- /dev/null
+++ b/CPLD_CTRL/CPLD_CTRL.qsf
@@ -0,0 +1,172 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		CPLD_CTRL_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "MAX II"
+set_global_assignment -name DEVICE EPM1270T144C5
+set_global_assignment -name TOP_LEVEL_ENTITY CPLD_CTRL
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:07:41  MAY 06, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION 16.0.0
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name VHDL_FILE CMD_Interprete_Sync.vhd
+set_global_assignment -name VHDL_FILE CMD_CPLD_CTRL.vhd
+set_global_assignment -name VHDL_FILE WR60RD20.vhd
+set_global_assignment -name VHDL_FILE Buffer_Bidireccional.vhd
+set_global_assignment -name BDF_FILE CPLD_CTRL.bdf
+set_global_assignment -name BDF_FILE Archit_Comandos_CPLD_CTRL.bdf
+set_location_assignment PIN_101 -to ACK1
+set_location_assignment PIN_95 -to aditional[27]
+set_location_assignment PIN_94 -to aditional[26]
+set_location_assignment PIN_93 -to aditional[25]
+set_location_assignment PIN_89 -to aditional[24]
+set_location_assignment PIN_88 -to aditional[23]
+set_location_assignment PIN_87 -to aditional[22]
+set_location_assignment PIN_86 -to aditional[21]
+set_location_assignment PIN_85 -to aditional[20]
+set_location_assignment PIN_104 -to aditional[19]
+set_location_assignment PIN_102 -to aditional[18]
+set_location_assignment PIN_80 -to aditional[17]
+set_location_assignment PIN_79 -to aditional[16]
+set_location_assignment PIN_78 -to aditional[15]
+set_location_assignment PIN_77 -to aditional[14]
+set_location_assignment PIN_76 -to aditional[13]
+set_location_assignment PIN_75 -to aditional[12]
+set_location_assignment PIN_74 -to aditional[11]
+set_location_assignment PIN_73 -to aditional[10]
+set_location_assignment PIN_72 -to aditional[9]
+set_location_assignment PIN_71 -to aditional[8]
+set_location_assignment PIN_70 -to aditional[7]
+set_location_assignment PIN_69 -to aditional[6]
+set_location_assignment PIN_68 -to aditional[5]
+set_location_assignment PIN_67 -to aditional[4]
+set_location_assignment PIN_48 -to aditional[3]
+set_location_assignment PIN_62 -to aditional[1]
+set_location_assignment PIN_103 -to CMD_CLK_PC
+set_location_assignment PIN_105 -to CMD_DATA_PC
+set_location_assignment PIN_49 -to DATA_CMD_Y[10]
+set_location_assignment PIN_50 -to DATA_CMD_Y[9]
+set_location_assignment PIN_51 -to DATA_CMD_Y[8]
+set_location_assignment PIN_52 -to DATA_CMD_Y[7]
+set_location_assignment PIN_53 -to DATA_CMD_Y[6]
+set_location_assignment PIN_55 -to DATA_CMD_Y[5]
+set_location_assignment PIN_57 -to DATA_CMD_Y[4]
+set_location_assignment PIN_58 -to DATA_CMD_Y[3]
+set_location_assignment PIN_59 -to DATA_CMD_Y[2]
+set_location_assignment PIN_60 -to DATA_CMD_Y[1]
+set_location_assignment PIN_66 -to DATA_CMD_Y[0]
+set_location_assignment PIN_63 -to DATA_RDY_Y
+set_location_assignment PIN_18 -to GCLK
+set_location_assignment PIN_144 -to Data_ni[31]
+set_location_assignment PIN_143 -to Data_ni[30]
+set_location_assignment PIN_140 -to Data_ni[29]
+set_location_assignment PIN_142 -to Data_ni[28]
+set_location_assignment PIN_141 -to Data_ni[27]
+set_location_assignment PIN_138 -to Data_ni[26]
+set_location_assignment PIN_137 -to Data_ni[25]
+set_location_assignment PIN_139 -to Data_ni[24]
+set_location_assignment PIN_134 -to Data_ni[23]
+set_location_assignment PIN_133 -to Data_ni[22]
+set_location_assignment PIN_130 -to Data_ni[21]
+set_location_assignment PIN_132 -to Data_ni[20]
+set_location_assignment PIN_131 -to Data_ni[19]
+set_location_assignment PIN_127 -to Data_ni[18]
+set_location_assignment PIN_125 -to Data_ni[17]
+set_location_assignment PIN_129 -to Data_ni[16]
+set_location_assignment PIN_124 -to Data_ni[15]
+set_location_assignment PIN_123 -to Data_ni[14]
+set_location_assignment PIN_122 -to Data_ni[13]
+set_location_assignment PIN_121 -to Data_ni[12]
+set_location_assignment PIN_120 -to Data_ni[11]
+set_location_assignment PIN_119 -to Data_ni[10]
+set_location_assignment PIN_118 -to Data_ni[9]
+set_location_assignment PIN_117 -to Data_ni[8]
+set_location_assignment PIN_114 -to Data_ni[7]
+set_location_assignment PIN_113 -to Data_ni[6]
+set_location_assignment PIN_112 -to Data_ni[5]
+set_location_assignment PIN_111 -to Data_ni[4]
+set_location_assignment PIN_110 -to Data_ni[3]
+set_location_assignment PIN_109 -to Data_ni[2]
+set_location_assignment PIN_108 -to Data_ni[1]
+set_location_assignment PIN_107 -to Data_ni[0]
+set_location_assignment PIN_44 -to DataIn[31]
+set_location_assignment PIN_42 -to DataIn[30]
+set_location_assignment PIN_40 -to DataIn[29]
+set_location_assignment PIN_38 -to DataIn[28]
+set_location_assignment PIN_32 -to DataIn[27]
+set_location_assignment PIN_30 -to DataIn[26]
+set_location_assignment PIN_28 -to DataIn[25]
+set_location_assignment PIN_24 -to DataIn[24]
+set_location_assignment PIN_22 -to DataIn[23]
+set_location_assignment PIN_20 -to DataIn[22]
+set_location_assignment PIN_15 -to DataIn[21]
+set_location_assignment PIN_13 -to DataIn[20]
+set_location_assignment PIN_11 -to DataIn[19]
+set_location_assignment PIN_7 -to DataIn[18]
+set_location_assignment PIN_5 -to DataIn[17]
+set_location_assignment PIN_3 -to DataIn[16]
+set_location_assignment PIN_45 -to DataIn[15]
+set_location_assignment PIN_43 -to DataIn[14]
+set_location_assignment PIN_41 -to DataIn[13]
+set_location_assignment PIN_39 -to DataIn[12]
+set_location_assignment PIN_37 -to DataIn[11]
+set_location_assignment PIN_31 -to DataIn[10]
+set_location_assignment PIN_29 -to DataIn[9]
+set_location_assignment PIN_27 -to DataIn[8]
+set_location_assignment PIN_23 -to DataIn[7]
+set_location_assignment PIN_21 -to DataIn[6]
+set_location_assignment PIN_16 -to DataIn[5]
+set_location_assignment PIN_14 -to DataIn[4]
+set_location_assignment PIN_12 -to DataIn[3]
+set_location_assignment PIN_8 -to DataIn[2]
+set_location_assignment PIN_6 -to DataIn[1]
+set_location_assignment PIN_4 -to DataIn[0]
+set_location_assignment PIN_91 -to PCLK1
+set_location_assignment PIN_98 -to Req
+set_location_assignment PIN_106 -to REQ2
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_61 -to RST_GENERAL
+set_location_assignment PIN_1 -to RDY_WR_CTRL[1]
+set_location_assignment PIN_2 -to RDY_WR_CTRL[0]
+set_location_assignment PIN_81 -to LED1
+set_location_assignment PIN_84 -to LED2
+set_location_assignment PIN_96 -to aditional[0]
+set_location_assignment PIN_97 -to aditional[2]
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 5
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH tb_CPLD_CTRL -section_id eda_simulation
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME tb_CPLD_CTRL -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id tb_CPLD_CTRL
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME tb_CPLD_CTRL -section_id tb_CPLD_CTRL
+set_global_assignment -name EDA_TEST_BENCH_FILE simulation/modelsim/CPLD_CTRL.vht -section_id tb_CPLD_CTRL
\ No newline at end of file
diff --git a/CPLD_CTRL/CPLD_CTRL.sdc b/CPLD_CTRL/CPLD_CTRL.sdc
new file mode 100644
index 0000000..570fd4d
--- /dev/null
+++ b/CPLD_CTRL/CPLD_CTRL.sdc
@@ -0,0 +1,109 @@
+## Generated SDC file "CPLD_TRANSFER.sdc"
+
+## Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, the Altera Quartus Prime License Agreement,
+## the Altera MegaCore Function License Agreement, or other 
+## applicable license agreement, including, without limitation, 
+## that your use is for the sole purpose of programming logic 
+## devices manufactured by Altera and sold by Altera or its 
+## authorized distributors.  Please refer to the applicable 
+## agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus Prime"
+## VERSION "Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
+
+## DATE    "Mon Jun 17 09:40:14 2019"
+
+##
+## DEVICE  "EPM1270T144C5"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+#create_clock -name {GCLK} -period 16.666 -waveform { 0.000 8.333 } [get_ports {GCLK}]
+create_clock -name {GCLK} -period 12.5 -waveform { 0.000 6.25 } [get_ports {GCLK}]
+create_clock -name {PCLK1} -period 12.5 -waveform { 0.000 6.25 } [get_ports {PCLK1}]
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+
diff --git a/CPLD_CTRL/CPLD_CTRL.vhd b/CPLD_CTRL/CPLD_CTRL.vhd
new file mode 100644
index 0000000..bf2c162
--- /dev/null
+++ b/CPLD_CTRL/CPLD_CTRL.vhd
@@ -0,0 +1,139 @@
+-- Copyright (C) 1991-2016 Altera Corporation. All rights reserved.
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, the Altera Quartus Prime License Agreement,
+-- the Altera MegaCore Function License Agreement, or other 
+-- applicable license agreement, including, without limitation, 
+-- that your use is for the sole purpose of programming logic 
+-- devices manufactured by Altera and sold by Altera or its 
+-- authorized distributors.  Please refer to the applicable 
+-- agreement for further details.
+
+-- PROGRAM		"Quartus Prime"
+-- VERSION		"Version 16.0.0 Build 211 04/27/2016 SJ Lite Edition"
+-- CREATED		"Sat Nov 04 12:09:00 2017"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY CPLD_CTRL IS 
+	PORT
+	(
+		GCLK :  IN  STD_LOGIC;
+		CMD_CLK_PC :  IN  STD_LOGIC;
+		CMD_DATA_PC :  IN  STD_LOGIC;
+		PCLK1 :  IN  STD_LOGIC;
+		REQ2 :  IN  STD_LOGIC;
+		ACK1 :  IN  STD_LOGIC;
+		RST_GENERAL :  IN  STD_LOGIC;
+		aditional :  IN  STD_LOGIC_VECTOR(27 DOWNTO 0);
+		Data_ni :  INOUT  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		DataIn :  IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
+		RDY_WR_CTRL :  IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
+		DATA_RDY_Y :  OUT  STD_LOGIC;
+		Req :  OUT  STD_LOGIC;
+		LED1 :  OUT  STD_LOGIC;
+		LED2 :  OUT  STD_LOGIC;
+		DATA_CMD_Y :  OUT  STD_LOGIC_VECTOR(10 DOWNTO 0)
+	);
+END CPLD_CTRL;
+
+ARCHITECTURE bdf_type OF CPLD_CTRL IS 
+
+COMPONENT wr60rd20
+GENERIC (BITS : INTEGER;
+			WORDS : INTEGER
+			);
+	PORT(PCLK1 : IN STD_LOGIC;
+		 GCLK : IN STD_LOGIC;
+		 Reset : IN STD_LOGIC;
+		 Enable : IN STD_LOGIC;
+		 DataIn : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 DataRDY : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 REQ : OUT STD_LOGIC;
+		 DataOut : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT archit_comandos_cpld_ctrl
+	PORT(GCLK : IN STD_LOGIC;
+		 RST_GENERAL : IN STD_LOGIC;
+		 CMD_CLK_PC : IN STD_LOGIC;
+		 CMD_DATA_PC : IN STD_LOGIC;
+		 DATA_CMD_IN : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+		 Reset : OUT STD_LOGIC;
+		 Enable : OUT STD_LOGIC;
+		 OE : OUT STD_LOGIC;
+		 DATA_RDY_Y : OUT STD_LOGIC;
+		 LED1 : OUT STD_LOGIC;
+		 LED2 : OUT STD_LOGIC;
+		 DATA_CMD_Y : OUT STD_LOGIC_VECTOR(10 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT buffer_bidireccional
+GENERIC (width : INTEGER
+			);
+	PORT(OE : IN STD_LOGIC;
+		 Data_Adq : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 Data_ni : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 Data_Cmd : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+SIGNAL	Data_Adq :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	Data_Comandos :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	Enable :  STD_LOGIC;
+SIGNAL	OE :  STD_LOGIC;
+SIGNAL	Reset :  STD_LOGIC;
+
+
+BEGIN 
+
+
+
+b2v_inst : wr60rd20
+GENERIC MAP(BITS => 32,
+			WORDS => 8
+			)
+PORT MAP(PCLK1 => PCLK1,
+		 GCLK => GCLK,
+		 Reset => Reset,
+		 Enable => Enable,
+		 DataIn => DataIn,
+		 DataRDY => RDY_WR_CTRL,
+		 REQ => Req,
+		 DataOut => Data_Adq);
+
+
+b2v_inst2 : archit_comandos_cpld_ctrl
+PORT MAP(GCLK => GCLK,
+		 RST_GENERAL => RST_GENERAL,
+		 CMD_CLK_PC => CMD_CLK_PC,
+		 CMD_DATA_PC => CMD_DATA_PC,
+		 DATA_CMD_IN => Data_Comandos(10 DOWNTO 0),
+		 Reset => Reset,
+		 Enable => Enable,
+		 OE => OE,
+		 DATA_RDY_Y => DATA_RDY_Y,
+		 LED1 => LED1,
+		 LED2 => LED2,
+		 DATA_CMD_Y => DATA_CMD_Y);
+
+
+b2v_inst3 : buffer_bidireccional
+GENERIC MAP(width => 31
+			)
+PORT MAP(OE => OE,
+		 Data_Adq => Data_Adq,
+		 Data_ni => Data_ni,
+		 Data_Cmd => Data_Comandos);
+
+
+END bdf_type;
\ No newline at end of file
diff --git a/CPLD_CTRL/WR60RD20.bsf b/CPLD_CTRL/WR60RD20.bsf
new file mode 100644
index 0000000..c84ea9f
--- /dev/null
+++ b/CPLD_CTRL/WR60RD20.bsf
@@ -0,0 +1,96 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 16 16 240 176)
+	(text "WR60RD20" (rect 5 0 64 12)(font "Arial" ))
+	(text "inst" (rect 8 144 25 156)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "PCLK1" (rect 0 0 34 12)(font "Arial" ))
+		(text "PCLK1" (rect 21 27 55 39)(font "Arial" ))
+		(line (pt 0 32)(pt 16 32)(line_width 1))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "GCLK" (rect 0 0 29 12)(font "Arial" ))
+		(text "GCLK" (rect 21 43 50 55)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 1))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "Reset" (rect 0 0 29 12)(font "Arial" ))
+		(text "Reset" (rect 21 59 50 71)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 1))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "Enable" (rect 0 0 33 12)(font "Arial" ))
+		(text "Enable" (rect 21 75 54 87)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 1))
+	)
+	(port
+		(pt 0 96)
+		(input)
+		(text "DataRDY[1..0]" (rect 0 0 74 12)(font "Arial" ))
+		(text "DataRDY[1..0]" (rect 21 91 95 103)(font "Arial" ))
+		(line (pt 0 96)(pt 16 96)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "DataIn[bits-1..0]" (rect 0 0 80 12)(font "Arial" ))
+		(text "DataIn[bits-1..0]" (rect 21 107 101 119)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 224 32)
+		(output)
+		(text "REQ" (rect 0 0 23 12)(font "Arial" ))
+		(text "REQ" (rect 180 27 203 39)(font "Arial" ))
+		(line (pt 224 32)(pt 208 32)(line_width 1))
+	)
+	(port
+		(pt 224 48)
+		(output)
+		(text "DataOut[bits-1..0]" (rect 0 0 88 12)(font "Arial" ))
+		(text "DataOut[bits-1..0]" (rect 115 43 203 55)(font "Arial" ))
+		(line (pt 224 48)(pt 208 48)(line_width 3))
+	)
+	(parameter
+		"BITS"
+		"32"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"WORDS"
+		"16"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(rectangle (rect 16 16 208 144)(line_width 1))
+	)
+	(annotation_block (parameter)(rect 240 -64 340 16))
+)
diff --git a/CPLD_CTRL/WR60RD20.vhd b/CPLD_CTRL/WR60RD20.vhd
new file mode 100644
index 0000000..b201fc8
--- /dev/null
+++ b/CPLD_CTRL/WR60RD20.vhd
@@ -0,0 +1,279 @@
+--x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)x-)
+--Descripcion final del la fifo de doble reloj para el bloque 
+--de control del JARS
+--Autores: R. Abad
+--Fecha: 20 de Agosto 2009
+--8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)8-)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+entity  WR60RD20 is
+generic(BITS	: integer:=32;	    
+	    WORDS	: integer:=8
+	   );
+port(PCLK1,GCLK		: in std_logic;
+	 Reset			: in std_logic;
+	 Enable			: in std_logic;	 
+	 DataRDY		: in std_logic_vector(1 downto 0);	 
+	 DataIn			: in std_logic_vector(BITS-1 downto 0);	 	 	  
+	 REQ			: out std_logic :='0';
+	 DataOut		: out std_logic_vector(BITS-1 downto 0)
+	);
+end WR60RD20;
+
+architecture ROJ of WR60RD20 is
+type RAMDI is array (0 to WORDS-1) of std_logic_vector(BITS-1 downto 0);
+type DisState is (InitDis,DisWait1,DisWait2,DisWait3);
+type BufferState is (InitBuff,ModeBuff1,ModeBuff2);
+
+signal MyRAM1: RAMDI; -- Buffer1
+signal MyRAM2: RAMDI; -- Buffer2
+signal MyDisState  	: DisState	:=InitDis;
+signal MyBuffState: BufferState:=InitBuff;
+
+signal WRPointer1: std_logic_vector (3 downto 0):="0000";
+signal RDPointer1: std_logic_vector (3 downto 0):="0000";
+signal WRPointer2: std_logic_vector (3 downto 0):="0000";
+signal RDPointer2: std_logic_vector (3 downto 0):="0000";
+signal EF1: std_logic:='0';	
+signal EF2: std_logic:='0';	
+signal DisRD		: std_logic:='0';
+signal DisRD1		: std_logic:='0';
+signal FallDisRD1 : std_logic:='0';
+signal ResyncDisRD1 : std_logic_vector(1 downto 0):="00";
+signal DataRDY_reg : std_logic_vector(1 downto 0):="00";
+signal DataIn_reg : std_logic_vector (BITS-1 downto 0); 
+
+begin
+	process(GCLK)
+	begin
+		if rising_edge(GCLK) then
+			DataRDY_reg <= DataRDY;
+			DataIn_reg <= DataIn;
+		end if;
+	end process;
+
+--****************************************************
+--Proceso para escribir en los buffers MyRAM1 y MyRAM2
+--de acuerdo a la seleccion de cada buffer
+--la señal DataRDY="11" indica cuando hay un dato válido
+--****************************************************
+	Process_Write:
+	process(GCLK)
+	begin
+		if rising_edge(GCLK) then
+			if(Reset='1')then			
+				WRPointer1<="0000";
+				WRPointer2<="0000";
+			else
+				if((DataRDY_reg="11") and (Enable='1'))then 							
+					if(((MyBuffState=InitBuff)) or (MyBuffState=ModeBuff2)) then				
+							MyRAM1(to_integer(unsigned(WRPointer1) mod WORDS))<=DataIn_reg;						
+							WRPointer1<=std_logic_vector((unsigned(WRPointer1)+1));
+					elsif(MyBuffState=ModeBuff1) then					
+							MyRAM2(to_integer(unsigned(WRPointer2) mod WORDS))<=DataIn_reg;						
+							WRPointer2<=std_logic_vector((unsigned(WRPointer2)+1));
+					end if;
+				end if;
+			end if;
+		end if;
+	end process Process_Write;
+
+--****************************************************
+--Proceso para seleccionar el buffer a escribir y leer
+--mediante la deteccion del flanco de bajada de DisRD1
+--****************************************************	
+
+	Process_SelectBuffer:
+	process(GCLK)
+	begin
+		if rising_edge(GCLK) then
+			if(Reset='1')then
+				MyBuffState <= InitBuff;						
+			else
+				ResyncDisRD1(1 downto 0) <= ResyncDisRD1(0) & DisRD1;
+				FallDisRD1 <= ResyncDisRD1(1) and not(ResyncDisRD1(0));
+				--FallDisRD1 <= DisRD;
+				case MyBuffState is
+					when InitBuff => -- Estado para esperar a que se escriba el primer buffer
+						if(FallDisRD1='1') then -- para indicar que se tienen los datos de los canales					
+							MyBuffState <= ModeBuff1; -- Ir al modo 1						
+						end if;
+					when ModeBuff1 => -- Estado para leer el primer buffer mientras se escribe en el segundo buffer
+						if(FallDisRD1='1') then
+							MyBuffState <= ModeBuff2;						
+						end if;
+					when ModeBuff2 => -- Estado para leer el segundo buffer mientras se escribe en el primer buffer
+						if(FallDisRD1='1') then
+							MyBuffState <= ModeBuff1;						
+						end if;
+				end case;
+			end if;
+		end if;
+	end process Process_SelectBuffer;
+
+--****************************************************
+--Proceso para determinar si el puntero de lectura alcanza
+--al puntero de escritura para detener la lectura del buffer MyRAM1
+--****************************************************
+	Process_EF1:
+	process(PCLK1)
+	begin
+		if falling_edge(PCLK1) then
+		--if rising_edge(PCLK1)then
+			if(Reset='1')then
+				EF1<='1';
+			else
+				if(WRPointer1=RDPointer1)then
+					EF1<='1';
+				else
+					EF1<='0';
+				end if;
+			end if;
+		end if;
+	end process Process_EF1;
+
+--****************************************************
+--Proceso para determinar si el puntero de lectura alcanza
+--al puntero de escritura para detener la lectura del buffer MyRAM2
+--****************************************************
+	Process_EF2:
+	process(PCLK1)
+	begin
+		if falling_edge(PCLK1) then
+		--if rising_edge(PCLK1)then
+			if(Reset='1')then
+				EF2<='1';
+			else
+				if(WRPointer2=RDPointer2)then
+					EF2<='1';
+				else
+					EF2<='0';
+				end if;
+			end if;			
+		end if;
+	end process Process_EF2;
+
+--****************************************************
+--Proceso para leer de los buffers MyRAM1 y MyRAM2
+--de acuerdo a la seleccion de cada buffer
+--****************************************************	
+	Process_Read:
+	process(PCLK1)
+	begin
+		if rising_edge(PCLK1) then
+			if(Reset='1')then
+				DataOut<=(others=>'0');
+				RDPointer1<=(others=>'0');
+				RDPointer2<=(others=>'0');
+				REQ<='0';
+			else
+				if (Enable='1')then
+					if(MyBuffState=ModeBuff1) then					
+						if(EF1='0')then						
+							DataOut<=MyRAM1(to_integer(unsigned(RDPointer1) mod WORDS));							
+							RDPointer1<=std_logic_vector(unsigned(RDPointer1)+1);
+							REQ<='1';
+						else						
+							DataOut<=(others=>'0');
+							REQ<='0';
+						end if;
+					elsif(MyBuffState=ModeBuff2) then
+						if(EF2='0')then						
+							DataOut<=MyRAM2(to_integer(unsigned(RDPointer2) mod WORDS));						
+							RDPointer2<=std_logic_vector(unsigned(RDPointer2)+1);						
+							REQ<='1';
+						else						
+							DataOut<=(others=>'0');
+							REQ<='0';
+						end if;
+					end if;
+				else
+					DataOut<=(others=>'0');
+					REQ<='0';				
+				end if;
+			end if;
+		end if;
+	end process Process_Read;
+
+--****************************************************
+--Proceso para determinar si aun se tiene un dato válido
+--mediante algunos test sucesivos de la senhal DataRDY
+--****************************************************
+	Process_DisableRead:
+	process(GCLK)
+	begin
+		if rising_edge(GCLK) then
+			if(Reset='1')then
+				MyDisState<=InitDis;
+				--DisRD<='0';
+			else
+				case MyDisState is
+					when InitDis=>						
+							if(DataRDY_reg="11")then
+								MyDisState<=DisWait1;
+							end if;
+							--DisRD<='0';
+					when DisWait1=>					
+						if(DataRDY_reg="11")then
+							MyDisState<=DisWait1;
+						else
+							MyDisState<=DisWait2;
+						end if;
+						--DisRD<='1';
+					when DisWait2=>					
+						if(DataRDY_reg="11")then
+							MyDisState<=DisWait1;
+						else
+							MyDisState<=DisWait3;
+						end if;
+						--DisRD<='1';
+					when DisWait3=>					
+						if(DataRDY_reg="11")then
+							MyDisState<=DisWait1;
+							--DisRD<='1';
+						else
+							MyDisState<=InitDis;
+							--DisRD<='0';
+						end if;						
+					when others=>	
+						MyDisState<=InitDis;
+						--DisRD<='0';
+				end case;
+			end if;
+		end if;
+	end process Process_DisableRead;
+
+--****************************************************
+--Proceso que determina el valor de DisRD para detener 
+--la escritura y comenzar la lectura
+--****************************************************	
+	Process_DisableReadFSM:
+	process(MyDisState)
+	begin
+		case MyDisState is
+			when InitDis=> -- para indicar cuando se termino la escritura de datos de los canales
+				DisRD<='0';
+			when others=> -- mientras se esta escribiendo los datos de los canales
+				DisRD<='1';
+		end case;
+	end process Process_DisableReadFSM;
+	
+--****************************************************
+--Determinar valor de DisRD1	en flanco de bajada de PCLK1
+--****************************************************
+	Process_SyncDisRD:
+	process(PCLK1)
+	--process(GCLK)
+	begin
+		-- 
+		if falling_edge(PCLK1)then
+		--if falling_edge(GCLK)then
+			DisRD1<=DisRD;
+		end if;
+	end process Process_SyncDisRD;	
+	
+end ROJ;
\ No newline at end of file