ClockMaster/ClockMasterFPGA Summary · Jicamarca Repository

Jicamarca Repository

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ClockMaster » ClockMasterFPGA

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2 Branches 0 Tags 70 Commits 0 Forks

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		Commit message	Age	Author	Refs
	`r69:fb9738563361`	Clock Master TINY FPGA BX version 2.0	Wed, 11 Dec 2019 19:03:02	jllanosjro	master	0
	`r68:ac764162d519`	Adding comments to the code. Cleaning code	Wed, 11 Dec 2019 18:51:50	jllanosjro	develop	0
	`r67:e70a75e9882a`	Fixing Reading bug. The PPS_DIV registers did not have a default value for reading process. When the address to read is out of range sends a vector of 0.	Thu, 24 Oct 2019 16:09:25	jllanosjro		0
	`r66:4b6f0487d6d3`	Pulse_generator.v Fixed Bug. The state transition logic infere a latch when the pps rising edge is read- The statament only has a IF. ELSE statement was added to solve the bug	Mon, 23 Sep 2019 19:30:39	jllanosjro		0
	`r65:98a3b599dffb`	Merge branch 'develop' of http://jro-dev.igp.gob.pe/rhodecode/ClockMasterFPGA into develop	Thu, 19 Sep 2019 22:34:34	Victor Vasquez		0
	`r64:503199ac0c39`	lalala	Thu, 19 Sep 2019 22:33:50	Victor Vasquez		0
	`r63:f714dfedc605`	Adding blinkin LED	Thu, 19 Sep 2019 22:32:18	jllanosjro		0
	`r62:6e8a54a87e98`	power on reset. reset signal for uart components	Wed, 18 Sep 2019 14:10:39	Victor Vasquez		0
	`r61:9e9132367075`	Changes in thunderbolt.v to fix handling of stuffing bytes. New testbench added to test fixes of stuffing.	Tue, 17 Sep 2019 16:40:56	Victor Vasquez		0
	`r60:d32e06f5d446`	Merge branch 'develop_vvasquez' into develop	Thu, 12 Sep 2019 19:35:03	Victor Vasquez		0

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CLOCK MANAGER USER GUIDE

inside components i_wr (write = 1) [6:0]i_addr [7:0]i_data [7:0]o_data

instantiation w_din w_dout

error code : 8'hCC

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