ClockMaster/ClockMasterFPGA Changelog

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ClockMaster » ClockMasterFPGA

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Select second commit Show combined diff		Commit Message	Age	Author	Refs
	`r69:fb9738563361`	Clock Master TINY FPGA BX version 2.0	Wed, 11 Dec 2019 19:03:02	jllanosjro	master	0
	`r68:ac764162d519`	Adding comments to the code. Cleaning code	Wed, 11 Dec 2019 18:51:50	jllanosjro	develop	0
	`r67:e70a75e9882a`	Fixing Reading bug. The PPS_DIV registers did not have a default value for reading process. When the address to read is out of range sends a vector of 0.	Thu, 24 Oct 2019 16:09:25	jllanosjro		0
	`r66:4b6f0487d6d3`	Pulse_generator.v Fixed Bug. The state transition logic infere a latch when the pps rising edge is read- The statament only has a IF. ELSE statement was added to solve the bug	Mon, 23 Sep 2019 19:30:39	jllanosjro		0
	`r65:98a3b599dffb`	Merge branch 'develop' of http://jro-dev.igp.gob.pe/rhodecode/ClockMasterFPGA into develop	Thu, 19 Sep 2019 22:34:34	Victor Vasquez	merge	0
	`r64:503199ac0c39`	lalala	Thu, 19 Sep 2019 22:33:50	Victor Vasquez		0
	`r63:f714dfedc605`	Adding blinkin LED	Thu, 19 Sep 2019 22:32:18	jllanosjro		0
	`r62:6e8a54a87e98`	power on reset. reset signal for uart components	Wed, 18 Sep 2019 14:10:39	Victor Vasquez		0
	`r61:9e9132367075`	Changes in thunderbolt.v to fix handling of stuffing bytes. New testbench added to test fixes of stuffing.	Tue, 17 Sep 2019 16:40:56	Victor Vasquez		0
	`r60:d32e06f5d446`	Merge branch 'develop_vvasquez' into develop	Thu, 12 Sep 2019 19:35:03	Victor Vasquez	merge	0
	`r59:4fbf875063c3`	Deleting unused from the Design sources	Thu, 12 Sep 2019 19:28:39	jllanosjro		0
	`r58:11c546babf61`	changes in communication with ThunderBolt. New architecture with stages based on PPS.	Thu, 12 Sep 2019 19:28:29	Victor Vasquez		0
	`r57:3aebf4437645`	Merge branch 'develop' into develop_vvasquez	Tue, 10 Sep 2019 21:05:51	Victor Vasquez	merge	0
	`r56:acc05c3bd964`	in process.....	Tue, 10 Sep 2019 21:04:33	Victor Vasquez		0
	`r55:a433e3788389`	PPS_DIVIDER changing clock_counter to 24 bits long. SPI_controller ADDRESS_OUT DEFAULT h'7F.	Tue, 10 Sep 2019 16:53:54	jllanosjro		0
	`r54:02791eb89653`	Merge branch 'develop' into develop_vvasquez	Tue, 10 Sep 2019 16:46:30	Victor Vasquez	merge	0
	`r53:b08b909c568b`	minor changes	Tue, 10 Sep 2019 16:44:49	Victor Vasquez		0
	`r52:2990604af279`	Removing the macros DATA_WIDTH for phase default values	Tue, 10 Sep 2019 16:35:38	jllanosjro		0
	`r51:26a35ef81b38`	Merge branch 'develop' of http://jro-dev.igp.gob.pe/rhodecode/ClockMaster into develop	Tue, 10 Sep 2019 16:01:34	jllanosjro	merge	0
	`r50:c77e68e51ad8`	Adding the macros of DATA_WIDTH to register length and default values length.	Tue, 10 Sep 2019 16:00:15	jllanosjro		0
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